Successive approximation register (SAR) analog to digital converter and method for thus a converter

Abstract

Converter circuit (2) comprising: A sampling and conversion unit (4), configured to - sample and store an analog input signal Vin and - to receive a digital input signal Vref and convert the digital input signal into a signal VDAC by a digital-to-analog converter (DAC) and - to combine the analog input signal Vin and the signal VDAC to form an output signal Vin- VDAC by a subtraction of the signal VDAC; - An amplifier unit (6) for amplifying the output signal of the sampling and conversion unit; - A decision unit for determining, whether an output signal of the amplifier unit has a positive or negative sign; - a clock and phase generator (10); and - a successive approximation register (SAR) unit (12); Wherein the converter circuit (2) further comprises a feed-back loop (16) for subtracting a signal tail of previous bit conversions, the feed-back signal to be subtracted from the signal to be amplified at the amplifier unit. The invention relates as well to a conversion method.

Description

[0001] SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG TO DIGITAL CONVERTER AND METHOD FOR THUS A CONVERTER

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The invention relates to an analog to digital converter with successive approximation register . It also relates to a corresponding method .

[0005] BACKGROUND

[0006] Successive approximation register analog to digital converter ( SAR ADC ) is one of the indispensable blocks in analog systems because of the robustness and simplicity of its architecture in producing a digital signal from an analog one .

[0007] It consists of the following maj or blocks :

[0008] - a digital to analog converter ( DAC ) which can be a capacitive type , a resistive type or mix type of resistive and capacitive .

[0009] - A comparator, which is operable to compare two input signals and might comprise a Pre-ampli fier and a Latch .

[0010] - A Clock and Phase generation network

[0011] - A successive approximation register ( SAR) Logic .

[0012] In general , the DAC provides an output signal to be feed into the comparator . Another input signal is provided by a sample and hold unit , sampling an input signal for feeding into the comparator as second signal . The comparator compares both input signals one to the other and takes a decision in form of a sign- function . Based on the sign function a " 0" bit or a " 1" bit is fed into the register . I f within the comparison for one of the bits , the output sign at the comparator is erroneous , the output in the SAR is erroneous . The clock and phase generation network is responsible for synchroni zation of the di f ferent steps within the circuit .

[0013] SAR ADC algorithm with redundancy, Tomohiko Ogawa et al . APCCAS 2008 - 2008 IEEE Asia Paci fic Conference on Circuits and Systems , 2008 , Conference Paper, IEEE describes a redundant algorithm for high reliable successive approximation Register, where mistakes can be digitally corrected . This method works by defining redundancy in generali zed non-binary search algorithm . However, the inclusion of redundancies into conversion circuits makes it necessary, to include a larger digital to analog converter and makes the calculation more time intensive .

[0014] According to the state-of-the-art SAR ADC circuits comprises a capacitive DAC ( CDAC ) . Such a CDAC comprises capacitive elements as well as switches . A capacitive element has a settling time , which results in the CDAC having a settling time itsel f . Such a settling time gives a minimal time for the operation in the CDAC to be able to provide a correct output signal .

[0015] For increasing the speed of SAR ADC, the settling time of the CDAC is one of the bottlenecks for the following reasons : I f the latch-based comparator gets triggered before the CDAC settling, SAR ADC will converge to a wrong output code . An SAR ADC without redundancy cannot converge to a correct output once a wrong decision is made within a comparator unit for example by a latch . Missing codes , di f ferential nonlinearity ( DNL ) , integral non-linearity ( INL ) and signal-to noise-and-distortion-ratio ( SNDR) degradation can be seen when a wrong decision occurs .

[0016] It is an obj ect of the present invention to provide a method and a device for increasing the performance of the conversion . It is a further obj ect of the invention to provide a method and a device for increasing the speed of the conversion . SUMMARY

[0017] In accordance with the invention a converter circuit comprises : a sampling and conversion unit , configured to sample and store an analog input signal Vin, to receive a digital input signal and convert the digital input signal Vref into a signal VDACby a digital-to-analog converter ( DAC ) and to combine the analog input signal Vin and the signal VDACto form an output signal Vin-Vref by a subtraction of the signal VDAC; an ampli fier unit for ampli fying the output signal of the sampling and conversion unit ; a decision unit for determining, whether an output signal of the ampli fier unit has a positive or negative sign; a clock and phase generator ; and a successive approximation register ( SAR) unit ; the converter circuit further comprises a feed-back loop for subtracting a signal tail of previous bit conversions , the feed-back signal to be subtracted from the signal to be ampli fied at the ampli fier unit .

[0018] The clock and phase generator is connected at least with the sampling unit , the ampli fier unit , and the latch unit , in order to provide a time signal for synchroni zing the di f ferent operations . It is preferably as well connected to the SAR .

[0019] The advantage of the feed-back loop is that the influence of the previous conversion is reduces . Due to the removal or at least partial removal of the signal tail , the decision whether the signal is negative or positive can be taken more precisely, which increases the performance of the circuit and makes it more reliable .

[0020] According to an embodiment , the feedback loop is a decision feed-back equali zation loop . According to an embodiment , the DAC consists of a switch and a capacitance forming a Capacitive DAC ( CDAC ) .

[0021] According to an embodiment , the ampli fier unit is a preamp 1 i f i e r .

[0022] Preferably the decision unit comprises a latch . The latch is a possible embodiment for the decision unit .

[0023] According to an embodiment the coef ficients are determined based on an RC constant of the CDAC .

[0024] According to an embodiment the feedback loop comprises a means for sensing, whether the previous input is negative or positive , wherein, o i f the previous input is positive , the loop subtracts it from the input , o i f the previous input is negative , the loop adds it to the input .

[0025] According to an embodiment the feedback loop comprises an additional CDAC .

[0026] According to an embodiment comprises an equali zation circuit , in particular a continuous time linear equali zation circuit , which is interposed between the sampling and conversion unit and the ampli fier unit . Such a continuous time linear equali zation circuit might increase the bandwith and enhance higher frequencies of the signal .

[0027] According to the invention the method for converting an analog signal into a digital signal comprises : sampling and storing an analog input signal Vinand receiving a digital input signal and converting the digital input signal Vref into a signal VDACby a digital-to-analog converter ( DAC ) and combining the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the reference signal ; ampli fying the signal Vin- VDAC; determining, whether an output signal of the ampli fier unit has a positive or negative sign;

[0028] Performing a successive approximation by a successive approximation register ( SAR) unit ;

[0029] Wherein at the beginning of one period, the signal residue of the previous period is determined, subtracting the signal residue from the signal before ampli fication, for ampli fying a net signal applying a sign function on the net signal before feeding it into the successive approximation .

[0030] According to an embodiment the method is performed by a decision feed-back equali zation loop .

[0031] According to an embodiment the coef ficients are determined based on an RC constant of the CDAC .

[0032] According to an embodiment the method comprises sensing, whether the previous input is negative or positive , wherein, o i f the previous input is positive , the loop subtracts it from the input , o i f the previous input is negative , the loop adds it to the input .

[0033] According to an embodiment the feedback loop comprises an additional CDAC .

[0034] According to an embodiment , the method further comprises performing a time equali zation operation on the output signal Vin-VDACbefore the ampli fication .

[0035] These and other features , embodiments , obj ectives , and advantages of the invention will become apparent from the subsequent description . BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings .

[0037] FIG . 1 shows a block diagram of a SAR ADC converter according to the state of the art .

[0038] FIG . 2 shows a clock scheme .

[0039] FIG . 3a shows an ideal output signal of a sampling and conversion unit .

[0040] FIG . 3b shows a typical output signal of a sampling and conversion unit .

[0041] FIG . 4 shows a diagram of the function of the subtraction .

[0042] FIG . 5 shows a block diagram of the decision feedback circuit unit .

[0043] FIG . 6 shows implementation embodiments of the continuous time equali zation unit .

[0044] DETAILED DESCRIPTION

[0045] FIG . 1 shows an SAR ADC converter circuit 2 according to the state of the art . The sampling and conversion unit 4 depicted at the right has an input for an analog signal Vin which is sampled for a predetermined time period . Thus , the sampling and conversion unit 4 comprises a sample and hold unit ( S / H) .

[0046] The sampling and conversion unit 4 comprises a further input for a reference signal Vref which might be split into a positive VRef also named as VRefPor a negative Vref also named as VRefn. The sampling and conversion unit further comprise a capacitive element 40 and one or more switches 42 . The sampling and conversion unit 4 is adapted to trans form the signal VRef , in particular VRefPoder VRefninto an analog signal by a CDAC . The conversion with the CDAC needs the time to load or unload the capacitive elements having a time constant depending on RC . The time constant of the CDAC is further called TCDAC - In the depicted block diagram, a switch 42 is assigned to each of the signal inputs . The signal Vin is compared to an output signal of a digital to analog converter DAC by subtraction in order to receive an output signal Vin-VCDAc - The VCDAC depends on the clock signal as consecutively a value for one of the bits is evaluated . In particular, the switching of the switches 42 in the sampling and conversion unit 4 is controlled by the clock signal of the clock and phase generator 10 .

[0047] The output signal Vin- VCDAC is then send to an ampli fier unit 6. The ampli fier unit 6 might be in particular a preampli fier . The di f ference signal Vin-VCDAc ampli fied in the ampli fier unit . The ampli fier unit 6 can be connected to the clock and phase generator 10 as well . The ampli fier unit needs as well a certain time Tampto ampli fy a signal . After ampli fication the signal is forwarded to decision unit , which is in the present case a latch that determines the sign of the signal . The time for the latch to decide the sign of the signal is called TiatCh - However, TiatCh is very small compared to the TCDAC resp . Tamp. Depending on the sign, the output is either a " 1" or a "0" . This signal is fed into the SAR logic . The cycle is the repeated for the next bit until each bit is evaluated .

[0048] FIG . 2 shows a clocking scheme of the SAR ADC . The clock and phase generator 10 generates a clock phase . After an initial sampling and of fset cancellation phase , the conversion starts . After this initial phase , within one clock cycle one bit is evaluated and the next bit is evaluated in the next clock cycle . Thus , the evaluation starts for bit number N, followed by bit number N- l until the last bit 1 . For each bit evaluation cycle a VDAC voltage is compared with the input signal within the sampling and conversion unit 4 , while the ampli fier unit 6 is reset , the output signal of the sampling and conversion unit 4 is moved to the ampli fier unit 6 for ampli fying the signal , which is passed after ampli fication to the latch 8 during a latch enabling phase .

[0049] The latch 8 decides about the sign of the signal and to pass the latch output signal to the SAR register for storage . Afterwards the latch is reset again . This cycle is repeated for each bit , wherein the time-consuming operations are the DAC comparison and the ampli fication . FIG . 2 shows a clocking scheme for a 10-bit SAR ADC, thus N is 10 . In the present embodiment VDAC is equal to for the ithbit ( 1 )

[0050] FIG . 3a shows a conversion of with an ideal behavior of the CDAC, when the settling time is very short compared to the clock cycle . The dotted lines show a first conversion for four conversion cycles . The first conversion starts in the second clock cycle , raising the cycle above 0-line , having a value of Vin-VCDAC= Vref / 4+Vlsb / 2 , wherein Vlsb is the least signi ficant bit . Vin-VCDAC drops below zero for the next three conversion but slowly approaching the O-Level .

[0051] The other dashed line shows an alternative conversion . The first conversion starts in the second clock cycle , raising the cycle j ust below 0-line , having a value of Vin-VCDAC= Vref / 4-Vlsb / 2 . Vin-VCDAC raises for the second conversion above zero for the next three conversion but slowly approaching the O-Level . In this case of ideal behavior, the signal is clearly larger or smaller as zero , in order not to induce any error in the determination of the sign .

[0052] However, with a real settling time the settling time of the CDAC might be in the order of the clock cycle , such that at certain conversions , as shown here for the second cycle , the signal is below zero even though it should be above , which induces an error into the conversion . Such a conversion is shown in FIG . 3b . For the second conversion, the signal of Vin-VCDAC does not raise above zero , independently on whether Vin-VCDAC= Vref / 4+Vlsb / 2 or Vin-VCDAC= Vref / 4-Vlsb / 2. Thus, an error is induced if Vin-VCDAC= Vref / 4+Vlsb / 2.

[0053] FIG. 4 shows a diagram showing the inter-symbol interference between the evaluation of several bits. The first signal shows the response for the first conversion, the second signal for the second conversion and the third signal for the third conversion. Each of the signal has a form as abeing the time constant of the CDAC .

[0054] The second conversion starts before the signal from the first conversion is completely settled, thus that at T2 the first signal has a function value of al. This value al has to be subtracted in order to get a net signal. By way of example, if Vin is equal to 3*Vref / 4+Vlsb / 2 the sign of the function is positive thus, the subtraction in principle does not have a influence on the sign. Vlsb is the least significant bit. However, if Vin is equal to 3*Vref / 4-Vlsb / 2 the function will change sign, thus there is an impact by the previous signal conversion on the sign.

[0055] FIG. 5 shows schematically a decision feed-back equalization with a feed-back loop 16. To the node Vln-VCDAc for the conversion n is fed to be further amplified in the amplifier unit 6. The unit stores for each conversion a coefficient ai, where al is equal to Vref / 4 ( 1-aT ) , wherein a~RC of the CDAC. For the subsequent coefficients, the coefficients can be determined to be ai=al / 2i-1with i>=2

[0056] Thus, for each evaluation the coefficient of the previous evaluation can be subtracted before the amplifier unit 6. The feedback-loop as depicted in FIG. 5 has a number of paths equal to the number of bits. For each evaluation, one of the paths is integrated in the complete circuit to perform the feed-back equalization function on the signal Vln-VCDAc for the respective conversion.

[0057] FIG. 6 now shows a block diagram according to the present invention. It shows a conversion circuit 2. The sampling and conversion unit 4 depicted at the right has an input for an analog signal Vin which is sampled for a predetermined time period . Thus the sampling an conversion unit 4 comprises a sample and hold unit ( S / H) . The sampling and conversion unit 4 comprises a further input for a reference signal VRef which might be split into an into for a positive VRef also named as VRefPor a negative VRef also named as VRefn. The sampling and conversion unit further comprise a capacitive element 40 and one or more switches 42 . The sampling and conversion unit 4 is adapted to trans form the signal VRef , in particular VRefPor VRefninto an analog signal by a CDAC . The conversion with the CDAC need the time to load or unload the capacitive elements having a time constant depending on RC . The time constant of the CDAC is further called TCDAC - In the depicted block diagram, a switch 42 is assigned to each of the signal inputs . The signal Vin is compared to an output signal of a digital to analog converter DAC by subtraction in order to receive an output signal Vin-VCDAC . The VCDAC depends on the clock signal as consecutively a value for one of the bits is evaluated . In particular, the switching of the switches 42 in the sampling and conversion unit 4 is controlled by the clock signal of the clock and phase generator 10 .

[0058] The output signal Vin-VCDAC is then send to an ampli fier unit 6. The ampli fier unit 6 might be in particular a preampli fier . The di f ference signal Vin-VCDAC is ampli fied in the ampli fier unit . The ampli fier unit 6 can be connected to the clock and phase generator 10 as well . The ampli fier unit needs as well as a certain time Tampto ampli fy a signal . After ampli fication the signal is forwarded to a decision unit , which is in the present case a latch that determines the sign of the signal . The time for the latch to decide the sign of the signal is called TiatCh - However, TiatCh is very small compared to the TCDAC resp . Tamp . Depending on the sign, the output is either a " 1" or a "0" . This signal is fed into the SAR logic . Thus , within the first conversion, the feedback loop 16 does not change the result . The cycle is the repeated for the next bit until each bit is evaluated . Starting from the second bit evaluation, the system now takes into account the tail from the previous evaluation through the feed-back loop 16 , by subtracting the respective coef ficients ai- 1 before the preampli fier unit from the respective di f ference signal Vin-VCDAC of the i-th bit evaluation .

[0059] By the subtraction of the tail a signi ficantly improved resolution on whether the signal feed into the latch is positive or negative , improving the reliability of the converter circuit . Even though not shown, the circuit comprises a clock and phase generator 10 .

[0060] LIST OF REFERENCE SIGNS

[0061] Sampling and conversion unit 4

[0062] Ampli fier unit 6 Latch 8

[0063] Clock and phase generator 10

[0064] SAR Logic 12

[0065] Feedback loop 16

[0066] Capacitive element 40 Switch 42

[0067] Input signal Vin

[0068] Reference signal VRef

[0069] Positive reference signal VRefp

[0070] Negative reference signal VRefn

Claims

CLAIMS1. Converter circuit (2) comprising:- - A sampling and conversion unit (4) , configured to sample and store an analog input signal Vin and to receive a digital input signal Vref and convert the digital input signal into a signal VDACby a digital-to-analog converter (DAC) and to combine the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the signal VDAC;- An amplifier unit (6) for amplifying the output signal of the sampling and conversion unit;- A decision unit for determining, whether an output signal of the amplifier unit has a positive or negative sign;- a clock and phase generator (10) ; and- a successive approximation register (SAR) unit (12) ;Wherein the converter circuit (2) further comprises a feed-back loop (16) for subtracting a signal tail of previous bit conversions, the feed-back signal to be subtracted from the signal to be amplified at the amplifier unit.

2. Converter circuit (2) of claim 1, wherein the feedback loop (16) is a decision feed-back equalization loop.

3. Converter circuit (2) of claim 1, wherein the DAC consists of a switch and a capacitance forming a Capacitive DAC (CDAC) .

4. Converter circuit (2) of claim 1 or 2, wherein the coefficients are determined based on an RC constant of the CDAC.

5. Converter circuit (2) according to one of the previous claims, wherein the feedback loop comprises a means for sensing, whether the previous input is negative or positive, wherein, o if the previous input is positive, the loop subtracts it from the input, o if the previous input is negative, the loop adds it to the input .

6. Converter circuit (2) according to one of the previous claims, wherein the feedback loop comprises an additional CDAC.

7. Converter circuit (2) according to one of the previous claims, wherein comprises an equalization circuit which is interposed between the sampling and conversion unit and the amplifier unit.

8. Method for converting an analog signal into a digital signal, the method comprising: sampling and storing an analog input signal Vin and receiving a digital input signal and converting the digital input signal Vref into a signal VDACby a digital-to-analog converter (DAC) and combining the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the signal VDAC;- amplifying the signal Vin- VDAC;- determining, whether an output signal of the amplifier unit has a positive or negative sign;- Performing a successive approximation by a successive approximation register (SAR) unit; wherein at the beginning of one period, the signal residue of the previous period is determined, the signal residue is subtracted from the signal before amplification, for amplifying a net signal applying asign function on the net signal before feeding it into the successive approximation register.

9. Method according to claim 8, wherein the method is performed by a decision feed-back equalization loop (16) .

10. Method of claim 8 or 9, wherein the coefficients are determined based on an RC constant of the CDAC .

11. Method according to one of claims 8 - 10, comprising sensing, whether the previous input is negative or positive, wherein, o if the previous input is positive, the loop (16) subtracts it from the input, o if the previous input is negative, the loop (16) adds it to the input.

12. Method according to one of claims 8 - 11, wherein the feedback loop comprises an additional CDAC.

13. Method according to one of claims 8 - 12, the method further comprises performing a time equalization operation on the output signal Vin-VDACbefore the amplification .

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