Power converter

Abstract

This power converter includes first and second capacitors, first to sixth switching elements, and a load, wherein switching between a third output state and a first output state occurs via a second dead-time state, switching between the third output state and a second output state occurs via a first dead-time state, and when transitioning back and forth between the third output state and the second dead-time state, the fifth switching element executes an operation of completing turn-on before the third switching element and / or completing turn-off after the third switching element, or, when transitioning back and forth between the third output state and the first dead-time state, the sixth switching element executes an operation of completing turn-on before the second switching element and / or completing turn-off after the second switching element.

Description

Power Converter

[0001] The present invention relates to a power converter including a three-level inverter.

[0002] In recent years, multilevel inverters have been actively studied to meet the need for higher bus voltages in power converters. For example, Patent Document 1 proposes a multilevel inverter circuit called an ANPC (Active Neutral-Point-Clamped).

[0003] Japanese Patent Application Laid-Open No. 2005-176538

[0004] However, in the conventional technology, there is an imbalance in surge voltage and loss between switching elements, which causes problems such as a decrease in power efficiency and reliability.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a power converter that can correct the imbalance in surge voltage and loss between switching elements and can improve power efficiency.

[0006] A power converter according to the present invention has first and second capacitors connected in series between a positive electrode and a negative electrode of a DC power supply, first to fourth switching elements further connected in series between the positive electrode and the negative electrode of the DC power supply, a fifth switching element connected between a junction of the first and second switching elements and a junction of the first and second capacitors, a sixth switching element connected between the junction of the third and fourth switching elements and a junction of the first and second capacitors, and the junction of the second and third switching elements and a load are connected, wherein a state in which the first, second and sixth switching elements are ON and the third, fourth and fifth switching elements are OFF is defined as a first output state, a state in which the third, fourth and fifth switching elements are ON and the first, second and sixth switching elements are OFF is defined as a second output state, and a state in which the second, third, fifth and sixth switching elements are ON and the first and fourth switching elements are OFF is defined as a third output state, A first dead time state is a state in which the third and fifth switching elements are ON and the first, second, fourth, and sixth switching elements are OFF, a second dead time state is a state in which the second and sixth switching elements are ON and the first, third, fourth, and fifth switching elements are OFF, switching between the third output state and the first output state occurs via the second dead time state, switching between the third output state and the second output state occurs via the first dead time state, and when transitioning between the third output state and the second dead time state, the fifth switching element performs at least one of completing turn-on before or completing turn-off after the third switching element, or when transitioning between the third output state and the first dead time state, the sixth switching element performs at least one of completing turn-on before or completing turn-off after the second switching element.

[0007] According to the present disclosure, it is possible to provide a power converter that can correct surge voltage and loss imbalances between switching elements and improve power efficiency. Further features related to the present invention will become apparent from the description of the present specification and the accompanying drawings. In addition, problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0008] 1 is a schematic diagram showing a power converter according to a reference example. A circuit diagram showing the U phase of FIG. 1. A state transition diagram showing a control method for an ANPC inverter in the reference example. A time chart showing the control method for the ANPC inverter in the reference example. A diagram for explaining a case in which switching loss and switching surge occur in a negative cycle. A diagram for comparing switching surge voltages and losses in the reference example. A state transition diagram showing a control method for an ANPC inverter in embodiment 1 of the present invention. A time chart showing the control method for the ANPC inverter in embodiment 1 of the present invention. A diagram for explaining a current flowing in state O and state Oec. A diagram for comparing switching surge voltages and losses in embodiment 1 of the present invention. A time chart for explaining a difference in switching delay time in embodiment 1.

[0009] First, a reference example useful for understanding this embodiment will be described below with reference to the drawings. A three-phase inverter power conversion device will be used as an example below, but the present invention can also be applied to single-phase inverters, polyphase inverters, and converters. FIG. 1 is a schematic diagram of a three-phase inverter power converter, as described in Patent Document 1. The device in FIG. 1 is a three-level ANPC (Active Neutral-Point-Clamped) inverter (hereinafter simply referred to as an ANPC inverter) having three phases. As shown in FIG. 1 , in the ANPC inverter, DC power supplies Vdc1 and Vdc2 are connected in series. The high-potential terminal of DC power supply Vdc1 is the P terminal, the connection point between DC power supplies Vdc1 and Vdc2 is the medium-potential terminal O terminal, and the low-potential terminal of DC power supply Vdc2 is the N terminal. A smoothing capacitor C1 is connected between the P terminal and the O terminal, and a smoothing capacitor C2 is also connected between the O terminal and the N terminal. A plurality of capacitors C1 and C2 may be connected in parallel. The P, O, and N terminals are further connected to the main circuit portions of the U, V, and W phases.

[0010] A specific configuration will be described using the U-phase as an example with reference to FIG. 2. As shown in FIG. 2(a), the U-phase includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, a fifth switching element Q5, and a sixth switching element Q6. While each switching element is a MOSFET, it is not limited to this and may be a parallel connection of a semiconductor switching element and a diode. The semiconductor switching elements may be, for example, semiconductor switching elements other than MOSFETs, such as IGBTs. The diodes may be, for example, PN junction diodes, Schottky barrier diodes, or other diodes. The switching elements may be made of materials such as Si, SiC, GaN, and GaO. Two or more types of switching elements may also be hybridly implemented. Capacitors are not shown in FIG. 2(a). In the following, to avoid redundancy, "switching elements Q1 to Q6" may be simply referred to as "Q1 to Q6."

[0011] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series in this order from terminal P to terminal N. A fifth switching element Q5 is connected between the O terminal and an intermediate connection point between the first switching element Q1 and the second switching element Q2. A sixth switching element Q6 is connected between the O terminal and an intermediate connection point between the third switching element Q3 and the fourth switching element Q4. The intermediate connection point between the second switching element Q2 and the third switching element Q3 is called the AC terminal, and this AC terminal is connected to a load (see FIG. 1 ).

[0012] 2B, the switching of the switching elements Q1 to Q6 is controlled by individual gate drivers (GD). The switching signals of the individual gate drivers are generated by a PWM generator 20 of the controller 10.

[0013] Next, we will explain the energization method of the ANPC inverter. Normally, DC power supplies Vdc1 and Vdc2 have a voltage of half the bus voltage, that is, VDC / 2. The O terminal is considered to be the voltage neutral point with a potential of 0. Then, the potential of the P terminal is +VDC / 2, and the potential of the N terminal is -VDC / 2. The voltage between the P terminal and the N terminal is exactly the bus voltage VDC. To energize the AC terminal and the P terminal in this state, at least the first switching element Q1 and the second switching element Q2 must be turned ON simultaneously. Similarly, to energize the AC terminal and the N terminal, at least the third switching element Q3 and the fourth switching element Q4 must be turned ON simultaneously.

[0014] On the other hand, there are two paths for energizing the AC terminal and the O terminal. Specifically, as shown in FIG. 9 (described later), there is a first path (route 1) in which the second switching element Q2 and the fifth switching element Q5 are simultaneously turned ON, and a second path (route 2) in which the third switching element Q3 and the sixth switching element Q6 are simultaneously turned ON. To energize the AC terminal and the O terminal, at least one of these two paths must be energized. When the AC terminal is energized with the P terminal, the O terminal, and the N terminal, respectively, the potentials of the AC terminal are +VDC / 2, 0, and -VDC / 2, respectively. Thus, the voltage output level of the AC terminal is three-stage.

[0015] Next, a control method for an ANPC inverter, particularly a reference example control method in which current is applied between the AC terminal and the O terminal via the two paths described above, will be described with reference to Figures 3 to 5. Figure 3 is a state transition diagram illustrating the control method for an ANPC inverter in the reference example, showing the switch states and the switching elements that are ON corresponding to the switch states. Figure 4 is a time chart illustrating the control method in the reference example, showing the ON / OFF states of each switching element and the AC terminal voltage Vout. Figure 5 is a diagram for explaining a case in which switching loss and switching surge occur during a negative cycle.

[0016] First, as shown in Fig. 3, the states when the AC terminals are energized with the P terminal, O terminal, and N terminal are called state P, state O, and state N, respectively. State P, state O, and state N correspond to tp, to, and tn, respectively, shown in Fig. 4. The transition between state P and state O is called a positive cycle, and the transition between state O and state P is called a negative cycle. The operation of the positive cycle is the same as that of the negative cycle, so a description thereof will be omitted, and only the transition operation of the negative cycle will be described.

[0017] As shown in Figures 3 and 4, in state N(tn), switching elements Q3, Q4, and Q5 are ON, and the voltage at the AC terminal is -VDC / 2. In state O(to), switching elements Q2, Q3, Q5, and Q6 are ON, and the output voltage at the AC terminal is 0. Here, in state O, current is simultaneously conducted through route 1 (Q2 and Q5) and route 2 (Q3 and Q6) between the O terminal and the AC terminal, and equal current flows through both paths. When transitioning from state N to state O, an intermediate state called state NO(tx) is first passed (state PO(ty) in the case of a positive cycle). In state NO(tx), switching elements Q3 and Q5 are ON.

[0018] Here, when a switching element is switched, if the direction of current when conducting is opposite to the forward direction of the diode included in the switching element, switching loss and surge voltage will occur in the switching element. Figure 5 shows cases in which loss and surge voltage will occur. Figure 5 shows cases in which a transition occurs between state N or state O and intermediate state NO, and switching elements in which loss or surge will occur are circled with a "circle".

[0019] First, as shown in Fig. 5A, when shifting from state NO to state N, switching element Q4 turns on. When a current flows from the AC terminal to the N terminal after turning on (state N), a turn-on switching loss occurs in switching element Q4, and a recovery loss and recovery surge occur in switching elements Q2 and Q6.

[0020] 5B, when shifting from state N to state NO, switching element Q4 is turned off. If a conducting current in state N flows from the AC terminal to the N terminal, a switching loss and a surge voltage occur in switching element Q4 when it is turned off.

[0021] Next, as shown in FIG. 5C, when shifting from state NO to state O, switching elements Q2 and Q6 are turned on simultaneously. When a conduction current (state O) flows from the O terminal to the AC terminal, turn-on switching loss occurs in switching elements Q2 and Q6, and recovery loss and recovery surge occur in switching element Q4.

[0022] 5(d), when the state shifts from state O to state NO, switching elements Q2 and Q6 are turned off simultaneously. If current flows from the O terminal to the AC terminal in state O, turn-off loss and surge voltage occur in switching elements Q2 and Q6.

[0023] Figure 6 is a diagram comparing the surge voltages and losses that occur in switching elements Q2, Q3, Q5, and Q6 in the reference example. First, let us explain the differences in surge voltages that occur in these elements. Here, surge voltage refers to an overvoltage that occurs when the parasitic capacitance of a switching element is excessively charged due to the influence of inductance components near the element when the switching element is turned off.

[0024] Normally, the greater the inductance of a circuit, the higher the surge voltage generated in the switching element. However, because the inductance components of the paths through which switching elements Q2 and Q6 are located (paths starting from the O terminal and returning to the N terminal) are different, a difference in surge voltages occurs between the two switching elements. Specifically, the path through which switching element Q6 is located is O terminal → Q6 → Q4 → N terminal. On the other hand, the path through which switching element Q2 is located is O terminal → Q5 → Q2 → Q3 → Q4 → N terminal, which is longer than the path through which switching element Q6 is located. Therefore, the surge voltage generated in switching element Q2 is greater than the surge voltage generated in switching element Q6. The same is true in the positive cycle, where the surge voltage generated in switching element Q3 is greater than the surge voltage generated in switching element Q5. In summary, as shown in Figure 6(a), the switching surge voltages generated in switching elements Q2 and Q3 are greater than the switching surge voltages generated in switching elements Q5 and Q6.

[0025] Next, we will explain the difference in losses that occur in the above switching elements. The losses that occur in switching elements include conduction loss caused by heat generated while current is flowing, and switching loss caused by heat generated during switching. The magnitude of these losses is proportional to the magnitude of the current flowing through the element.

[0026] A conduction current flows through switching element Q4 in state N, and a conduction current flows through switching element Q6 in state O. In contrast, a conduction current flows through switching element Q3 in both state O and state N. Therefore, the conduction loss of switching element Q3 is higher than the conduction losses of switching elements Q4 and Q6. Furthermore, because the conduction current flows equally through switching elements Q3 and Q6 in state O, the currents flowing through switching elements Q3 and Q6 are also equal when switching. Therefore, the switching losses of switching elements Q3 and Q6 are comparable. Therefore, considering the total loss (conduction loss and switching loss), the loss of switching element Q3 is greater than the loss of switching element Q6. The same is true in the positive cycle, where the loss of switching element Q2 is greater than the loss of switching element Q5. In summary, as shown in Figure 6(b), the losses of switching elements Q2 and Q3 are greater than the losses of switching elements Q5 and Q6.

[0027] 6, it can be seen that the switching elements Q2 and Q3 are larger in both loss and surge voltage than the switching elements Q5 and Q6. In this way, in an ANPC inverter, the problem of imbalance in loss and surge voltage between the switching elements arises.

[0028] <Embodiment 1> An embodiment of the present invention will be described below with reference to the drawings. Fig. 7 is a state transition diagram showing the control method of the ANPC inverter in embodiment 1 of the present invention. Fig. 8 is a time chart showing the control method of the ANPC inverter in embodiment 1. Differences from the reference example will be described below.

[0029] This embodiment differs from the state transition diagram of the reference example in that a state Odf is added between state PO and state O, and a state Oec is added between state NO and state O. State Odf corresponds to td and tf shown in FIG. 7, and state Oec corresponds to te and tc shown in FIG. 7. Comparing the time chart of this embodiment shown in FIG. 8 with the time chart of the reference example shown in FIG. 4, it can be seen that periods te and tc (tf and td in the positive cycle) are added before and after time to. During these periods, for example, in the negative cycle, only switching elements Q3 and Q5 are ON, and no current flows anywhere. This period is defined as dead time in this specification. The same applies to tf and td in the positive cycle.

[0030] In this embodiment, the operation of the positive cycle is similar to that of the negative cycle, so a description thereof will be omitted and only the transition operation of the negative cycle will be described. As shown in FIG. 9 , there are two current conduction routes between state O and state Oec. In state Oec, switching element Q2 is turned OFF from state O, and switching elements Q3, Q5, and Q6 are ON, so current mainly flows along route 2. Considering the transition from state NO (only Q3 and Q5 are ON) to state O (Q2, Q3, Q5, and Q6 are ON) via state Oec (Q3, Q5, and Q6 are ON), current first primarily flows along route 2 at the moment of transition to state Oec. After a while, switching element Q2 turns on, transitioning to state O, and the current is shared, with current flowing equally along both route 1 and route 2.

[0031] Conversely, when transitioning from state O to state NO via state Oec, current first flows equally through both routes in state O. Then, in state Oec, the current through route 1 is reduced and the current through route 2 increases. Eventually, all of the current flowing through route 1 may flow through route 2. In this state, switching element Q6 is turned OFF, resulting in transition to state NO. That is, in the reference example, during the transition from state O to state NO, switching elements Q2 and Q6 were simultaneously turned OFF with currents flowing equally through them, resulting in equivalent switching losses. However, in this embodiment, during the transition from state O to state NO, Q2 is first turned OFF with currents flowing equally through switching elements Q2 and Q6, and then Q6 is turned OFF with the current concentrated on route 2.

[0032] To summarize, when transitioning between state O and state Oec, the fifth switching element performs at least one of the following operations: completing turn-on before the third switching element or completing turn-off after the third switching element. Also, during a positive cycle, when transitioning between state O and state Odf, the sixth switching element performs at least one of the following operations: completing turn-on before the second switching element or completing turn-off after the second switching element.

[0033] As described above, in the reference example, the currents flowing through switching elements Q2 and Q6 were equal during switching. However, in this embodiment, switching element Q6 switches with a current greater than that of switching element Q2. Therefore, in this embodiment, the switching loss occurring in Q6 is greater than the switching loss occurring in Q2. Similarly, in the positive cycle, the switching loss occurring in Q5 is greater than the switching loss occurring in Q3. Note that, unlike the reference example, Q5 and Q6 are still ON at the moment they are turned off, and the current continues to flow toward Q5 and Q6 without being completely shut off. Therefore, the switching loss occurring in Q2 and Q3 is smaller than in the reference example.

[0034] Furthermore, it is preferable that the times te and tc in the state Oec are shorter than the time to in the state O. This is because by setting them in this way, it becomes possible to ignore the increase in the conduction loss of the switching element Q6 in the state Oec.

[0035] FIG. 10 is a graph comparing the surge voltages and losses generated in switching elements Q2, Q3, Q5, and Q6 in this example. The solid line and dashed line represent the results for this example and the reference example, respectively. Because switching element Q2 is switched at a smaller current than in the reference example, the surge voltage in switching element Q2 is reduced. On the other hand, because switching element Q6 is switched at a larger current than in the reference example, the surge voltage in switching element Q6 increases. The same is true for the positive cycle, where the surge voltage generated in switching element Q3 decreases and the surge voltage generated in switching element Q5 increases. Therefore, the imbalance between the switching surge voltages in switching element Q2 (Q3) and switching element Q5 (Q6) is corrected and they become approximately the same.

[0036] Furthermore, because switching element Q2 was switched at a smaller current than in the reference example, the switching loss in switching element Q2 was reduced. On the other hand, because switching element Q6 was switched at a larger current than in the reference example, the switching loss in switching element Q6 increased. As described above, the conduction loss is negligible and therefore is at the same level as in the reference example. Therefore, when considering the total loss (conduction loss and switching loss), the loss imbalance between switching element Q2 (Q3) and switching element Q5 (Q6) is corrected and is at the same level.

[0037] As described above, according to this embodiment, the loss in the switching elements of the ANPC inverter and the imbalance of the surge voltage are reduced.

[0038] To obtain the effects of this embodiment described above, it is essential to pass through state Oec (Q3, Q5, and Q6 are ON) when transitioning between state NO (Q3 and Q5 are ON) and state O (Q2, Q3, Q5, and Q6 are ON). In other words, it is essential that Q6 is turned ON before Q2 when transitioning from state NO to state O, and that Q6 is turned OFF after Q2 when transitioning from state O to state NO.

[0039] Here, "ON" and "OFF" in this specification refer to "completion of turn-on operation" and "completion of turn-off operation," respectively, and more specifically, to "maximization of the main current flowing through the element" and "minimization of the main current flowing through the element," respectively. Furthermore, the start of turn-on (turn-off) refers to the start of the increase (decrease) in the voltage applied to the element. Furthermore, the completion of turn-on (turn-off) refers to the net drain current becoming 100% (0%), respectively.

[0040] In the above-described first embodiment, both te and tc (td and tf) are set before and after state O, but depending on the situation, only one of te or tc (td or tf) may be set. For example, if the turn-off loss is significant and the imbalance is large, only tc (td) may be set. Furthermore, it is preferable to set the lengths of te, tc, td, and tf longer than the switching delay time of the switching element (the time from the rise or fall of the gate voltage to the rise or fall of the element's main current).

[0041] The reason for this will be explained with reference to Figure 11. It takes time T1 from when switching element Q6 (Q5) starts to turn on (when gate voltage starts to rise) until current actually starts to flow through Q6 (Q5). If switching element Q2 (Q3) starts to turn on during this time T1, current will also start to flow through Q2 (Q3) before the current flowing through Q6 (Q5) has fully risen, and sufficient imbalance correction effect will not be obtained.

[0042] Similarly, at turn-off, it takes time T2 from when switching element Q2 (Q3) starts to turn off until the current flowing through Q2 (Q3) actually starts to decrease. If switching element Q6 (Q5) starts to turn off during this time T2, the current flowing through Q6 (Q5) will also start to decrease before the current flowing through Q2 (Q3) is minimized, and a sufficient imbalance correction effect will not be obtained.

[0043] The settings of te, tc, td, and tf may be made by the PWM generator 20 on the controller 10 side shown in FIG. 2, or by adding a time adjustment circuit between the PWM generator 20 and the gate driver, or by adding a time adjustment circuit inside the gate driver.

[0044] <Example 2> Next, a power converter according to Example 2 will be described. Differences from Example 1 will be mainly described below. In Example 1, dead times te, tc, td, and tf were set to offset the switching timing between switching element Q6 (Q5) and switching element Q2 (Q3), thereby correcting the imbalance in surge voltage and loss. In contrast, in this example, the offset in switching timing is achieved by setting different switching speeds for switching element Q6 (Q5) and switching element Q2 (Q3).

[0045] Specifically, the turn-on speed of the switching element Q5 (Q6) is set to be faster than that of the switching element Q2 (Q3). For example, the turn-on drive resistance of the switching element Q5 (Q6) is set to be smaller than the turn-on drive resistance of the switching element Q2 (Q3).

[0046] Alternatively, instead of the driving resistance, the driving current may be set. For example, the turn-on gate current of the switching element Q5 (Q6) may be set higher than the turn-on gate current of the switching element Q2 (Q3). In this case, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to rise at the same time, the gate voltage of the switching element Q5 (Q6) exceeds the threshold voltage first, and the main current starts to flow through the switching element Q5 (Q6) before the switching element Q2 (Q3).

[0047] On the other hand, it is also possible to set the turn-off speed of the switching element Q5 (Q6) slower than that of the switching element Q2 (Q3). For example, the turn-off drive resistance of the switching element Q5 (Q6) is set larger than the turn-off drive resistance of the switching element Q2 (Q3). In addition to the drive resistance, the drive current may also be set. For example, the turn-off gate current of the switching element Q5 (Q6) is set lower than the turn-on gate resistance of the switching element Q2 (Q3). In this case, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to drop at the same timing, the gate voltage drop of the switching element Q5 (Q6) is slower, so the timing at which the main current of Q5 (Q6) starts to drop is also slower than that of Q2 (Q3).

[0048] When the turn-on (turn-off) drive resistance or turn-on (turn-off) gate current of each switching element is set as described above, even if each switching element starts to turn on simultaneously, current begins to flow through switching element Q5 (Q6) before switching element Q2 (Q3), resulting in a large current at turn-on and larger turn-on losses. Similarly, even if each switching element is turned off simultaneously, the main current begins to drop through switching element Q5 (Q6) later than switching element Q2 (Q3) at turn-off, resulting in a large current at turn-off, larger turn-off losses, and larger surge voltages. Therefore, as in the first embodiment, the imbalance in losses and surge voltages in the switching elements is corrected.

[0049] Next, a power converter according to a third embodiment will be described. The following mainly describes the differences between the third embodiment and the previously described embodiments. In this embodiment, the lag in switching timing is achieved by selecting elements having different threshold voltages for the switching element Q6 (Q5) and the switching element Q2 (Q3).

[0050] Specifically, an element having a lower threshold voltage than the switching element Q2 (Q3) is selected as the switching element Q5 (Q6). Then, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to rise at the same time, the gate voltage of the switching element Q5 (Q6) exceeds the threshold voltage first, and the main current starts to flow through the switching element Q5 (Q6) before the switching element Q2 (Q3). On the other hand, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to fall at the same time, the threshold voltage of the switching element Q5 (Q6) is low, so the timing at which the main current finishes falling is delayed.

[0051] When the switching elements are selected in this manner, current begins to flow through switching element Q5 (Q6) before switching element Q2 (Q3) at turn-on, resulting in a larger current at turn-on and larger turn-on losses. Furthermore, the main current of switching element Q5 (Q6) takes a longer time to fall than that of switching element Q2 (Q3) at turn-off, resulting in a larger current at turn-off, resulting in larger turn-off losses and surge voltages. Therefore, as in the previously described embodiments, the imbalance in losses and surge voltages in the switching elements is corrected.

[0052] Next, a power converter according to a fourth embodiment will be described. The following mainly describes the differences between the fourth embodiment and the previously described embodiments. In this embodiment, a shift in switching timing is achieved by setting different gate voltages (negative bias) when the switching element Q6 (Q5) and the switching element Q2 (Q3) are turned off.

[0053] Specifically, the OFF gate voltage of the switching element Q5 (Q6) is adjusted to be higher than the OFF gate voltage of the switching element Q2 (Q3). For example, the OFF gate voltage of the switching element Q5 (Q6) is adjusted to -1 V, and the OFF gate voltage of the switching element Q2 (Q3) is adjusted to -3 V. Then, even if the gate voltages of the switching elements Q5 (Q6) and Q2 (Q3) begin to rise at the same time and at the same speed, the gate voltage of the switching element Q5 (Q6) exceeds the threshold voltage first, and the main current begins to flow through the switching element Q5 (Q6) before the switching element Q2 (Q3). On the other hand, at turn-off, the lower the OFF gate voltage, the faster the gate voltage drops, i.e., the faster the turn-off speed. Therefore, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to drop at the same timing, the gate voltage of the switching element Q5 (Q6) drops slowly, so the timing at which the current starts to drop is also delayed.

[0054] In this way, when turned on, current begins to flow through switching element Q5 (Q6) before switching element Q2 (Q3), so the current at turn-on is large and the turn-on loss is larger. Also, when turned off, the main current begins to drop through switching element Q5 (Q6) later than through switching element Q2 (Q3), so the current at turn-off is large and the turn-off loss and surge voltage are also larger. Therefore, as in the previously described embodiments, the imbalance in the loss and surge voltage in the switching elements is corrected.

[0055] The above-described embodiment of the present invention provides the following advantageous effects.

[0056] (1) A power converter according to the present invention includes first and second capacitors connected in series between a positive electrode and a negative electrode of a DC power supply, first to fourth switching elements further connected in series in this order between the positive electrode and the negative electrode of the DC power supply and in parallel with the first and second capacitors, a fifth switching element connected between a junction of the first and second switching elements and a junction of the first and second capacitors, a sixth switching element connected between a junction of the third and fourth switching elements and a junction of the first and second capacitors, and a load connected to the junction of the second and third switching elements, wherein a first output state is a state in which the first, second, and sixth switching elements are ON and the third, fourth, and fifth switching elements are OFF, and a second output state is a state in which the third, fourth, and fifth switching elements are ON and the first, second, and sixth switching elements are OFF, and a third output state is a state in which the third and fifth switching elements are ON and the first, second, fourth, and sixth switching elements are OFF; a first dead-time state is a state in which the second and sixth switching elements are ON and the first, third, fourth, and fifth switching elements are OFF; a second dead-time state is a state in which the second and sixth switching elements are ON and the first, third, fourth, and fifth switching elements are OFF; switching between the third output state and the first output state occurs via the second dead-time state; switching between the third output state and the second output state occurs via the first dead-time state; when transitioning between the third output state and the second dead-time, the fifth switching element performs at least one of completing turn-on before or completing turn-off after the third switching element; or when transitioning between the third output state and the first dead-time, the sixth switching element performs at least one of completing turn-on before or completing turn-off after the second switching element.

[0057] The above configuration makes it possible to correct the imbalance in surge voltage and loss between the switching elements, thereby improving power efficiency.

[0058] (2) When transitioning from the third output state to the second dead time, the fifth switching element starts to turn off with a delay of at least the time from when the gate voltage of the third switching element starts to fall until the main current starts to fall, or when transitioning from the third output state to the first dead time, the sixth switching element starts to turn off with a delay of at least the time from when the gate voltage of the second switching element starts to fall until the main current starts to fall. This ensures that the main current of the fifth (sixth) switching element also starts to fall after the main current of the third (second) switching element has reliably started to fall, making it possible to prevent the fifth (sixth) switching element from completing turn-off earlier and reliably correct the imbalance.

[0059] (3) When transitioning from the second dead time to the third output state, the fifth switching element starts to turn on before the third switching element starts to turn on for at least the time from when the gate voltage of the fifth switching element starts to rise until the main current starts to rise, or when transitioning from the first dead time to the third output state, the sixth switching element starts to turn on before the second switching element starts to turn on for at least the time from when the gate voltage of the sixth switching element starts to rise until the main current starts to rise. This prevents the third (second) switching element from completing turn-on earlier, as in (2), and makes it possible to reliably correct the imbalance.

[0060] (4) The turn-on drive resistance of the fifth switching element is set lower than the turn-on drive resistance of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or the turn-on drive resistance of the sixth switching element is set lower than the turn-on drive resistance of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element. As a result, even if the fifth (sixth) switching element and the third (second) switching element start to turn on at the same time, the fifth (sixth) switching element completes turning on first, thereby reliably achieving the effects of the present invention.

[0061] (5) The turn-on gate current of the fifth switching element is set higher than the turn-on gate current of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or the turn-on gate current of the sixth switching element is set higher than the turn-on gate current of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element. As a result, as in (4), even if the fifth (sixth) switching element and the third (second) switching element start to turn on at the same time, the fifth (sixth) switching element completes turning on first, thereby reliably achieving the effects of the present invention.

[0062] (6) The turn-off drive resistance of the fifth switching element is set higher than the turn-on drive resistance of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-off speed of the third switching element, or the turn-off drive resistance of the sixth switching element is set higher than the turn-off drive resistance of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. In this way, even if the fifth (sixth) switching element and the third (second) switching element start to turn off at the same time, the fifth (sixth) switching element completes turning off later, thereby reliably achieving the effects of the present invention.

[0063] (7) The turn-off gate current of the fifth switching element is set lower than the turn-on gate current of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-on speed of the third switching element, or the turn-off gate current of the sixth switching element is set lower than the turn-off gate current of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. As a result, as in (6), even if the fifth (sixth) switching element and the third (second) switching element start to turn off at the same time, the fifth (sixth) switching element completes turning off later, thereby reliably achieving the effects of the present invention.

[0064] (8) The fifth switching element and the third switching element are selected so that the threshold voltage of the fifth switching element is lower than the threshold voltage of the third switching element, or the sixth switching element and the second switching element are selected so that the threshold voltage of the sixth switching element is lower than the threshold voltage of the second switching element. As a result, as in the above, the fifth (sixth) switching element is turned on before (turned off after) the third (second) switching element, thereby reliably achieving the effects of the present invention.

[0065] (9) The gate voltages of the fifth switching element and the third switching element are adjusted so that the gate voltage of the fifth switching element is higher than the gate voltage of the third switching element when it is OFF, or the gate voltages of the sixth switching element and the second switching element are adjusted so that the gate voltage of the sixth switching element is higher than the gate voltage of the second switching element when it is OFF. This provides the same effect as (8).

[0066] Although several embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit of the present invention. For example, configurations that arbitrarily combine the setting methods of the first to fourth embodiments are easily conceivable. These modifications are included in the scope of the invention described in the claims and their equivalents.

[0067] Vdc1 to Vdc2: DC power supplies, C1 to C2: smoothing capacitors (first and second capacitors), L: load, Q1 to Q6: semiconductor switching elements (first to sixth switching elements)

Claims

1. A power converter including first and second capacitors connected in series between the positive and negative poles of a DC power source, first to fourth switching elements further connected in series between the positive and negative poles of the DC power source, a fifth switching element connected between the connection point of the first and second switching elements and the connection point of the first and second capacitors, a sixth switching element connected between the connection point of the third and fourth switching elements and the connection point of the first and second capacitors, and connecting the connection point of the second and third switching elements to a load, wherein a first output state is a state in which the first, second and sixth switching elements are ON and the third, fourth and fifth switching elements are OFF, a second output state is a state in which the third, fourth and fifth switching elements are ON and the first, second and sixth switching elements are OFF, and a third output state is a state in which the second, third, fifth and sixth switching elements are ON and the first and fourth switching elements are OFF, a first dead-time state is a state in which the third and fifth switching elements are ON and the first, second, fourth and sixth switching elements are OFF, and a second dead-time state is a state in which the second and sixth switching elements are ON and the first, third, fourth and fifth switching elements are OFF; switching between the third output state and the first output state is via the second dead-time state, and switching between the third output state and the second output state is via the first dead-time state; and when transitioning between the third output state and the second dead-time state, the fifth switching element performs at least one of an operation of completing turn-on before or completing turn-off after the third switching element, or when transitioning between the third output state and the first dead-time state, the sixth switching element performs at least one of an operation of completing turn-on before or completing turn-off after the second switching element.

2. A power converter as claimed in claim 1, characterized in that, when transitioning from the third output state to the second dead-time state, the fifth switching element initiates turn-off with a delay of at least the time from when the gate voltage of the third switching element starts to fall until the main current starts to fall, or, when transitioning from the third output state to the first dead-time state, the sixth switching element initiates turn-off with a delay of at least the time from when the gate voltage of the second switching element starts to fall until the main current starts to fall.

3. A power converter as claimed in claim 1, characterized in that, when transitioning from the second dead time state to the third output state, the fifth switching element starts to turn on before the third switching element starts to turn on for at least the time from when the gate voltage of the fifth switching element starts to rise to when the main current starts to rise, or, when transitioning from the first dead time state to the third output state, the sixth switching element starts to turn on before the second switching element starts to turn on for at least the time from when the gate voltage of the sixth switching element starts to rise to when the main current starts to rise.

4. A power converter as claimed in claim 1, characterized in that the turn-on drive resistance of the fifth switching element is set lower than the turn-on drive resistance of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or the turn-on drive resistance of the sixth switching element is set lower than the turn-on drive resistance of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element.

5. A power converter as claimed in claim 1, characterized in that the turn-on gate current of the fifth switching element is set higher than the turn-on gate current of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or the turn-on gate current of the sixth switching element is set higher than the turn-on gate current of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element.

6. A power converter as claimed in claim 1, characterized in that the turn-off drive resistance of the fifth switching element is set higher than the turn-on drive resistance of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-off speed of the third switching element, or the turn-off drive resistance of the sixth switching element is set higher than the turn-off drive resistance of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element.

7. A power converter as claimed in claim 1, characterized in that the turn-off gate current of the fifth switching element is set lower than the turn-on gate current of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-on speed of the third switching element, or the turn-off gate current of the sixth switching element is set lower than the turn-off gate current of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element.

8. A power converter as claimed in claim 1, characterized in that the fifth switching element and the third switching element are selected so that the threshold voltage of the fifth switching element is lower than the threshold voltage of the third switching element, or the sixth switching element and the second switching element are selected so that the threshold voltage of the sixth switching element is lower than the threshold voltage of the second switching element.

9. A power converter as claimed in claim 1, characterized in that the OFF-time gate voltages of the fifth switching element and the third switching element are adjusted so that the OFF-time gate voltage of the fifth switching element is higher than the OFF-time gate voltage of the third switching element, or the OFF-time gate voltages of the sixth switching element and the second switching element are adjusted so that the OFF-time gate voltage of the sixth switching element is higher than the OFF-time gate voltage of the second switching element.

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