Semiconductor substrate, production method and production apparatus for same, and semiconductor device

Abstract

This semiconductor substrate comprises: a base substrate that includes, in the surface portion, a first crystal that is not a GaN-based semiconductor; a seed part that partially overlaps the base substrate; and a GaN-based semiconductor part located above the base substrate. The GaN-based semiconductor part has a base section that overlaps the seed part, and a wing section that does not overlap the seed part, that has a smaller threading dislocation density than the base section, and that contains a second crystal which is a GaN-based semiconductor. The first crystal and the second crystal are bonded via a boundary crystal layer that contains at least one main constituent element of the first crystal and at least one main constituent element of the second crystal.

Description

Semiconductor substrate, manufacturing method and manufacturing apparatus thereof, and semiconductor device

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] Patent Document 1 discloses a method for obtaining a semiconductor substrate by laterally growing a gallium nitride compound semiconductor on a substrate.

[0003] Japanese Patent Publication No. 2005-60227

[0004] This semiconductor substrate comprises a base substrate including a first crystal in a surface portion that is not a GaN-based semiconductor, a seed portion overlapping a portion of the base substrate, and a GaN-based semiconductor portion located above the base substrate, wherein the GaN-based semiconductor portion has a base portion overlapping the seed portion and wing portions that do not overlap the seed portion, have a lower threading dislocation density than the base portion, and include a second crystal that is a GaN-based semiconductor, and the first crystal in the surface portion and the second crystal in the wing portions are bonded via a boundary crystal layer that includes at least one of the main constituent elements of the first crystal and at least one of the main constituent elements of the second crystal.

[0005] 1 is a perspective view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 2 is a planar image showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 3 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment and an enlarged image thereof; FIG. 4 is a graph showing the results of EELS (Electron Energy Loss Spectroscopy) measurement; FIG. 5 is an image showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 6 is a perspective view showing a manufacturing method of a semiconductor substrate according to the present embodiment; FIG. 7 is a flowchart showing a manufacturing method of a semiconductor substrate according to the present embodiment; FIG. 8 is a block diagram showing an apparatus for manufacturing a semiconductor substrate according to the present embodiment; FIG. 9 is a perspective view showing the configuration of a semiconductor device according to the present embodiment; FIG. 10 is a flowchart showing a manufacturing method of a semiconductor device according to the present embodiment; FIG. 11 is a perspective view showing a manufacturing method of a semiconductor device according to the present embodiment; FIG. 12 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 13 is a plan view showing the configuration of a surface portion of a base substrate; FIG. 14 is a plan view showing the configuration of a surface portion of a base substrate; FIG. 15 is a cross-sectional view showing a manufacturing method of a semiconductor substrate according to Example 1; FIG. 16 is a perspective view showing a manufacturing method of a semiconductor substrate according to Example 2; FIG. 17 is a perspective view showing the configuration of a semiconductor substrate according to Example 2; FIG. 18 is a planar image of the surface portion; FIG. 19 is a cross-sectional image of the vicinity of the surface portion; FIG. 19 is an enlarged cross-sectional image of the vicinity of the surface portion and a corresponding element distribution map; FIG. 19 is a cross-sectional image of the vicinity of the surface portion and an enlarged image thereof; FIG. 20 is an element distribution map of the vicinity of a filled recess; 31 is a perspective view showing a method for manufacturing a semiconductor substrate according to Example 2. FIG. 32 is a perspective view showing a configuration of a semiconductor substrate according to Example 2. FIG. 33 is a plan view showing an example of a configuration of a surface portion. FIG. 34 is a plan view showing an example of a configuration of a surface portion. FIG. 35 is a plan view showing an example of a configuration of a surface portion. FIG. 36 is a plan view showing an example of a configuration of a semiconductor device according to Example 3. FIG. 37 is a cross-sectional view showing an example of a configuration of the semiconductor device of FIG. 28. FIG. 38 is a cross-sectional view showing an example of a configuration of the semiconductor device of FIG. 28. FIG. 39 is a plan view showing a configuration of a semiconductor device according to Example 4. FIG. 39 is a cross-sectional view of the semiconductor device of FIG. 34. FIG. 40 is a plan view showing a configuration of a semiconductor device according to Example 4.FIG. 42 is a plan view showing the configuration of a semiconductor device according to Example 4. FIG. 43 is a plan view showing the configuration of a semiconductor device according to Example 4. FIG. 44 is a cross-sectional view of the semiconductor device of FIG. 38. FIG. 45 is a plan view showing the configuration of a semiconductor device according to Example 4. FIG. 46 is a cross-sectional view of the semiconductor device of FIG. 42. FIG. 47 is a cross-sectional view showing the configuration of a semiconductor device according to Example 4. FIG. 48 is a cross-sectional view showing the configuration of a semiconductor device according to Example 5. FIG. 49 is a cross-sectional view showing the configuration of a semiconductor device according to Example 5.

[0006] FIG. 1 is a perspective view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 2 is a planar image showing the configuration of the semiconductor substrate according to this embodiment. FIG. 3A is a cross-sectional view and an enlarged image showing the configuration of the semiconductor substrate according to this embodiment. As shown in FIGS. 1, 2, and 3A, a semiconductor substrate 10 includes a base substrate 2 including a first crystal QF that is not a GaN-based semiconductor in a surface portion F, a seed portion S overlapping a portion of the base substrate 2, and a GaN-based semiconductor portion 8 located above the base substrate 2. The GaN-based semiconductor portion 8 has a base portion B overlapping the seed portion S and a wing portion W not overlapping the seed portion S, having a lower threading dislocation density than the base portion B, and including a second crystal QS that is a GaN-based semiconductor. The template substrate TS may include the base substrate 2 and the seed portion S. Note that in this specification, "A to B" means "greater than or equal to A and less than or equal to B."

[0007] In the semiconductor substrate 10, as shown in FIG. 3A , the first crystal QF (e.g., a silicon-based crystal) in the surface portion F and the second crystal QS in the wing portion W are bonded via a boundary crystal layer QL containing at least one of the main constituent elements of the first crystal QF and at least one of the main constituent elements of the second crystal QS. The thickness of the boundary crystal layer QL may be 0.1 nm to 2.0 nm. The surface portion F may have a growth-inhibited region (non-seed region) DA that does not overlap with the seed portion S. On the growth-inhibited region DA (including QF), vertical (c-axis direction) growth of the GaN-based semiconductor crystal is inhibited, and the wing portion W (including QS) is formed by lateral overgrowth (ELO).

[0008] In this way, the boundary crystal layer QL precisely bonds the surface portion F (first crystal QF) and the wing portion W (second crystal QS) of the base substrate 2, reducing energy loss, such as phonon scattering, at the heterojunction interface. Therefore, the semiconductor substrate 10 has a wing portion W with a low dislocation density, while exhibiting excellent properties, such as mechanical strength, heat resistance, thermal conductivity, optical properties, electrical properties, and magnetic properties. Therefore, semiconductor devices with excellent device characteristics can be formed on the semiconductor substrate 10. The semiconductor devices may be light-emitting elements such as LEDs and lasers, charge-control elements such as transistors, optical elements, electromagnetic wave control elements, MEMS, and the like. It is also possible for the semiconductor substrate 10 to not include the boundary crystal layer QL, but to directly bond the first crystal QF and the second crystal QS with high precision, thereby forming semiconductor devices with excellent device characteristics on the semiconductor substrate 10.

[0009] The first crystal QF may be silicon carbide, diamond, sapphire, or aluminum nitride. The second crystal QS may be GaN, AlGaN, AlGaInN, or InGaN. When the first crystal QF is SiC (silicon carbide crystal), the boundary crystal layer QL may contain at least one of Si or C. When the second crystal QS is GaN (gallium nitride crystal), the boundary crystal layer QL may contain at least Ga. When the second crystal QS is GaN (gallium nitride crystal), the boundary crystal layer QL may contain at least N. When the first crystal QF is SiC (silicon carbide crystal) and the second crystal QS is GaN (gallium nitride crystal), the boundary crystal layer QL may be SiGaN, SiGaC, or GaCN.

[0010] The boundary crystal layer QL may contain all of the main constituent elements of the second crystal QS. The boundary crystal layer QL may contain all of the main constituent elements of the first crystal QF. The boundary crystal layer QL may not contain amorphous. For example, when the first crystal QF is SiC (silicon carbide crystal), the boundary crystal layer QL may contain Si and C. For example, when the second crystal QS is GaN (gallium nitride crystal), the boundary crystal layer may contain Ga and N. When the first crystal QF is SiC (silicon carbide crystal) and the second crystal QS is GaN (gallium nitride crystal), the boundary crystal layer QL may be a SiGaCN layer. The boundary crystal layer QL may have a lattice mismatch.

[0011] The GaN-based semiconductor portion 8 contains a GaN-based semiconductor as a main component. A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples of GaN-based semiconductors include GaN, AlGaN, AlGaInN, and InGaN. GaN-based semiconductors may be doped or non-doped. A semiconductor substrate refers to a substrate containing a semiconductor. The base substrate 2 may contain a semiconductor (e.g., silicon carbide) or may not contain a semiconductor.

[0012] The a-axis direction of a GaN-based semiconductor is, for example, the <11-20> direction, and the m-axis direction is, for example, the <1-100> direction. The thickness direction of the GaN-based semiconductor portion 8 may be the c-axis direction of the GaN-based semiconductor (for example, the <0001> direction). In a hexagonal GaN-based semiconductor, on the c-plane (a plane perpendicular to the c-axis), the three directions of 0° and 180°, 60° and 240°, and 120° and 300° may be the a-axis directions, and the three directions of 30° and 210°, 90° and 270°, and 150° and 330° may be the m-axis directions. In FIG. 1 and other figures, the first direction X may be the a-axis direction (hereinafter sometimes referred to as the lateral direction), the second direction Y may be the m-axis direction, and the third direction Z may be the c-axis direction (thickness direction).

[0013] The GaN-based semiconductor portion 8 may be composed of a GaN-based semiconductor crystal (for example, a GaN crystal) grown by ELO (Epitaxial Lateral Overgrowth) starting from the seed portion S. The GaN-based semiconductor portion 8 may cover the top and side surfaces of the seed portion S. In the GaN-based semiconductor portion 8, the threading dislocation density of the wing portions W may be 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the threading dislocation density of the base portion B. The threading dislocation density of the wing portions W may be 5×10 ６ / cm ２ The width of the wing portion W in the lateral direction (first direction X) may be, for example, 15 μm or more, or 50 μm or more.

[0014] Two GaN-based semiconductor portions 8A and 8C may be located above the base substrate 2 and adjacent to each other in the first direction X with a gap GP between them. The GaN-based semiconductor portion 8 may include an edge E located above the growth inhibition region DA. The two GaN-based semiconductor portions 8A and 8C can be formed by stopping the growth of GaN-based semiconductor crystals growing by ELO in opposite directions on the growth inhibition region DA (by stopping the supply of raw materials) before they merge. Note that the two GaN-based semiconductor portions 8A and 8C may also be merged without the gap GP between them.

[0015] The first crystal QF may have a higher thermal conductivity than the second crystal QS. This allows for a semiconductor substrate 10 with high thermal conductivity (excellent heat dissipation), which can be used for laser applications, for example. For example, if the first crystal QF is silicon carbide and the second crystal QS is GaN, the thermal conductivity of the first crystal QF (4.9 W / cm K) is higher than the thermal conductivity of the second crystal QS (2.0 W / cm K).

[0016] The first crystal QF of the surface portion F may be silicon carbide, diamond, sapphire, or aluminum nitride. The base substrate 2 may be a silicon carbide wafer, a diamond wafer, a sapphire wafer, or an aluminum nitride wafer. The wafer may be a free-standing substrate cut from a bulk crystal. The first crystal QF of the surface portion F of the base substrate 2 may be SiC, the second crystal QS may be GaN, and the seed portion S may include AlN.

[0017] The seed portion S may include a nitride semiconductor. The seed portion S may be GaN, AlGaN, AlGaInN, or InGaN. The seed portion S may have a shape whose longitudinal direction is the m-axis direction (second direction Y) of the GaN-based semiconductor portion 8. The seed portion S may have a longitudinal island shape whose longitudinal direction is the m-axis direction of the GaN-based semiconductor portion 8. The seed portion S may be located on the base substrate 2. The seed portion S may be in contact with the base substrate 2. The seed portion S may be bonded to the base substrate 2. The seed portion S may be made of a material different from that of the GaN-based semiconductor portion 8.

[0018] The thickness of the boundary crystal layer QL may be smaller than the sum of the lattice constants in the c-axis direction of the first crystal QF and the lattice constants in the c-axis direction of the second crystal QS. The thickness of the boundary crystal layer QL may be 1.0 nm or less. The thickness of the boundary crystal layer QL may be measured from a HAADF-STEM image of a cross section including the boundary crystal layer QL.

[0019] The enlarged image (HAADF-STEM image) of FIG. 3A shows a case where the first crystal QF in the surface portion F is 4H—SiC (lattice constant in the c-axis direction: approximately 1.0 nm) and the second crystal QS in the wing portion W is GaN (lattice constant in the c-axis direction: approximately 0.5 nm). In this case, the 4H—SiC crystal (first crystal) of the base substrate 2 and the GaN crystal (second crystal) of the wing portion W are bonded at the atomic level. In the semiconductor substrate 10, the boundary crystal layer QL may be a mixed crystal layer (e.g., a SiGaCN layer) of the first and second crystals with a thickness of less than 1.0 nm, without including an amorphous layer. The boundary crystal layer QL (mixed crystal layer) may include Si (silicon atom)-N (nitrogen atom) covalent bonds. When the boundary crystal layer QL (mixed crystal layer) contains a Si (silicon atom)-N (nitrogen atom) covalent bond, for example, the Si-N covalent bond may be generated by partially replacing the Ga atoms in the Ga-N bond with Si atoms. According to this growth method, by laterally growing the second crystal QS on the first crystal QF, the first crystal QF and the second crystal QS are bonded at the interface while growing heterogeneous materials (hetero growth), and defects due to lattice mismatch are less likely to occur in the second crystal QS of the heterogeneous material formed on the first crystal QF. In the semiconductor substrate 10, defects due to lattice mismatch do not necessarily occur in the second crystal QS. The bond between the first crystal QF and the second crystal QS via the boundary crystal layer QL is achieved by growing the second crystal QS from a seed portion S under growth conditions that prevent the second crystal QS from growing on the first crystal QF, and then growing the second crystal QS under deposition conditions that cause lateral growth. This method allows for high-quality crystal growth on a heterogeneous substrate, and also allows for a heterogeneous interface in which the second crystal QS is bonded to the first crystal QF with high precision. This growth method achieves both unprecedented crystal quality and excellent thermal conductivity at the interface.

[0020] FIG. 3B is a graph showing the results of EELS (Electron Energy Loss Spectroscopy) measurement (when the first crystal QF is SiC). As shown in FIG. 3B , the boundary crystal layer QL may have a smaller peak energy value (peak loss energy value) in the EELS measurement compared to the SiC bulk. This is thought to be due to Si-N covalent bonds. Generally, if the upper surface of the base substrate and the GaN-based semiconductor crystal are not bonded with high precision at the atomic level, peaks are difficult to detect in the EELS measurement. In the semiconductor substrate 10, the upper surface of the base substrate 2 and the GaN-based semiconductor crystal are bonded with high precision at the atomic level, so peaks thought to be due to covalent bonds can be detected by the EELS measurement. Note that, depending on the material of the base substrate 2, contrary to the example of FIG. 3B , the crystal boundary layer QL may have a larger (higher) peak energy value in the EELS measurement than the bulk of the base substrate 2.

[0021] FIG. 3C (HAADF-STEM image) shows the case where the first crystal QF of the surface portion F is sapphire. In this case, the first crystal QF of the surface portion F (sapphire:Al ２ O ３ , a-axis lattice constant: approximately 0.5 nm, c-axis lattice constant: approximately 1.2 nm) and the second crystal QS (GaN) of the wing portion W are bonded via a boundary crystal layer QL having a thickness of 0.1 nm to 2.0 nm.

[0022] Fig. 4 is a perspective view showing a method for manufacturing a semiconductor substrate according to this embodiment. Fig. 5 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. As shown in Figs. 4 and 5 , this method for manufacturing a semiconductor substrate includes the steps of: preparing a template substrate TS including a base substrate 2 having a surface F containing a first crystal QF that is not a GaN-based semiconductor; and a seed portion S overlapping a portion of the base substrate 2; and forming, above the template substrate TS, a GaN-based semiconductor portion 8 having a base portion B overlapping the seed portion S and a wing portion W not overlapping the seed portion S, having a lower threading dislocation density than the base B, and including a second crystal QS that is a GaN-based semiconductor. The boundary crystal layer QL includes at least one of the main constituent elements of the first crystal QF and at least one of the main constituent elements of the second crystal QS, and bonds the first crystal QF and the second crystal QS.

[0023] Fig. 6 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M70 that performs step S70 in Fig. 5, an apparatus M80 that performs step S80 in Fig. 5, and a control device MC that controls the apparatuses M70 and M80.

[0024] 7 is a perspective view showing the configuration of a semiconductor device according to this embodiment. As shown in Fig. 7, the semiconductor device 20 includes a semiconductor substrate 10 and an upper layer portion UL including a functional layer 9. The upper layer portion UL may include at least one of an insulating film and an electrode.

[0025] FIG. 8 is a flowchart illustrating a method for manufacturing a semiconductor device according to this embodiment. FIG. 9 is a perspective view illustrating a method for manufacturing a semiconductor device according to this embodiment. As shown in FIGS. 8 and 9 , this method for manufacturing a semiconductor device includes a step S85 of preparing a semiconductor substrate 10 and a step S95 of forming an upper layer portion UL including a functional layer 9 on the semiconductor substrate 10. The GaN-based semiconductor portion 8 of the semiconductor substrate 10 and the functional layer 9 including a nitride semiconductor can also be continuously formed. In this case, the functional layer 9 does not grow on the growth inhibition region DA, so that the functional layer 9 can be individually (separately) formed without performing a post-process such as etching.

[0026] Fig. 10 is a perspective view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 11 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figs. 10 and 11 , base substrate 2 may include a main substrate 1 and an underlayer 4 located above main substrate 1 and including a surface portion F. Main substrate 1 may be a silicon wafer or a nitride semiconductor wafer (e.g., a GaN wafer or an AlN wafer). Underlayer 4 may be a silicon carbide (SiC) layer.

[0027] 12 to 14 are plan views showing the configuration of the surface portion of the base substrate. In the semiconductor substrate 10, as shown in FIG. 12, the surface portion F of the base substrate 2 includes a plurality of periodically arranged recesses U, and the wing portions W may have a shape that does not fill the plurality of recesses U. The recesses U may have a striped groove shape as shown in FIG. 12. When the recesses U have a striped groove shape, the groove width of the recesses U may be, for example, 10 nm to 1000 nm. The recesses U may also have a recessed shape as shown in FIG. 13. When the recesses U have a recessed shape, the diameter of the recesses U may be, for example, 10 nm to 1000 nm.

[0028] In the semiconductor substrate 10, as shown in FIG. 14 , the surface portion F of the base substrate 2 includes a plurality of periodically arranged protrusions T, and the wing portions W may have a shape that does not fill the gaps between the plurality of protrusions T. The protrusions T may have a striped ridge shape as shown in FIG. 14 . When the protrusions T have a striped ridge shape, the ridge width of the protrusions T may be, for example, 10 nm to 1000 nm. By providing the recesses U or the protrusions T, it is possible to reduce warping of the semiconductor substrate 10 or to impart specific properties (for example, optical properties, electrical properties, or magnetic properties) to the surface portion F.

[0029] The surface portion F may function as a metasurface. Specifically, the surface portion F may be a structured surface layer for manipulating the properties of electromagnetic waves, such as phase, polarization, and amplitude. When the surface portion F functions as a metasurface, the surface portion F may be applicable to a wide range of optical devices with subwavelength functionality and high efficiency, such as lenses, diffraction gratings, and polarizers. The surface portion F may also function as a photonic crystal. Specifically, the refractive index of the surface portion F may be periodically modulated on the order of the wavelength of light, allowing for control of light propagation, reflection, and the like.

[0030] Example 1 FIG. 15 is a cross-sectional view showing a semiconductor substrate manufacturing method according to Example 1. As shown in FIG. 15 , a planarly deposited seed material SZ may be patterned by a lift-off method using a resist RZ to form a seed portion S. Specifically, a resist RZ may be formed on the base substrate 2 in an area other than the area where the seed portion S is to be formed, and the planarly deposited seed material SZ may be patterned on the base substrate 2 and the resist RZ. The resist RZ may then be removed together with the seed material SZ formed on the resist RZ to form the seed portion S. The seed material SZ may also be planarly deposited by a sputtering method. Before forming the GaN-based semiconductor portion 8, the native oxide film i (e.g., silicon oxide) on the surface portion F may be removed using a carrier gas (e.g., hydrogen) in an MOCVD apparatus. Alternatively, a template substrate TS may be created by transferring a highly crystalline striped seed pattern formed on a growth substrate by a MOCVD method or the like to a base substrate 2 with high heat dissipation properties. Alternatively, the template substrate TS can be obtained by forming a planar film of a seed material SZ by MOCVD on the surface portion F on which the stripe-shaped grooves are formed, and then polishing and removing the seed material SZ outside the grooves by, for example, CMP. Alternatively, the seed portions S may be formed by forming a planar seed material SZ on the base substrate 2, forming a resist RZ on the seed material SZ in an area where the seed portions S are to be formed, and removing the seed material in areas other than the area where the seed portions S are to be formed by wet etching or the like.

[0031] In step S80, for example, the GaN-based semiconductor portion 8 may be a GaN layer, and a MOCVD apparatus may be used to grow gallium nitride crystal (8Q in FIG. 3) on the base substrate 2, which is a SiC wafer, by ELO. The seed portion S may be AlN (aluminum nitride). Examples of growth conditions include substrate temperature: 700°C to 1500°C (e.g., 1120°C), growth pressure: 10 to 120 kPa (e.g., 50 kPa), TMG (trimethylgallium) supply: 5 to 60 sccm (e.g., 22 sccm), and NH ３ Ammonia supply: 4 to 50 slm (e.g., 15 slm), and V / III: 500 to 15,000 (e.g., 900 to 6,000), which indicates the ratio of the supply rate of group V raw materials to the supply rate of group III raw materials, can be adopted. When wing portions W (including gallium nitride crystals QS) undergo lateral overgrowth (ELO) on a SiC wafer (including silicon carbide crystals QF), a boundary crystal layer QL is formed between the silicon carbide crystals QF and the gallium nitride crystals QS.

[0032] Example 2 FIG. 16A is a perspective view showing a method for manufacturing a semiconductor substrate according to Example 2. FIG. 16B is a perspective view showing the configuration of a semiconductor substrate according to Example 2. FIGS. 17 and 18 are planar images of the surface region. FIG. 19 is a cross-sectional image of the vicinity of the surface region. FIG. 20 is an enlarged cross-sectional image of the vicinity of the surface region and a corresponding element distribution map. FIG. 21 is a cross-sectional image of the vicinity of the surface region and an enlarged image thereof. FIG. 22 is an element distribution map of the vicinity of the filled recesses. Here, a group of stripe-shaped nanotrenches with a width (size in the a-axis direction) of approximately 20 nm, a depth (depth in the c-axis direction) of approximately 100 nm, and a pitch of approximately 200 nm were formed as multiple recesses U in the surface region F (4H—SiC crystal) of the base substrate 2. Wing portions W (GaN crystals) with a width (size in the a-axis direction) of approximately 20 μm were laterally grown above the group of stripe-shaped nanotrenches (multiple recesses U) using the ELO method. The seed portion S was an AlN layer with a width of approximately 10 μm and a thickness of approximately 200 nm. As shown in FIG. 16B, the stripe-shaped nano-trenches (plurality of recesses U) may be formed only in the region below the GaN-based semiconductor portion 8.

[0033] 16A and 17 to 20 show that the wing portions W grow laterally without filling the striped nanotrenches (multiple recesses U) (the recesses U remain voids), and that the shape of the striped nanotrenches (SiC micropattern) and, in turn, their characteristics are maintained in the semiconductor substrate 10. Specifically, elemental analysis of the recesses U (voids) by TEM-EDS confirmed that GaN crystals did not grow inside the recesses U during the ELO process after the SiC wafer was subjected to micropattern processing, and that no change in the shape of the micropattern due to mass transport occurred. The oxygen O detected in FIG. 20 was deposited during the TEM processing process.

[0034] The width of the recesses U (nanotrenches) may be 0.0005 to 0.3 times the width of the wing portions W, and the pitch width of the nanotrenches may be 0.002 to 0.5 times the width of the wing portions W. The width of the wing portions W may be 10 μm or more. The recesses U do not all need to be voids; as shown in FIG. 22 , some of the recesses U may be filled with gallium metal. In the ELO method, growth is performed by appropriately setting the ratio between vertical and lateral growth conditions. However, it has been found that the proportion of recesses that are filled can be reduced by using conditions in which the lateral growth conditions are strong and growth in the c-axis direction is largely suppressed (e.g., temperature: 1150°C to 1500°C, growth pressure: 40 to 70 kPa).

[0035] Fig. 23A is a perspective view showing a method for manufacturing a semiconductor substrate according to Example 2. Fig. 23B is a perspective view showing a configuration of a semiconductor substrate according to Example 2. In Fig. 16A, a group of striped nanotrenches is formed as the plurality of recesses U, but this is not limiting. As shown in Fig. 23A, a plurality of nano-sized recesses may be arranged two-dimensionally as the plurality of recesses U, and wing portions W may be grown laterally above the plurality of recesses.

[0036] In Example 1, GaN is subjected to ELO using an optically functional crystal (e.g., a SiC crystal with a fine pattern formed thereon) located on the surface portion F of the base substrate 2 (SiC wafer) as a growth suppression mask, and the optically functional crystal is bonded to the GaN with extremely high precision (at the atomic level, as shown in FIG. 21 , with no amorphous or recrystallized layer present at the GaN-SiC interface). This allows for the production of a semiconductor substrate 10 (optically functional substrate) with low interfacial thermal resistance at the GaN-SiC interface and minimal optical loss at the GaN-SiC interface. As shown in FIG. 23B , the nano-sized depressions (the recesses U) may be formed only in the region below the GaN-based semiconductor portion 8.

[0037] 24 to 27 are plan views showing configuration examples of the surface portion. The optically functional crystal of the surface portion F may be a photonic crystal including triangular depression-shaped recesses U as shown in Fig. 24, or a honeycomb-shaped topological photonics crystal as shown in Fig. 25. In addition, it may be a metalens crystal including columnar protrusions T as shown in Fig. 26, or a high-refractive-index diffraction grating crystal including ridge-shaped protrusions T as shown in Fig. 27.

[0038] Example 3 FIG. 28 is a plan view showing the configuration of a semiconductor device according to Example 3. FIGS. 29 and 30 are cross-sectional views of the semiconductor device of FIG. 28. As shown in FIGS. 28 to 30, the semiconductor device 20 includes a lower substrate US, a lower reflective layer RS ​​(e.g., a multilayer mirror film), a base substrate 2, a GaN-based semiconductor portion 8, and an upper layer portion UL, in this order. The upper layer portion UL includes a functional layer 9 including an active layer 9a, an insulating film ZF, a transparent conductive film TE, an anode EA, a cathode EC, and an upper reflective layer RU (e.g., a multilayer mirror film DBR). The base substrate 2 may be a SiC wafer, and the GaN-based semiconductor portion 8 may be GaN. The functional layer 9 may have a stacked structure including a GaN-based semiconductor, and the active layer 9a may have a quantum well structure. The transparent conductive film TE may be indium tin oxide (ITO).

[0039] The semiconductor device 20 may be a VCSEL (Vertical Cavity Surface Emitting Laser) in which laser light generated in the active layer 9a (light-emitting layer) and oscillated between the lower reflective layer RS ​​and the upper reflective layer RU is emitted upward (in the direction normal to the substrate) from the upper reflective layer RU. In the semiconductor device 20, the base substrate 2 and the GaN-based semiconductor portion 8 are bonded with high precision via the boundary crystal layer QL, resulting in high heat dissipation and reduced optical loss at the bonding interface. The lower substrate US may be a SiC wafer, and the lower reflective layer RS ​​may be a semiconductor DBR.

[0040] Example 4 FIG. 31 is a plan view showing the configuration of a semiconductor device according to Example 4. FIG. 32 is a cross-sectional view of the semiconductor device of FIG. 31. As shown in FIGS. 31 and 32, a semiconductor device 20 includes a base substrate 2, a GaN-based semiconductor portion 8, and an upper layer portion UL, in this order. The upper layer portion UL has a functional layer 9, a source portion ES, and a drain portion ED. The functional layer 9 includes a high-resistance layer 9h, a first nitride semiconductor layer 9n, a second nitride semiconductor layer 9s, and a buffer layer 9p. The high-resistance layer 9h may be a high-resistance GaN layer (shield layer) doped with C (carbon) or Fe (iron). The first nitride semiconductor layer 9n may be an n-type semiconductor layer (e.g., an n-GaN layer), and the second nitride semiconductor layer 9s may be an AlGaN layer (electron supply layer). The buffer layer 9p may be a p-type semiconductor layer (e.g., a p-GaN layer) that suppresses charge transfer from the gate portion EG. The first and second nitride semiconductor layers 9n and 9s are hetero-bonded, and a hetero-interface (a two-dimensional electron gas DG (channel)) is generated near the lower surface of the second nitride semiconductor layer 9s. The source portion ES and the drain portion ED may be in contact with the first nitride semiconductor layer 9n. The gate portion EG may be in contact with the second nitride semiconductor layer 9s via the buffer layer 9p. The seed portion S may have a shape in which the first direction X is the short-side direction and the second direction Y is the long-side direction. The first direction X may be the a-axis direction of the GaN-based semiconductor portion 8, and the second direction Y may be the m-axis direction of the GaN-based semiconductor portion 8. The gate portion EG may not overlap the seed portion S in a planar view. In a planar view, the source portion ES may be closer to the gate portion EG than the drain portion ED. The semiconductor device 20 may be a transistor 20 (for example, a HEMT) that uses a two-dimensional electron gas DG as a channel, and may function as a power transistor that controls a large current.

[0041] 33 is a plan view showing the configuration of a semiconductor device according to Example 4. As shown in Fig. 33 , a semiconductor device 30 may include a transistor 20 and a support substrate TK (circuit board, mounting substrate) electrically connected to the transistor 20. A pad PS of the support substrate TK may be connected to a source portion ES of the transistor 20, and a pad PD of the support substrate TK may be connected to a drain portion ED of the transistor 20.

[0042] Fig. 34 is a plan view showing the configuration of a semiconductor device according to Example 4. Fig. 35 is a cross-sectional view of the semiconductor device of Fig. 34. As shown in Figs. 34 and 35, the semiconductor device 20 includes first and second source electrodes E1 and E2 and a drain electrode DR extending in a second direction Y, the gate portion EG includes first and second gate electrodes G1 and G2 extending in the second direction Y, the seed portion S and the drain electrode DR overlap in a plan view, the first gate electrode G1 is located between the first source electrode E1 and the drain electrode DR in a plan view, and the second gate electrode G2 is located between the second source electrode E2 and the drain electrode DR in a plan view.

[0043] 36 is a plan view showing the configuration of a semiconductor device according to Example 4. As shown in Fig. 36, a semiconductor device 30 may include a transistor 20 and a support substrate TK (circuit board, mounting substrate) electrically connected to the transistor 20. Pads P1 and P2 of the support substrate TK may be connected to source electrodes E1 and E2 of the transistor 20, and a pad PD may be connected to a drain electrode DR of the transistor 20.

[0044] 37 is a plan view showing the configuration of a semiconductor device according to Example 4. As shown in Fig. 37 , the semiconductor device 20 may include first and second drain electrodes D1 and D2 and a source electrode SR extending in the second direction Y, and the gate portion EG may include first and second gate electrodes G1 and G2 extending in the second direction Y. The seed portion S and the source electrode SR may overlap in a plan view, the first gate electrode G1 may be located between the first drain electrode D1 and the source electrode SR in a plan view, and the second gate electrode G2 may be located between the second drain electrode D2 and the source electrode SR in a plan view.

[0045] FIG. 38 is a plan view showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 39 is a cross-sectional view of the semiconductor device of FIG. 38. As shown in FIGS. 38 and 39 , the source portion ES includes first and second source electrodes E1 and E2 extending in a first direction X, the drain portion ED includes a drain electrode DR extending in the first direction X, the gate portion EG includes first and second gate electrodes G1 and G2 extending in the first direction X, the seed portion S and the drain electrode DR intersect in a plan view, the first gate electrode G1 may be located between the first source electrode E1 and the drain electrode DR in a plan view, and the second gate electrode G2 may be located between the second source electrode E2 and the drain electrode DR in a plan view.

[0046] 40 to 41 are plan views showing the configuration of a semiconductor device according to Example 4. As shown in Figures 40 to 41, the source portion ES may include first and second source electrodes E1 and E2 extending in a first direction X, the drain portion ED may include a drain electrode DR extending in the first direction X, the gate portion EG may include first and second gate electrodes G1 and G2 extending in the first direction X, the seed portion S and the drain electrode DR may intersect in a plan view, the first gate electrode G1 may be located between the first source electrode E1 and the drain electrode DR in a plan view, and the second gate electrode G2 may be located between the second source electrode E2 and the drain electrode DR in a plan view.

[0047] FIG. 42 is a plan view showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 43 is a cross-sectional view of the semiconductor device of FIG. 42. As shown in FIGS. 42 and 43, the source portion ES includes first and second source electrodes E1 and E2 extending in a first direction X, the drain portion ED includes a drain electrode DR extending in the first direction X, and the gate portion EG includes first and second gate electrodes G1 and G2 extending in the first direction X. In a plan view, the seed portion S and the drain electrodes DR may intersect, the first gate electrode G1 may be located between the first source electrode E1 and the drain electrode DR, and the second gate electrode G2 may be located between the second source electrode E2 and the drain electrode DR. In an overlapping portion of the drain portion ED and the gate portion EG, the drain portion ED may be disposed on the gate portion EG via an insulating layer ZF.

[0048] 44 and 45 are cross-sectional views showing the configuration of a semiconductor device according to a fourth embodiment. As shown in FIG. 44 , a semiconductor device 20 may include a plurality of stacked bodies SB formed on a base substrate 2. Each stacked body SB may include a GaN-based semiconductor portion and an upper layer portion (including a functional layer). Furthermore, as shown in FIG. 45 , a semiconductor device 30 may include a plurality of stacked bodies SB formed on a base substrate 2 and a counter substrate TK electrically connected to the plurality of stacked bodies SB via a plurality of pads PX aligned in the first direction X.

[0049] Fifth Example

[0101] Figures 46 and 47 are cross-sectional views showing the configuration of a semiconductor device according to a fifth example. As shown in Figures 46 and 47, the semiconductor device 20 includes, in this order, a lower substrate US, a reflective layer RS ​​(e.g., a multilayer reflector film), an intermediate layer BL, a base substrate 2, a GaN-based semiconductor portion 8, and an upper layer portion UL. The upper layer portion UL includes a functional layer 9 including an active layer 9a, a contact layer 9c, an anode EA, and a cathode EC. The base substrate 2 may be a SiC wafer, and the GaN-based semiconductor portion 8 may be GaN. The functional layer 9 has a layered structure including GaN-based semiconductors, and the active layer 9a may have a quantum well structure. The intermediate layer BL and the contact layer 9c may be highly conductive AlGaN layers. The cathode EC may be provided on the intermediate layer BL (Figure 46) or on the back surface of the lower substrate US (Figure 47).

[0050] The surface portion F of the base substrate 2 may include, for example, a nano-sized fine pattern as shown in FIGS. 24 to 27 . The surface portion F may be a photonic crystal ( FIG. 24 ) that functions as a two-dimensional optical resonator. In the semiconductor device 20, laser light generated in the active layer 9 a (light-emitting layer) and oscillated between the reflecting layer RS ​​and the surface portion F may be emitted upward (in the direction normal to the substrate). In the semiconductor device 20, the base substrate 2 and the GaN-based semiconductor portion 8 are bonded with high precision via the boundary crystal layer QL, resulting in high heat dissipation and reduced optical loss at the bonding interface. The lower substrate US may be a SiC wafer, and the reflecting layer RS ​​may be a semiconductor DBR.

[0051] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0052] REFERENCE SIGNS LIST 1 Main substrate 2 Base substrate 4 Underlayer 8 GaN-based semiconductor portion 9 Functional layer 9n First nitride semiconductor layer (n-type semiconductor layer) 9s Second nitride semiconductor layer 10 Semiconductor substrate 20 Semiconductor device 30 Semiconductor device TS Template substrate QF First crystal (crystal that is not a GaN-based semiconductor) QS Second crystal QL Boundary crystal layer S Seed portion B Base portion F Surface portion W Wing portion DA Growth inhibition region UL Upper layer portion

Claims

1. A semiconductor substrate comprising: a base substrate including a first crystal in a surface portion which is not a GaN-based semiconductor; a seed portion overlapping a portion of the base substrate; and a GaN-based semiconductor portion located above the base substrate, wherein the GaN-based semiconductor portion has a base portion overlapping the seed portion and a wing portion not overlapping the seed portion, the wing portion including a second crystal which is a GaN-based semiconductor and has a lower threading dislocation density than the base portion, and wherein the first crystal in the surface portion and the second crystal in the wing portion are bonded via a boundary crystal layer which includes at least one of the main constituent elements of the first crystal and at least one of the main constituent elements of the second crystal.

2. The semiconductor wafer of claim 1, wherein the thickness of the boundary crystal layer is between 0.1 nm and 2.0 nm.

3. The semiconductor substrate according to claim 1, wherein said boundary crystal layer contains all of the main constituent elements of said second crystal.

4. The semiconductor substrate according to claim 3, wherein said boundary crystal layer contains all of the main constituent elements of said first crystal.

5. The semiconductor substrate according to any one of claims 1 to 4, wherein the boundary crystal layer does not contain an amorphous phase.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein the first crystal is SiC, and the boundary crystal layer is a SiGaCN layer.

7. A semiconductor substrate according to any one of claims 1 to 6, wherein the first crystal is SiC, the second crystal is GaN, and the boundary crystal layer has a smaller peak loss energy value in EELS measurement compared to SiC bulk.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein the first crystal has a higher thermal conductivity than the second crystal.

9. The semiconductor substrate according to any one of claims 1 to 8, wherein the first crystal is silicon carbide, diamond, sapphire or aluminum nitride.

10. The semiconductor substrate according to any one of claims 1 to 9, wherein the base substrate is a silicon carbide wafer, a diamond wafer, a sapphire wafer or an aluminum nitride wafer.

11. A semiconductor wafer according to any one of claims 1 to 10, wherein the thickness of the boundary crystal layer is smaller than the sum of the lattice constant in the c-axis direction of the first crystal and the lattice constant in the c-axis direction of the second crystal.

12. The semiconductor substrate according to claim 1, wherein the boundary crystal layer has a thickness of 1.0 nm or less.

13. The semiconductor substrate according to any one of claims 1 to 12, wherein the base substrate includes a main substrate and an underlayer located above the main substrate and including the surface portion.

14. The semiconductor substrate according to claim 13, wherein the main substrate is a silicon wafer or a nitride semiconductor wafer, and the underlayer is a silicon carbide layer.

15. A semiconductor substrate according to any one of claims 1 to 14, wherein the seed portion includes a nitride semiconductor and has an elongated shape with its longitudinal direction being the m-axis direction of the GaN-based semiconductor portion.

16. A semiconductor substrate according to any one of claims 1 to 15, wherein the surface portion has a plurality of recesses arranged periodically, and the wing portion has a shape that does not fill the plurality of recesses.

17. A semiconductor substrate according to any one of claims 1 to 16, wherein the surface portion has a plurality of periodically arranged protrusions, and the wing portion is shaped so as not to fill the gaps between the plurality of protrusions.

18. The semiconductor substrate according to claim 16, wherein the plurality of recesses are a plurality of grooves extending in the m-axis direction of the GaN-based semiconductor portion.

19. The semiconductor substrate according to claim 16, wherein the plurality of recesses are a plurality of depressions arranged two-dimensionally.

20. The semiconductor substrate according to any one of claims 1 to 19, wherein the first crystal is SiC, the second crystal is GaN, and the seed portion includes AlN.

21. The threading dislocation density of the wing portion is 5.0×10 ６ [pcs / cm ２ 21. The semiconductor substrate according to claim 1, wherein the thickness of the semiconductor substrate is less than or equal to 100 nm.

22. A method for manufacturing a semiconductor substrate, comprising the steps of: preparing a template substrate including a base substrate including a first crystal on a surface portion thereof that is not a GaN-based semiconductor, and a seed portion overlapping a portion of the base substrate; and forming, above the template substrate, a GaN-based semiconductor portion having a base portion overlapping the seed portion and wing portions not overlapping the seed portion, having a lower threading dislocation density than the base, and including a second crystal that is a GaN-based semiconductor, and a boundary crystal layer including at least one of the main constituent elements of the first crystal and at least one of the main constituent elements of the second crystal, and bonding the first crystal and the second crystal together.

23. The method for manufacturing a semiconductor substrate according to claim 22, wherein the thickness of the boundary crystal layer is 0.1 nm to 2.0 nm.

24. The method for producing a semiconductor substrate according to claim 22 or 23, further comprising removing the native oxide film on the surface before forming the GaN-based semiconductor portion.

25. The method for manufacturing a semiconductor substrate according to any one of claims 22 to 24, wherein the surface portion includes a plurality of periodically arranged recesses or a plurality of periodically arranged protrusions.

26. The method for producing a semiconductor substrate according to any one of claims 22 to 25, wherein the seed material formed into a planar film is patterned by a lift-off method to form the seed portion.

27. The method for producing a semiconductor substrate according to claim 26, wherein the seed material is formed into a planar film by a sputtering method.

28. A semiconductor substrate manufacturing apparatus which performs each of the steps recited in claim 22.

29. A semiconductor device comprising the semiconductor substrate according to any one of claims 1 to 21.

30. The semiconductor device according to claim 29, comprising: first and second nitride semiconductor layers above the GaN-based semiconductor portion; a source portion and a drain portion in contact with the first nitride semiconductor layer; and a gate portion located above the first and second nitride semiconductor layers.

31. The semiconductor device according to claim 30, wherein a two-dimensional electron gas is formed in the first nitride semiconductor layer, and the seed portion has a shape whose short side direction is the first direction and whose long side direction is the second direction.

32. The semiconductor device according to claim 31, wherein the gate portion does not overlap the seed portion in a plan view.

33. The semiconductor device of claim 31, wherein the source portion includes first and second source electrodes extending in the second direction, the drain portion includes a drain electrode extending in the second direction, the gate portion includes first and second gate electrodes extending in the second direction, the seed portion and the drain electrode overlap in a planar view, a first gate electrode is located between the first source electrode and the drain electrode in a planar view, and a second gate electrode is located between the second source electrode and the drain electrode in a planar view.

34. The semiconductor device of claim 31, wherein the source portion includes first and second source electrodes extending in the first direction, the drain portion includes a drain electrode extending in the first direction, the gate portion includes first and second gate electrodes extending in the first direction, the seed portion and the drain electrode intersect in a planar view, a first gate electrode is located between the first source electrode and the drain electrode in a planar view, and a second gate electrode is located between the second source electrode and the drain electrode in a planar view.

35. The semiconductor device according to claim 29, further comprising a light emitting layer above the GaN-based semiconductor portion.

36. The semiconductor device described in claim 35, wherein the surface portion of the base substrate has a plurality of periodically arranged recesses or a plurality of periodically arranged protrusions, and the wing portion has a shape that does not fill the plurality of recesses or does not fill the gaps between the plurality of protrusions.

37. The semiconductor device according to claim 35, further comprising a DBR below the GaN-based semiconductor portion.

38. The semiconductor device of claim 36, wherein the surface portion functions as an optical element.

39. The semiconductor device of claim 36, wherein the surface portion functions as a two-dimensional optical resonator.

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