Apparatus for generating electrical model and characteristic information of resistive random-access memory, and operation method therefor

Abstract

An operation method for an apparatus for generating an electrical model and characteristic information of a resistive random-access memory, according to an embodiment, comprises the steps of: obtaining first current-time characteristic information for the resistive random-access memory in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions; generating second current-time characteristic information for the resistive random-access memory by applying, to at least one compact model prepared in advance for the resistive random-access memory, the one or more input conditions and a plurality of model variables associated with the at least one compact model; determining whether a difference value between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value; and storing the plurality of model variables associated with the second current-time characteristic information as modeling data for the resistive random-access memory if the difference value is determined to be less than the threshold value.

Description

Device for generating electrical model and characteristic information of resistance change memory and operating method therefor

[0001] The present specification relates to a device for generating an electrical model and characteristic information of a resistance change memory and an operating method therefor, and more particularly, to a device for automatically generating an electrical model of a resistance change memory and characteristic information including at least one model variable, as well as calibrating the same, and an operating method therefor.

[0002] Resistive RAM (ReRAM) is a next-generation AI semiconductor that performs calculations within memory beyond the von Neumann system of the existing first-generation AI. It is expected to increase power efficiency and computational performance, and its importance is increasing as a technology that will enable the application of ICT technology.

[0003] Meanwhile, in a resistance change memory device composed of a metal-insulator-metal structure, various switching characteristics occur depending on the type of insulator or the interface state between the metal and the insulator, and therefore, various models exist that simulate the physical variables and device characteristics related to this.

[0004] The general model variable extraction method is presented only in a CPU-operated form that presents the maximum and minimum values ​​of the parameter range and then selects and applies only one or two algorithms within that range.

[0005] In addition, in the case of existing commercial technologies for deriving model variables related to resistive random access memory (ReRAM), the target is limited to diodes or transistors in terms of characteristic derivation and parameter extraction.

[0006] In particular, in the case of physics-based models of resistive random access memory (ReRAM), there are drawbacks such as the complexity of the formulas and the large number of model variables, which make it difficult to achieve accuracy and the time required for automatic calculation of model variables.

[0007] The purpose of this specification is to provide a device for generating characteristic information including an electrical model and model variables of a resistance change memory, and an operating method therefor.

[0008] An operating method for a device for generating electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention comprises the steps of: obtaining first current-time characteristic information for the resistance change memory in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions; generating second current-time characteristic information for the resistance change memory by applying one or more input conditions and a plurality of model variables associated with at least one compact model to at least one compact model provided in advance for the resistance change memory; determining whether a difference value between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value; and storing the plurality of model variables associated with the second current-time characteristic information as modeling data for the resistance change memory when the difference value is determined to be less than the threshold value.

[0009] According to the present embodiment, when it is determined that the difference value is greater than or equal to a threshold value, a step of updating multiple model variables using preset global and local optimizers may be further included.

[0010] According to one embodiment of the present invention, the step of updating a plurality of model variables includes: performing a first search procedure associated with a global optimizer using at least one first method pre-selected based on a derivative or a metaheuristic, wherein the plurality of model variables having preset initial values ​​are individually adjusted through the first search procedure; and, after the first search procedure is completed, performing a second search procedure associated with a local optimizer using at least one second method pre-selected with or without constraints and a function associated with the at least one second method, wherein the plurality of individually adjusted model variables are further adjusted through the second search procedure.

[0011] According to one embodiment of the present invention, the initial values ​​for each of the plurality of model variables are individually inferred according to a random selection algorithm.

[0012] A device for generating an electrical model and model information of a resistance change memory according to an embodiment of the present invention includes: an input information acquisition module for acquiring first current-time characteristic information for the resistance change memory in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions; a modeling module for generating second current-time characteristic information for the resistance change memory by applying one or more input conditions and a plurality of model variables associated with at least one compact model to at least one compact model provided in advance for the resistance change memory; a comparison module for determining whether a difference value between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value; and a calibration module for updating the plurality of model variables using preset global and local optimizers when it is determined that the difference value is greater than or equal to the threshold value.

[0013] According to the present embodiment, a device having a calibration function and an operating method therefor can be provided, which automatically generates characteristic information including an electrical model of a resistance change memory and at least one model variable.

[0014] Accordingly, subjective judgment and errors of human resources can be avoided, and the optimization and evaluation process of model variables can be automated to provide high accuracy and reliability, and efficiency can be improved through faster output time and shortened response time compared to existing manual methods.

[0015] Figure 1 is a conceptual diagram showing the structure of a SiOx-based resistive change memory.

[0016] Figure 2 is a conceptual diagram for explaining the state of a SiOx-based resistance change memory.

[0017] FIG. 3 is a circuit diagram related to a compact model of a resistance change memory according to an embodiment of the present invention.

[0018] FIG. 4 is a block diagram showing a device for generating an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0019] FIG. 5 is a flowchart showing an operating method for a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0020] FIG. 6 shows an exemplary image of a calibration corresponding to a measurement result by a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0021] FIG. 7 shows an exemplary image of a calibration corresponding to a simulation result by a device that generates characteristic information of a resistance change memory according to an embodiment of the present invention.

[0022] FIG. 8 is a block diagram showing the structure of hardware and software for a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0023] Fig. 9 is a block diagram showing the hardware configuration of a circuit simulation and optimization algorithm according to an embodiment of the present invention.

[0024] FIG. 10 shows an exemplary image for explaining an optimization process corresponding to a measurement result by a device for generating electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0025] FIG. 11 shows an exemplary image for explaining an optimization process corresponding to a simulation result by a device that generates electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0026] FIG. 12 is a block diagram illustrating a computing environment including a computing device suitable for use in exemplary embodiments.

[0027] The aforementioned features and the detailed description below are all exemplary, intended to aid in the description and understanding of this specification. That is, this specification is not limited to these embodiments and may be embodied in other forms. The following embodiments are merely examples intended to fully disclose this specification and are intended to convey the disclosure of this specification to those skilled in the art.

[0028] Therefore, when there are multiple ways to implement the components of this specification, it is necessary to make it clear that the specification can be implemented using any one of these methods or any method that is identical thereto.

[0029] When it is stated in this specification that a composition includes certain elements, or that a process includes certain steps, it is intended that other elements or other steps may be included.

[0030] In other words, the terms used in this specification are intended only to describe specific embodiments and are not intended to limit the concepts of this specification. Furthermore, the examples described to aid understanding of the invention also include complementary embodiments.

[0031] The terms used in this specification have the meanings commonly understood by those skilled in the art to which this specification pertains. In general, terms used should be interpreted consistently within the context of this specification.

[0032] Furthermore, terms used in this specification should not be interpreted in an overly idealistic or formal sense unless their meanings are clearly defined. Embodiments of this specification are described below with reference to the accompanying drawings.

[0033] Figure 1 is a conceptual diagram showing the structure of a SiOx-based resistive change memory.

[0034] Referring to FIG. 1, a SiOx-based resistive memory (100) corresponding to the resistive random access memory (ReRAM) mentioned in this specification can be implemented to include a plurality of regions (TE, RS, BE).

[0035] For example, a SiOx-based resistive memory (100) may include a first region corresponding to a top electrode (hereinafter referred to as 'TE'), a second region corresponding to electrically driven resistive switching (hereinafter referred to as 'RS') of an active material (e.g., metal oxide), and a third region corresponding to a bottom electrode (hereinafter referred to as 'BE').

[0036] For example, a second region corresponding to resistance switching (RS) arranged between two metal electrodes (TE, BE) can be implemented based on metal oxides, which are insulators.

[0037] Here, it will be understood that the second region corresponding to resistance switching (RS) can be deposited mainly by applying atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering, which can precisely control thickness and uniformity.

[0038] For example, when a voltage of a predetermined size is applied to the first region corresponding to the upper electrode (TE), the oxygen atoms of the metal oxide included in the second region corresponding to the resistance switching (RS) are ionized, and the resulting negative charge moves toward the upper electrode (TE).

[0039] Referring to FIG. 1, the SiOx-based resistance change memory (100) can be understood as an OxRAM (Metal Oxide ReRAM) in which filament formation begins inside an insulating layer containing an oxygen compound, and a plurality of oxygen vacancies are implemented to form a filament.

[0040] Figure 2 is a conceptual diagram for explaining the state of a SiOx-based resistance change memory.

[0041] Referring to FIGS. 1 and 2, the resistive random access memory (ReRAM) mentioned in this specification can be understood as a non-volatile memory element that stores and reads data by utilizing changes in electrical resistance.

[0042] For example, ReRAM (Resistive RAM) can express binary data based on a change in resistance state, with '1' corresponding to a low resistance state (hereinafter 'LRS') and '0' corresponding to a high resistance state (hereinafter 'HRS').

[0043] The X-axis of FIG. 2 may be related to the voltage applied to the resistive random access memory (ReRAM) element, and the Y-axis may be related to the current flowing in the resistive random access memory (ReRAM) element.

[0044] For example, the voltage corresponding to the first point (P1) of FIG. 2 may be defined as the SET voltage, and the voltage corresponding to the fourth point (P4) may be defined as the RESET voltage.

[0045] The section according to the origin (P0) and the first point (P1) of Fig. 2 can be defined as a pre-SET state. The pre-SET state of a resistive random access memory (ReRAM) may be a high resistance (HRS) state in which sufficient voltage is not applied to cause a process of moving or reducing ions within the device (i.e., ReRAM) to reconnect conductive filaments that were disconnected by RESET.

[0046] As shown in Fig. 2, it can be understood that as the voltage applied to the device increases before the SET of the resistance change memory (ReRAM), i.e. in the high resistance (HRS) state, the current also increases and its slope is low.

[0047] The section according to the first point (P1) and the second point (P2) of Fig. 2 can be defined as a state in which a voltage higher than the SET voltage is applied, thereby gradually or rapidly changing the device into a low resistance (LRS) state. In this section of a resistance change memory (ReRAM), the current can rapidly increase when the voltage is increased on the device compared to the section from the origin (P0) to the first point (P1).

[0048] The section corresponding to the second point (P2) and the third point (P3) of Fig. 2 may be a state in which the low resistance (LRS) state is maintained without any change in current depending on the applied voltage and no additional SET process occurs. This can be implemented by limiting the current flowing in the resistive random access memory (ReRAM), and may be introduced for the purpose of preventing excessive SET process from occurring and becoming stuck in the low resistance (LRS) state, but this is not essential.

[0049] The section corresponding to the third point (P3), the origin (P0), and the fourth point (P4) of Fig. 2 may be defined as a low resistance (LRS) state. This state may be a process in which a voltage sufficient to destroy the filament by applying a reverse voltage to the device and thereby reduce the conductivity of the device is not applied.

[0050] As shown in Fig. 2, it can be understood that as the voltage applied to the device decreases in the low resistance (LRS) state of the resistive random access memory (ReRAM), the current also decreases and the slope is steeper compared to the high resistance (HRS) state.

[0051] The section corresponding to the fourth point (P4) and the fifth point (P5) of Fig. 2 can be defined as a state in which a voltage higher than the RESET voltage is applied, causing the device to gradually or rapidly change to a high resistance (HRS) state. In this section of a resistive random access memory (ReRAM), even if the voltage applied to the device increases, the current may decrease.

[0052] The section between the fifth point (P5) and the origin (P0) of Fig. 2 can be defined as a state in which RESET is completed and high resistance (HRS) is maintained. This state may be a process in which no additional RESET is performed.

[0053] As shown in Fig. 2, it can be understood that as the voltage applied to the device decreases in the high resistance (HRS) state of the resistive random access memory (ReRAM), the current also decreases and the slope is gentler than in the low resistance (LRS) state.

[0054] For example, a sweep operation can be implemented to go through a series of voltage changes from the origin (P0) to points P1 to P5, including or only partially including points P1 to P5, over a predetermined period of time, and then return to the origin (P0).

[0055] For example, the shape of the voltage according to the length adjustment for a predetermined time during a sweep operation can be associated with one or more input conditions of at least one compact model provided in advance for the resistance change memory according to the present embodiment.

[0056] Meanwhile, the resistive random access memory (ReRAM) mentioned in this specification can be implemented with bipolar switching that switches states through voltages with different polarities.

[0057] FIGS. 3A and 3B are circuit diagrams related to a compact model of a resistance change memory according to an embodiment of the present invention.

[0058] Referring to FIG. 3A, a transport model equivalent circuit for a resistive random access memory (ReRAM) can be represented by two diodes and a contact resistor connected in series in a mutually reversed parallel manner, which simulate reverse and forward currents, respectively, between an upper electrode (e.g., TE in FIG. 1) and a lower electrode (e.g., BE in FIG. 1).

[0059] For example, the Transport Equation associated with the transport model equivalent circuit for resistive random access memory (ReRAM) can be defined as shown in the following mathematical expression 1.

[0060]

[0061] Specifically, I of mathematical expression 1 may correspond to the current flowing between node (D) and node (n) of the transport model equivalent circuit of FIG. 3A.

[0062] Here, λ in mathematical expression 1 is a state variable, which can be associated with the memory state (e.g., LRS, HRS) of the resistive random access memory (ReRAM) at a specific point in time.

[0063] The state variable (λ) mentioned in this specification may be changed to a value corresponding to '0' to '1' depending on the state (LRS, HRS) of the resistive random access memory (ReRAM), rather than a value set by a device (e.g., 400 in FIG. 4) that generates an electrical model and characteristic information of the resistive random access memory (ReRAM).

[0064] Meanwhile, the model variables mentioned in this specification can be understood as variables that can be set by a device (e.g., 400 in FIG. 4) that generates an electrical model and characteristic information of a resistive random access memory (ReRAM).

[0065] For reference, adjustments to multiple model variables can change the current level on the current-voltage curve (IV curve) such as in FIG. 6 or FIG. 7, the slope on the IV graph, the point associated with the SET voltage, the point associated with the RESET voltage, and the asymmetry of the IV graph.

[0066] In addition, β in mathematical expression 1 is a model variable and can be related to the voltage at both ends of a conductive filament (hereinafter referred to as 'CF') formed inside an insulating layer (e.g., RS in FIG. 1) of a resistive random access memory (ReRAM).

[0067] For example, in the above mathematical expression 1 is defined as in the following mathematical expression 2, and in the above mathematical expression 1 is defined as in the following mathematical formula 3, and in the above mathematical formula 1 can be defined as in the following mathematical formula 4.

[0068]

[0069] Here, I in mathematical expression 2 max and I min is a model variable that can be associated with the maximum and minimum current flowing through the resistive random access memory (ReRAM).

[0070]

[0071] Here, α in mathematical formula 3 max and α min As a model variable, it can be associated with the maximum conduction mechanism variable and the minimum conduction mechanism variable flowing through the resistive random access memory (ReRAM).

[0072]

[0073] Here, Rs in mathematical formula 4 max and Rs min is a model variable that can be associated with the maximum and minimum resistance of resistive random access memory (ReRAM).

[0074] Referring to FIG. 3B, a memory model equivalent circuit for a resistive random access memory (ReRAM) can be expressed in the form of a capacitor (C) that simulates a memory state (i.e., a λ state variable) in the memory equivalent circuit, a resistor (R) that controls the dynamic behavior of the SET / RESET state, and a power source (V) in which the resistance of the resistive random access memory changes.

[0075] For example, the Memory Equation associated with the memory model equivalent circuit for a resistive random access memory (ReRAM) may be as shown in Mathematical Formula 5 below.

[0076]

[0077] Specifically, τ in Equation 5 S and τ R The resistance between node (H) and node (A) of the memory model equivalent circuit of Figure 3B may correspond to the resistance between node (H) and ground.

[0078] For example, τ in the above mathematical expression 5 S (V) is defined as in the following mathematical expression 6, and τ in the above mathematical expression 5 R (V) can be defined as in the following mathematical expression 7.

[0079]

[0080] Here, τ in mathematical expression 6 0S is associated with the characteristic time of the SET state for the resistive random access memory (ReRAM), and V 0S can be associated with the characteristic voltage of the SET state for resistive random access memory (ReRAM).

[0081]

[0082] Here, τ in mathematical formula 7 0R is associated with the characteristic time of RESET state for resistive random access memory (ReRAM), and V 0Rmay be associated with the characteristic voltage of the RESET state for a resistive random access memory (ReRAM).

[0083] It will be understood that the model variables mentioned in the above mathematical expressions 1 to 7 are 11 in total, and that the characteristics of the resistive random access memory (ReRAM) device can be determined by adjusting the values ​​of the 11 model variables.

[0084] More specifically, the current level, asymmetry, slope, and points for the SET and RESET states of the current-voltage (IV) characteristics associated with a resistive random access memory (ReRAM) device can be determined by adjusting the values ​​of 11 model variables.

[0085] At least one compact model mentioned in the present specification may include a first equivalent model associated with a transport model equivalent circuit of a resistive random access memory (ReRAM) as in FIG. 3 and a second equivalent model associated with a memory model equivalent circuit of the resistive random access memory (ReRAM).

[0086] Furthermore, at least one compact model mentioned in the present specification may be implemented to further include a third equivalent model associated with an equivalent circuit of a switching dynamics model of a resistive random access memory (ReRAM).

[0087] Here, the Switching Dynamics Equation associated with the switching dynamics model equivalent circuit can be defined as in the following mathematical expressions 8 to 10.

[0088]

[0089]

[0090]

[0091] For reference, more details on the transport model equivalent circuit and memory model equivalent circuit mentioned in FIG. 3A and FIG. 3B can be found in the paper (Title: SPICE Simulation of RRAM-Based Cross-Point Arrays Using the Dynamic Memdiode Model) published in Frontiers in Physics (www.frontiersin.org) on ​​September 23, 2021, Volume 9, Article number (735021).

[0092] FIG. 4 is a block diagram showing a device for generating an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0093] Referring to FIGS. 1 to 4, a device (400) for generating an electrical model and characteristic information of a resistive random access memory (ReRAM) may include an input information acquisition module (410), a modeling module (420), a comparison module (430), and a calibration module (440).

[0094] The input information acquisition module (410) of FIG. 4 can acquire first current-time characteristic information for a resistive random access memory (ReRAM) in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions.

[0095] For example, the input information acquisition module (410) inputs a plurality of voltage-time input waveforms associated with one or more input conditions preset to a resistive random access memory (ReRAM) actual element, and in response thereto, first current-time characteristic information for the measured resistive random access memory (ReRAM) can be acquired.

[0096] As another example, the input information acquisition module (410) inputs a plurality of voltage-time input waveforms associated with one or more preset input conditions on a TCAD simulation model for a resistive random access memory (ReRAM) device, and in response thereto, first current-time characteristic information for the resistive random access memory (ReRAM) can be acquired.

[0097] In other words, the first current-time characteristic information may include information about a first point (P1) associated with the SET voltage, information about a second point (P2) associated with the RESET voltage, information about maximum and minimum values ​​of the current flowing through the device, and slope information on the IV graph.

[0098] The modeling module (420) of FIG. 4 can generate second current-time characteristic information for a resistive random access memory (ReRAM) by applying one or more input conditions and a plurality of model variables associated with at least one compact model (e.g., FIGS. 3A and 3B) prepared in advance for the ReRAM.

[0099] The multiple model variables mentioned in this specification may correspond to the 11 model variables described above.

[0100] For example, one or more input conditions may be in the form of a voltage over time sweeping through a series of voltage changes from the origin (P0) through each of the first point (P1) to the fifth point (P5), including (or excluding) a first point (P1) associated with a SET voltage, a fourth point (P4) associated with a RESET voltage, and so on, and then back to the origin (P0).

[0101] More specifically, one or more input conditions may be associated with an input voltage implemented in a predetermined shape (e.g., a triangle wave).

[0102] In this case, one or more of the input conditions may include a first time duration (TD1) corresponding to the time it takes to change from a starting voltage associated with the origin (P0) to a SET voltage associated with the first point (P1) and a voltage corresponding to the second point (P2') and then return to the starting voltage associated with the origin (P0).

[0103] Furthermore, one or more of the input conditions may include a second time duration (TD2) corresponding to the time it takes for the voltage to change from a starting voltage associated with the origin (P0) to a RESET voltage associated with the fifth point (P5) and a voltage corresponding to the fifth point (P5') and then return to the starting voltage associated with the origin (P0).

[0104] In summary, when one or more input conditions are associated with an input voltage implemented in a predetermined form (e.g., a triangle wave), the total time for a sweep operation for the voltage as in Fig. 2 may correspond to the sum of the first required time (TD1) and the second required time (TD2) or to the individual times.

[0105] Meanwhile, it will be understood that the shape of the current-voltage curve (IV curve) associated with the first current-time characteristic information may change depending on the adjustment of the total time length for the sweep operation.

[0106] There is no specific limitation on the shape of the input voltage in this specification, and the input voltage may be associated with a square wave, a sine wave, a step wave, or a random wave.

[0107] For example, the plurality of characteristic variables associated with at least one compact model may include at least one of the eleven model variables mentioned in Equations 1 to 7.

[0108] In this case, the initial values ​​of multiple model variables can be set based on a pre-existing initial value inference algorithm or on previously acquired first current-time characteristic information (e.g., point P1, point P4, maximum and minimum current values, slope on the IV graph).

[0109] Additionally, multiple model variables can be implemented to be continuously updated or optimized according to the process described later in this specification.

[0110] The comparison module (430) of FIG. 4 can determine whether the difference between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value.

[0111] For example, if the first current-time characteristic information is information measured from an actual resistive random access memory (ReRAM) element, a relative error can be obtained by calculating the difference (d) between the values ​​on the graph obtained through actual measurement and the graph obtained through an automated compact model, as shown in FIG. 6 described below, at each of multiple input voltages.

[0112] Here, the difference value between the first current-time characteristic information and the second current-time characteristic information may correspond to the average value of multiple relative errors obtained on multiple input voltages actually measured.

[0113] As another example, if the first current-time characteristic information is information simulated on a TCAD simulation model for a resistive random access memory (ReRAM) device, a relative error can be obtained by calculating the difference between the values ​​on the graph obtained through simulation and the graph obtained through an automatic compact model, as shown in FIG. 7 described below, at each of multiple input voltages.

[0114] Here, the difference value between the first current-time characteristic information and the second current-time characteristic information may correspond to the average value of multiple relative errors obtained on multiple input voltages that are virtually simulated.

[0115] The calibration module (440) of FIG. 4 can update multiple model variables using preset global and local optimizers when it is determined that the difference value is greater than or equal to a threshold value (e.g., 5%).

[0116] For example, global and local optimizers can be understood as being based on the computer code-based SciPy library.

[0117] Meanwhile, the process of updating multiple model variables using preset global and local optimizers is described in more detail with reference to FIG. 5 described below.

[0118] FIG. 5 is a flowchart showing an operating method for a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0119] Referring to FIGS. 1 to 5, in step S510, a device (400 of FIG. 4) for generating an electrical model and characteristic information of a resistive random access memory (ReRAM) according to an embodiment of the present invention can obtain first current-time characteristic information for the resistive random access memory (ReRAM) in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions.

[0120] In step S520, a device (400 in FIG. 4) for generating an electrical model and characteristic information of a resistive random access memory (ReRAM) according to an embodiment of the present invention can generate second current-time characteristic information for the resistive random access memory (ReRAM) by applying one or more input conditions and a plurality of model variables associated with at least one compact model prepared in advance for the resistive random access memory (ReRAM).

[0121] At step S530, the device (400 in FIG. 4) for generating an electrical model and characteristic information of a resistance change memory according to the present embodiment can determine whether a difference value between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value.

[0122] If the difference is determined to be less than the threshold value, the procedure may proceed to step S540. On the other hand, if the difference is determined to be greater than or equal to the threshold value, the procedure may proceed to step S550.

[0123] In step S540, a device (400 in FIG. 4) for generating an electrical model and characteristic information of a resistance change memory according to the present embodiment can be implemented to store a plurality of model variables associated with the second current-time characteristic information as modeling data for the resistance change memory.

[0124] At step S550, a device (400 in FIG. 4) for generating an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention can update multiple model variables using a global optimizer and a local optimizer according to Table 1 below.

[0125]

[0126] Referring to Table 1, with respect to the first search procedure associated with the global optimizer, at least one first method, either derivative-based or metaheuristic-based, may be selected.

[0127] In addition, a plurality of model variables (e.g., β, a) with preset initial values ​​are selected using at least one first method (e.g., Differential Evolution, Dual Annealing) related to the first search procedure. max , amin , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be adjusted individually.

[0128] In this case, the initial value can be understood as a value that is randomly changed within a preset range according to a random selection algorithm to prevent cases where the optimization process does not converge to a critical value even if it is repeated infinitely using a random initial value.

[0129] Referring to Table 1, with respect to the second search procedure associated with the local optimizer performed after the completion of the first search procedure, at least one second method, constrained or unconstrained, may be selected.

[0130] Additionally, multiple model variables (e.g., β, a) are selected using a function (e.g., minimize) associated with at least one second method (e.g., L-BFGS-B) associated with the second search procedure. max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be further adjusted.

[0131] For example, in order to improve the performance of the local optimizer, the 11 model variables mentioned above (e.g., β, a max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) Constrained methods and functions (e.g., minimize(L-BFGS-B)) can be applied to specify the range during each optimization process.

[0132] Multiple model variables for the second current-time characteristic information (e.g., 11 model variables; β, a max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) may be performed prior to the first execution step (i.e., the first search procedure).

[0133] Multiple model variables for the second current-time characteristic information (e.g., 11 model variables; β, a max , a min , Rs max , Rs min , Imax , I min , V 0S , V 0R , τ 0S , τ 0R ), the first search procedure and the second search procedure can be implemented to be repeated alternately a predetermined number of times.

[0134] FIG. 6 shows an exemplary image of a calibration corresponding to a measurement result by a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0135] Referring to FIG. 6, the results of automatic calibration for current-voltage hysteresis characteristics for each region of the SET / RESET start point, HRS (High Resistance State) and LRS (Low Resistance State) of the ReRAM by adjusting one or more model variables associated with the ReRAM, and the results of calibration by a skilled expert are shown.

[0136] It will be appreciated that the automated performance implemented by the device (e.g., 400 in FIG. 4) for generating electrical model and characteristic information of a resistive random access memory (ReRAM) according to the present embodiment can be implemented to have an accuracy level (11.36%) similar to that of a skilled expert (average relative error of 12.73%).

[0137] FIG. 7 shows an exemplary image of a calibration corresponding to a simulation result by a device that generates characteristic information of a resistance change memory according to an embodiment of the present invention.

[0138] Referring to Fig. 7, there may be errors due to the SET process of the actual device (i.e., ReRAM) partially exhibiting stochastic behavior, and calibration can be performed on the simulation result values ​​that control the stochastic behavior.

[0139] It will be understood that the automation performance implemented by the device (e.g., 400 in FIG. 4) for generating an electrical model and characteristic information of a resistive random access memory (ReRAM) according to the present embodiment exhibits excellent performance similar to the calibration accuracy of a skilled expert of 5.08% with a large error average (4.00%), and that it can predict the main characteristics of the resistive random access memory simulated in the simulation in the same manner.

[0140] For reference, details on the image acquisition process according to the calibration mentioned in FIGS. 6 and 7 can be found in the paper (Title: A Comprehensive Oxide-Based ReRAM TCAD Model with Experimental Verification) corresponding to 978-1-7281-8517-0 / 21 / $31.00 ⓒIEEE.

[0141] FIG. 8 is a block diagram showing the structure of hardware and software for a device that generates an electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0142] Referring to FIGS. 1 to 8, a plurality of software may be used to implement automation of the calculation of one or more model variables performed by a device (e.g., 400 of FIG. 4) that generates an electrical model and characteristic information of a resistive random access memory (ReRAM).

[0143] For example, it will be understood that Excel software can be utilized in the process of externally storing and providing input values ​​for target measurements or simulation values, the ngspice program can be utilized for simulation execution and storage, the scipy library can be utilized in the optimization process, and the jupyter notebook and matplot libraries can be utilized for visualizing and outputting results.

[0144] For example, it will be understood that the overall automated operation for a device that generates characteristic information of a resistive random access memory (ReRAM) can be implemented based on the Pycharm program environment of the python 3.8 environment.

[0145] Fig. 9 is a block diagram showing the hardware configuration of a circuit simulation and optimization algorithm according to an embodiment of the present invention.

[0146] Referring to FIGS. 1 to 9, the automation software installed in a device (e.g., 400 of FIG. 4) that generates an electrical model and characteristic information of a resistive random access memory (ReRAM) according to an embodiment of the present invention can be implemented in a PyCharm environment.

[0147] For example, the SciPy library can be utilized in the optimization process of a device (e.g., 400 in FIG. 4) that generates an electrical model and characteristic information of a resistive random access memory (ReRAM), and the ngspice program can be utilized in the simulation execution and model variable application process.

[0148] Meanwhile, it will be understood that the circuit simulation by the device (e.g., 400 in FIG. 4) that generates the electrical model and characteristic information of the resistive random access memory (ReRAM) according to the present embodiment can be driven based on CPU resources, and the optimization algorithm can be driven by utilizing both CPU and GPU resources as needed.

[0149] Accordingly, a device (e.g., 400 of FIG. 4) for generating an electrical model and characteristic information of a resistive random access memory (ReRAM) according to the present embodiment can be implemented to enable parallel computing of circuit simulation and optimization algorithms, as shown in FIG. 9.

[0150] FIG. 10 shows an exemplary image for explaining an optimization process corresponding to a measurement result by a device for generating electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0151] Referring to Fig. 10 and Table 1, for the application of the global function, multiple model variables (β, a) are selected according to a random selection algorithm. max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be preset as an example, as in the first row (Initial) of Table 2 below.

[0152]

[0153] Additionally, multiple model variables (β, a) with initial values ​​are set. max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be exemplarily tuned as in the second row (global optimizer) of Table 2.

[0154] Additionally, multiple model variables (β, a) that completed the first search procedure max , a min , Rs max , Rs min , Imax , I min , V 0S , V 0R , τ 0S , τ 0R ) can be exemplarily tuned as in the third row (local optimizer) of Table 2 above.

[0155] In addition, when the first search procedure and the second search procedure are performed alternately a predetermined number of times and the difference value is judged to be less than the threshold value, the final result of the optimization process using the actual measurement results is presented in the fourth row (Final) of Table 2 above, and multiple model variables (β, a) max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be expressed illustratively as in Fig. 10.

[0156] FIG. 11 shows an exemplary image for explaining an optimization process corresponding to a simulation result by a device that generates electrical model and characteristic information of a resistance change memory according to an embodiment of the present invention.

[0157] Referring to Fig. 11 and Table 1, for the application of the global function, multiple model variables (β, a) are selected according to a random selection algorithm. max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be preset as an example, as in the first row (Initial) of Table 3 below.

[0158]

[0159] Additionally, multiple model variables (β, a) with initial values ​​are set. max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be exemplarily tuned as in the second row (global optimizer) of Table 3.

[0160] Additionally, multiple model variables (β, a) that completed the first search procedure max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R) can be exemplarily tuned as in the third row (local optimizer) of Table 3 above.

[0161] In addition, when the first search procedure and the second search procedure are alternately performed a predetermined number of times and the difference value is judged to be less than the threshold value, the final result of the optimization process using the TCAD simulation results is presented in the fourth row (Final) of Table 3 above, with multiple model variables (β, a max , a min , Rs max , Rs min , I max , I min , V 0S , V 0R , τ 0S , τ 0R ) can be expressed illustratively as in Fig. 11.

[0162] FIG. 12 is a block diagram illustrating a computing environment including a computing device suitable for use in exemplary embodiments.

[0163] In the illustrated embodiment, each component may have different functions and capabilities other than those described below, and may include additional components other than those described below.

[0164] The illustrated computing environment (10) includes a computing device (12). In one embodiment, the computing device (12) may correspond to a device referred to herein (e.g., 400 of FIG. 4).

[0165] A computing device (12) includes at least one processor (14), a computer-readable storage medium (16), and a communication bus (18). The processor (14) may cause the computing device (12) to operate according to the exemplary embodiments mentioned above. For example, the processor (14) may execute one or more programs stored in the computer-readable storage medium (16). The one or more programs may include one or more computer-executable instructions, which, when executed by the processor (14), may be configured to cause the computing device (12) to perform operations according to the exemplary embodiments.

[0166] A computer-readable storage medium (16) is configured to store computer-executable instructions or program code, program data, and / or other suitable forms of information. A program (20) stored in the computer-readable storage medium (16) includes a set of instructions executable by the processor (14). In one embodiment, the computer-readable storage medium (16) may be a memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, any other form of storage medium that is accessible by the computing device (12) and capable of storing desired information, or a suitable combination thereof.

[0167] A communication bus (18) interconnects various other components of the computing device (12), including the processor (14) and computer-readable storage media (16).

[0168] The computing device (12) may also include one or more input / output interfaces (22) and one or more network communication interfaces (26) that provide interfaces for one or more input / output devices (24). The input / output interfaces (22) and the network communication interfaces (26) are connected to the communication bus (18). The input / output devices (24) may be connected to other components of the computing device (12) via the input / output interfaces (22). Exemplary input / output devices (24) may include input devices such as pointing devices (such as a mouse or trackpad), keyboards, touch input devices (such as a touchpad or touchscreen), voice or sound input devices, various types of sensor devices, and / or photographing devices, and / or output devices such as display devices, printers, speakers, and / or network cards. An exemplary input / output device (24) may be included within the computing device (12) as a component constituting the computing device (12), or may be connected to the data management server (110) as a separate device distinct from the computing device (12).

[0169] While the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics thereof. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0170] While the detailed description of this specification has described specific embodiments, various modifications are possible without departing from the scope of this specification. Therefore, the scope of this specification should not be limited to the above-described embodiments, but should be determined not only by the claims set forth below but also by equivalents of the claims of this invention.

Claims

1. In an operating method for a device that generates electrical model and characteristic information of a resistance change memory, A step of obtaining first current-time characteristic information for the resistance change memory in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions; A step of generating second current-time characteristic information for the resistance change memory by applying at least one input condition and a plurality of model variables associated with the at least one compact model to at least one compact model prepared in advance for the resistance change memory; A step of determining whether the difference value between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value; and A method comprising the step of storing the plurality of model variables associated with the second current-time characteristic information as modeling data for the resistance change memory when it is determined that the difference value is smaller than the threshold value.

2. In paragraph 1, A method further comprising the step of updating the plurality of model variables using preset global and local optimizers when it is determined that the above difference value is greater than or equal to the threshold value.

3. In paragraph 2, The step of updating the above multiple model variables is: A first search procedure associated with a global optimizer is performed using at least one first method selected in advance, which is derivative-based or metaheuristic-based, A step in which multiple model variables having preset initial values ​​are individually adjusted through the first search procedure; and After the above first search procedure is completed, a second search procedure associated with a local optimizer is performed using at least one pre-selected second method, which is constrained or unconstrained, and a function associated with the at least one second method, A method comprising a step of further adjusting the plurality of individually adjusted model variables through the second search procedure.

4. In paragraph 1, A method characterized in that the initial values ​​for each of the plurality of model variables are individually inferred according to a random selection algorithm.

5. An input information acquisition module for acquiring first current-time characteristic information for the resistance change memory in response to a plurality of voltage-time input waveforms associated with one or more preset input conditions; A modeling module that generates second current-time characteristic information for the resistance change memory by applying at least one input condition and a plurality of model variables associated with the at least one compact model prepared in advance for the resistance change memory; A comparison module that determines whether the difference between the first current-time characteristic information and the second current-time characteristic information is less than a preset threshold value; and A device for generating an electrical model and characteristic information of a resistance change memory, comprising a calibration module that updates the plurality of model variables using preset global and local optimizers when the difference value is determined to be greater than or equal to the threshold value.

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