Calibration of process, temperature, and supply compensated regulator

Abstract

A control value controllable voltage regulator is calibrated for variations in process, temperature, and input supply voltage using a reference clock and at least one process monitor oscillator. The process monitor oscillator is powered by the output of the voltage regulator. The frequency of the process monitor oscillator varies with the output voltage of the voltage regulator output. The frequency of the process monitor oscillator is compared with the frequency of a reference clock signal. Differences between the process monitor oscillator frequency and the reference clock frequency are fed back to generate control values to control the output voltage of the voltage regulator thereby completing a feedback loop that seeks to equalize the process monitor oscillator frequency and the reference clock frequency by varying the voltage regulator output voltage.

Description

CALIBRATION OF PROCESS, TEMPERATURE, AND SUPPLY COMPENSATEDREGULATORBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1 is a block diagram illustrating a voltage regulator calibration system.

[0002] Figure 2 is a block diagram illustrating a multiple transistor characteristic voltage regulator calibration system.

[0003] Figure 3 is a diagram illustrating a memory module.

[0004] Figure 4 is a flowchart illustrating a method of operating an integrated circuit.

[0005] Figure 5 is a flowchart illustrating a method of calibrating a voltage regulator circuit.

[0006] Figure 6 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0007] In an embodiment, a control value controllable voltage regulator is calibrated for variations in process, temperature, and input supply voltage using a reference clock and at least one process monitor oscillator. The process monitor oscillator is powered by the output of the voltage regulator. The frequency of the process monitor oscillator varies with the output voltage of the voltage regulator output. The frequency of the process monitor oscillator is compared with the frequency of a reference clock signal. Differences between the process monitor oscillator frequency and the reference clock frequency are fed back to generate control values to control the output voltage of the voltage regulator thereby completing a feedback loop that seeks to equalize the process monitor oscillator frequency and the reference clock frequency by varying the voltage regulator output voltage. When the feedback loop has substantially stabilized, the current control value being input to the voltage regulator is considered to be calibrating the voltage regulator across variations in process, temperature, and input supply voltage.

[0008] Multiple process monitor oscillators comprising different types of device characteristics (e.g., low threshold voltage, standard threshold voltage, high threshold voltage, input / output device, etc.) may each be calibrated and then one of the calibrating code words selected as the code word to be used by the voltage regulator during normal operation to power other circuitry.

[0009] Figure 1 is a block diagram illustrating a voltage regulator calibration system. In Figure 1, calibration system 100 comprises voltage regulator circuitry 110, process monitoroscillator circuitry 120, optional frequency scaling circuitry 112, frequency comparison feedback circuitry 114, and other circuitry 190. Voltage regulator circuitry 110 outputs a regulated voltage that may be used to power other circuitry 190 during (at least) normal operating conditionsr Voltage regulator circuitry 110 also powers process monitor oscillator circuitry 120. Process monitor oscillator circuitry 120 may comprise free-running oscillator circuitry having a clock signal output with a frequency that depends (or is based) on the power supply voltage provided to process monitor oscillator circuitry 120 by voltage regulator circuitry 110. The clock signal output by process monitor oscillator circuitry 120 is optionally provided to frequency scaling circuitry 112. Frequency scaling circuitry 112 may, in some embodiments, scale, divide, or otherwise reduce the frequency of the clock signal output by process monitor oscillator circuitry 120 before providing the scaled, divided, or otherwise reduced version of the clock signal output by process monitor oscillator circuitry 120 to frequency comparison feedback circuitry 114. If frequency scaling circuitry 112 is not present, the clock signal output by process monitor oscillator circuitry 120 is provided to frequency comparison feedback circuitry 114 without scaling, division, or other reduction in frequency.

[0010] Frequency comparison feedback circuitry 114 receives reference clock signal RCK and the clock signal output by process monitor oscillator circuitry 120. Based on a comparison of the frequency of RCK and the frequency of the clock signal output by process monitor oscillator circuitry 120 (or divided version thereof), frequency comparison feedback circuitry 114 adjusts the control value 115 that controls voltage regulator circuitry 110. In an embodiment, control value(s) 115 are, or comprise, a multi-bit digital value. Frequency comparison feedback circuitry 114 adjusts the control value 115 that controls voltage regulator circuitry 110 to reduce the difference between the frequency of RCK and the frequency of the clock signal output by process monitor oscillator circuitry 120 (or divided version thereof).

[0011] For example, if frequency comparison feedback circuitry 114 determines that the frequency of RCK is greater than the frequency of the clock signal output by process monitor oscillator circuitry 120 (or divided version thereof), frequency comparison feedback circuitry 114 may adjust control value 115 to increase the voltage being output by voltage regulator circuitry 110. Similarly, for example, if frequency comparison feedback circuitry 114 determines that the frequency of RCK is less than the frequency of the clock signal output by process monitor oscillator circuitry 120 (or divided version thereof), frequency comparisonfeedback circuitry 114 may adjust control value 115 to decrease the voltage being output by voltage regulator circuitry 110.

[0012] Thus, it should be understood that voltage regulator circuitry 110, process monitor oscillator circuitry 120, frequency scaling circuitry 112 (if present), and frequency comparison feedback circuitry 114 form a feedback loop. This feedback loop is configured to seek to equalize the frequency of the output of process monitor oscillator circuitry 120 with the frequency of reference clock signal RCK by adjusting control value 115 to control voltage regulator circuitry 110 in a manner that iteratively reduces the difference between the frequency of the output of process monitor oscillator circuitry 120 and the frequency of reference clock signal RCK. In some embodiments, once this feedback loop has stabilized, further adjustments to control value 115 are not made. In some embodiments, once this feedback loop has stabilized, further adjustments to control value 115 may be made to compensate for changes in operating conditions (e.g., temperature, power supply input voltage to voltage regulator circuitry 110, etc.)

[0013] Figure 2 is a block diagram illustrating a multiple transistor characteristic voltage regulator calibration system. In Figure 2, calibration system 200 comprises voltage regulator circuitry 210, process monitor oscillator circuit 221 (oscillator 1), process monitor oscillator circuit 222 (oscillator2), process monitor oscillator circuit 223 (oscillator3), optional frequency scaling circuitry 212, frequency comparison feedback circuitry 214, multiplexor circuitry (MUX) 230, control circuitry 240, and other circuitry 290. Voltage regulator circuitry 210 outputs a regulated voltage that may be used to power other circuitry 290 during (at least) normal operating conditions.

[0014] Voltage regulator circuitry 210 also powers multiple process monitor oscillator circuits 221-223. Process monitor oscillator circuits 221-223 may comprise free-running oscillator circuitry having respective clock signal outputs with respective frequencies that depend (or are based) on the power supply voltage provided by voltage regulator circuitry 210. The clock signals output by process monitor oscillator circuits 221-223 are input to multiplexor circuitry 230. In an embodiment, process monitor oscillator circuits 221-223 each comprise circuitry that includes (or consists of) different transistor types. For example, process monitor oscillator circuit 221 may comprise transistors with a low threshold voltage characteristic, process monitor oscillator circuit 221 may comprise transistors with a standard threshold voltage characteristic, process monitor oscillator circuit 221 may comprise transistors with a high threshold voltage characteristic, and so on for other transistor typessuch as, but not limited to, for example, ultra-low threshold voltage characteristic, and / or input / output (I / O) type transistors.

[0015] Control circuitry 240 controls multiplexor circuitry 230 to sequence through the selection of the output of two or more (or all) of the output signals produced by process monitor oscillator circuits 221-223. Control circuitry 240 controls multiplexor circuitry 230 to sequence through the selection of process monitor oscillator circuit 221-223 output signals so that a respective control value that equalizes the frequency of RCK and process monitor oscillator circuit 221-223 output signals maybe determined for each of the different types of transistors used by respective process monitor oscillator circuits 221-223.

[0016] Thus, as control circuitry 240 sequences through the selection of each of the output signals of process monitor oscillator circuits 221-223, the currently selected (by MUX230) output signal is optionally provided to frequency scaling circuitry 212. Frequency scaling circuitry 212 may, in some embodiments, scale, divide, or otherwise reduce the frequency of the selected clock signal output by process monitor oscillator circuitry 220 before providing the scaled, divided, or otherwise reduced version of the selected clock signal output to frequency comparison feedback circuitry 214. If frequency scaling circuitry 212 is not present, the selected clock signal is provided to frequency comparison feedback circuitry 214 without scaling, division, or other reduction in frequency.

[0017] Frequency comparison feedback circuitry 214 receives reference clock signal RCK and the selected clock signal. Based on a comparison of the frequency of RCK and the frequency of the selected clock signal (or divided version thereof), frequency comparison feedback circuitry 214 outputs control values 216 to control circuitry 240 which provides the control values 215 to control voltage regulator circuitry 210. Frequency comparison feedback circuitry 214 adjusts the control values 215-216 to, for each of the selected clock signals in the sequence, reduce the difference between the frequency of RCK and the frequency of the selected clock signal (or divided version thereof). In an embodiment, control value(s) 215-216 are, or comprise, a multi -bit digital value.

[0018] Thus, it should be understood that voltage regulator circuitry 210, respective selected process monitor oscillator circuit 221-223, frequency scaling circuitry 212 (if present), and frequency comparison feedback circuitry 214 form respective feedback loops. These feedback loops are each, in turn, configured to seek to equalize the frequency of the output of the selected process monitor oscillator circuit 221-223 with the frequency of reference clock signal RCK by adjusting control values 216 (which is relayed as control value 215) to control voltage regulator circuitry 210 in a manner that iteratively reduces thedifference between the frequency of the select output signal and the frequency of reference clock signal RCK. Once a respective feedback loop has stabilized, control circuitry 240 may store the value of the code word.

[0019] In an embodiment, after control values 215-216 corresponding to each of process monitor oscillator circuit 221-223 have been determined, control circuitry 240 may select one of the generated and stored code words to be used to set the output of voltage regulator circuitry 210 for the normal operation of other circuitry 290. For example, control circuitry 240 may select the stored control value 215-216 that produces the highest output voltage by voltage regulator circuitry 210. Other criteria for selecting the stored control value 215-216 for normal operation of other circuitry 290 are contemplated.

[0020] Figure 3 is a diagram illustrating a memory module. In Figure 3, memory module 300 comprises registering clock driver integrated circuit (IC) 310, first rank of memory devices 340-348, second rank of memory devices 350-358, DQ (data) buffers 360-368, DQ connections 370, and command / address (C / A) connections 380. Registering clock driver integrated circuit (IC) 310, memory devices 340-349, memory devices 350-358, and / or DQ buffers 360-369 may include circuitry that implements, functions like, and / or corresponds to, system 100, system 200, and / or their components.

[0021] In the configuration shown in Figure 3, C / A signals received at C / A connections 380 are buffered by IC 310 and sent to memory devices 350-358 via links. C / A signals received at C / A connections 380 are also buffered by IC 310 and sent to memory devices 340-348 via links. Thus, IC 310 necessarily includes command / address interfaces (not explicitly shown in Figure 3) configured to connect to memory devices 340-348 and memory devices 350-358. DQ signals received / sent by DQ buffers 360-368 from DQ connections 370 are sent / received to / from memory devices 350-358 via links. DQ signals received / sent by DQ buffers 360-368 from DQ connections 370 are sent / received to / from memory devices 340-348 via links 374. One or more reference clock signals (e.g., RCK) may be received by, and transmitted by, IC 310 to memory devices 340-348, memory devices 350-358, DQ buffers 360-368 via links. One or more control signals may be transmitted by IC 310 to DQ buffers 360-368 via links. In an embodiment, it should be understood that memory module 300 includes a memory interface (e.g., C / A connections 380 and DQ connections 370) configured to interface to a memory controller.

[0022] Figure 4 is a flowchart illustrating a method of operating an integrated circuit. One or more steps illustrated in Figure 4 may be performed by, for example, system 100, system 200, module 300, and / or their components. Based on a first output frequency of first-free running oscillator circuitry, a first voltage regulator control value is generated by minimizing a first difference between a reference signal frequency and a first indicator of the first output frequency, the first free-running oscillator circuitry receiving a first power supply voltage that is based on the first voltage regulator control value (402). For example, the feedback loop of system 200 may generate, while the output of process monitor oscillator circuit 221 is selected by control circuitry 240 and MUX 230, a first control value to control voltage regulator circuitry 210 such that the frequency difference between RCK and the output of process monitor oscillator circuit 221 is minimized.

[0023] Based on a second output frequency of second-free running oscillator circuitry, a second voltage regulator control value is generated by minimizing a second difference between a reference signal frequency and a second indicator of the second output frequency, the second free-running oscillator circuitry receiving a second power supply voltage that is based on the second voltage regulator control value (404). For example, the feedback loop of system 200 may generate, while the output of process monitor oscillator circuit 222 is selected by control circuitry 240 and MUX 230, a second control value to control voltage regulator circuitry 210 such that the frequency difference between RCK and the output of process monitor oscillator circuit 222 is minimized.

[0024] A one of the first voltage regulator control value and the second voltage regulator control value is selected as an operation condition control value to produce a power supply voltage for circuitry other than the first free-running oscillator circuitry and the second free- running oscillator circuitry (406). For example, control circuitry 240 may select a one of the first control value and the second control value to control voltage regulator circuitry 210 while voltage regulator circuitry 210 provides a power supply voltage to other circuitry 290 during normal operation.

[0025] Figure 5 is a flowchart illustrating a method of calibrating a voltage regulator circuit. One or more steps illustrated in Figure 5 may be performed by, for example, system 100, system 200, module 300, and / or their components. Power is provided to a plurality of free-running oscillators from a voltage regulator controlled by digital control values (502). For example, voltage regulator circuitry 210 may provide power to at least process monitor oscillator circuit 221 and process monitor oscillator circuit 221.

[0026] A plurality of digital control values are generated by respectively minimizing the difference between the respective output signals of the plurality of free-running oscillators and a reference clock (504). For example, control circuitry may generate respective digital control values associated with process monitor oscillator circuit 221 and process monitoroscillator circuit 222 by selectively including (e.g., by controlling MUX 230) each of process monitor oscillator circuit 221 and process monitor oscillator circuit 222 in the feedback loop of system 200 that minimizes the difference between the selected output signal and reference clock RCK. Based on the plurality of digital control values, a one of the plurality of digital control values is selected to be provided to the voltage regulator during normal operation to power other circuitry (506). For example, one of the digital control values associated with process monitor oscillator circuit 221 and process monitor oscillator circuit 222 may be selected by control circuitry 240 based on the value of one or more of the digital control values (e.g., maximum of the set, minimum, average, etc.) to control voltage regulator circuitry 210 during normal operation of other circuitry 290 while other circuitry 290 is powered by the output of voltage regulator circuitry 210.

[0027] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable fdes containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, system 200, module 300, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0028] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0029] Figure 6 is a block diagram illustrating one embodiment of a processing system 600 for including, processing, or generating, a representation of a circuit component 620. Processing system 600 includes one or more processors 602, a memory 604, and one or more communications devices 606. Processors 602, memory 604, and communications devices 606 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 608.

[0030] Processors 602 execute instructions of one or more processes 612 stored in a memory 604 to process and / or generate circuit component 620 responsive to user inputs 614 and parameters 616. Processes 612 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 620 includes data that describes all or portions of system 100, system 200, module 300, and their components, as shown in the Figures.

[0031] Representation 620 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 620 may be stored on storage media or communicated by carrier waves.

[0032] Data formats in which representation 620 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0033] User inputs 614 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 616 may include specifications and / or characteristics that are input to help define representation 620. For example, parameters 616 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0034] Memory 604 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 612, user inputs 614, parameters 616, and circuit component 620.

[0035] Communications devices 606 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 600 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 606 may transmit circuit component 620 to another system. Communications devices 606 may receive processes 612, user inputs 614, parameters 616, and / or circuit component620 and cause processes 612, user inputs 614, parameters 616, and / or circuit component 620 to be stored in memory 604.

[0036] Implementations discussed herein include, but are not limited to, the following examples:

[0037] Example 1: An integrated circuit, comprising: a voltage regulator circuitry having an output voltage and a voltage regulator control input that determines the output voltage of the voltage regulator circuitry; a first free-running oscillator to be powered by the output voltage from the voltage regulator circuitry to produce a first oscillator clock signal with a first oscillator frequency that is based on the output voltage; and feedback circuitry to adjust the voltage regulator control input to minimize a first difference between a reference signal frequency and a first indicator of the first oscillator frequency.

[0038] Example 2: The integrated circuit of example 1, wherein the first indicator of the first oscillator frequency is a first frequency scaled version of the first oscillator clock signal.

[0039] Example 3: The integrated circuit of example 1, wherein the voltage regulator control input receives a multi-bit digital value from the feedback circuitry.

[0040] Example 4: The integrated circuit of example 1, wherein the feedback circuitry comprises a frequency comparator.

[0041] Example 5: The integrated circuit of example 1, further comprising: a second free-running oscillator powered by the output voltage from the voltage regulator circuitry to produce a second oscillator clock signal with a second oscillator frequency that is based on the output voltage.

[0042] Example 6: The integrated circuit of example 5, wherein the feedback circuitry to further adjust the voltage regulator control input to minimize a second difference between the reference signal frequency and a second indicator of the second oscillator frequency.

[0043] Example 7: The integrated circuit of example 6, wherein a first relationship between the first oscillator frequency and the output voltage is based on a first type of transistor used by the first free-running oscillator and a second relationship between the second oscillator frequency and the output voltage is based on a second type of transistor used by the second free-running oscillator.

[0044] Example 8: The integrated circuit of example 7, wherein the first type of transistor and the second type of transistor have different threshold voltage characteristics.

[0045] Example 9: An integrated circuit, comprising: a voltage regulator circuitry having an output voltage and a voltage regulator control input that determines the output voltage of the voltage regulator circuitry; a plurality of free-running oscillators to be poweredby the output voltage from the voltage regulator circuitry to produce a plurality of oscillator clock signals with a respective plurality of oscillator frequencies that are based on the output voltage; and feedback circuitry to iteratively adjust the voltage regulator control input to minimize respective differences between a reference signal frequency and respective indicators of the respective plurality of oscillator frequencies to produce a respective plurality of voltage regulator input values.

[0046] Example 10: The integrated circuit of example 9, wherein the feedback circuitry is to select an operating voltage regulator control input value from the respective plurality of voltage regulator input values.

[0047] Example 11: The integrated circuit of example 10, wherein the feedback circuitry is to select a one of the respective plurality of voltage regulator input values that resulted in a greatest output voltage as the operating voltage regulator control input value.

[0048] Example 12: The integrated circuit of example 9, wherein respective indicators of the plurality of the respective oscillator frequencies are frequency scaled versions of the respective plurality of oscillator frequencies.

[0049] Example 13: The integrated circuit of example 9, wherein the voltage regulator control input receives a multi-bit digital value from the feedback circuitry.

[0050] Example 14: The integrated circuit of example 9, wherein the feedback circuitry comprises a frequency comparator.

[0051] Example 15: The integrated circuit of example 9, wherein respective relationships between the respective plurality of oscillator frequencies and the output voltage is based on a respective plurality of types of transistors used by the plurality of free-running oscillators.

[0052] Example 16: The integrated circuit of example 15, wherein at least two of the respective plurality of types of transistors have different threshold voltage characteristics.

[0053] Example 17: The integrated circuit of example 16, wherein at least one of the respective plurality of types of transistors are associated with input / output (I / O) type circuitry.

[0054] Example 18: A method, comprising: generating, based on a first output frequency of first free-running oscillator circuitry, a first voltage regulator control value by minimizing a first difference between a reference signal frequency and a first indicator of the first output frequency, the first free-running oscillator circuitry receiving a first power supply voltage that is based on the first voltage regulator control value; generating, based on a second output frequency of second free-running oscillator circuitry, a second voltage regulator control value by minimizing a second difference between the reference signalfrequency and a second indicator of the second output frequency, the second free-running oscillator circuitry receiving a second power supply voltage that is based on the second voltage regulator control value; and selecting a one of the first voltage regulator control value and the second voltage regulator control value as an operating condition control value to produce a power supply voltage for circuitry other than the first free-running oscillator circuitry and the second free-running oscillator circuitry.

[0055] Example 19: The method of example 18, wherein the first free-running oscillator circuitry and the second free-running oscillator circuitry comprise transistors with different threshold voltage characteristics.

[0056] Example 20: The method of example 18, wherein the one of the first voltage regulator control value and the second voltage regulator control value selected as an operating condition control value produces a greater power supply voltage for circuitry other than the first free-running oscillator circuitry and the second free-running oscillator circuitry.

[0057] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit, comprising: a voltage regulator circuitry having an output voltage and a voltage regulator control input that determines the output voltage of the voltage regulator circuitry; a first free-running oscillator to be powered by the output voltage from the voltage regulator circuitry to produce a first oscillator clock signal with a first oscillator frequency that is based on the output voltage; and feedback circuitry to adjust the voltage regulator control input to minimize a first difference between a reference signal frequency and a first indicator of the first oscillator frequency.

2. The integrated circuit of claim 1, wherein the first indicator of the first oscillator frequency is a first frequency scaled version of the first oscillator clock signal.

3. The integrated circuit of claim 1, wherein the voltage regulator control input receives a multi-bit digital value from the feedback circuitry.

4. The integrated circuit of claim 1, wherein the feedback circuitry comprises a frequency comparator.

5. The integrated circuit of claim 1, further comprising: a second free-running oscillator powered by the output voltage from the voltage regulator circuitry to produce a second oscillator clock signal with a second oscillator frequency that is based on the output voltage.

6. The integrated circuit of claim 5, wherein the feedback circuitry to further adjust the voltage regulator control input to minimize a second difference between the reference signal frequency and a second indicator of the second oscillator frequency.

7. The integrated circuit of claim 6, wherein a first relationship between the first oscillator frequency and the output voltage is based on a first type of transistor used by the first free- running oscillator and a second relationship between the second oscillator frequency and theoutput voltage is based on a second type of transistor used by the second free-running oscillator.

8. The integrated circuit of claim 7, wherein the first type of transistor and the second type of transistor have different threshold voltage characteristics.

9. An integrated circuit, comprising: a voltage regulator circuitry having an output voltage and a voltage regulator control input that determines the output voltage of the voltage regulator circuitry; a plurality of free-running oscillators to be powered by the output voltage from the voltage regulator circuitry to produce a plurality of oscillator clock signals with a respective plurality of oscillator frequencies that are based on the output voltage; and feedback circuitry to iteratively adjust the voltage regulator control input to minimize respective differences between a reference signal frequency and respective indicators of the respective plurality of oscillator frequencies to produce a respective plurality of voltage regulator input values.

10. The integrated circuit of claim 9, wherein the feedback circuitry is to select an operating voltage regulator control input value from the respective plurality of voltage regulator input values.

11. The integrated circuit of claim 10, wherein the feedback circuitry is to select a one of the respective plurality of voltage regulator input values that resulted in a greatest output voltage as the operating voltage regulator control input value.

12. The integrated circuit of claim 9, wherein respective indicators of the plurality of the respective oscillator frequencies are frequency scaled versions of the respective plurality of oscillator frequencies.

13. The integrated circuit of claim 9, wherein the voltage regulator control input receives a multi-bit digital value from the feedback circuitry.

14. The integrated circuit of claim 9, wherein the feedback circuitry comprises a frequency comparator.

15. The integrated circuit of claim 9, wherein respective relationships between the respective plurality of oscillator frequencies and the output voltage is based on a respective plurality of types of transistors used by the plurality of free-running oscillators.

16. The integrated circuit of claim 15, wherein at least two of the respective plurality of types of transistors have different threshold voltage characteristics.

17. The integrated circuit of claim 16, wherein at least one of the respective plurality of types of transistors are associated with input / output (I / O) type circuitry.

18. A method, comprising: generating, based on a first output frequency of first free-running oscillator circuitry, a first voltage regulator control value by minimizing a first difference between a reference signal frequency and a first indicator of the first output frequency, the first free-running oscillator circuitry receiving a first power supply voltage that is based on the first voltage regulator control value; generating, based on a second output frequency of second free-running oscillator circuitry, a second voltage regulator control value by minimizing a second difference between the reference signal frequency and a second indicator of the second output frequency, the second free-running oscillator circuitry receiving a second power supply voltage that is based on the second voltage regulator control value; and selecting a one of the first voltage regulator control value and the second voltage regulator control value as an operating condition control value to produce a power supply voltage for circuitry other than the first free-running oscillator circuitry and the second free-running oscillator circuitry.

19. The method of claim 18, wherein the first free-running oscillator circuitry and the second free-running oscillator circuitry comprise transistors with different threshold voltage characteristics.

20. The method of claim 18, wherein the one of the first voltage regulator control value and the second voltage regulator control value selected as an operating condition control value produces a greater power supply voltage for circuitry other than the first free-running oscillator circuitry and the second free-running oscillator circuitry.

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