Switching arrangement for bidirectional amplification

Abstract

Methods and devices enabling bidirectional utilization of amplifiers are disclosed. The described devices employ switching arrangements which facilitate the use of a single amplifier for two distinct modes of operation. Tradeoffs between the cost / dimensions and the performance parameters including insertion loss and isolation are also presented through various examples.

Description

SWITCHING ARRANGEMENT FOR BIDIRECTIONAL AMPLIFICATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 603,317 filed on November 28, 2023, for “Switching Arrangement For Bidirectional Amplification”, the content of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure is related to switching arrangements that enable the bidirectional use of amplifiers.BACKGROUND

[0003] 5G beamforming transceivers require bidirectional amplification (BIDI) to compensate for inherent losses. A typical beamforming transceiver consists of four vertical and four horizontal channels, with the input signal split into each path via a 4-way power splitter. Each channel contains phase shifters and step attenuators that introduce losses in both transmission and reception directions. BIDI amplifiers placed between the power splitter and channels help offset these losses by providing amplification in both directions.

[0004] Conventional BIDI implementations utilize separate transmit (TX) and receive (RX) amplifiers selected via single-pole double-throw (SPDT) switches at the input and output. While the SPDT switches are fast, the settling times of turning the TX and RX amplifiers on and off limit the switching speed from TX to RX and vice versa. Using two separate amplifiers also increases die size and cost.

[0005] In view of the above, solutions to reduce the die size / cost, and improving the overall transceiver performance including switching times are needed.SUMMARY

[0006] The described methods and devices address the above-mentioned issues and challenges. The disclosed devices utilize a single amplifier and a switching scheme that allows bidirectional functionality of the single amplifier. Moreover, these ideas could be used to convert non-reciprocal blocks into reciprocal blocks.

[0007] According to a first aspect of the present disclosure, a radio frequency (RF) circuital arrangement switchable between a forward mode and a reverse mode is provided, comprising: a forward mode signal transmission arrangement comprising switchable input side components configured to route a forward side signal from an amplifier input side of the RF circuital arrangement to an input of an amplifier, and switchable output side components configured to route the forward side signal, once amplified, from the output of the amplifier to an amplifier output side of the RF circuital arrangement; and a reverse mode signal transmission arrangement comprising switchable input side components configured to route a reverse side signal from the amplifier output side of the RF circuital arrangement to the input of the amplifier, and switchable output side components configured to route the reverse side signal, once amplified, from the output of the amplifier to the amplifier input side of the RF circuital arrangement.

[0008] According to a second aspect of the present disclosure, an amplification circuit is provided, comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: a) each of the first and the second set of elements comprises: a. l) a first and a second transistor arranged in a series configuration, source terminals of the first and the second transistor being tied together; a.2) a third and a fourth transistor arranged in a series configuration, source terminals of the first and the second transistor being tied together; a.3) a first and a second isolation transistor, the first isolation transistor being connected to the source terminal of the third and fourth transistor, and the second isolation transistor being connected to the source terminals of the first and the second transistors; a.4) a first, and a second inductors; b) the first node is coupled to drainterminal of the first and the third transistors of the first set of elements via the first inductor of the first set of elements; c) drain-terminals of the second and the fourth transistors of the first set of elements are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to drain-terminals of the second and the fourth transistors of the second set of elements via the second inductor of the second set ofelements; e) the second node is coupled to drain-terminals of the first and the third transistors of the second set of elements via the first inductor of the second set of elements; f) source terminals of the third transistor of the first set of elements and the fourth transistor of the second set of elements are tied together, and g) source terminals of the fourth transistor of the first set of elements and the third transistor of the second set of elements are tied together.

[0009] According to a third aspect of the present disclosure, an amplification circuit is provided, comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: a) each of the first and the second set of elements comprises: a.1) a first, a second, and a third transistor; a.2) a first, a second, and a third inductors; a.3) an isolation transistor connected to the source terminal of the third transistor; b) the first node is coupled to a source terminal of the first transistor and to a drain-terminal of the second transistor of the first set of elements via the first inductor of the first set of elements; c) drain-terminals of the first and the third transistors are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to drain-terminals of the first and the third transistors of the second set of elements via the second inductor of the second set of elements; e) the second node is coupled to a source terminal of the first transistor and to a drain-terminal of the second transistor of the second set of elements via the first inductor of the second set of elements; f) source terminals of the second transistor of the first set of elements and the third transistor of the second set of elements are tied together, and g) source terminals of the third transistor of the first set of elements and the second transistor of the second set of elements are tied together.

[0010] According to a fourth aspect of the present disclosure, an amplification circuit is provided, comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: al) the first set of elements comprises: a.11) a first, a second, and a third transistor; a.12) a first, a second, a third, a fourth, and a fifth inductors; a2) the second set of elements comprises: a.21) a transistor; a.22) a first, a second, and a third inductor; b) the first node is coupled to a source terminal of the first transistor and to a drain-terminal of the second transistor of the first set of elements via the first inductor of the first set of elements; c) drain-terminals of the first and the third transistors are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to a drain-terminal of the transistor of the second set of elements via the second inductor of the second set of elements; e) the secondnode is coupled to a source terminal of the transistor of the second set of elements via the first inductor of the second set of elements; f) a source terminal of the second transistor of the first set of elements is connected to the first inductor of the second set of elements, and g) a source terminals of the third transistor of the first set of elements is connected to the first inductor of the second set of elements.

[0011] Further aspects of the disclosure are provided in the description, drawings and claims of the present application.DESCRIPTION OF THE DRAWINGS

[0012] Fig. 1 A shows a circuit with different modes of operation.

[0013] Figs. 1B-1C, 2A-2B, and 3A-3B show exemplary amplification circuits according to embodiments of the present disclosure.

[0014] Figs. 4A-4D show exemplary charts illustrating the insertion loss and isolation performances of the amplification circuits according to the embodiments of the present disclosure.DETAILED DESCRIPTION

[0015] Fig. 1A shows a circuit (100A) including an antenna element (ANT), a first amplifier (Apl), a second amplifier (Ap2), a third amplifier (Ap3), a switching circuitry (SWC), a receive circuitry block (Rx), and a transmit circuitry block (Tx). As shown, depending on the mode of operation, the input and / or output of various elements in the circuit can be selectively interconnected to one another.

[0016] Circuit (100A) may need to operate in various modes depending on the particular application. In certain modes of operation, the transmit and receive signals for the circuit may be required to propagate along alternative signal paths. As an example, in a first mode of operation (e.g., transmit mode), the output of the second amplifier (Ap2) is coupled to the input of the third amplifier (Ap3) by switching circuitry (SWC). In this mode of operation, the transmit circuitry block (Tx) is coupled to the input of the second amplifier (Ap2) by the switching circuitry (SWC). Moreover, in this mode, the antenna element (ANT) is coupled to the output of the third amplifier (Ap3).

[0017] As a further example, in a second mode of operation (e.g. , receive mode), the output of the first amplifier (Apl) is coupled to the input of the second amplifier (Ap2) by the switching circuitry (SWC), and the output of the second amplifier (Ap2) is coupled to the receive circuitry block (Rx) by the switching circuitry (SWC). Moreover, in this mode, the antenna element (ANT) is coupled to the input of the first amplifier (Apl).

[0018] In some circuits the first amplifier (Apl) may be a low noise amplifier and the third amplifier (Ap3) may be a power amplifier.

[0019] As can be noticed, three amplifiers are implemented to accommodate various modes of operations required by circuit (100A). Using separate amplifiers can increase the die size and cost. In what follows, various embodiments according to the present disclosure, addressing such issues are described in detail.

[0020] Fig. IB shows an exemplary amplification circuit (100B) according to an embodiment of the present disclosure. The amplification circuit (100B) comprises an amplifier (Al), and a switching arrangement (101), the switching arrangement including a first set of transistors (Tl, . . . , T6) and a second set of transistors (TU, . . . T6’). Each of the transistor pairs (Tl, T2), (T3, T4), (TU, T2’) and (T3’, T4’) are arranged in a series configuration, with thesource terminals of the constituent transistors of each pair being tied together. As described more in detail later, transistors (T5, T6, T5’, T6’) are essentially isolation transistors implemented to enhance the isolation performance of the circuit. Each of such isolation transistors is connected to the source terminals of its corresponding transistor pair. As an example, transistor (T6) is connected to the source terminals of the transistor pair (Tl, T2).

[0021] Continuing with the embodiment of Fig. IB, in operative conditions, each transistor functions as a switch that is either in an ON state or an OFF state. Amplification circuit (100) further comprises a first set of inductors (LI, L2) and a second set of inductors (LI’, L2’). The embodiment of Fig. IB shows a schematical symmetry between the transistors of the first set and the second set. As an example, transistors (Tl, TL) may be similar. The same applies to transistors (T2, T2’), (T3, T3’), etc. However, other embodiments may also be envisaged where the corresponding transistors from each of the first and second set of transistors are different. As an example, corresponding transistors from the two sets may be of different size and / or type. As also shown, the source terminals of transistors (T3, T4’) are connected to each other. Similarly, the source terminals of transistors (T3’, T4) are interconnected. Thus, the schematic depicts a crossing shown by numeral (102), representing a direct interconnection between the first and the second transistor sets. However, it should be noted that there is no physical connection present at crossing (102).

[0022] With continued reference to Fig. IB, the circuit has two modes of operation: a first mode and a second mode. Throughout the present disclosure, the first mode will be also called forward mode, while the second mode will be called reverse mode. By way of example, the forward mode can be a signal transmission mode and the reverse mode can be a signal reception mode, or vice versa. In the first mode of operation, the input signal enters the circuit through node (Nl) and exits the circuit at node (N2). This is indicated by signal path (P1B). Thus, the input signal at node (Nl) is directed through elements (LI, Tl, T2, L2) before being received at the input of amplifier (Al). After being amplified, the signal passes through the elements (L21, T2', Tl', LI') sequentially before reaching node (N2).

[0023] The inductor (LI) of Fig. 1A is utilized for impedance matching purposes. In the first mode of operation, transistor (T3) is in an OFF state, and its OFF-state capacitance can potentially cause RF leakage that may degrade the overall circuit performance. Accordingly, inductor (LI) is designed to match to system impedance, at a frequency within the operational frequency band, with the OFF-state capacitance of transistor (T3), thus mitigating the negativeeffects of such capacitance on the circuit performance. This same principle applies to the element pairs (L2, T4), (L21, T4'), and (LT, T3'), wherein the inductors absorb the impacts of the corresponding transistors' OFF-state capacitances. In accordance with embodiments of the present disclosure, each of the inductors (LI, L2, LT, L2’) may be fixed or variable.

[0024] With continued reference to Fig. IB, transistors (T5, T6, T5’, T6’) are generally utilized for isolation purposes. As shown, in the first operational mode, transistors (T5, T5') are situated outside of the signal path (P1B) and are thus in an ON state for additional isolation. Conversely, transistors (T6, T6') are in an OFF state so as to avoid impacting the signal path (P1B). Amplifier (Al) can be any type of amplifier providing any gain value depending on the application and associated requirements. However, isolation of the switching arrangement should be higher than amplifier gain to ensure stability. As an example, amplifier (Al) can be a low noise amplifier (LNA), a mid-level gain amplifier, or a power amplifier providing a higher gain. An exemplary gain provided by the amplifier is 20 dB.

[0025] Also shown in Fig. IB, are control voltages (Vs, Vsb) applied to the gates of various transistors. When operating in the first mode, the transistors with the control voltage (Vs) at their gate are in the ON state (closed) and the transistors with the control voltage (Vsb) are in the OFF state (open). Thus, in the first mode, control voltages (Vs, Vsb) represent ON and OFF control voltages, respectively. The control voltages (Vs, Vsb) can take on various values depending on the transistor type and design technology. In the case of NMOS FETs, exemplary values for the first mode are Vs = 1.8 V and Vsb = -1.8 V.

[0026] Fig. 1C shows the amplification circuit (100B) of Fig. IB, but this time operating in the second mode where the input signal enters the circuit through node (N2) and exits the circuit at node (Nl). This is indicated by signal path (PIC). Thus, when operating in the second mode, the input signal at node (N2) is directed through elements (LI’, T3’, T4, L2) before being received at the input of amplifier (Al). After being amplified, the signal passes through the elements (L21, T4', T3, LI) sequentially before reaching node (Nl).

[0027] With further reference to Fig. 1C, when operating in the second mode, in contrast with the first mode of operation, the transistors with the control voltage (Vs) at their gate are in the OFF state (open) and the transistors with the control voltage (Vsb) are in the ON state (closed). Thus, in the second mode, control voltages (Vs, Vsb) represent OFF and ON controlvoltages, respectively. In the case of NMOS FETs, exemplary values for the second mode are Vs = -1.8V and Vsb = 1.8V.

[0028] With continued reference to Fig. 1C, similarly to what was described with regards to the embodiment of Fig. 1A, inductor (LI) is utilized for impedance matching purposes. In the second operational mode, transistor (Tl) is in an OFF state, and its OFF-state capacitance can potentially cause RF leakage that may degrade the overall circuit performance. Accordingly, inductor (LI) is designed to match to system impedance with the OFF-state capacitance of transistor (Tl), thus mitigating the negative effects of said capacitance on the circuit performance. This same principle applies to the element pairs (L2, T2), (L21, T2'), and (LI1, Tl'), wherein the inductors absorb the impacts of the corresponding transistors' OFF-state capacitances. As also shown, in the second operational mode, transistors (T6, T6') are situated outside of the signal path (PIC) and are thus in an ON state for additional isolation. On the other hand, transistors (T5, T5') are in an OFF state so as to avoid impacting the signal path (PIC).

[0029] With reference to Figs. 1B-1C, it is noted that amplifier (Al) is the same and stays in the active state during both the first and the second modes operation. This removes the settling time of the amplifier (Al) from the total circuit switching time, thereby reducing the total circuit switching time to the switching times of the transistors of the switching arrangement (101). Moreover, by virtue of using a single amplifier for both modes, instead of two or more amplifiers as used in conventional transceivers, the overall cost and size of the amplification circuit (100B) can be significantly reduced.

[0030] Figs. 2A-2B show an exemplary amplification circuit (200) according to an embodiment of the present disclosure. Fig. 2A represents the first mode of operation, while Fig. 2B shows the second mode of operation. The principle of operation and the structure of this circuit is similar to what was described with regards to amplification circuit (100B) of Figs. 1A-1B, except for some differences between the switching arrangement (201) of Figs. 2A-2B with respect to the switching arrangement (101) of Figs. 1A-1B. Transistors (Tl, T6, TL, T6’) inside switching arrangement (101) of Figs. 1A-1B are now removed and this has the benefit of reducing the size, cost and signal loss of the circuit in the transmit direction. Moreover, amplification circuit (200) has additional inductors (L3, L3’) implemented across the drainsource terminals of corresponding transistors (T2, T2’). The inductors (L3, L3’) are utilized for further isolation. In the first mode of operation (Fig. 2A), transistor (T2) is in an ON state,meaning there is a small transistor ON resistance in parallel with the small resistance of inductor (L3). Thus, in this first mode, the presence of inductor (L3) does not significantly impact the circuit operation / performance. Conversely, during the second operational mode (Fig. 2B), transistor (T2) is in an OFF state, and its OFF-state capacitance can potentially cause leakage that negatively affects the overall circuit performance. Therefore, inductor (L3) is selected to resonate with the OFF-state capacitance of transistor (T3), thereby reducing negative effects. The same principles apply to the pair (T2’, L3’). Paths (P2A, P2B) of Figs. 2A-2B represent signal paths during the first and the second mode of operation, respectively. According to the teachings of the present disclosure, inductors (L3, L3’) may be fixed or variable. In some embodiments, only one of the inductors (L3, L3’) may be implemented, while other embodiments may use both of the inductors. The configuration in Figs. 2A-2B favors the first operational mode (e.g., signal transmission) in that a signal input at node (Nl) traverses only two transistors on the way to node (N2), while in the second operational mode (e.g., signal reception) a signal input at node (N2) traverses four transistors on the way to node (Nl). However, the switching arrangement (201) is reversible, so that the first operational mode (e.g., signal transmission) can input a signal at node (N2) while the second operational mode (e.g., signal reception) inputs a signal at node (Nl), thus favoring the second mode of operation.

[0031] Figs. 3A-3B show an exemplary amplification circuit (300) according to an embodiment of the present disclosure. Fig. 3A represents the first mode of operation, while Fig. 3B shows the second mode of operation. The principle of operation and the structure of this circuit is similar to what was described with regards to amplification circuit (200) of Figs. 2A-2B, except for some differences between the switching arrangement (301) of Figs. 3A-3B with respect to the switching arrangement (201) of Figs. 2A-2B. Transistors (T5, T3’, T4’, T5’) inside the switching arrangement (201) of Figs. 2A-2B are now removed and this has the benefit of reducing the size / cost and signal loss of the circuit, as well as the insertion loss. On the other hand, additional inductors (L4, L5) are added for the sake of further isolation. The principle of operation of inductors (L4, L5) with respect to their corresponding transistors (T3, T4) is similar to what was described with regards to the pairs (T2, L3) and (T2’, L3’) of Figs. 2A-2B. Signal paths (P3 A, P3B) of Figs. 3 A-3B respectively represent the first and the second mode of operation for this embodiment.

[0032] Fig. 4A shows an exemplary chart (400A) according to an embodiment of the present disclosure, the chart illustrating the performance of disclosed teachings during the firstmode of operation. With regards to the amplification circuits (100, 200, 300) shown in Figures 1A-1B, 2A-2B, and 3A-3B, respectively, each of the curves (410A, 420A, 430A) represents the variation of the S21 parameter (insertion loss) as a function of frequency. As mentioned previously, transistors (Tl, Tl’) are not used in the amplification circuits (200, 300). That is the reason why, during the first mode of operation, amplification circuits (200, 300) exhibit an improved insertion loss (curves 420 A, 430 A) over the insertion loss of amplification circuit (100) (curve 410A) where transistors (Tl, Tl’) are present and disposed in the signal path (P1B).

[0033] Fig. 4B shows an exemplary chart (400B) according to an embodiment of the present disclosure, the chart illustrating the performance of disclosed teachings, during the first mode of operation. With regards to the amplification circuits (100, 200, 300) shown in Figures 1A-1B, 2A-2B, and 3A-3B, respectively, each of the curves (410B, 420B, 430B) represents the variation of the S12 parameter (isolation) as a function of frequency. Due to the presence of transistors (T5, T5’) providing further isolation for circuits (100, 200), the isolation performance of circuits (100, 200) (curves 410B, 420B) exhibits improvement compared to circuit (300) (curve 430B).

[0034] Fig. 4C shows an exemplary chart (400C) according to an embodiment of the present disclosure, the chart illustrating the performance of disclosed teachings during the second mode of operation. With regards to the amplification circuits (100, 200, 300) shown in Figures 1A-1B, 2A-2B, and 3A-3B, respectively, each of the curves (410C, 420C, 430C) represents the variation of the S21 parameter (insertion loss) as a function of frequency. As can be noticed, amplification circuit (300) provides improved insertion loss (curve 430C) compared to amplification circuits (100, 200) (curves 410C, 420C). The reason is that transistors (T3’, T4’) are not used in amplification circuit (300), resulting in a lower number of transistors in the signal path and therefore a better insertion loss.

[0035] Fig. 4D shows an exemplary chart (400D) according to an embodiment of the present disclosure, the chart illustrating the performance of disclosed teachings during the second mode of operation. With regards to the amplification circuits (100, 200, 300) shown in Figures 1A-1B, 2A-2B, and 3A-3B, respectively, each of the curves (410D, 420D, 430D) represents the variation of the S12 parameter (isolation) as a function of frequency. Due to the presence of transistors (T6, T6’) which provide further isolation, amplification circuit (100)offers an improved isolation (curve 410D) compared to amplification circuits (200, 300) (curves 420D, 430D).

[0036] The aforementioned observations pertaining to the charts in Figures 4A-4D may serve as tradeoff principles to strike an enhanced balance for a design driven by strict and often conflicting requirements.

[0037] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0038] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0039] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, forexample, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0040] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g. , filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher- level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0041] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0042] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMS1. A radio frequency (RF) circuital arrangement switchable between a forward mode and a reverse mode, comprising: a forward mode signal transmission arrangement comprising switchable input side components configured to route a forward side signal from an amplifier input side of the RF circuital arrangement to an input of an amplifier, and switchable output side components configured to route the forward side signal, once amplified, from the output of the amplifier to an amplifier output side of the RF circuital arrangement; and a reverse mode signal transmission arrangement comprising switchable input side components configured to route a reverse side signal from the amplifier output side of the RF circuital arrangement to the input of the amplifier, and switchable output side components configured to route the reverse side signal, once amplified, from the output of the amplifier to the amplifier input side of the RF circuital arrangement.

2. The RF circuital arrangement of claim 1, further comprising: a forward mode signal isolation arrangement comprising input side isolation components configured to isolate the forward side signal while the forward side signal is routed from the amplifier input side of the RF circuital arrangement to the input of the amplifier, and output side isolation components configured to isolate the forward side signal, once amplified, while the forward side signal, once amplified, is routed from the output of the amplifier to the amplifier output side of the RF circuital arrangement; and a reverse mode signal isolation arrangement comprising input side isolation components configured to isolate the reverse side signal while the reverse side signal is routed from the amplifier output side of the RF circuital arrangement to the input of the amplifier, and output side isolation components configured to isolate the reverse side signal, once amplified, while the reverse side signal, once amplified, is routed from the output of the amplifier to the amplifier input side of the RF circuital arrangement.

3. The RF circuital arrangement of claim 2, wherein the input side isolation components and the output side isolation components of the forward mode signal isolation arrangement comprise switchable transistors.

4. The RF circuital arrangement of claim 3, wherein the input side isolation components and the output side isolation components of the reverse mode signal isolation arrangement comprise switchable transistors.

5. The RF circuital arrangement of claim 2, wherein the input side isolation components and the output side isolation components of the forward mode signal isolation arrangement comprise inductors.

6. The RF circuital arrangement of claim 5, wherein the input side isolation components and the output side isolation components of the reverse mode signal isolation arrangement comprise switchable transistors.

7. The RF circuital arrangement of claim 5 or 6, wherein the input side isolation components and the output side isolation components of the reverse mode signal isolation arrangement comprise inductors.

8. The RF circuital arrangement of any of any of claims 1 to 4, wherein the forward mode is a signal transmission mode and the reverse mode is a signal receiving mode.

9. The RF circuital arrangement of any of claims 1 to 4, wherein the forward mode is a signal receiving mode and the reverse mode is a signal transmission mode.

10. An amplification circuit comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: a) each of the first and the second set of elements comprises: a. l) a first and a second transistor arranged in a series configuration, source terminals of the first and the second transistor being tied together; a.2) a third and a fourth transistor arranged in a series configuration, source terminals of the first and the second transistor being tied together; a.3) a first and a second isolation transistor, the first isolation transistor being connected to the source terminal of the third and fourth transistor, and the secondisolation transistor being connected to the source terminals of the first and the second transistors; a.4) a first, and a second inductors; b) the first node is coupled to drain-terminal of the first and the third transistors of the first set of elements via the first inductor of the first set of elements; c) drain-terminals of the second and the fourth transistors of the first set of elements are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to drain-terminals of the second and the fourth transistors of the second set of elements via the second inductor of the second set of elements; e) the second node is coupled to drain-terminals of the first and the third transistors of the second set of elements via the first inductor of the second set of elements; f) source terminals of the third transistor of the first set of elements and the fourth transistor of the second set of elements are tied together, and g) source terminals of the fourth transistor of the first set of elements and the third transistor of the second set of elements are tied together.

11. The amplification circuit of claim 10, wherein: in a first mode of operation: the first and the second transistors of each of the first and the second set of elements are in an ON state; the third and the fourth transistors of each of the first and the second set of elements are in an OFF state.

12. The amplification circuit of claim 11, wherein in the first mode of operation, the first isolation transistors of each of the first set of elements are in the ON state, and the second isolation transistors of each of the first and the second set of elements are in the OFF state.

13. The amplification circuit of claim 12, wherein in the first mode of operation: a combination of the first inductor and an OFF-capacitance of the third transistor of each of the first and the second set of elements is configured to resonate at a resonance frequency within a frequency band of operation of the amplification circuit;a combination of the second inductor and an OFF-capacitance of the fourth transistor of each of the first and the second set of elements is configured to resonate at said resonance frequency.

14. The amplification circuit of claim 13 configured to: receive an input signal from the first node; direct the input signal via the first and the second transistor and the first and the second inductor of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the first and the second transistors and the first and the second inductors of the second set of elements to the second node.

15. The amplification circuit of claim 12, wherein in a second mode of operation: the third and the fourth transistors of each of the first and the second set of elements are in the ON state; the first and the second transistors of each of the first and the second set of elements are in the OFF state.

16. The amplification circuit of claim 15, wherein in the second mode of operation, the first isolation transistors of each of the first and the second set of elements are in the OFF state, and the second isolation transistors of each of the first and the second set of elements are in the ON state.

17. The amplification circuit of claim 16, wherein in the second mode of operation: a combination of the first inductor and an OFF-capacitance of the first transistor of each of the first and the second set of elements is configured to resonate at a resonance frequency within a frequency band of operation of the amplification circuit; a combination of the second inductor and an OFF-capacitance of the second transistor of each of the first and the second set of elements is configured to resonate at said resonance frequency.

18. The amplification circuit of claim 17, configured to: receive an input signal from the second node;direct the input signal via the first inductor and the third transistor of the second set of elements, the fourth transistor and the second inductor of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the second inductor and the fourth transistor of the second set of elements, and third transistor and the first inductor of the first set of elements to the first node.

19. An amplification circuit, comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: a) each of the first and the second set of elements comprises: a.l) a first, a second, and a third transistor; a.2) a first, a second, and a third inductors; a.3) an isolation transistor connected to the source terminal of the third transistor; b) the first node is coupled to a source terminal of the first transistor and to a drainterminal of the second transistor of the first set of elements via the first inductor of the first set of elements; c) drain-terminals of the first and the third transistors are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to drain-terminals of the first and the third transistors of the second set of elements via the second inductor of the second set of elements; e) the second node is coupled to a source terminal of the first transistor and to a drain-terminal of the second transistor of the second set of elements via the first inductor of the second set of elements; f) source terminals of the second transistor of the first set of elements and the third transistor of the second set of elements are tied together, and g) source terminals of the third transistor of the first set of elements and the second transistor of the second set of elements are tied together.

20. The amplification circuit of claim 19, wherein each of the first and the second set of elements further comprises a third inductor coupled across drain-source terminal of the first transistor.

21. The amplification circuit of claim 20, wherein: in a first mode of operation: the first transistor of each of the first and the second set of elements is in an ON state; the second and the third transistors of each of the first and the second set of elements are in an OFF state.

22. The amplification circuit of claim 21, wherein in the first mode of operation, the isolation transistors of each of the first set of elements are in the ON state.

23. The amplification circuit of claim 22, wherein in the first mode of operation: a combination of the first inductor and an OFF-capacitance of the second transistor of each of the first and the second set of elements is configured to resonate at a resonance frequency within a frequency band of operation of the amplification circuit; a combination of the second inductor and an OFF-capacitance of the third transistor of each of the first and the second set of elements is configured to resonate at said resonance frequency.

24. The amplification circuit of claim 23 configured to: receive an input signal from the first node; direct the input signal via the first transistor and the first and the second inductor of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the first transistor and the first and the second inductors of the second set of elements to the second node.

25. The amplification circuit of claim 22, wherein in a second mode of operation: the second and the third transistors of each of the first and the second set of elements are in the ON state;the first transistor of each of the first and the second set of elements are in the OFF state.

26. The amplification circuit of claim 23, wherein in the second mode of operation, the isolation transistor of each of the first and the second set of elements is in the OFF state.

27. The amplification circuit of claim 26, wherein in the second mode of operation: a combination of the third inductor and an OFF-capacitance of the first transistor of each of the first and the second set of elements is configured to resonate at a resonance frequency within a frequency band of operation of the amplification circuit.

28. The amplification circuit of claim 27, configured to, in the second mode of operation: receive an input signal from the second node; direct the input signal via the first inductor and the second transistor of the second set of elements, the third transistor and the second inductor of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the second inductor and the third transistor of the second set of elements, and second transistor and the first inductor of the first set of elements to the first node.

29. An amplification circuit, comprising: a first node and a second node; an amplifier; a switching arrangement including a first set of elements and a second set of elements; wherein: al) the first set of elements comprises: a.11) a first, a second, and a third transistor; a.12) a first, a second, a third, a fourth, and a fifth inductors; a2) the second set of elements comprises: a.21) a transistor; a.22) a first, a second, and a third inductor; b) the first node is coupled to a source terminal of the first transistor and to a drainterminal of the second transistor of the first set of elements via the first inductor of the first set of elements;c) drain-terminals of the first and the third transistors are coupled to an input of the amplifier via the second inductor of the first set of elements; d) an output of the amplifier is coupled to a drain-terminal of the transistor of the second set of elements via the second inductor of the second set of elements; e) the second node is coupled to a source terminal of the transistor of the second set of elements via the first inductor of the second set of elements; f) a source terminal of the second transistor of the first set of elements is connected to the first inductor of the second set of elements, and g) a source terminal of the third transistor of the first set of elements is connected to the first inductor of the second set of elements.

30. The amplification circuit of claim 29, wherein: in the first set of elements: the third inductor is coupled across source-drain terminals of the first transistor; the fourth inductor is coupled across source-drain terminals of the second transistor, and the fifth inductor is coupled across source-drain terminals of the third transistor; in the second set of elements: the third inductor is coupled across source-drain terminals of the transistor.

31. The amplification circuit of claim 30, wherein: in a first mode of operation: the first transistor of the first set of elements is in an ON state; the second and the third transistors of the first set of elements are in an OFF state, and the transistor of the second set of elements is in the ON state; in a second mode of operation: the first transistor of the first set of elements is in an OFF state; the second and the third transistors of the first set of elements are in an ON state, and the transistor of the second set of elements is in the OFF state.

32. The amplification circuit of claim 31, wherein: in the first mode of operation:a combination of the fourth inductor and an OFF-capacitance of the second transistor of the first set of elements is configured to resonate at a resonance frequency within a frequency band of operation of the amplification circuit; a combination of the fifth inductor and an OFF-capacitance of the third transistor of the first set of elements is configured to resonate at said resonance frequency; in the second mode of operation: a combination of the third inductor and an OFF-capacitance of the first transistor of the first set of elements is configured to resonate at said resonance frequency within a frequency band of operation of the amplification circuit; a combination of the third inductor and an OFF-capacitance of the transistor of the second set of elements is configured to resonate at said resonance frequency.

33. The amplification circuit of claim 32 configured to: in the first mode operation: receive an input signal from the first node; direct the input signal via the first transistor and the first and the second inductors of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the transistor and the first and the second inductors of the second set of elements to the second node; in the second mode operation: receive an input signal from the second node; direct the input signal via the first inductor of the second set of elements, the fourth transistor and the second inductor of the first set of elements to an input of the amplifier, thereby generating an amplified signal; direct the amplified signal via the second inductor of the second set of elements, the second transistor and the first inductor of the first set of elements to the second node.

34. A radio frequency (RF) circuit configured to be coupled to an amplifier including an input and an output, the RF circuit including: a first mode configuration including a first set of switchable components configured to route a first signal from a first node of the RF circuit to the input of the amplifier and to route an amplified first signal from the output of the amplifier to a second node of the RF circuit; anda second mode configuration including a second set of switchable components configured to route a second signal from the second node of the RF circuit to the input of the amplifier and to route an amplified second signal from the output of the amplifier to the first node of the RF circuit.

35. The RF circuit of claim 34, wherein at least one of the first and second sets of switchable components includes: a first inductor coupled to the first node, a first pair of switches coupled in series with the first inductor, and a second inductor coupled in series between the first pair of switches and the input of the amplifier; and a third inductor coupled to output of the amplifier, a second pair of switches coupled in series with the third inductor, and a fourth inductor coupled in series between the second pair of switches and the second node.

36. The RF circuit of claim 34, wherein at least one of the first and second sets of switchable components includes: a first inductor coupled to the first node, a first switch coupled in series with the first inductor, a second inductor coupled in series between the first switch and the input of the amplifier, and a third inductor coupled in parallel with the first switch; and a fourth inductor coupled to output of the amplifier, a second switch coupled in series with the fourth inductor, a fifth inductor coupled in series between the second switch and the second node, and a sixth inductor coupled in parallel with the second switch.

37. A method of switching radio frequency (RF) signals to an amplifier including an input and an output, the method including: operating a first set of switchable components in a first mode to route a first signal from a first circuit node to the input of the amplifier and to route an amplified first signal from the output of the amplifier to a second circuit node; and operating a second set of switchable components in a second mode to route a second signal from the second circuit node to the input of the amplifier and to route an amplified second signal from the output of the amplifier to the first circuit node.

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