Anode for a battery and method of manufacturing same

Abstract

There is described an anode for a battery. The anode generally having: a monocrystalline silicon wafer having a porous layer, the porous layer having pillars extending in a direction substantially normal to the monocrystalline silicon wafer, the pillars defining pores interspersed between the pillars, and ending in respective tip portions, the tip portions of the pillars forming an anode surface sitting on the pillars and closing the pores.

Description

ANODE FOR A BATTERY AND METHOD OF MANUFACTURING SAMEFIELD

[0001] The improvements generally relate to batteries and more specifically to anodes of such batteries.BACKGROUND

[0002] The rising demand for high-energy density batteries fuelled by advances in portable electronic devices and electric vehicles requires the development of alternative anode materials with a specific capacity beyond that of traditional graphite anode. This is particularly the case with the Internet of Things (loT) which consists of electronic devices with sensors and increasingly complex functionalities, connecting and exchanging data with other devices over the internet or other communication networks. Illustratively, loT can be used in many applications such as smart homes, automobiles, medical devices, transportation systems, agriculture, and environmental monitoring devices, to name a few. This clear trend of increasing development and use of the loT requires new electrochemical energy storage solutions as each connected device consumes energy to gather data and exchange it with their connected peers. The foreseeable increasing use of loT for an energy-demanding, allconnected future calls for the development of new batteries, with better safety, durability, performance, recyclability, and smaller size to cope with the integration of micro- nanoelectronics through ever smaller technological nodes. In addition, the use of microsystems and the miniaturization of components requires redesigning the power supplies to integrate them directly into the production line of thin film-based devices.

[0003] In most cases, the energy is provided by Lithium-Ion Batteries (LIBs) embarked on loT devices, so-called microbatteries. In this respect, a thriving research effort has been directed toward solid-state and on-chip systems for energy application. Such an interest is particularly driven by the direct active material substrate use as the current collector, which increases the specific capacity by removing the inactive compounds (e.g., binders and conductive additives) and enhances electrical contacts leading to higher energy density and rate performance. Microbatteries have been integrated into loT electronic devices such assmart contact lenses, smart medical devices and miniaturized wireless devices to supply the required power but with low to moderate autonomy. Critical roadblocks faced today by microbatteries are their low performance and short lifespan. Since their performances are highly affected by their constituting sub-components, striving toward better microbatteries architecture is of paramount importance to improve next generation performance.

[0004] As state-of-the-art LiBs, based on graphite anodes, have almost reached their optimal technological development, LiBs may not be able to comply with the performance requirements necessary for next-generation loT devices. An alternative that gains increasing support (e.g., through integration into the roadmaps of many battery manufacturers and micro / nano-electronics key players) is the use of silicon-based electrodes. Indeed, its superior energy density and power density make it ideal candidates to match the areal capacities of commercial batteries targeting 3-4 mAh cm-2and for integration into miniaturized energy utilization systems.

[0005] However, if silicon exhibits a remarkable theoretical specific capacity of 3579 mAh g-1(i.e., one order of magnitude higher than that of graphite, 372 mAh g_1) and shows advantages in terms of price, abundance, and non-toxicity, it has the major problem of substantial morphological changes during charge / discharge, with large volumetric expansion (-400 %), and contraction accompanied by structural transformations and interfacial reactions inducing mechanical stress, and causing chemo-mechanical degradations. The volume change of Si during lithiation and delithiation then leads to severe particle pulverization, unstable solid-electrolyte interphase (SEI) formation, and loss of electrical contact at the electrode level, which result in capacity fading and limited cycle life. These relationships between electrochemical transformations and solid mechanics often play a defining role in the behavior and stability of alloy electrodes.

[0006] Solving these issues to enable high performance electrodes and microbatteries is foreseen for loT devices. Efforts have been made to address these bottlenecks in the Si anode. Structure modification, and in particular nanostructuration, is a way to accommodate volume expansion of Si anode during discharging / charging process. Some Si structural designs tackling this issue that significantly optimized Si- based anodes for LIBs performance include Si nanoparticles, nanowires, nanotubes, nanolayers, nanovaults, and porous.Recently, the use of porous Si and Ge have been suggested as a prominent candidate in the literature as an on-chip anode for supercapacitors, as well as high power density and high energy density devices. Nanowire nest structure obtained an areal capacity of 4.1 mAh cm-2after 1 cycle and an average areal capacity below 3 mAh cm-2. 3D silicon nanowire for lithium battery anodes, delivered an areal capacity of 14 mAh cm-2, however, this capacity dropped after a few cycles and achieved an areal capacity below 3 mAh cm-2after 50 cycles. Si nanotrees structure allowed reaching a cumulative capacity of 7.1 mAh cm-2, but the maximum areal capacity was around 5 mAh cm-2that rapidly decreased below 3 mAh cm-2after 100 cycles.

[0007] However, even if the downsizing of active material limits volume expansion stress and enhances capacity retention, the increase of the specific surface area leads to a higher amount of solid electrolyte interface (SEI) formation resulting in higher irreversible capacity. Therefore, two main challenges must be addressed in parallel: i) Reduction of the effect of volume expansion on structure integrity, and ii) stabilization of the SEI. The two main indicators for the electrochemical performance are cycle life and Coulombic efficiency. In addition to these points, from the perspective of applications, the process should be compatible with microelectronics and should be cost-effective. There thus remains room for improvement.SUMMARY

[0008] Silicon remains one of the most promising anode materials for Li-ion batteries. However, the development of such batteries is hindered by mechanical and electrochemical failures resulting from massive volume expansion and continuous growth of solid electrolyte interphase. It was found that monocrystalline silicon wafers made porous, such as shown in Fig. 1 , were not exhibiting satisfactory performances through repeated lithiation and delithiation processes. However, if those same porous monocrystalline silicon wafers were to be annealed at sufficiently high temperatures, then the porous structure can form a continuous anode surface which is well suited for repeated lithiation and delithiation processes, as will be described in detail below.

[0009] In this disclosure, a novel on-chip anode architecture using rapid thermal annealing on monocrystalline silicon wafers made porous is proposed. The structure consists of acomposite of a nanomembrane of silicon on top of an isotropic structure of a porous layer. It was found that such structure can enhance both Coulombic efficiency and mechanical stability, achieving areal capacities ranging between 5 and 20 mAh cm-2over 100-200 cycles with a high Coulombic efficiency near 100% in some embodiments.

[0010] In accordance with a first aspect of the present disclosure, there is provided an anode for a battery, the anode comprising: a monocrystalline silicon wafer having a porous layer, said porous layer having a plurality of pillars extending in a direction substantially normal to said monocrystalline silicon wafer, said plurality of pillars defining a plurality of pores interspersed between said plurality of pillars, and ending in respective tip portions, said tip portions of said plurality of pillars forming an anode surface sitting on said plurality of pillars and closing said plurality of pores.

[0011] Further in accordance with the first aspect of the present disclosure, said anode surface can for example have a plurality of crack propagation blockers made integral to said anode surface.

[0012] Still further in accordance with the first aspect of the present disclosure, said plurality of crack propagation blockers can for example be provided in the form of shallow cracks running in closed paths on said anode surface.

[0013] Still further in accordance with the first aspect of the present disclosure, said crack propagation blockers can for example have a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns.

[0014] Still further in accordance with the first aspect of the present disclosure, said crack propagation blockers can for example recess from said anode surface by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

[0015] Still further in accordance with the first aspect of the present disclosure, said porous layer can for example have a hardness gradient extending along a thickness orientation of said porous layer.

[0016] Still further in accordance with the first aspect of the present disclosure, said hardness gradient can for example include a first layer portion having a first hardness value, and a second layer portion deeper than said first layer portion, said second layer portion having a second hardness value below said first hardness value.

[0017] Still further in accordance with the first aspect of the present disclosure, said first hardness value can for example be above a first hardness threshold and said second hardness value is below a second hardness threshold.

[0018] Still further in accordance with the first aspect of the present disclosure, said first hardness value can for example be above 2.5 GPa, said second hardness value below 2.5 GPa, preferably below 2.0 GPa and most preferably below 1.8 GPa.

[0019] Still further in accordance with the first aspect of the present disclosure, said hardness gradient can for example have a hardness profile extending along said thickness orientation, said hardness profile increasing to a maximal hardness value at a shallow depth from said anode surface and then decreasing below a hardness threshold at a deeper depth.

[0020] Still further in accordance with the first aspect of the present disclosure, said pores can for example have an isotropic structure.

[0021] Still further in accordance with the first aspect of the present disclosure, said isotropic structure can for example define pores of pseudo-spherical shapes.

[0022] Still further in accordance with the first aspect of the present disclosure, said pores of pseudo-spherical shapes can for example be at least partially filled with lithium ions.

[0023] Still further in accordance with the first aspect of the present disclosure, said tip portions can for example at least partially merge together to form said anode surface.

[0024] Still further in accordance with the first aspect of the present disclosure, said direction can for example correspond to a crystalline orientation of said monocrystalline silicon wafer.

[0025] Still further in accordance with the first aspect of the present disclosure, said porous layer can for example have a thickness ranging between 10 microns and 75 microns.

[0026] Still further in accordance with the first aspect of the present disclosure, said porous layer can for example have a thickness above 45 microns.

[0027] In accordance with a second aspect of the present disclosure, there is provided a method of manufacturing an anode for a lithium-ion battery, the method comprising: etching a monocrystalline silicon wafer, said etching creating a plurality of pillars extending in a direction substantially normal to said monocrystalline silicon wafer, said plurality of pillars defining a plurality of pores interspersed between said plurality of pillars, said pillars and pores forming a porous layer within said monocrystalline silicon wafer; and heating the porous layer above a given temperature threshold, said heating causing tip portions of said pillars to merge to one another, thereby forming an anode surface sitting on said pillars and closing said pores.

[0028] Further in accordance with the second aspect of the present disclosure, said given temperature threshold can for example be above 900°C, preferably above 950°C and most preferably above 1000°C.

[0029] Still further in accordance with the second aspect of the present disclosure, said heating can for example cause forming a plurality of crack propagation blockers made integral to said anode surface, said crack propagation blockers can for example have a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns, and said crack propagation blockers can for example recess from said anode surface by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

[0030] Still further in accordance with the second aspect of the present disclosure, said heating can for example cause a hardness profile along a thickness orientation of said monocrystalline silicon wafer, said hardness profile can for example increase to a maximal hardness value at a shallow depth from said anode surface and then decrease below a hardness threshold at a deeper depth.

[0031] Still further in accordance with the second aspect of the present disclosure, said heating can for example transform said pillars into isotropically-shaped pillars.

[0032] Still further in accordance with the second aspect of the present disclosure, said porous layer can for example have a thickness ranging between 10 microns and 75 microns.

[0033] Still further in accordance with the second aspect of the present disclosure, said porous layer can for example have a thickness above 45 microns.

[0034] Still further in accordance with the second aspect of the present disclosure, the method can for example further comprise, prior to said etching, selecting a desired anode capacity and associating the desired anode capacity to a porous layer thickness, said etching performed until the porous layer reaches the porous layer thickness.

[0035] It is understood that, in this disclosure, the use of the term “micron” is meant to refer to a length unit corresponding to a millionth of a meter, i.e., 1 *1 O'6m. This length unit is also referred to as “pm” in the field.

[0036] All technical implementation details and advantages described with respect to a particular aspect of the present invention are self-evidently mutatis mutandis applicable for all other aspects of the present invention.

[0037] Many further features and combinations thereof concerning the present improvements will appear to those skilled in the art following a reading of the instant disclosure.DESCRIPTION OF THE FIGURES

[0038] In the figures,

[0039] Fig. 1 is a side elevation view of an unannealed porous layer of a monocrystalline silicon wafer shown at room temperature, after a first lithiation process and after a first delithiation process;

[0040] Fig. 2 is a side elevation view of another example of a porous layer of a monocrystalline silicon wafer shown after an annealing step, after a first lithiation process and after a first delithiation process, in accordance with one or more embodiments;

[0041] Fig. 3 is a flow chart of an exemplary method of manufacturing an anode for a lithium- ion battery, in accordance with one or more embodiments;

[0042] Figs. 4A-F include scanning electron microscopy (SEM) images characterizing top plan view and cross-sectional views for three different monocrystalline porous wafers including a porous silicon wafer at room temperature (referred to herein as “P-Si (RT)”), a porous silicon wafer which has undergone a rapid thermal annealing up to 800 °C (referred to herein as “P- Si / RTA-800°C”); and a porous silicon wafer which has undergone a rapid thermal annealing up to 1000 °C (referred to herein as “P-Si / RTA-1000°C”), respectively, in accordance with one or more embodiments;

[0043] Figs. 5A-B include graphs showing X-ray reflectivity (XRR) curves measured for non- porous bulk monocrystalline silicon, P-Si (RT) wafer, P-Si / RTA-800°C wafer, and P-Si / RTA- 1000°C wafer, in accordance with one or more embodiments;

[0044] Fig. 5C is a graph showing surface porosity for the P-Si (RT) wafer, the P-Si / RTA- 800°C wafer, and the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0045] Figs. 6A-C are pre-cycling SEM cross-sectional images of the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0046] Fig. 7A is a graph showing discharge capacity as a function of cycle number for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0047] Fig. 7B is a graph showing corresponding 1stcycle differential capacity curves as a function of potential for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA- 1000°C wafer, in accordance with one or more embodiments;

[0048] Fig. 7C is a graph showing initial Coulombic efficiency (ICE) at C / 40 full-lithiation and AUC (area under the curve) of differential capacity curves from 0.25 V to 2.0 V linking to the amount of SEI growth as a function of XRR surface porosity (%) for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0049] Fig. 7D is a graph showing relative irreversible capacity as a function of cycle number for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0050] Fig. 8 includes optical post-mortem images of a non-porous bulk monocrystalline silicon wafer, a P-Si (RT) wafer, a P-Si / RTA-800°C wafer, and a P-Si / RTA-1000°C wafer after 50 cycles at 1 mA cm-2 with a discharge cut-off time of 1 h, in accordance with one or more embodiments;

[0051] Fig. 9A is a graph showing discharge capacity (darker / left-axis) and Coulombic efficiency (lighter / right-axis) for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P- Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0052] Fig. 9B is a graph showing RICSEI cumulated as a function of cycle number for the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer cycled at 1 mA cm'2, in accordance with one or more embodiments;

[0053] Fig. 10 includes post-mortem SEM images showing top views and cross-sectional views of the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer after 50 cycles at 1 mA cm'2current density, in accordance with one or more embodiments;

[0054] Fig. 11A is a graph showing cycle life plot with Coulombic efficiency at 3 mAh cm'2capacity of the P-Si / RTA-1000°C wafer after 200 cycles, in accordance with one or more embodiments;

[0055] Fig. 11 B is a graph showing voltage-capacity profile at 1 mA cm'2current density for the P-Si / RTA-1000°C wafer after 200 cycles, in accordance with one or more embodiments;

[0056] Figs. 11 C-D are post-mortem SEM images showing a top view and a cross-sectional view of the P-Si / RTA-1000°C wafer after 200 cycles, in accordance with one or more embodiments;

[0057] Fig. 12A is a graph showing different areal-capacity-rate measurements for the P- Si / RTA-1000°, in accordance with one or more embodiments;

[0058] Fig. 12B is a graph showing voltage-capacity profile at 1 mA cm-2current density and variable capacity for the P-Si / RTA-1000°, in accordance with one or more embodiments;

[0059] Fig. 12C is a graph showing differential capacity curves at 1st cycle of each various capacity rate for the P-Si / RTA-1000°, in accordance with one or more embodiments;

[0060] Fig. 12D is a post-mortem SEM image showing structural integrity of the P-Si / RTA- 1000°C wafer after reaching 20 mAh cm-2, in accordance with one or more embodiments;

[0061] Fig. 13A is a graph showing a cycle life plot as a function of cycle number for the P- Si / RTA-1000°C wafer, showing a Coulombic efficiency at 9 mAh cm-2capacity for 200 cycles, in accordance with one or more embodiments;

[0062] Fig. 13B is a graph showing voltage-capacity profile at 1 mA cm-2 current density for the P-Si / RTA-1000°C wafer, in accordance with one or more embodiments;

[0063] Fig. 14A is an optical image of a top surface of the P-Si / RTA-1000°C wafer after nanoindentation tests, in accordance with one or more embodiments;

[0064] Fig. 14B is a graph showing load on sample as a function of displacement into the surface for the nanoindentation tests of Fig. 14B, in accordance with one or more embodiments; and

[0065] Fig. 15 is a graph showing hardness of different silicon structures extending within the P-Si (RT) wafer, the P-Si / RTA-800°C wafer, and the P-Si / RTA-1000°C wafer before cycling as a function of displacement obtained by nanoindentation tests, in accordance with one or more embodiments.DETAILED DESCRIPTION

[0066] Fig. 2 shows an example of an anode 100 for a battery 10. As depicted, the anode 100 has a monocrystalline silicon wafer 102 with a porous layer 104. The porous layer 104 can be made by etching the monocrystalline silicon wafer 102 using known etching techniques which may vary depending on the embodiment. As illustrated, the porous layer 104 has pillars 106 extending in a given direction D substantially normal to the monocrystalline silicon wafer102. In some embodiments, the given direction D corresponds to a crystalline orientation of the monocrystalline silicon wafer 102. The pillars 106 define pores 108 interspersed between the pillars 106. As shown, the pillars 106 end in respective tip portions 110. Thanks to a heating step (also referred to an “annealing” step or “rapid annealing” step herein), which will be discussed in detail below, the tip portions 110 of the pillars 106 form an anode surface 112 sitting on the pillars 106 and closing the pores 108.

[0067] In some embodiments, it is intended that the anode surface 112 has crack propagation blockers 114 made integral to the anode surface 112. For instance, the crack propagation blockers 114 can be provided in the form of shallow pores or cracks running in closed paths underneath, within or on the anode surface 112. The shapes of such pores or closed paths can vary from one embodiment to another, or from one crack propagation blocker 114 to another. However, pores or closed paths forming circular shapes, ovoid shapes, island shapes, a combination and / or mosaic thereof were found to be satisfactory. For instance, it was found that spherical or ovoidal pores can help reducing the volume expansion by making the resulting structure more isotropic thus breaking a path for crack propagation. Depending on the embodiment, the crack propagation blockers 114 have a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns. The crack propagation blockers 114 typically recess from the anode surface 112 by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

[0068] Additionally or alternatively, the porous layer 104 can have a hardness gradient extending along a thickness orientation O or depth d of the porous layer 104. The hardness gradient can include a first layer portion 104a having a first hardness value H1 , and a second layer portion 104b deeper than the first layer portion 104a. In these latter embodiments, the second layer portion 104b has a second hardness value H2 which is below the first hardness value H1 , i.e. , H2 < H1. For instance, the first hardness value H1 can be above a first hardness threshold Ht1 , i.e., H1 > Ht1 , and the second hardness value H2 can be below a second hardness threshold Ht2, i.e., H2 < Ht2. In one example, the first hardness value H1 is above 2.5 GP and / or the second hardness value H2 is below 2.5 GPa, preferably below 2.0 GPa and most preferably below 1.8 GPa. In some embodiments, the hardness value can peak before decreasing considerably. In these embodiments, the hardness gradient has a hardness profile116 extending along the thickness orientation O. More specifically, in these embodiments, the hardness profile 116 increases to a maximal hardness value Hmax at a shallow depth from the anode surface 112 and then decreasing below a hardness threshold Hth at a deeper depth.

[0069] In some embodiments, the heating step transform the pillars 106 and / or pores 108 into an isotropic structure 120. As such, the pillars can be transformed into isotropically- shaped pillars 106’. Similarly, the pores 108 can be transformed into isotropically-shaped pores 108’ as well. The isotropic structure 120 can define pillars 106 and / or pores 108 of spherical- or pseudo-spherical shapes. It was found that such an isotropic structure 120 is particularly convenient, as it can provide greater strength than anisotropic structures, especially when at least partially filled with lithium ions. Indeed, it was found that pores having an anisotropic transverse cross-section can encourage the formation of cracks in a particular direction. Anisotropic pores are generally defined by having a first lateral dimension being shorter or longer than a second lateral dimension being perpendicular to the first lateral dimension. As such, if adjacent anisotropic pores each have their longest lateral dimension parallel to one another, this could lead to crack formation along that dimension. Accordingly, if pores are isotropically shaped, the first and second lateral dimensions of their transverse cross-sections can act as crack propagation blockers, as crack formation would not be encouraged from propagating in any of the first and second lateral dimensions. In other words, pores having transversion cross-sections of circular or pseudo-circular shapes may prevent crack from propagating within the anode surface 112, which was found to be particularly convenient, especially in the production of highly performing anodes.

[0070] Fig. 3 is a flow chart of an example method 300 of manufacturing an anode for a lithium-ion battery.

[0071] At step 302, a monocrystalline silicon wafer is etched. The etching step creates pillars extending in a direction substantially normal to the monocrystalline silicon wafer. The pillars define pores interspersed between the pillars. As such, the pillars and pores form together a porous layer within the monocrystalline silicon wafer.

[0072] At step 304, the porous layer is heated above a given temperature threshold for a given period of time. The heating step causes tip portions of the pillars to merge to oneanother, thereby forming an anode surface sitting on the pillars and closing the pores. It can be said that the tip portions can at least partially merge to one another to form the anode surface. In some embodiments, the given temperature threshold is above 900°C, preferably above 950°C and most preferably above 1000°C.

[0073] At step 306, the heating step causes crack propagation blockers to be formed. The crack propagation blockers are made integral to the anode surface. In some embodiments, the crack propagation blockers have a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns. Alternately or additionally, the crack propagation blockers recess from the anode surface by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

[0074] At step 308, the heating step causes a hardness profile along a thickness orientation of the monocrystalline silicon wafer. The hardness profile increases to a maximal hardness value at a shallow depth from the anode surface and then decreases below a hardness threshold at a deeper depth.

[0075] At step 310, the heating step causes the pillars to transform into isotropically-shaped pillars. As such, the pillars and complimentary pores exhibit an isotropic shape, with spherically- and / or pseudo-spherically shaped members and portions.

[0076] It is noted that the steps 306, 308 and 310 are optional. As such, any one or all of these latter steps can be omitted in some embodiments. However, in some preferred embodiments, the steps 306, 308 and 310 are all performed in the method 300.

[0077] Example - High-areal-capacity Si architecture as an on-chip anode for lithium-ion batteries

[0078] In this example, we propose to use a porous silicon structure with a closed surface porosity, the porosity is expected to contribute to reducing the effect of volume expansion and thereby preserving structure integrity. While the closed surface will contribute to reducing the effect of SEI. Anodic etching of silicon combined with RTA are chosen as a technique for the structure fabrication, these techniques are low-cost, versatile and scalable method and are compatible with industrial constraints. This approach offers a high degree of flexibility inobtaining a material having the microstructural characteristics desired for use in LIBs. Subsequent annealing treatment can modify both the chemical and structural characteristics. For instance, in the case of conventional batteries, Roland et al. fabricated tuned porous Si by backside post-annealing treatment that allowed the growth of the wall thickness (crystallite size) and pores size. This process reveals a positive impact on battery performance due to a higher wettability of the Si (slurry) electrode with the electrolyte, and reduction of specific area. Here, in the framework of on-chip anode, the porous layer grown on a doped-Si substrate can be modified by thermal annealing, a treatment that leads to improvement of electrochemical and mechanical behaviours during cycling.

[0079] The next paragraphs discuss the tuning of the porous Si architecture with rapid thermal annealing. Porous Si (P-Si) samples were fabricated by electrochemical etching. This process allows tuning the morphology of P-Si (porous layer thickness, porosity and the pore sizes) by adjusting electrolyte concentration and current density. In the present example, a mesoporous type of porous silicon was used, where the porosity of the initial Si sample was set at 40 ± 3 % with pore diameter of 8 ± 5 nm. The thickness of the initial porous layer was set at 25 microns. Batches of this sample were then heat-treated at 800°C and 1000°C using a rapid thermal annealing (RTA) process. Henceforth, all P-Si samples were named based on the annealing temperature conditions: P-Si (RT) (room temperature, no RTA treatment), P- Si / RTA-800°C, and P-Si / RTA-1000°C.

[0080] Regarding electrochemical etching, Si samples with a porosity of 40 % were fabricated using a custom-made Teflon electrochemical cell. P-type Si (100) wafer (WaferPro) with resistivity of 0.01-0.02 Qo cm was used as the working electrode and Pt wire as the counter electrode. The electrolyte was composed of hydrofluoric (HF) acid (Sigma-Aldrich, 49 %) and anhydrous ethanol (Sigma-Aldrich, 99.9 %) with a ratio of 1 :1 (v:v). The etching process was made through two steps: etching pulse and rest time. A 50 mA cm-2 current density was used for the 1 s etching pulse and 1 s for the rest time. The total etching time was 900 s.

[0081] Regarding rapid thermal annealing (RTA), RTA equipment (Jet-First from JIPELEC) was used to close the Si surface pores. These samples were placed under an Ar gas at 1 atmthat were exposed to two different annealing temperatures of 800°C and 1000°C with time duration of 60 s.

[0082] Regarding structure and surface characterization, the surface morphology of the Si samples was investigated using a scanning electron microscope (FE-SEM) in plain and cross- sectional views. Porosity measurements were done using the software, Imaged. The XRR was performed using Rigaku Smartlab HRXRD system with Cu K-alpha X-ray source (monochromated by Ge (220) x 4 monochromator) and HYPIX-3000 hybrid pixel array 2D detector.

[0083] Regarding electrochemical measurements, different porous Si and non-porous (bulk) Si were studied as active materials. For the loading calculation, half of the porous layer was chosen (12.5 microns) to prevent lithiation of the wafer. The mass loading density of the active material is typically 1.74 mg cm'2and 2.91 mg cm-2for P-Si and bulk Si, respectively. Swagelok cells were assembled in a glovebox under Ar field (MBraun system) using the prepared electrode as the working electrode, the Li disc (MTI-XTL) as the reference and counter electrode, a Whatman® glass microfibre filters, Grade GF / D (Sigma-Aldrich) as the separator, and 1 M lithium hexafluorophosphate (LiPFe) solution in ethylene carbonate and dimethyl carbonate [EC / DMC = 50 / 50 (v / v)] battery grade (Sigma-Aldrich) and 10 % wt. fluoroethylene carbonate (FEC) as the electrolyte.

[0084] As displayed in Fig. 4, the use of RTA treatment resulted in significant structural changes. The reorganization of the P-Si surface was clearly observed in Figs. 4A-F, demonstrating a decrease in surface porosity as the temperature increased due to the sintering effect. Specifically, X-ray reflectivity (XRR) analysis revealed that the initial surface porosity of P-Si (RT) at 46% decreased to 29% and 4% after RTA treatment at 800°C and 1000°C, respectively (Fig. 5).

[0085] Fig. 5 summarizes the evolution of surface porosity measured in two different methods: X-Ray Reflectometry (XRR) and Scanning Electron Microscopy (SEM) (Fig. 6) processed with Imaged. In the case of XRR, porosity (P) was calculated using the critical angle of porous Si (0PS) and bulk Si (0si) :

[0086] 100, (eq. 1)

[0087] Both measurements showed that porosity decreases as a function of the temperature. The values from XRR and SEM quantitatively behaves in similar fashion with a bit discrepancy for P-Si / RTA-1000°C that can be related to the fact that porous structure underneath the top surface may be probed.

[0088] Similar trends were observed with porosity measurements using SEM analysis (Figs. 4A-C). However, since the electron beam can penetrate into the material, it is possible that the probed depth is greater than the thickness of the silicon layer densified by heat treatment (~1 pm). Therefore, XRR measurement is preferred as a more accurate measurement.

[0089] Although the densification resulting from RTA treatment is most apparent on the first 1 micron of the porous layer (Figs. 4E-F), this process also led to reorganization in the bulk of the material, indicating that RTA treatment induces changes in both surface and depth properties of the porous layer. The bulk porosity is observed to remain centered on 40%, but the pore size and shape are modified (Fig.4). Thus, representative pore size measurements at the middle of the porous layer of P-Si / RTA-800°C and P-Si / RTA-1000°C are 14 ± 4 nm and 16.5 ± 2 nm2, respectively, while 8 ± 5 nm2for P-Si (RT) sample (Fig. 6). In addition, the morphology of the porous structure is modified by the annealing treatment. While the structure is a tree-like for P-Si(RT), the structure is made more spherical pores for P-Si / RTA-800°C and P-Si / RTA-1000°C. This is a classical spheroidisation induced by the reduction of the surface energy.

[0090] Therefore, the annealing allows tuning both the surface porosity and the bulk porous morphology and the final structure (RTA-treated) can be described as a sandwich structure, in which the original porous layer is covered by a thin Si layer on top and supported by the silicon wafer at the bottom. Contact angle measurements show that the top layer has similar wettability by the electrolyte than the bulk (no porous) silicon, This can be attributed to both frictional forces and surface chemistry, as it indicates that the behavior of the restructured porous material's surface closely resembles that of bulk silicon

[0091] The next paragraphs discuss the effect of thermal treatment on electrochemical performance. In a first cycle, the initial Coulombis efficiency was quantified.

[0092] The three samples with different morphologies have been investigated between 2 and 0.05 V vs. Li / Li+and cut-off time of 40h, with a low current density of 0.15 mA cm ~2to study the lithiation. Electrochemical cycling at low current density allows to increase the amount of lithium ions penetrating inside the Si structure.

[0093] For the three different Si samples a discharge (lithiation) gravimetric capacity of 3579 mAh g-1with a loading of ~1 .74 mg cm-2corresponding to a surface capacity of ~ 6 mAh cm-2(Fig. 7A) was fixed. P-Si / RTA-1000°C showed no capacity fading after 50 cycles, contrary to P-Si (RT) and P-Si / RTA-800°C that dropped after the 9thand 17thcycles, respectively.

[0094] The differential capacity (dQ / dV vs. V) curves for the 1stcycle of each sample are shown in Fig. 7B. A peak observed at ~ 0.1 V for 1stcycle of each of the samples can be attributed to initial alloying of the crystalline silicon (c-Si) with lithium, while the 0.8 V peak can be accounted for SEI formation the shape of the P-Si(RT) curve differs from that of other samples. This difference could be due to the reduction of impurities on the surface of the p- Si(RT) electrode (SiOx, SiOH, SiH. etc). The two broad anodic peaks around 0.32 V and 0.47 V confirm the delithiation of amorphous silicon (a-Si), as they are characteristic of lithium extraction from a-LixSi.

[0095] To compare the SEI formation in the three samples, we focused on the cathodic region from 0.25 V to 2.0 V. Specifically, SEI was determined quantitatively using the area under the curve (AUG). This latter is plotted as a function of the surface porosity measured by XRR in Fig. 7C and show clear dependence of the AUG with the surface porosity. This tendency is confirmed by showing that ICE is inversely proportional to the surface porosity (Fig. 7C). Thus, decreasing the surface porosity from 46% (P-Si (RT)) to 4% (P-Si / RTA- 1000°C) improved the ICE by more than 20%.

[0096] Therefore, one can conclude that the morphology modifications induced by surface annealing has a strong effect on the growth of the SEI and consequently on the ICE. This maybe due to the lower specific surface in contact with the electrolyte limiting the growth of detrimental SEI.

[0097] The effect of SEI on the relative irreversible capacity (RIC) can be evaluated by:

[0099] where Qcharge and Qchargencorrespond to the charge capacity at n cycle and QDischargenthe discharge at the n discharge.

[0100] RICSEI is plotted for the three samples on Fig. 7D. For P-Si(RT), a continuous increase with the number of cycles is observed with an acceleration concomitant with the capacity fading. The tendency is the same for (P-Si / RTA-800°C) but with a lower RICSEI rate in the first 14 cycles. The case of (P-Si / RTA-1000°C) is special. During the four first cycles, the tendecy is very similar to P-Si(RT). Then, a plateau is observed indicating the arrest of the growth of the SEI. Above the 12thcycle, a resumption of this growth can be noticed and catch up with the trend of the (P-Si / RTA-800°C). However, contrary to this latter, a new plateau is observed and the RICSEI is stabilized over the remaining cycles. This observation is crucial as it shows that the growth of the RICSEI is inihibited thanks to the structure modification induced by RTA.

[0101] The next paragraphs discuss the performance of the unit over 50 cycles with a capacity of 1 mAh cm-2. Additional electrochemical galvanostatic and cycle life measurements were performed between 1 and 0.01 V vs. Li / Li+at a current density of 1 mA cm-2with discharge cut-off time of 1 h. Fig. 9A displays the discharge capacity and coulombic efficiency of the different samples: P-Si (RT), P-Si / RTA-800°C, and P-Si / RTA-1000°C. A non-porous silicon (bulk) was added as a reference. The latter attained a very low areal capacity of 0.1 to 0.2 mAh cm-2during the first three cycles before stopping to work. This low performance of bulk Si is usual and can be ascribed to the fragmentation of the electrode.

[0102] A stable areal capacity of 1 mAh cm-2was observed for P-Si (RT), P-Si / RTA-800°C, and P-Si / RTA-1000°C samples (Fig. 9A) with classical potential curves after 1stlithiation (which is considered as the prelithiation step) over 50 cycles. After the 1stcycle, the initialCoulombic efficiency (ICE) of P-Si (RT), P-Si / RTA-800°C, and P-Si / RTA-1000°C are ~80 %, ~84 % and ~90 %, respectively, confirming the effect of the porous morphology on the ICE as already shown in Fig. 7C.

[0103] The RICSEI cumulated for the three samples are compared in Fig. 9B. As in the previous section, it shows that over the first cycles, the RTA has an effect on SEI by decreasing the rate of the increase of the RICSEI with the number of cycles. P-Si / RTA-800°C and P- Si / RTA-1000°C have a similar trend until the 25thcycle. The increase of SEI in P-Si / RTA- 800°C may be due to some large cracks in the structure that expose new surface area (Fig. 11 B) as observed in the following section.

[0104] Post-mortem SEM analysis was performed on all samples after 50 cycles. Top view and cross-sectional SEM images with different scales featured the impact of lithiation / delithiation on the Si structure of the three different samples studied (Fig. 10). After cycling, the morphology of the on-chip electrodes changes substantially. P-Si (RT) and P- Si / RTA-800°C showed crack propagation on the top porous layer (top view and cross- sectional). The crack deflection produced peeled off surfaces (island formation). The thickness of islands formed on P-Si (RT) and P-Si / RTA-800°C are approximately 3.3 ± 0.8 microns and 9 ± 2 microns, respectively. The lateral dimensions also differ significantly. For P-Si(RT), the size of the domains is heterogeneous with characteristic length varying from 5 microns to 50 microns. In the case of P-Si / RTA-800°C, the size distribution is narrower and centered around 30 microns. Contrastingly, micro cracks on the surface with no apparent delamination for P- Si / RTA-1000°C after 50 cycles was observed. The cross-sectional SEM images present an intact porous layer.

[0105] The larger islands and cracks that propagate in the porous layer to the silicon wafer are certainly the origin of a SEI growth that increases over the number of cycles. Here, it is interesting to note that i) nanostructuration is not sufficient to obtain significant performances both on the SEI growth and on the cycle life; ii) it exists a structure that can optimize both the SEI growth and the life cycle.

[0106] In conclusion of this screening of the performances for different architectures, it appears that P-Si / RTA-1000°C is promising both in terms of minimization of the SEI andstructural stability during lithiation / delithiation. In the following part, the electrochemical performances in terms of cycle life and high areal capacity levels of this specific sample are investigated.

[0107] Electrochemical galvanostatic and cycle life measurements on P-Si / RTA-1000°C were performed between 1 and 0.01 V vs. Li / Li+at a current density of 1 mA cm-2with discharge cut-off time of 3 h to reach 3 mAh cm-2.

[0108] The cycle life profile of P-Si / RTA-1000°C electrode shown in Fig. 11A exhibits an excellent cycling stability at high areal capacity of 3 mAh cm-2over 200 cycles with an average Coulombic efficiency of 99.3 % after the 1stcycle (which is considered as the prelithiation step) and 99.7 % after the first 10 cycles. A selection of charge / discharge curves is shown in Fig. 11 B showing usual lithiation / delithiation processes. It must be noted that, during the prelithiation (1stcycle) shown in Fig. 11 B, a plateau can be seen at 1.2 V followed by an immediate potential drop at 1 mAh cm'2. This plateau can be assigned to the decomposition of FEC associated to the reduction of impurities and surface chemistry as mentioned previously. After prelithiation, during the second cycle, a plateau at 0.2 V and the sudden decrease at 0.05 V indicate the presence of two reactions: 1) the production of amorphous Si alloy (a-LixSi), and 2) the formation of crystalline LiisSi4 alloy from lithiation of the a-LixSi.

[0109] Polarization obtained by the difference between the middle charge and discharge voltage shows a stability around 0.3 V over the 200 cycles with even a slight decrease after 50 cycles. This observation agrees with a stabilized SEI after the 50thcycle.

[0110] After 200 cycles, post-mortem SEM analysis was performed (Fig. 11C and 11 D). The top surface shows some large, buckled domains (tens of pm2) and some cracks (Fig. 11C). In cross-section images (Fig. 11 D), a difference in gray contrast can be noticed. It corresponds to a difference in composition and it indicates that two different phases exist: 1) a pure silicon, which appears lighter at the bottom, and 2) a Li-Si alloy, appearing darker at the top.

[0111] It appears that only a part of the porous layer is involved in the lithiation process. As approximately 14 microns of the porous layer seems unaffected, that indicates that 11 micronswas lithiated i.e., -44% of the porous layer was involved in the lithiation process. The dimension after lithiation being 26 microns, this gives approximately an expansion of 140% due to a cumulative irreversible expansion of 140%. This is due to irreversible morphological changes (cracks, SEI accumulation, etc.). It is worth noting that there is no delamination between the two types of porous layer (lithiated and non-lithiated). The lithiated layer show some internal cracks but no clear delamination can be considered, and the structure keeps its integrity even after 200 cycles.

[0112] To further test the stability of P-Si / RTA-1000°C, a variable capacity level (Q- evaluation) at constant current density of 1 mA cm'2but changing the duration of lithitation was conducted to examine if the sample can withstand high-capacity levels. As presented in Fig. 12A, the sample was subsequently subjected to 3, 5, 10 and 20 mAh cm'2for 5 cycles for each discharge capacity. Additional 5 cycles at 3 mAh cm'2were then performed to check the state of the battery.

[0113] The corresponding potential curves of the 1stcycle for each surface capacity are shown in Fig. 12B. The 2ndcycle of the first step at 3 mAh cm'2, i.e., after prelithiation, is also included. Typical Si cycling profiles can be observed and Fig. 12C displays the differential capacity curves for the 1stcycle of each step of Q-rate.

[0114] Similar characteristics to that of the previous lithiation / delithiation results mentioned above were observed. During lithiation for various capacity rates, peaks at 0.2 V and 0.1 V can be seen due to the nucleation process and the stepwise lithiation of c-Si leading to the formation of a-LixSi. At 0.05 V, a slight peak shift with the Q-rate, as shown in Fig. 12C (inset), can be noted in the region of c-l_ii5Si4 formation. It should be mentioned that the formation of c-l_ii5Si4 has been found to occur at around 50mV, but not specifically at 50mV. To prevent the formation of c-l_ii5Si4, a cut-off of 70mV is necessary. This shift can be explained by the particle size modification. This can also originate in a reduction of the polarization.

[0115] In the highest Q-rate evaluated, 20 mAh cm'2, a sharp cathodic peak at 0.2 V for the lithiation process is observed. A decrease in the intensity of these peaks can indicate a loss of active material involved in the reaction. In our case, the increase in peak intensity can be attributed to an increased amount of lithiated active material and to an incomplete delithiationprocess during previous cycles. This suggests that when lithiation is carried out at 20 mAh cm-2, a greater amount of silicon reacts due to the deeper lithiation into the porous layer, and most probably, to a lithiation of the wafer underneath.

[0116] In the case of delithiation, the sudden rise in potential at the beginning of the charging process, indicates a return to the amorphous state. Two broad peaks can be seen in the anodic process, which correspond to a single-phase reaction. It is the transformation from lithium rich amorphous LixSi to lithium less amorphous LixSi phase. There was no sign of a prominent anodic peak, which would have been present in a two-phase reaction from c-Lii5Si4 to a-Si.

[0117] It should be noted that as -44% of the porous layer is lithiated at 3 mAh cm'2, it is then expected that for 10 and 20 mAh cm'2, the lithiation reach the wafer underneath leading to potential degradation of the on-chip anode. Thus, post-mortem SEM images shown on Fig. 12D does not indicate any contrast of grey in the porous layer contrary to the previous section (Fig. 11 D). This suggests that the whole porous layer has been lithiated during the cycling. Several cracks are observed but their propagation stop at the interface between the porous layer and the bulk Si layer. This effect preserves the integrity of the sample without breaking in several parts. It must be noted that despite the deterioration of the porous layer, probably due to the large capacity levels, the cell is still running when the capacity level was reestablished at 3 mAh cm'2(Fig. 12A). The porous layer after lithiation measured 92 microns revealing an expansion of the porous layer of approximately 270 %.

[0118] These results indicate that this architecture based of a sandwich structure remains operative even after high-capacity levels and allows to mitigate the damage during cycling by confining the cracks inside the porous layer and keeping with excellent electrochemical behavior.

[0119] Several research investigations have been reported using Si-based anodes for applications in micro-LiBs. In Table 1 , the different capacities and the techniques used in Si electrode fabrication are listed. Our process and architecture detailed in this example reached 9 mAh cm'2without capacity fading after 200 cycles (Figs. 13A-B).

[0120] Table 1 Comparison of areal capacity (mAh cm-2) using Si as an anode for Li-ion microbatteriesEnd areal Initial areal capacity,o. , *■P y’ capacity, Si fabricationCycler 7mAh cm-2ProcessmAh cm-2electrochemical312 3 3 etching / RTA electrochemical50 6.24 6.24 etching / RTA electrochemical200 9 9 etching / RTA electrochemical1000 1 1 etching / RTA

[0121] The cycle life of the silicon electrodes is mostly dependent on the mechanical degradations induced during the electrochemical cycling. The large stresses related to the volume expansion explain why single-crystalline show mechanical breaking during the first cycles and why nanostructuration is helpful. During the lithiation on Si single crystal (c-Si), cracks are initiated at the surface during the first cycles. Then, the propagation is rapid, perpendicularly to the surface in the electrochemically amorphized Si (a-Si) until it reaches the a-Si / c-Si interface. Then, the cracks deviate along this interface causing delamination. As c- Si is a brittle material, the crack may still propagate and cross all the structure leading the wafer to break into pieces (see Fig. 8). Nanostructuration, with an amount of free volume, allows for volume expansion and therefore stress accommodation which reduces the probability to generate cracks. However, the results shown in the previous section highlights that nanostructuring is not sufficient or, at least, must be optimized. As a matter of fact, P-Si (RT) has the smallest pore size but does not show the best electrochemical and stabilityperformances. Thermal annealing and the induced modification of the structure play a key role in improving performances.

[0122] Recently, it has been proposed that the mechanical properties of the architecture play a significant role in the structural stability. Using nanoindentation techniques, it was found out that the best performing samples was the one with the highest Young modulus.

[0123] Therefore, following this example, nano-indentation tests have been performed on our samples. First, tests with spherical indenters shown a value of the Young modulus of 49±2 GPa, 58±1 , and 51 ±1 for P-Si (RT), P-Si / RTA-800°C and P-Si / RTA-1000°C, respectively. The value obtained for P-Si (RT) is in good agreement with the value expected for a 40% porous silicon. The value for P-Si / RTA-1000°C is also in the same range indicating that the closing of the surface porosity on a thickness of 1 pm does not significantly influence the nanoindentation measurements that probes much larger volume. From these results, it appears that the Young modulus is not a discriminating parameter in explaining the cycling stability. During nanoindentation tests, it was noticed that for P-Si (RT) and P-Si / RTA-800°C have a perfect elastic behaviour (no mark of the indenter, no hysteresis in the loading / unloading curves (Fig. 14) contrary to P-Si / RTA-1000°C.

[0124] Therefore, it then appears that P-Si / RTA-1000°C is a more damageable structure contrary to the two other samples that are more resistant. To further explore this observation, new nano-indentation tests in Berkovich configuration were performed to access the hardness i.e., the plastic behaviour of the three different samples. Results of the hardness as a function of the penetration depth (displacement of the indenter) are given in Fig. 15. The hardness of P-Si (RT) and P-Si / RTA-800°C ranges between 2.5 and 3 GPa and is rather constant with respect to the indenter displacement. The situation is different for P-Si / RTA-1000°C that exhibits a gradient of hardness along the depth. Near the surface the hardness is similar to the two other samples (~2 GPa) but with increasing depth the hardness first increases to ~2.6 over the first 500 nm before decreasing to 1 .7 GPa.

[0125] The evolution of the hardness with the penetrating depth suggests that the structure is not homogeneous and that the top layer plays a significant role in P-Si / RTA-1000°C. This layer of higher hardness corresponds to the densified layer obtained by surface annealing andobserved by SEM (Fig. 4) and which can be considered as a silicon thin film. In this case, the critical fracture stress, Oracture, increases as the film thickness decreases. According to the Griffith- Irwin relation, the critical fracture stress is given by:

[0127] where K is the fracture toughness (of the order of 1 MPa m in the case of single crystalline silicon) and d is the film thickness. Considering a film thickness of 1 m as observed on SEM images (Fig.4), afractureis then of the order of GPa which is the order of the maximum stress appearing during the lithiation. The same conclusions apply for if we consider a-Si as the fracture toughness is even larger in the amorphous state.

[0128] Therefore, cracks will have less propensity to propagate into the structure. It is established that cracks must propagate by ~5-8 pm in depth to allow deflection and delamination of the domains. In our case, to release the elastic energy the sandwich-like structure shows a collection of micro-cracks that do not propagate far enough to generate delamination as it can be observed on Fig. 10 on the top view of the P-Si / RTA-1000°C.

[0129] In addition, as the hardness decreases with the penetration depth, the RTA treatment did not only modify the surface (densification) but also the bulk structure. In particular, the top part (just underneath the surface) of the P-Si / RTA-1000°C shows a more heterogenous pore size distribution (Fig. 4). This heterogeneity may participate in the mechanical stability of the structure. For example, the elastic modulus of the arch nanostructure has been taken as the parameter governing the behaviour under lithiation. However, if the average Young modulus is higher for their best sample, it is also the one showing a much larger dispersion of this property compared to the other structure, indicating that the heterogeneity of the structure may be beneficial for a longer life cycle in LiBs. Indeed, in brittle materials, cracks propagate along the path of maximum strain energy release. However, this is mitigated by the nature of the microstructure of the materials. As a matter of fact, a crack propagates along a crystallographic axis but stops when it meets a sufficiently large obstacle, such as a sufficiently large pore that relaxes the stress concentration and can prevent the propagation.

[0130] Additional factors may also play a critical role, in particular, by considering the anisotropic growth of the lithiated silicon. It is now established that the expansion during lithiation of c-Si occurs preferentially in the <110> directions. The anisotropic growth can lead to the merging of nanostructures and generation of compressive stresses. In our case, the wafer is oriented along the <100> direction and it is well known that electrochemical etching preserves the crystalline orientation. Therefore, the tree-like structure obtained after etching is interesting. If the lithiated silicon come into contact, i.e., merging of the growing edges, this can generate internal compressive stresses in lateral directions that can lead to cracks. As shown in Fig. 4, annealing modified both the pore size and morphology. First, the tree-like (anisotropic) structure is replaced by more isotropic (spherical) pores. This change in the symmetry of the pores must influence the lithiation-induced internal stress field that must be more homogeneous and with less critical stresses, thus reducing the probability of cracks. The round corner of the micro-pillars can expand significantly less than the edges.

[0131] In this example, we have developed a novel silicon-based architecture as an anode for on-chip batteries. Its fabrication involved electrochemical etching followed by rapid thermal annealing processes. Surface transformation of the porous layer through sintering reorganizations during the annealing process leads to a sandwich-like structure. It consists in the combination of densified thin Si layer (~1 m) on top of a mesoporous layer (~25pm).

[0132] This architecture simultaneously demonstrates good electrochemical performance with apparent enhanced Coulombic efficiency and stable areal capacity combined with high mechanical stability during lithiation / delithiation processes. Thus, this design addresses the challenges for silicon anode commercialization.

[0133] If the general design appears clearly, several important insights are established. First, we show that the smallest pore size is not necessarily the best for stability. Pore size and shape are certainly important parameters. Indeed, the role of the porosity is to have significant free volume to absorb the swelling of the silicon during lithiation. However, more spherical pores can help to reduce the volume expansion by making the structure more isotropic and breaking the easiest path for crack propagation. Second, the size of the pores must be optimized to allow a homogeneous lithiation-induced expansion without merging and induced local stresses but also to act as potential obstacles for the crack propagation. Finally,one of the main information is that this is not the structure with the highest mechanical properties that provides the best performance.

[0134] The structure must be a composite of thin layer of silicon on top of an isotropic structure of porous layer. The top prevents the propagation of stress and reduce the specific surface of the electrode (to better control the SEI growth), while the porous allows for accommodating the volume expansion due to the lithiation.

[0135] Additionally, several parameters can be tuned to optimize the structure and to adapt it to the desired performances. For instance, the thickness of the porous layer (in this example fixed to 25 microns) can be increased for very high areal capacity (>10 mAh cm'2). This point allows adjusting the design to the requirements of the targeted microbatteries (compromise between the capacity and the thickness of the microbatteries).

[0136] Besides usage performances, method in designing the new structure of Si integrated two simple processes: electrochemical etching and rapid thermal annealing. This on-chip architecture considerably simplifies the fabrication process of batteries by eliminating some steps and downsizing the dimensions with a relative ease of implementation in microelectronics industry. Moreover, our novel structure brings new potentials in the design of new materials for microbatteries but can be extended to other applications in which surface area is a key concern.

[0137] In addition to the above, it was hypothesized that the thickness of the porous layer of the anode may have an influence of the overcall capacity of the anode. A rationale supporting this hypothesis was that since the porous layer is thicker, then more electrical charges could be available for current generation purposes. For instance, as the anode described above reached a capacity of 9 mAh cm-2with a porous layer having a thickness of 25 microns, another anode having a thicker porous layer was manufactured and tested. The porous layer of this other anode was set to 50 microns. Results showed that the capacity of this latter anode reached 20 mAh cm'2after 100 cycles, which confirmed the initial hypothesis. Accordingly, depending on the embodiment, it was found that one could modify the thickness of the porous layer based on a desired capacity outcome. For instance, if an anode with a capacity of about 9 mAh cm'2is desired, then the thickness of the porous layer can be set to25 microns. However, if an anode with a capacity of about 20 mAh cm-2is desired, then the thickness of the porous layer can be set to 50 microns. A regression or a reference database associating porous layer thicknesses to corresponding anode capacities could be made based on experimental results or simulation, depending on the embodiment. In any case, prior to the actual step of etching the monocrystalline silicon wafer, a desired anode capacity can be selected and then associated to a corresponding a porous layer thickness using the regression or reference database introduced above. In these embodiments, the etching step can be performed until (or such that) the thickness of the porous layer reaches the porous layer thickness. For instance, in embodiments where a desired anode capacity ranges between 3 mAh cm'2and 30 mAh cm'2, the porous layer can have a thickness varying between 10 microns and 75 microns. In other embodiments the porous layer has a thickness above 45 microns.

[0138] As can be understood, the examples described above and illustrated are intended to be exemplary only. The scope is indicated by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. An anode for a battery, the anode comprising: a monocrystalline silicon wafer having a porous layer, said porous layer having a plurality of pillars extending in a direction substantially normal to said monocrystalline silicon wafer, said plurality of pillars defining a plurality of pores interspersed between said plurality of pillars, and ending in respective tip portions, said tip portions of said plurality of pillars forming an anode surface sitting on said plurality of pillars and closing said plurality of pores.

2. The anode of claim 1 wherein said anode surface has a plurality of crack propagation blockers made integral to said anode surface.

3. The anode of claim 2 wherein said crack propagation blockers have a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns.

4. The anode of claim 2 wherein said crack propagation blockers recess from said anode surface by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

5. The anode of claim 1 wherein said porous layer has a hardness gradient extending along a thickness orientation of said porous layer.

6. The anode of claim 5 wherein said hardness gradient includes a first layer portion having a first hardness value, and a second layer portion deeper than said first layer portion, said second layer portion having a second hardness value below said first hardness value.

7. The anode of claim 6 wherein said first hardness value is above a first hardness threshold and said second hardness value is below a second hardness threshold.

8. The anode of claim 6 wherein said first hardness value is above 2.5 GPa, said second hardness value below 2.5 GPa, preferably below 2.0 GPa and most preferably below 1.8 GPa.

9. The anode of claim 5 wherein said hardness gradient has a hardness profile extending along said thickness orientation, said hardness profile increasing to a maximal hardness value at a shallow depth from said anode surface and then decreasing below a hardness threshold at a deeper depth.

10. The anode of claim 1 wherein said pores have an isotropic structure.

11. The anode of claim 10 wherein said isotropic structure defines pores of pseudo- spherical shapes.

12. The anode of claim 1 wherein said tip portions at least partially merge together to form said anode surface.

13. The anode of claim 1 wherein said direction corresponds to a crystalline orientation of said monocrystalline silicon wafer.

14. The anode of claim 1 wherein said porous layer has a thickness ranging between 10 microns and 75 microns.

15. The anode of claim 1 wherein said porous layer has a thickness above 45 microns.

16. A method of manufacturing an anode for a lithium-ion battery, the method comprising: etching a monocrystalline silicon wafer, said etching creating a plurality of pillars extending in a direction substantially normal to said monocrystalline silicon wafer, said plurality of pillars defining a plurality of pores interspersed between said plurality of pillars, said pillars and pores forming a porous layer within said monocrystalline silicon wafer; and heating the porous layer above a given temperature threshold, said heating causing tip portions of said pillars to merge to one another, thereby forming an anode surface sitting on said pillars and closing said pores.

17. The method of claim 16 wherein said given temperature threshold is above 900°C, preferably above 950°C and most preferably above 1000°C.

18. The method of claim 16 wherein said heating causes forming a plurality of crack propagation blockers made integral to said anode surface, said crack propagation blockers having a dimension of at most 10 microns, preferably at most 5 microns and most preferably at most 2 microns, and said crack propagation blockers recessing from said anode surface by less than 8 microns, preferably less than 5 microns, and most preferably less than 3 microns.

19. The method of claim 16 wherein said heating causes a hardness profile along a thickness orientation of said monocrystalline silicon wafer, said hardness profile increasing to a maximal hardness value at a shallow depth from said anode surface and then decreasing below a hardness threshold at a deeper depth.

20. The method of claim 16 wherein said heating causes transforming said pillars into isotropically-shaped pillars.

21. The method of claim 16 wherein said porous layer has a thickness ranging between 10 microns and 75 microns.

22. The method of claim 16 further comprising, prior to said etching, selecting a desired anode capacity and associating the desired anode capacity to a porous layer thickness using reference data, said etching performed until the porous layer reaches the porous layer thickness.

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