Reset circuit, daughter board initialization method, and display device

Abstract

A reset circuit, a daughter board initialization method, and a display device. The reset circuit comprises an output control module (20) and at least one sampling module (10). The sampling module (10) is connected to a daughter board in one-to-one correspondence. The at least one sampling module (10) is configured to collect power-on information of a circuit channel which is the latest in a power-on time sequence in the daughter board. A control end of the output control module (20) is connected to an output end of the at least one sampling module (10), an input end of the output control module (20) is connected to a power supply voltage, and an output end of the output control module (20) is connected to a reset end of a mainboard. The output control module (20) is configured to output a reset signal to the reset end of the mainboard on the basis of the power-on information so as to control the mainboard to reset, so that the mainboard outputs a complete driving time sequence signal to the daughter board.

Description

Reset circuit, daughter board initialization method and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 5, 2023, with application number 202311662590.X. The entire contents of this application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a reset circuit, a sub-board initialization method, and a display device. Background Art

[0003] With the continuous development of display technology, micro light emitting diodes (Micro-LEDs) are widely used in the display field due to their advantages such as wide color gamut, fast response speed, high brightness and long life.

[0004] Due to the limitations of chip functions between the Micro-LED driver board and the control board, if there is no support for relevant communication protocols, in actual applications, the power supply system of the control board will not start stably, resulting in poor screen display. Summary of the Invention

[0005] The embodiments of the present application provide a reset circuit, a method for initializing a daughter board, and a display device, which can enable a main board and a daughter board to operate normally without the support of a communication protocol.

[0006] According to one aspect of the present application, a reset circuit is provided, comprising: an output control module and at least one sampling module, wherein the sampling modules are connected to the daughter boards in a one-to-one correspondence, and at least one of the sampling modules is configured to collect power-on information of a circuit channel with the latest power-on sequence in the daughter board;

[0007] The control end of the output control module is connected to the output end of the at least one sampling module, the input end of the output control module is connected to the power supply voltage, and the output end of the output control module is connected to the reset end of the mainboard. The output control module is configured to output a reset signal to the reset end of the mainboard according to the power-on information to control the mainboard to reset, so that the mainboard outputs a complete driving timing signal to the daughter board.

[0008] Optionally, the sampling module includes a first switch unit, a first resistor, a second resistor and a third resistor;

[0009] The first end of the first resistor is the input end of the sampling module and is connected to the circuit channel with the latest power-on sequence in the daughter board. The second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded.

[0010] The control end of the first switch unit is connected to the second end of the first resistor, the first end of the first switch unit is connected to the first end of the first resistor, the second end of the first switch unit is connected to the first end of the third resistor, and the second end of the third resistor is the output end of the sampling module;

[0011] Optionally, the first switching unit includes a first transistor, the base of the first transistor is connected to the second end of the first resistor, the first electrode of the first transistor is connected to the first end of the first resistor, and the second electrode of the first transistor is connected to the first end of the third resistor.

[0012] Optionally, the sampling module further includes a first capacitor, and the first capacitor is connected in parallel with the second resistor.

[0013] Optionally, the output control module includes a second switch unit, a fourth resistor and a second capacitor;

[0014] The control end of the second switch unit is the control end of the output control module, the first end of the second switch unit is connected to the power end of the mainboard via the fourth resistor, the second end of the second switch unit is grounded, the first end of the second switch unit is the output end of the output control module, the first electrode of the second capacitor is connected to the first end of the second switch unit, and the second electrode of the second capacitor is grounded;

[0015] Optionally, the output control module further includes a fifth resistor, a first end of the fifth resistor is connected to the control end of the second switch unit, and a second end of the fifth resistor is grounded;

[0016] Optionally, the second switch unit includes a second transistor, the base of the second transistor is the control end of the second switch unit, the first pole of the second transistor is the first end of the second switch unit, and the second pole of the second transistor is the second end of the second switch unit.

[0017] Optionally, the output control module includes a second switch unit, a third switch unit, a fourth resistor, a sixth resistor and a second capacitor;

[0018] The control end of the second switch unit is the control end of the output control module, the first end of the second switch unit is connected to the power end of the mainboard via the fourth resistor, the second end of the second switch unit is grounded, the control end of the third switch unit is connected to the first end of the second switch unit, the first end of the third switch unit is connected to the power end of the mainboard via the sixth resistor, the second end of the third switch unit is grounded, the first end of the third switch unit is the output end of the output control module, the first electrode of the second capacitor is connected to the first end of the third switch unit, and the second electrode of the second capacitor is grounded;

[0019] Optionally, the output control module further includes a fifth resistor, a first end of the fifth resistor is connected to the control end of the second switch unit, and a second end of the fifth resistor is grounded;

[0020] Optionally, the second switch unit includes a second transistor, and the third switch unit includes a third transistor. The base of the second transistor is the control end of the second switch unit, the base of the third transistor is the control end of the third switch unit, the first pole of the second transistor is the first end of the second switch unit, the second pole of the second transistor is the second end of the second switch unit, the first pole of the third transistor is the first end of the third switch unit, and the second pole of the third transistor is the second end of the third switch unit.

[0021] Optionally, the polarity of the first transistor included in the sampling module is opposite to the polarity of the second transistor included in the second switch unit.

[0022] According to another aspect of the present application, a method for initializing a daughter board is provided, comprising:

[0023] Controlling the sampling module to collect power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board;

[0024] The control output control module outputs a reset signal to the reset terminal of the mainboard according to the power-on information to control the mainboard to reset;

[0025] After the mainboard is reset, the mainboard is controlled to output a complete driving timing signal to the daughterboard.

[0026] Optionally, the controlling output control module outputs a reset signal to a reset terminal of the mainboard according to the power-on information to control the mainboard to reset, including:

[0027] Before the voltage of the circuit channel with the latest power-on timing in the daughter board reaches the starting voltage of the sampling module, the sampling module is controlled to output a sampling signal, and the output control module is controlled to output a reset signal to the reset terminal of the main board according to the sampling signal, so as to control the main board to reset;

[0028] When the voltage of the circuit channel with the latest power-on sequence in the daughter board reaches the starting voltage of the sampling module, the sampling module is controlled not to output the sampling signal, and the output control module is controlled to stop outputting the reset signal, and the main board completes the reset.

[0029] After the control sampling module collects the power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board, the method further includes:

[0030] Replace the daughter board and control the daughter board to power on again.

[0031] Optionally, after replacing the daughter board and controlling the daughter board to be powered on again, the method further includes:

[0032] The sampling module is controlled to re-collect the power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board.

[0033] According to another aspect of the present application, a display device is provided. The display device includes a plurality of sub-boards and the reset circuit provided in any embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic structural diagram of a reset circuit provided in an embodiment of the present application;

[0035] FIG2 is a schematic structural diagram of another reset circuit provided in an embodiment of the present application;

[0036] FIG3 is a schematic structural diagram of another reset circuit provided in an embodiment of the present application;

[0037] FIG4 is a schematic structural diagram of another reset circuit provided in an embodiment of the present application;

[0038] FIG5 is a schematic diagram of the structure of another reset circuit provided in an embodiment of the present application;

[0039] FIG6 is a flowchart of a method for initializing a daughter board provided in an embodiment of the present application;

[0040] FIG7 is a flowchart of another method for initializing a daughter board provided in an embodiment of the present application;

[0041] FIG8 is a flowchart of another method for initializing a daughter board provided in an embodiment of the present application;

[0042] FIG9 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus comprising a series of steps or units.

[0044] FIG1 is a schematic diagram of the structure of a reset circuit provided in an embodiment of the present application. Referring to FIG1 , the reset circuit provided in an embodiment of the present application includes: an output control module 20 and at least one sampling module 10. The sampling modules 10 are connected to the daughter boards in a one-to-one correspondence. The sampling modules 10 are configured to collect power-on information of the circuit channel with the latest power-on sequence in the daughter board.

[0045] The control end of the output control module 20 is connected to the output end of at least one sampling module 10, the input end of the output control module 20 is connected to the power supply voltage, and the output end of the output control module 20 is connected to the reset end of the mainboard. The output control module 20 is configured to output a reset signal to the reset end of the mainboard based on the power-on information of the circuit channel with the latest power-on timing in the daughter board, so as to control the mainboard to complete the reset, so that the mainboard outputs a complete drive timing signal to the daughter board.

[0046] Optionally, the main board may be a driver board including a driver chip; the sub-board may be a control board including multiple control modules, which are powered on in a predetermined order. In this embodiment, the circuit path with the latest power-on sequence in the sub-board is used as a sampling point, and the sampling module 10 collects power-on information of the circuit path with the latest power-on sequence in the sub-board to ensure that all modules in the sub-board can start normally.

[0047] The control end of the output control module 20 is connected to the output ends of multiple sampling modules 10. The sampling modules 10 monitor the power-on information of the circuit channel with the latest power-up sequence in the daughter board in real time. When the circuit channel with the latest power-up sequence in the daughter board is powered on, the output control module 20 provides a reset signal to the reset end of the main board based on the signal output by the sampling module 10, thereby controlling the driver chip in the main board to reset. After the driver chip in the main board completes the reset process based on the received reset signal, it outputs a complete drive timing signal to the daughter board, thereby controlling the daughter board to operate according to the newly received complete drive timing signal to ensure normal image display. After the circuit channel with the latest power-up sequence in the daughter board is powered on, the output control module 20 can stop providing the reset signal to the reset end of the main board.

[0048] There can be multiple sampling modules 10 to sample different sub-boards (sub-board 1, sub-board 2, ..., sub-board n). The multiple sampling modules 10 are independent of each other and do not affect each other. Specifically, the sampling module 10 corresponding to at least one sub-board can be selected for operation as needed, while the remaining sampling modules 10 that are inoperative remain unaffected.

[0049] In this embodiment of the present application, the circuit channel with the latest power-up sequence in the daughterboard is used as a sampling point. The sampling module 10 monitors the power-up information of the corresponding sampling point in real time. When the circuit channel with the latest power-up sequence in the daughterboard is powered on, the sampling module 10 outputs a pulse signal to the control terminal of the output control module 20. The output control module 20 transmits a reset signal to the reset terminal of the mainboard based on the received pulse signal to control the mainboard to reset, thereby causing the mainboard to re-output a complete drive timing signal to the daughterboard. Even in the absence of a communication protocol between the mainboard and the daughterboard, this solution can achieve signal transmission between the mainboard and the daughterboard through the sampling, feedback, and reset functions of the reset circuit. By resetting the mainboard, the daughterboard drive timing is initialized to ensure that multiple modules on the daughterboard can start normally and stably, preventing poor display problems caused by unstable power system startup on the daughterboard.

[0050] For pre-maintenance products, hot-swappable devices may be used. In this embodiment, after the sampling module 10 detects the power-on information (voltage) of the circuit path that powered on the latest among multiple daughterboards, at least some of the daughterboards are replaced, and the replaced daughterboards are powered on again. The power-on information of the circuit path that powered on the latest among the multiple daughterboards is then detected again. When the circuit path with the latest power-on sequence among the daughterboards is powered on, the output control module 20 transmits a reset signal to the reset terminal of the mainboard based on the pulse signal output by the sampling module 10, thereby controlling the mainboard to reset. Therefore, the implementation method provided in this embodiment is still applicable to hot-swappable daughterboards.

[0051] Optionally, the power supply voltage connected to the input terminal of the output control module 20 may be the voltage output by the power supply of the mainboard.

[0052] In an optional implementation provided in this embodiment, the mainboard can be reset in response to a low-level reset signal output by the output control module 20. Figure 2 is a structural schematic diagram of another reset circuit provided in an embodiment of the present application, and Figure 3 is a structural schematic diagram of another reset circuit provided in an embodiment of the present application, specifically a schematic diagram of the reset circuit shown in Figure 1 refined into a device structure. Among them, Figure 2 is a structural schematic diagram including a single sampling module 10, and Figure 3 is a structural schematic diagram including multiple sampling modules 10. Referring to Figures 1 to 3, the sampling module 10 includes a first switching unit 101, a first resistor R1, a second resistor R2 and a third resistor R3. The first end of the first resistor R1 is the input end of the sampling module 10, and is connected to the circuit channel with the latest power-on sequence in the sub-board. The second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded;

[0053] The control end of the first switch unit 101 is connected to the second end of the first resistor R1, the first end of the first switch unit 101 is connected to the first end of the first resistor R1, the second end of the first switch unit 101 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is the output end of the sampling module 10.

[0054] The output control module 20 includes a second switch unit 201, a fourth resistor R4 and a second capacitor C2. The control end of the second switch unit 201 is the control end of the output control module 20. The first end of the second switch unit 201 is connected to the power end of the mainboard via the fourth resistor R4. The second end of the second switch unit 201 is grounded. The first end of the second switch unit 201 is the output end of the output control module 20. The first pole of the second capacitor C2 is connected to the first end of the second switch unit 201, and the second pole of the second capacitor C2 is grounded.

[0055] Optionally, each sampling module 10 includes a first switch unit 101, a first resistor R1, a second resistor R2, and a third resistor R3, wherein the first switch unit 101 may include a first transistor Q1. For example, the first sampling module 10 includes a first first transistor Q1(1), a first first resistor R1(1), a first second resistor R2(1), and a first third resistor R3(1), and the nth sampling module 10 includes an nth first transistor Q1(n), an nth first resistor R1(n), an nth second resistor R2(n), and an nth third resistor R3(n).

[0056] Here, terminal A1 is the input terminal of sampling module 10, used to monitor the power-on information of the circuit channel with the latest power-on sequence in the daughterboard. Terminal B is the power terminal, which can be connected to the power terminal of the mainboard. Terminal D is the output terminal of output control module 20 (i.e., the output terminal of the reset circuit), which is connected to the reset terminal of the mainboard.

[0057] Taking the reset circuit shown in FIG2 as an example, which includes a single sampling module 10, during power-up, the voltage at sampling point A1 is an instantaneous voltage. The first resistor R1 and the second resistor R2 are used to set the delay time for A1 to rise to the startup voltage of the sampling module 10. Different startup voltages can be adjusted using the first resistor R1 and the second resistor R2. The voltage at the base of the first transistor Q1 is [r2 / (r1+r2)]*VA1, where r1 is the resistance of the first resistor R1, r2 is the resistance of the second resistor R2, and VA1 is the voltage at sampling point A1.

[0058] At the initial power-up moment, that is, before sampling point A1 reaches the startup voltage of sampling module 10, the voltage difference between terminal A1 and the base of first transistor Q1 is greater than the threshold voltage of first transistor Q1, and first transistor Q1 is turned on. Because the first electrode of first transistor Q1 is connected to terminal A1, the voltage divider of third resistor R3 turns on second transistor Q2, and the first electrode of second transistor Q2 is pulled low. In other words, output control module 20 transmits a low-level reset signal to the reset terminal of the mainboard, resetting the mainboard.

[0059] As the voltage at sampling point A1 increases, when sampling point A1 reaches the startup voltage of sampling module 10, the voltage difference between A1 and the base of first transistor Q1 becomes less than or equal to the threshold voltage of first transistor Q1, causing first transistor Q1 to turn off. Consequently, second transistor Q2 turns off, and the pull-up action of fourth resistor R4 pulls the first electrode of second transistor Q2 high. This means that output control module 20 stops transmitting the reset signal to the reset terminal of the mainboard, and the mainboard completes the reset. By adjusting the capacitance of second capacitor C2, the reset delay can be adjusted to improve system stability.

[0060] In this embodiment, the signal output by the sampling module 10 is a pulse signal. Within the effective pulse width of the pulse signal, the output control module 20 outputs a reset signal to reset the mainboard; when power-on is completed, the level of the output signal of the output control module 20 jumps, and the mainboard reset is completed, thereby completing the reset operation.

[0061] Alternatively, with continued reference to FIG2 , the base of the first transistor Q1 is connected to the second end of the first resistor R1, the first electrode of the first transistor Q1 is connected to the first end of the first resistor R1, and the second electrode of the first transistor Q1 is connected to the first end of the third resistor R3. The base of the second transistor Q2 is the control end of the second switch unit 201, the first electrode of the second transistor Q2 is the first end of the second switch unit 201, and the second electrode of the second transistor Q2 is the second end of the second switch unit 201.

[0062] Optionally, the output control module 20 further includes a fifth resistor R5, a first end of which is connected to the control end of the second switch unit 201, and a second end of which is grounded. By providing the fifth resistor R5, the base of the second transistor Q2 can be pulled low when the first transistor Q1 is turned off, thereby ensuring that the second transistor Q2 is reliably turned off and preventing the motherboard from resetting.

[0063] FIG4 is a schematic diagram of the structure of another reset circuit provided in an embodiment of the present application. Referring to FIG4 , based on the above embodiment, the sampling module 10 further includes a first capacitor C1, which is connected in parallel with the second resistor R2. The first capacitor C1 is used to adjust the pulse width of the pulse signal output by the first transistor Q1, that is, to adjust the reset time, to adapt to the reset requirements in different application scenarios.

[0064] In another optional implementation provided by this embodiment, the mainboard can also be reset in response to a high-level reset signal output by the output control module 20. Figure 5 is a schematic structural diagram of another reset circuit provided in an embodiment of the present application. Referring to Figure 5, on the basis of the above embodiments, the output control module 20 optionally includes a second switch unit 201, a third switch unit 202, a fourth resistor R4, a sixth resistor R6, and a second capacitor C2. The control end of the second switch unit 201 is the control end of the output control module 20. The first end of the second switch unit 201 is connected to the power supply end of the mainboard via the fourth resistor R4. The second end of the second switch unit 201 is grounded. The control end of the third switch unit 202 is connected to the first end of the second switch unit 201. The first end of the third switch unit 202 is connected to the power supply end of the mainboard via the sixth resistor R6. The second end of the third switch unit 202 is grounded. The first end of the third switch unit 202 is the output end of the output control module. The first electrode of the second capacitor C2 is connected to the first end of the third switch unit 202, and the second electrode of the second capacitor C2 is grounded.

[0065] Among them, the second switch unit 201 includes a second transistor Q2, the third switch unit 202 includes a third transistor Q3, the base of the second transistor Q2 is the control end of the second switch unit 201, the base of the third transistor Q3 is the control end of the third switch unit 202, the first pole of the second transistor Q2 is the first end of the second switch unit 201, the second pole of the second transistor Q2 is the second end of the second switch unit 201, the first pole of the third transistor Q3 is the first end of the third switch unit 202, and the second pole of the third transistor Q3 is the second end of the third switch unit 202.

[0066] At the initial power-on moment, i.e., before sampling point A1 reaches the startup voltage of sampling module 10, the voltage difference between terminal A1 and the base of first transistor Q1 is greater than the threshold voltage of first transistor Q1, turning on first transistor Q1. Because the first electrode of first transistor Q1 is connected to terminal A1, the voltage divider of third resistor R3 turns on second transistor Q2, pulling the base of third transistor Q3 low, turning off third transistor Q3. Pull-up action of sixth resistor R6 pulls the first electrode of third transistor Q3 high, causing output control module 20 to transmit a high-level reset signal to the reset terminal of the mainboard, resetting the mainboard.

[0067] As the voltage at sampling point A1 increases, when sampling point A1 reaches the startup voltage of sampling module 10, the voltage difference between A1 and the base of first transistor Q1 becomes less than or equal to the threshold voltage of first transistor Q1, and first transistor Q1 turns off. Consequently, second transistor Q2 turns off. Under the pull-up action of fourth resistor R4, the first electrode of second transistor Q2 is pulled high, turning on third transistor Q3. The first electrode of third transistor Q3 is pulled low, and the output control module 20 transmits a low-level signal to the reset terminal of the mainboard, completing the mainboard reset. Adjusting the capacitance of second capacitor C2 can adjust the reset delay time to improve system stability.

[0068] Optionally, the output control module 20 further includes a fifth resistor R5, a first end of which is connected to the control end of the second switch unit 201, and a second end of which is grounded. By providing the fifth resistor R5, the base of the second transistor Q2 can be pulled low when the first transistor Q1 is turned off, thereby ensuring that the second transistor Q2 is reliably turned off and preventing the motherboard from resetting.

[0069] The embodiment of the present application resets the mainboard by controlling the output control module 20 to output a high-level or low-level reset signal. When the power is turned on, the signal level output by the output control module 20 is flipped, thereby completing the reset operation. In the absence of a communication protocol, this ensures that the daughter board can work normally.

[0070] In the sampling modules 10 corresponding to the multiple daughter boards, after power-on, the first transistor Q1 is in the off state to isolate the sampling point signals of the multiple daughter boards from each other, prevent interference, and enable each sampling channel to work independently.

[0071] Optionally, in each of the above embodiments, the polarities of the first transistor Q1 and the second transistor Q2 are opposite. For example, the first transistor Q1 is a PNP transistor, and the second transistor Q2 is an NPN transistor.

[0072] An embodiment of the present application also provides a method for initializing a daughter board, which uses the reset circuit provided in any embodiment of the present application to complete the power-on initialization process of the daughter board, so that the daughter board can control the panel to display the image normally according to the received complete power-on timing sequence.

[0073] FIG6 is a flow chart of a method for initializing a daughter board according to an embodiment of the present application. Referring to FIG6 , the method for initializing the daughter board includes:

[0074] S110 , controlling the sampling module to collect power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board.

[0075] S120 , controlling the output control module to output a reset signal to the reset terminal of the mainboard according to the power-on information, so as to control the mainboard to reset.

[0076] S130: After the mainboard is reset, the mainboard is controlled to output a complete driving timing signal to the daughterboard.

[0077] The daughterboard initialization method provided in an embodiment of the present application uses the circuit channel with the latest power-on sequence in the daughterboard as a sampling point. The sampling module 10 monitors the power-on information of the corresponding sampling point in real time. When the circuit channel with the latest power-on sequence in the daughterboard is powered on, the sampling module 10 outputs a pulse signal to the control terminal of the output control module 20. The output control module 20 transmits a reset signal to the reset terminal of the mainboard based on the received pulse signal to control the mainboard to reset, thereby causing the mainboard to re-output a complete drive timing signal to the daughterboard. Even in the absence of a communication protocol between the mainboard and the daughterboard, this method can achieve signal transmission between the mainboard and the daughterboard through the sampling, feedback, and reset functions of the reset circuit. The daughterboard drive timing is initialized by resetting the mainboard to ensure that each module of the daughterboard can start normally and stably, and to prevent poor display problems caused by unstable power system startup of the daughterboard.

[0078] Optionally, FIG7 is a flowchart of another method for initializing a daughter board provided in an embodiment of the present application. Referring to FIG7 , step S120 specifically includes:

[0079] S1201. Before the voltage of the circuit channel with the latest power-on sequence in the daughter board reaches the starting voltage of the sampling module, control the sampling module to output a sampling signal, and control the output control module to output a reset signal to the reset terminal of the main board according to the sampling signal to control the main board to reset.

[0080] S1202: When the voltage of the circuit channel with the latest power-on sequence in the daughter board reaches the starting voltage of the sampling module, the sampling module is controlled not to output the sampling signal, and the output control module is controlled to stop outputting the reset signal, and the main board completes the reset.

[0081] The specific working process of the method can refer to the relevant description of Figures 2 to 5 in the above embodiments, which will not be repeated here. It has the same beneficial effects as the above embodiments.

[0082] Optionally, FIG8 is a flowchart of another method for initializing a daughter board provided in an embodiment of the present application. Referring to FIG8 , the method includes:

[0083] S110 , controlling the sampling module to collect power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board.

[0084] S210: Replace the daughter board and power on the control daughter board again.

[0085] S110 ′: Control the sampling module to re-collect the power-on information of the circuit channel with the latest power-on sequence in the corresponding daughter board.

[0086] S120 , controlling the output control module to output a reset signal to the reset terminal of the mainboard according to the power-on information, so as to control the mainboard to reset.

[0087] S130: After the mainboard is reset, the mainboard is controlled to output a complete driving timing signal to the daughterboard.

[0088] The method can be applied to the hot-swap situation in the front maintenance product. When the power-on information (voltage) of the circuit channel that is powered on last among multiple daughter boards is detected by the sampling module 10, at least part of the daughter boards are replaced, and the replaced daughter boards are powered on again, and the power-on information of the circuit channel that is powered on last among the multiple daughter boards is detected again. When the circuit channel with the latest power-on timing in the daughter board is powered on, the output control module 20 transmits a reset signal to the reset end of the main board according to the pulse signal output by the sampling module 10, controls the main board to reset, and enables the daughter board to receive a complete drive timing signal.

[0089] Optionally, an embodiment of the present application further provides a display device, which includes multiple sub-boards and the reset circuit provided by any of the above embodiments, and the multiple sub-boards are electrically connected to the reset circuit. Figure 9 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in Figure 9, the display device is spliced ​​together by multiple sub-boards. The display device 200 can be, for example, a television, or a flat-panel, as well as a large-sized electronic device such as an in-vehicle display or a conference display. Since the display device includes the reset circuit provided by any embodiment of the present application, the display device provided by the embodiment of the present application also has the beneficial effects described in any embodiment of the present application.

Claims

1. A reset circuit, comprising: An output control module and at least one sampling module, wherein the sampling modules are connected to the sub-boards in a one-to-one correspondence, and at least one of the sampling modules is configured to collect power-on information of a circuit channel having the latest power-on timing in the corresponding sub-board; The control end of the output control module is connected to the output end of the at least one sampling module, the input end of the output control module is connected to the power supply voltage, the output end of the output control module is connected to the reset end of the mainboard, and the output control module is configured to output a reset signal to the reset end of the mainboard according to the power-on information to control the mainboard to reset, so that the mainboard outputs a complete driving timing signal to the sub-board.

2. The reset circuit according to claim 1, wherein: The sampling module includes a first switch unit, a first resistor, a second resistor and a third resistor; The first end of the first resistor is the input end of the sampling module, connected to the circuit channel with the latest power-on timing in the sub-board, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The control end of the first switch unit is connected to the second end of the first resistor, the first end of the first switch unit is connected to the first end of the first resistor, the second end of the first switch unit is connected to the first end of the third resistor, and the second end of the third resistor is the output end of the sampling module.

3. The reset circuit according to claim 2, wherein: The first switch unit includes a first transistor, a base of the first transistor is connected to the second end of the first resistor, a first electrode of the first transistor is connected to the first end of the first resistor, and a second electrode of the first transistor is connected to the first end of the third resistor.

4. The reset circuit according to claim 2 or 3, wherein: The sampling module further includes a first capacitor, which is connected in parallel with the second resistor.

5. The reset circuit according to claim 1, wherein: The output control module includes a second switch unit, a fourth resistor and a second capacitor; The control end of the second switch unit is the control end of the output control module, the first end of the second switch unit is connected to the power end of the mainboard via the fourth resistor, the second end of the second switch unit is grounded, the first end of the second switch unit is the output end of the output control module, the first pole of the second capacitor is connected to the first end of the second switch unit, and the second pole of the second capacitor is grounded.

6. The reset circuit according to claim 5, wherein: The output control module further includes a fifth resistor, a first end of the fifth resistor is connected to the control end of the second switch unit, and a second end of the fifth resistor is grounded.

7. The reset circuit according to claim 5, wherein: The second switch unit includes a second transistor, a base of the second transistor is a control end of the second switch unit, a first pole of the second transistor is a first end of the second switch unit, and a second pole of the second transistor is a second end of the second switch unit.

8. The reset circuit according to claim 1, wherein: The output control module includes a second switch unit, a third switch unit, a fourth resistor, a sixth resistor and a second capacitor; The control end of the second switch unit is the control end of the output control module, the first end of the second switch unit is connected to the power supply end of the mainboard via the fourth resistor, the second end of the second switch unit is grounded, the control end of the third switch unit is connected to the first end of the second switch unit, the first end of the third switch unit is connected to the power supply end of the mainboard via the sixth resistor, the second end of the third switch unit is grounded, the first end of the third switch unit is the output end of the output control module, the first pole of the second capacitor is connected to the first end of the third switch unit, and the second pole of the second capacitor is grounded.

9. The reset circuit according to claim 8, wherein: The output control module further includes a fifth resistor, a first end of the fifth resistor is connected to the control end of the second switch unit, and a second end of the fifth resistor is grounded.

10. The reset circuit according to claim 8, wherein: The second switch unit includes a second transistor, and the third switch unit includes a third transistor. The base of the second transistor is the control end of the second switch unit, the base of the third transistor is the control end of the third switch unit, the first pole of the second transistor is the first end of the second switch unit, the second pole of the second transistor is the second end of the second switch unit, the first pole of the third transistor is the first end of the third switch unit, and the second pole of the third transistor is the second end of the third switch unit.

11. The reset circuit according to claim 7 or 10, wherein: The polarity of the first transistor included in the sampling module is opposite to the polarity of the second transistor included in the second switch unit.

12. A method for initializing a daughter board, comprising: Controlling the sampling module to collect power-on information of the circuit channel with the latest power-on timing in the corresponding sub-board; The control output control module outputs a reset signal to the reset terminal of the mainboard according to the power-on information, so as to control the mainboard to reset; After the mainboard is reset, the mainboard is controlled to output a complete driving timing signal to the sub-board.

13. The method for initializing a daughter board according to claim 12, wherein: The control output control module outputs a reset signal to the reset terminal of the mainboard according to the power-on information to control the mainboard to reset, including: Before the voltage of the circuit channel with the latest power-on timing in the sub-board reaches the starting voltage of the sampling module, the sampling module is controlled to output a sampling signal, and the output control module is controlled to output a reset signal to the reset terminal of the main board according to the sampling signal, so as to control the main board to reset; When the voltage of the circuit channel with the latest power-on timing in the daughter board reaches the starting voltage of the sampling module, the sampling module is controlled not to output the sampling signal, the output control module is controlled to stop outputting the reset signal, and the main board completes the reset.

14. The method for initializing a daughter board according to claim 12, after the control sampling module collects power-on information of the circuit channel with the latest power-on timing in the corresponding daughter board, the method further comprises: Replace the daughter board and control the daughter board to power on again.

15. The method for initializing a daughter board according to claim 14, after replacing the daughter board and controlling the daughter board to be powered on again, the method further comprises: The sampling module is controlled to re-collect the power-on information of the circuit channel with the latest power-on timing in the corresponding sub-board.

16. A display device, comprising a plurality of sub-boards and a reset circuit as claimed in any one of claims 1 to 11, wherein the plurality of sub-boards are electrically connected to the reset circuit.

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