Display panel and preparation method therefor, and display apparatus

Abstract

The present application relates to the technical field of displays. Provided are a display panel and a preparation method therefor, and a display apparatus. The display panel comprises a first display area and at least one second display area, wherein the transmittance of the second display area is greater than that of the first display area, the first display area comprises a plurality of first sub-pixels arranged in an array, the second display area comprises a plurality of second sub-pixels arranged in an array, each first sub-pixel comprises a first pixel circuit, each second sub-pixel comprises a second pixel circuit, and the transmittance of the second pixel circuit is greater than that of the first pixel circuit. The display panel is applicable to the preparation of a display apparatus having an under-display facial recognition and / or under-display camera function.

Description

Display panel, manufacturing method thereof, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 4, 2023, with application number 202311650046.3 and titled “A display panel, its preparation method, and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0004] As living standards gradually improve, people's performance requirements for display products are becoming increasingly higher. Currently, increasing the screen-to-body ratio has become one of the core themes of mobile phone product innovation. Although existing solutions for increasing the screen-to-body ratio can already place the camera below the display area by externalizing the pixel circuit,

[0005] However, for products with facial recognition functions, since the facial recognition sensor or infrared projector occupies a large space, when the facial recognition sensor or infrared projector is set below the display area, the design space limitation can no longer meet the requirements of the external pixel circuit arrangement, which makes it particularly difficult to set the facial recognition sensor or infrared projector below the display area. Summary of the Invention

[0006] This application adopts the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide a display panel, comprising a first display area and at least one second display area, wherein the transmittance of the second display area is greater than the transmittance of the first display area; the first display area comprises a plurality of first sub-pixels arranged in an array, and the second display area comprises a plurality of second sub-pixels arranged in an array;

[0008] The first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit. The transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0009] In at least one display panel provided by an embodiment of the present application, the first sub-pixel includes a first light-emitting area and a first non-light-emitting area other than the first light-emitting area, and the second sub-pixel includes a second light-emitting area and a second non-light-emitting area other than the second light-emitting area;

[0010] The transmittance of the second light-emitting area is greater than or equal to the transmittance of the first light-emitting area, and the transmittance of the second non-light-emitting area is greater than the transmittance of the first non-light-emitting area.

[0011] In at least one display panel provided in an embodiment of the present application, the first pixel circuit and the second pixel circuit each include a first-type transistor and a plurality of second-type transistors, the first-type transistors being polysilicon transistors, and the second-type transistors being oxide transistors; an orthographic projection of the first-type transistor on a substrate of the display panel at least partially falls within a light-emitting area, and an orthographic projection of the second-type transistor on the substrate at least partially falls within a non-light-emitting area;

[0012] The transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor.

[0013] In at least one display panel provided in an embodiment of the present application, each of the first sub-pixel and the second sub-pixel includes a gate line, a light-emission control signal line, a reset signal line, an initialization signal line, a data signal line, and a first power signal line; the gate line, the light-emission control signal line, and the reset signal line are electrically connected to gates of different second-type transistors, respectively; and the initialization signal line, the data signal line, and the first power signal line are electrically connected to sources or drains of different second-type transistors, respectively.

[0014] The transmittance of at least one of the data signal line and the first power signal line is less than or equal to the transmittance of the gate line, the light emitting control signal line, the reset signal line, and the initialization signal line.

[0015] In at least one display panel provided in an embodiment of the present application, the display panel includes:

[0016] a first semiconductor layer on the substrate, the first semiconductor layer including an active portion of the first type transistor;

[0017] a first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor;

[0018] a second gate layer, located on a side of the first gate layer away from the substrate, comprising a second electrode of the storage capacitor and at least a portion of the first gates of the second-type transistors;

[0019] a second semiconductor layer, located on a side of the second gate layer away from the substrate, and including an active portion of each of the second-type transistors;

[0020] a third gate layer, located on a side of the second semiconductor layer away from the substrate, comprising at least a portion of the second gate of the second type transistor;

[0021] a first source-drain conductive layer, located on a side of the third gate layer away from the substrate, comprising a source and a drain of each transistor;

[0022] In which, the gate line, the light-emitting control signal line, the reset signal line and the initialization signal line are respectively located on at least one layer among the first gate layer, the second gate layer and the third gate layer, and the data signal line and the first power signal line are respectively located on at least one layer among the first source-drain conductive layer and the second source-drain conductive layer.

[0023] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include a first sublayer and a second sublayer;

[0024] The material of one of the first sub-layer and the second sub-layer includes a light-transmitting conductive material, and the material of the other sub-layer includes a metal.

[0025] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include the first sublayer and the second sublayer;

[0026] The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all include a third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

[0027] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include a fourth sublayer;

[0028] Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-emission area of ​​the second display area all include a third sublayer;

[0029] Wherein, the materials of the third sub-layer and the fourth sub-layer both include light-transmitting conductive materials.

[0030] In at least one display panel provided in an embodiment of the present application, portions of the first gate layer, the second gate layer, and the third gate layer located in the first display area each include a first sublayer and a second sublayer; a material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and a material of the other includes a metal; portions of the first source-drain conductive layer and the second source-drain conductive layer located in the first display area each include a metal;

[0031] The first gate layer, the second gate layer, and the third gate layer located in the second non-luminous area of ​​the second display area all comprise a light-transmitting conductive material; the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all comprise a metal;

[0032] The first source-drain conductive layer and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area both include metal.

[0033] In at least one display panel provided in an embodiment of the present application, the first gate layer, the second gate layer, and the portion of the third gate layer located in the second light-emitting area of ​​the second display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0034] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, and the third gate layer located in the second light-emitting area of ​​the second display area all include metal.

[0035] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include metal.

[0036] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second display area all include light-transmitting conductive material.

[0037] In at least one display panel provided by an embodiment of the present application, portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area include a light-transmitting conductive material;

[0038] The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include metal; or, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes metal.

[0039] In at least one display panel provided by an embodiment of the present application, the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all comprise metal;

[0040] The first gate layer, the second gate layer and the third gate layer located in the second non-luminous area of ​​the second display area all include light-transmitting conductive materials, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all include metals.

[0041] In at least one display panel provided in an embodiment of the present application, the display panel further includes a passivation layer and a first planarization layer located between the first source-drain conductive layer and the second source-drain conductive layer and sequentially arranged in a direction away from the substrate, and a light-transmitting conductive layer located between the passivation layer and the first planarization layer;

[0042] Partial line segments of the data signal line and partial line segments of the first power signal line are arranged on the light-transmitting conductive layer.

[0043] In at least one display panel provided in an embodiment of the present application, when the materials of the first gate layer, the second gate layer and the third gate layer include light-transmitting conductive materials, the portions of the first gate layer, the second gate layer and the third gate layer used as gates of transistors include a light-transmitting sublayer and a light-shielding sublayer, and the light-shielding sublayer is located on a side of the light-transmitting sublayer away from the active portion of the transistor.

[0044] In a second aspect, an embodiment of the present application provides a display device comprising a display panel as described in any one of the first aspects.

[0045] In a third aspect, an embodiment of the present application provides a method for manufacturing a display panel as described in the first aspect, wherein the method comprises:

[0046] forming a first gate layer;

[0047] forming a second gate layer;

[0048] A third gate layer is formed; the first gate layer, the second gate layer, and the portion of the third gate layer located in the first display area and the portion located in the second light-emitting area of ​​the second display area all include a stacked light-transmitting sub-layer and a metal sub-layer, and the first gate layer, the second gate layer, and the portion of the third gate layer located in the second non-light-emitting area of ​​the second display area include the light-transmitting sub-layer.

[0049] In at least one method for manufacturing a display panel provided in an embodiment of the present application, forming the third gate layer includes:

[0050] forming a light-transmitting film;

[0051] forming a metal film;

[0052] performing patterning on the light-transmitting film and the metal film to obtain a light-transmitting sub-layer and a metal sub-layer;

[0053] forming a photoresist film, wherein the photoresist film covers the metal sublayer;

[0054] Using a first mask to pattern the photoresist film to obtain a photoresist pattern, wherein the photoresist pattern covers a portion of the metal sublayer located in the first display area and a portion of the metal sublayer located in the second light-emitting area of ​​the second display area;

[0055] The portion of the metal sublayer located in the second non-luminous area of ​​the second display area is etched using the photoresist pattern as a second mask to obtain the third gate layer.

[0056] In at least one method for preparing a display panel provided in an embodiment of the present application, the method for forming the first gate layer, the second gate layer, and the third gate layer is the same, and the first mask used to form the first gate layer, the second gate layer, and the third gate layer is the same mask.

[0057] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] FIG1A is a schematic cross-sectional view of a display panel in the related art provided by an embodiment of the present application;

[0060] 1B and 1C are diagrams illustrating the characteristics of a low-temperature polysilicon transistor and an oxide transistor, respectively;

[0061] FIG. 2A (1), FIG. 2A (2), FIG. 2B (1), and FIG. 2B (2) are schematic top views of four display panels provided in embodiments of the present application;

[0062] FIG3 is a diagram illustrating an arrangement of pixel circuits in a first display area and a second display area of ​​a display panel provided by an embodiment of the present application;

[0063] 4A to 11 are schematic cross-sectional views of ten display panels provided in embodiments of the present application;

[0064] FIG12 is a simplified structural diagram of a gate of a transistor in a display panel provided by an embodiment of the present application;

[0065] 13 to 16 are schematic structural diagrams of four pixel circuits provided in embodiments of the present application;

[0066] FIG17 and FIG18 are simplified schematic diagrams of circuit distribution in the peripheral area of ​​two display panels according to an embodiment of the present application;

[0067] 19 to 23B are schematic diagrams of intermediate structures during the preparation process of seven display panels provided in embodiments of the present application. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0069] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0070] In the embodiments of the present application, words such as "first" and "second" are used to indicate parts of identical or similar items with substantially the same functions and effects only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0071] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0072] In this specification, the terms "electrically connected" and "coupled" include components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0073] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0074] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0075] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0076] In the embodiments of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiments of the present application, one of the source and drain of the transistor can also be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0077] Figure 1A provides a schematic diagram of the cross-sectional structure of a display panel in a related art. In Figure 1A, it can be seen that a pixel circuit is provided in the display area of ​​the display panel. Since the overall transmittance of the pixel circuit and the wiring between the pixel circuits is very low, it is impossible to set sensors (such as ambient light sensors, distance sensors, face recognition sensors), cameras and other devices below the display area; for this reason, for smaller sensors, the related art adopts the method of relocating the pixel circuit in the display area above the sensor (for example, the pixel circuit in the corresponding area of ​​the sensor is externalized to the display area outside the corresponding area of ​​the sensor) to improve the transmittance of the corresponding area of ​​the sensor, thereby increasing the screen-to-body ratio of the display product, and improving the aesthetics and user experience of the display product.

[0078] However, for products with facial recognition functions, since the facial recognition sensor or infrared projector occupies a large space, when the facial recognition sensor or infrared projector is set below the display area, the design space limitation can no longer meet the requirements of the layout of the external pixel circuit, and it is difficult to reduce the transmittance of the local area of ​​the display area corresponding to the facial recognition sensor or infrared projector, which makes it particularly difficult to set the facial recognition sensor or infrared projector below the display area.

[0079] Based on this, an embodiment of the present application provides a display panel and a preparation method thereof, a display device, wherein the display panel includes a first display area and at least one second display area, the transmittance of the second display area is greater than the transmittance of the first display area; the first display area includes a plurality of first sub-pixels arranged in an array, and the second display area includes a plurality of second sub-pixels arranged in an array; the first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit, the circuit structures of the first pixel circuit and the second pixel circuit are the same, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0080] Among them, by also setting a second pixel circuit in the second sub-pixel of the second display area, setting the circuit structure of the first pixel circuit and the second pixel circuit to be the same, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit, in this way, sensors (such as ambient light sensors, distance sensors, face recognition sensors), cameras and other devices can be set in the area below the second display area in the display panel, thereby realizing the preparation of a display device with a high screen-to-body ratio.

[0081] Hereinafter, the display panel and its manufacturing method, and the display device provided by the embodiments of the present application will be specifically described and introduced with reference to the accompanying drawings.

[0082] An embodiment of the present application provides a display panel, as shown in (1) and (2) in FIG. 2A and (1) and (2) in FIG. 2B , wherein the display panel includes a first display area AA1 and at least one second display area AA2, wherein the transmittance of the second display area AA2 is greater than the transmittance of the first display area AA1; as shown in FIG. 3 , the first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array;

[0083] The first sub-pixel P1 includes a first pixel circuit, and the second sub-pixel P2 includes a second pixel circuit, wherein the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

[0084] Exemplarily, the equivalent circuits of the first pixel circuit and the second pixel circuit have the same structure (both marked as Pixel Circuit in FIG3 ).

[0085] This does not limit the shape of the plane figure of the above-mentioned second display area AA2. For example, the shape of the plane figure of the above-mentioned second display area AA2 may include a polygon, an arc, or a combination of a polygon and an arc, wherein the combination of a polygon and an arc refers to a figure of a spliced ​​shape of a polygon and an arc, or a figure formed by removing a local area on a polygon or an arc.

[0086] In some embodiments, the first display area AA1 may surround the second display area AA2; in other embodiments, the first display area AA1 may partially surround the second display area AA2, that is, a portion of the outer contour of the second display area AA2 serves as the outer contour of the display area.

[0087] The display area AA includes a first display area AA1 and a second display area AA2 , and both the first display area AA1 and the second display area AA2 can emit display light.

[0088] The first display area AA1 includes a first pixel unit, and the second display area AA2 includes a second pixel unit, wherein the display colors of the first pixel unit and the second pixel unit are the same.

[0089] The display colors of the above-mentioned multiple sub-pixels are not limited here.

[0090] In some embodiments, the display colors of each sub-pixel in the above-mentioned display panel are the same; in some embodiments, the above-mentioned display panel simultaneously includes multiple sub-pixels that display different colors, for example, simultaneously including red sub-pixels, green sub-pixels and blue sub-pixels; that is, multiple first sub-pixels P1 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels, and multiple second sub-pixels P2 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels.

[0091] In some embodiments, the number of the second sub-pixels is smaller than the number of the first sub-pixels.

[0092] In an exemplary embodiment, the display panel may be an organic light emitting diode (OLED) display panel, wherein each sub-pixel includes a light emitting device, and the light emitting device may include an OLED light emitting device.

[0093] The light emitting device Q includes a light emitting functional layer 21 and an anode 18 and a cathode 22 located on both sides of the light emitting functional layer 21 .

[0094] In an exemplary embodiment, the light-emitting colors of all light-emitting devices are the same, for example, all light-emitting devices emit blue light; for another example, all light-emitting devices emit white light; in this case, when used as a display, a color conversion layer needs to be set on the light-emitting side of the light-emitting device, for example, a color filter (Color Filter) can be set on the light-emitting side of the light-emitting device, such as a red filter, a green filter and a blue filter; for another example, quantum dot layers (QD Film) of different colors can be set on the light-emitting side of the light-emitting device, such as a red quantum dot layer, a green quantum dot layer and a white resin layer, the blue light emitted by the light-emitting functional layer passes through the red quantum dot layer and then emits red light, the blue light emitted by the light-emitting functional layer passes through the green quantum dot layer and then emits green light, and the blue light emitted by the light-emitting functional layer passes through the white resin layer and then emits blue light, thereby realizing a colored display.

[0095] In an exemplary embodiment, the display panel includes a plurality of light-emitting devices emitting different colors, for example, a red light-emitting device, a green light-emitting device, and a blue light-emitting device.

[0096] Among them, the first sub-pixel P1 includes a first pixel circuit, and the second sub-pixel P2 includes a second pixel circuit. The circuit structures of the first pixel circuit and the second pixel circuit are the same (both marked as Pixel Circuit in Figure 3). Here, the first pixel circuit and the second pixel circuit are collectively referred to as pixel circuits.

[0097] The specific circuit structure of the above-mentioned pixel circuit is not limited here. For example, the pixel circuit may include two transistors and one capacitor (2T1C); or, the pixel circuit may include four transistors and two capacitors (4T2C); or, the pixel circuit may include five transistors and two capacitors (5T2C); or, the pixel circuit may include six transistors and two capacitors (6T1C); or, the pixel circuit may include seven transistors and one capacitor (7T1C); or, the pixel circuit may include eight transistors and one capacitor (8T1C). The embodiments of the pixel circuit in this application are not limited to this. In other embodiments, the pixel circuit may further include more transistors, more capacitors, or other devices.

[0098] In addition, the types of transistors in the above pixel circuit are not limited here. For example, the transistors may include N-type transistors; or the transistors may include P-type transistors; or the transistors may include both N-type transistors and P-type transistors.

[0099] Wherein, when the circuit structures of the first pixel circuit and the second pixel circuit are the same, the transmittance of the second pixel circuit being greater than the transmittance of the first pixel circuit can be achieved by at least one of the following methods:

[0100] First, by setting the transmittance of the material of the wiring and the material of the device in the second pixel circuit, the transmittance of at least a part of the material of the wiring and the material of the device in the second pixel circuit is greater than the transmittance of the material of the wiring and the material of the device in the first pixel circuit.

[0101] Second, by setting the thickness and line width of the traces in the second pixel circuit, the traces in the second pixel circuit have a higher transmittance while maintaining the same electrical properties as the traces in the first pixel circuit. For example, the thickness of the traces in the second pixel circuit is smaller than the thickness of the traces in the first pixel circuit, and the line width of the traces in the second pixel circuit is greater than or equal to the line width of the traces in the first pixel circuit. Generally, the smaller the thickness of the film layer, the higher the transmittance.

[0102] The increase in resistivity caused by the reduction in trace thickness can be balanced by selecting conductive materials with different resistivities.

[0103] Third, by setting the planar dimensions of the devices in the second pixel circuit, while maintaining the same electrical properties as the first pixel circuit, the planar dimensions of at least one device in the second pixel circuit are smaller than the planar dimensions of the corresponding device in the first pixel circuit, wherein the difference in electrical properties caused by the difference in planar dimensions can be compensated and balanced by the dimensions in the substrate direction perpendicular to the display panel.

[0104] In an exemplary embodiment, the transmittance of the wiring in the second pixel circuit is greater than or equal to the transmittance of each wiring in the first pixel circuit. The wiring may include signal lines (e.g., data signal lines, reset signal lines, light emission control signal lines, etc.) and connecting lines (e.g., connecting lines between two transistors, etc.).

[0105] It should be noted that the “transmittance” in this specification includes the transmittance of visible light and / or the transmittance of infrared light.

[0106] In the display panel provided in the embodiments of the present application, the display panel is provided with a first display area AA1 and at least one second display area AA2, wherein the first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array; the first sub-pixel P1 includes a first pixel circuit, and the second sub-pixel P2 includes a second pixel circuit, and the first pixel circuit and the second pixel circuit have the same circuit structure (both labeled as "Pixel Circuit" in FIG3 ), wherein the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit. In this way, by embedding the second pixel circuit in the second display area AA2 and setting the transmittance of the second pixel circuit to be greater than the transmittance of the first pixel circuit, sensors (such as ambient light sensors, distance sensors, face recognition sensors, fingerprint sensors, etc.), cameras, and other devices can be installed in the area below the second display area AA2 in the display panel, thereby enabling the preparation of a display device with a high screen-to-body ratio and facilitating the preparation of a display device with a high PPI (Pixels Per Inch, image resolution, also known as pixel density).

[0107] In at least one display panel provided in an embodiment of the present application, as shown in Figures 4A, 6A and 8, the first sub-pixel P1 includes a first light-emitting area KK1 and a first non-light-emitting area FKK1 other than the first light-emitting area KK1, and as shown in Figures 4B, 5, 6B, 7, 9 to 11, the second sub-pixel P2 includes a second light-emitting area KK2 and a second non-light-emitting area FKK2 other than the second light-emitting area KK2; wherein the transmittance of the second light-emitting area KK2 is greater than or equal to the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 is greater than the transmittance of the first non-light-emitting area FKK1.

[0108] In this specification, the meanings of the luminous area and the non-luminous area are as follows: the luminous area refers to the area in the sub-pixel that cannot emit display light (including the area where circuits and wiring are set).

[0109] In practical applications, taking FIG. 4B as an example, the area of ​​the light-emitting region is consistent with the area occupied by the pixel opening in the pixel definition layer 19 , the light-emitting functional layer 21 is arranged in the pixel opening, and the area of ​​the anode 18 is usually larger than the area of ​​the pixel opening.

[0110] In addition, in some embodiments, as shown in conjunction with Figures 4A and 4B , the transmittance of the portion of the second pixel circuit where the anode 18 electrically connected thereto overlaps is greater than or equal to the transmittance of the portion of the first pixel circuit where the anode 18 electrically connected thereto overlaps; and the transmittance of the region of the second pixel circuit where the anode 18 electrically connected thereto does not overlap is greater than the transmittance of the region of the first pixel circuit where the anode 18 electrically connected thereto does not overlap. In other words, the overall transmittance of the structure below the anode 18 in the second display area AA2 is greater than or equal to the overall transmittance of the structure below the anode 18 in the first display area AA1; and the overall transmittance of the structure outside the anode 18 in the second display area AA2 is greater than the overall transmittance of the structure outside the anode 18 in the first display area AA1.

[0111] In practical applications, in order to improve the transmittance of the second display area AA2 while taking into account the display effect of the display panel, priority is given to ensuring that the transmittance in the second light-emitting area KK2 remains as unchanged as possible, and the purpose of improving the transmittance of the second display area AA2 is achieved by adjusting the part of the second pixel circuit located in the second non-light-emitting area FKK2 as much as possible.

[0112] It should be noted that, in actual applications, the area where display light is actually emitted in the same sub-pixel is less than or equal to the planar area where the anode 18 is located, and the area where the anode 18 is in direct contact with the light-emitting functional layer 21 of the light-emitting device Q is the area where display light is actually emitted in the sub-pixel.

[0113] In an exemplary embodiment, the transmittance of the second light-emitting area KK2 is greater than the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 is greater than the transmittance of the first non-light-emitting area FKK1;

[0114] In an exemplary embodiment, the transmittance of the second light-emitting region KK2 is equal to the transmittance of the first light-emitting region KK1 , and the transmittance of the second non-light-emitting region FKK2 is greater than the transmittance of the first non-light-emitting region FKK1 .

[0115] In an embodiment of the present application, by setting the transmittance of the second light-emitting area KK2 to be greater than or equal to the transmittance of the first light-emitting area KK1, and the transmittance of the second non-light-emitting area FKK2 to be greater than the transmittance of the first non-light-emitting area FKK1, it is possible to ensure the consistency of the display effects in the first display area AA1 and the second display area AA2 as much as possible while improving the transmittance of the second display area AA2. While taking into account the display effects of different areas of the display panel, sensors (such as ambient light sensors, distance sensors, face recognition sensors), cameras and other devices can be set in the area below the second display area AA2 in the display panel, thereby enabling the preparation of a display device with a high screen-to-body ratio, and is also conducive to the preparation of a high PPI (Pixels Per Inch, image resolution, also called pixel density) display device.

[0116] In at least one display panel provided in an embodiment of the present application, as shown in Figures 13 to 16, the first pixel circuit and the second pixel circuit both include a first-type transistor (for example, transistor T3) and multiple second-type transistors (other transistors except transistor T3 in the circuit diagrams shown in Figures 13 to 16), the first-type transistor is a polysilicon transistor, and the second-type transistor is an oxide transistor; the orthographic projection of the first-type transistor on the substrate 1 of the display panel at least partially falls into the light-emitting area (KK1 or KK2), and the orthographic projection of the second-type transistor on the substrate 1 at least partially falls into the non-light-emitting area (FKK1 or FKK2); wherein the transmittance of the first-type transistor is less than or equal to the transmittance of the second-type transistor.

[0117] In an exemplary embodiment, the first type transistor may be a driving transistor, and the second transistor may be at least one of a light emission control transistor, a reset transistor, and an initialization transistor.

[0118] In an exemplary embodiment, the polysilicon transistor may include a low temperature polysilicon transistor (LTPS); and the oxide transistor may include a metal oxide semiconductor transistor (MOS).

[0119] Figures 1B and 1C illustrate the transistor characteristics of polysilicon and oxide transistors. Compared to polysilicon transistors, oxide transistors have better light transmittance. Furthermore, when exposed to infrared light, polysilicon transistors experience significant changes in source-drain current, resulting in unstable transistor characteristics. In contrast, oxide transistors experience minimal changes in source-drain current, resulting in stable transistor characteristics. Oxide transistors exhibit poor stability under visible light.

[0120] Based on the difference in stability between polysilicon transistors (such as low-temperature polysilicon transistors) and oxide transistors to visible light and infrared light, low-temperature polysilicon transistors are more sensitive to infrared light. When an infrared sensor for face recognition is set below the second display area AA2, the orthographic projection of the first-type transistor on the substrate 1 of the display panel is set to at least partially fall into the light-emitting area (KK1 or KK2). The anode 18 in the light-emitting area usually has a low transmittance. Providing a shading structure 2 on the side of the first-type transistor away from the anode 18 will hardly reduce the transmittance of the light-emitting area, and will also have little effect on the overall transmittance of the second display area AA2. In this way, the anode 18 can block light above the first-type transistor, and the shading structure 2 can block light below the first-type transistor. In this way, setting the orthographic projection of the first-type transistor on the substrate 1 of the display panel to at least partially fall into the light-emitting area can avoid the first-type transistor from being irradiated with light as much as possible, thereby preventing the characteristics of the low-temperature polysilicon transistor from shifting.

[0121] Here, at least partially falling within means that part of the area falls within or the entire area falls within.

[0122] In an embodiment of the present application, the first-type transistor is a polysilicon-type transistor and the second-type transistor is an oxide-type transistor; the orthographic projection of the first-type transistor on the substrate 1 of the display panel at least partially falls into the light-emitting area (KK1 or KK2), and the orthographic projection of the second-type transistor on the substrate 1 at least partially falls into the non-light-emitting area (FKK1 or FKK2); wherein the transmittance of the first-type transistor is less than or equal to the transmittance of the second-type transistor. In this way, while ensuring the consistency of the display effects in the first display area AA1 and the second display area AA2 as much as possible and taking into account the display effects of different areas of the display panel, the transmittance of the second display area AA2 in the display panel can be increased as much as possible, so that a sensor or camera and other devices can be set in the area below the second display area AA2, thereby realizing the preparation of a display device with a high screen-to-body ratio, and facilitating the preparation of a display device with a high PPI (Pixels Per Inch, image resolution, also called pixel density).

[0123] In at least one display panel provided in an embodiment of the present application, as shown in FIG13 to FIG16 , each of the first sub-pixel and the second sub-pixel includes a gate line (also referred to as a scan line Scan), an emission control signal line EM, a reset signal line Reset, an initialization signal line Vinit, a data signal line Data, and a first power signal line VDD or ELVDD; the gate line Scan, the emission control signal line EM, and the reset signal line Reset are electrically connected to the gates of different second-type transistors, respectively; the initialization signal line Vinit, the data signal line Data, and the first power signal line VDD or ELVDD are electrically connected to the sources or drains of different second-type transistors, respectively;

[0124] The transmittance of at least one of the data signal line Data and the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0125] In an exemplary embodiment, the transmittance of the data signal line Data is less than or equal to the transmittance of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0126] In an exemplary embodiment, the transmittance of the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0127] In an exemplary embodiment, transmittances of the data signal line Data and the first power signal line VDD or ELVDD are less than or equal to transmittances of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0128] In an exemplary embodiment, the first power signal line VDD or ELVDD refers to a positive voltage signal line. Typically, the pixel circuit also includes a negative voltage signal line, such as a VSS or ELVSS signal line, which is electrically connected to the cathode 22 of the light-emitting device Q.

[0129] In addition, in actual applications, when the impedance of the data signal line Data and the first power signal line VDD or ELVDD is large, it is very easy to cause large signal differences in different areas of the display panel, resulting in uneven brightness of the display screen. Therefore, they have high conductivity requirements. Therefore, the data signal line Data and the first power signal line VDD or ELVDD can be set to generally be a metal material, such as titanium aluminum titanium Ti / Al / Ti, copper (Cu), etc. with high conductivity. The impedance of the gate line Scan, the light control signal line EM, the reset signal line Reset, and the initialization signal line Vinit has a smaller negative impact on the display effect of the display panel. Therefore, they can be at least partially made of a transparent conductive material. In this way, the transmittance has the following rule: the transmittance of the data signal line Data and the first power signal line VDD or ELVDD is less than or equal to the transmittance of the gate line Scan, the light control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0130] In at least one display panel provided in an embodiment of the present application, as shown in FIG. 4A , FIG. 6A , and FIG. 8 , or as shown in FIG. 4B , FIG. 5 , FIG. 6B , FIG. 7 , and FIG. 9 to FIG. 11 , the display panel includes:

[0131] A first semiconductor layer 4, a first gate insulating layer 5, a first gate layer 6 (including 6A, 6B and 6C), a second gate insulating layer 7, a second gate layer 8 (including 8A, 8B and 8C), a third gate insulating layer 9, a second semiconductor layer 10, a fourth gate insulating layer 11, a third gate layer 12 (including 12A and 12B), an interlayer dielectric layer 13, a first source-drain conductive layer 14 (including at least 14A, 14B and 14C), a passivation layer 28, a first planarizing layer 15, a second source-drain conductive layer 16 (including 16A and 16B), a second planarizing layer 17 and an anode layer 18 are sequentially arranged on the substrate 1;

[0132] The first semiconductor layer 4 includes the active portion of the first type transistor, the first gate layer 6 includes the gate 6C of the first type transistor and the first electrode 6B of the storage capacitor Cst, the second gate layer 8 includes the second electrode 8B of the storage capacitor Cst and the first gate 8C of at least part of the second type transistor, the second semiconductor layer 10 includes the active portion of each second type transistor, the third gate layer 12 includes the second gate 12B of at least part of the second type transistor, and the first source-drain conductive layer 14 includes the source and drain of each transistor;

[0133] The gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit are respectively located on at least one layer of the first gate layer 6, the second gate layer 8, and the third gate layer 12, and the data signal line Data and the first power supply signal line VDD or ELVDD are respectively located on at least one layer of the first source-drain conductive layer 14 and the second source-drain conductive layer 16.

[0134] In an exemplary embodiment, some of the second type transistors are dual-gate transistors, which may include a first gate 8C and a second gate 12B.

[0135] In some embodiments, the conductive structure 6A in the first gate layer 6 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0136] In some embodiments, the conductive structure 8A in the second gate layer 8 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0137] In an exemplary embodiment, the conductive structure 12A in the third gate layer 12 may be one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit.

[0138] In at least one display panel provided in an embodiment of the present application, as shown in Figure 4A, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 all include a first sublayer and a second sublayer (in order to avoid clarity caused by too many labels in the drawings, the first sublayer and the second sublayer are drawn in the drawings but not labeled); wherein, the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0139] In an exemplary embodiment, the portion of any one of the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14, and the second source-drain conductive layer 16 located in the first display area AA1 includes a first sublayer and a second sublayer. The first sublayer (e.g., a light-transmitting conductive material) is located on a side of the second sublayer (e.g., a metal) away from the substrate 1 (i.e., the first sublayer is disposed away from the substrate); or, as shown in FIG4A , the second sublayer (e.g., a metal) is located on a side of the first sublayer (e.g., a light-transmitting conductive material) away from the substrate 1 (i.e., the second sublayer is disposed away from the substrate).

[0140] Exemplarily, the light-transmitting conductive material includes, but is not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0141] Exemplarily, the light-transmitting conductive material may also include graphene, PEDOT [a polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotubes, carbon nanorods (carbon nanobuds), silver nanowires (SNWs), and the like.

[0142] Exemplarily, the metal may include any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb).

[0143] In at least one display panel provided in an embodiment of the present application, as shown in Figure 5, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second light-emitting area KK2 of the second display area AA2, all including the first sublayer and the second sublayer; the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are located in the second non-light-emitting area FKK2 of the second display area AA2, all including the third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

[0144] In at least one display panel provided in an embodiment of the present application, as shown in Figure 4B, the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 all include a fourth sublayer (not marked in Figure 4B); the first gate layer 6, the second gate layer 8 and the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-light-emitting area FKK2 of the second display area AA2 all include a third sublayer (not marked in Figure 4B); wherein the materials of the third sublayer and the fourth sublayer both include light-transmitting conductive materials.

[0145] Exemplarily, the light-transmitting conductive material includes, but is not limited to, metal oxides, such as indium tin oxide and indium zinc oxide.

[0146] Exemplarily, the light-transmitting conductive material may also include graphene, PEDOT [a polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotubes, carbon nanorods (carbon nanobuds), silver nanowires (SNWs), and the like.

[0147] There is no limitation on whether the third sub-layer and the fourth sub-layer are made of the same material, which can be determined based on product design and preparation process.

[0148] In at least one display panel provided in an embodiment of the present application, as shown in FIG6A , portions of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal; portions of the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 all include metal; as shown in FIG7 , portions of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-luminous area FKK2 of the second display area AA2 all include a light-transmitting conductive material; portions of the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-luminous area FKK2 of the second display area AA2 all include metal; as shown in FIG7 , portions of the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 all include metal.

[0149] In at least one display panel provided by an embodiment of the present application, as shown in FIG7 , portions of the first gate layer 6 , the second gate layer 8 , and the third gate layer 12 located in the second light-emitting area KK2 of the second display area AA2 all include metal.

[0150] In at least one display panel provided in an embodiment of the present application, based on the structure shown in Figure 7, the film layers of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second light-emitting area KK2 of the second display area AA2 are adjusted, and the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second light-emitting area KK2 of the second display area AA2 can also be set to include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0151] In at least one display panel provided in an embodiment of the present application, as shown in FIG8 , portions of the first gate layer 6 , the second gate layer 8 , the third gate layer 12 , the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 all include metal.

[0152] In at least one display panel provided in an embodiment of the present application, as shown in FIG4B , the first gate layer 6 , the second gate layer 8 , the third gate layer 12 , the first source-drain conductive layer 14 , and the second source-drain conductive layer 16 located in the second display area AA2 all include light-transmitting conductive materials.

[0153] In the display panel provided in the embodiment of the present application, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 are all located in the first display area AA1. The portions thereof include metal, and the portions of the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second display area AA2 include light-transmitting conductive material, so that the overall transmittance of the second display area AA2 of the display panel is improved as much as possible, which is beneficial for improving the light transmittance of the sensor or camera when a sensor or camera and other devices are set in the area below the second display area AA2, thereby enabling the preparation of a display device with a high screen-to-body ratio, and is also beneficial for the preparation of a display device with a high PPI (Pixels Per Inch, image resolution, also called pixel density).

[0154] In at least one display panel provided in an embodiment of the present application, as shown in Figure 9, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-luminous area FKK2 of the second display area AA2 include a light-transmitting conductive material; the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second luminous area KK2 of the second display area AA2 include a metal.

[0155] Alternatively, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-luminous area FKK2 of the second display area AA2 include a light-transmitting conductive material; the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second luminous area KK2 of the second display area AA2 include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

[0156] In at least one display panel provided in an embodiment of the present application, as shown in Figure 11, the first gate layer 6, the second gate layer 8, the third gate layer 12, the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 all include metal; the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 all include light-transmitting conductive material, and the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the second non-light-emitting area FKK2 of the second display area AA2 all include metal.

[0157] In at least one display panel provided in an embodiment of the present application, as shown in Figures 6B and 10, the display panel also includes a light-transmitting conductive layer 27 (including 27A, 27B and 27C) located between the passivation layer 28 and the first flat layer 15; partial line segments of the data signal line Data and partial line segments of the first power signal line ELVDD or VDD are arranged on the light-transmitting conductive layer 27.

[0158] Exemplarily, the material of the light-transmitting conductive layer 27 includes, but is not limited to, metal oxides, such as indium tin oxide and indium zinc oxide.

[0159] Exemplarily, the material of the light-transmitting conductive layer 27 may also include graphene, PEDOT [a polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal mesh, carbon nanotubes, carbon nanorods (carbon nanobuds), silver nanowires (SNW), etc.

[0160] Exemplarily, the light-transmitting conductive layer 27 may further include other wirings and leads, such as a conductive structure 27C for connecting the drain and anode 18 of the second type transistor, and a wiring 27B for connecting the first type transistor and the second type transistor.

[0161] Exemplarily, a partial line segment of the first power signal line ELVDD or VDD disposed on the light-transmitting conductive layer 27 is the conductive structure 27A.

[0162] In at least one display panel provided in an embodiment of the present application, as shown in Figure 12, when the materials of the first gate layer 6, the second gate layer 8 and the third gate layer 12 include light-transmitting conductive materials, the parts of the first gate layer 6, the second gate layer 8 and the third gate layer 12 used as the gate Gate of the transistor include a light-transmitting sublayer TG and a light-shielding sublayer ZG, and the light-shielding sublayer ZG is located on the side of the light-transmitting sublayer TG away from the active part of the transistor.

[0163] In an exemplary embodiment, when the transistor is a dual-gate transistor, the two gates Gate of the transistor can be set to include a light-transmitting sublayer TG and a light-shielding sublayer ZG. The light-shielding sublayer ZG in the gate Gate close to the side of the substrate 1 can be used to block the light emitted by the infrared projector below, and the light-shielding sublayer ZG in the gate Gate close to the side of the light-emitting functional layer 21 can be used to block the light emitted by the light-emitting functional layer 21 or ambient light.

[0164] In an exemplary embodiment, the material of the light-shielding sublayer ZG in the gate Gate may include an organic light-shielding material, such as black resin; or, the material of the light-shielding sublayer ZG in the gate Gate may include a metal or a metal compound, such as titanium nitride (TiNx), etc., wherein the metal can block light while also increasing the resistivity of the gate Gate, improving the electrical characteristics of the transistor, and preventing hydrogen elements in other film layers from diffusing into the channel of the transistor during the preparation process.

[0165] It should be noted that the display panel provided in the embodiment of the present application also includes a support portion 20 arranged on the pixel definition layer 19, and the support portion 20 is used to support the mask plate during the evaporation process (BP process) to prevent scratches between the mask plate and the film layer on the display panel; in some embodiments, the display panel also includes an encapsulation layer 29, a touch layer 23, an anti-reflection layer 24 (used to reduce reflectivity, which may include multiple sub-layers), an adhesive layer 25 and a cover plate 26.

[0166] Of course, the display panel may also include other structures and components. This specification only introduces structures and components related to the invention. For other structures and components included in the display panel, reference may be made to the introduction in the relevant technology.

[0167] An embodiment of the present application provides a display device, including the display panel as described above.

[0168] The specific structure of the display panel can be referred to in the previous description and will not be repeated here.

[0169] The display device provided in the embodiments of the present application may be an OLED display device, wherein the OLED display device may include a glass-based OLED display device and a silicon-based OLED display device.

[0170] In addition, the display device can be a display device such as an OLED display, as well as any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0171] An embodiment of the present application provides a method for manufacturing a display panel as described above, wherein the method comprises:

[0172] S1. Forming a first gate layer 6 (including 6A, 6B, and 6C) as shown in FIG. 20A and FIG. 20B ;

[0173] S2, forming the second gate layer 8 (including 8A, 8B and 8C) shown in FIG. 20A and FIG. 20B;

[0174] S3. Form a third gate layer 12 as shown in Figures 23A and 23B; the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 and the second light-emitting area KK2 of the second display area AA2 all include stacked transparent sub-layers and metal sub-layers, and the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 include a transparent sub-layer.

[0175] In at least one method for manufacturing a display panel provided by an embodiment of the present application, S1, forming the third gate layer 12 includes:

[0176] S11, forming a light-transmitting film;

[0177] The light-transmitting film is a continuous light-transmitting material film over the entire surface, and is the film layer of the light-transmitting sub-layer before patterning.

[0178] S12, forming a metal thin film;

[0179] The metal thin film is a continuous light-transmitting material film over the entire surface, and is the film layer of the metal sublayer before patterning.

[0180] S13, patterning the light-transmitting film and the metal film to obtain a light-transmitting sub-layer and a metal sub-layer as shown in FIG19 ;

[0181] For example, the light-transmitting film and the metal film can be patterned at the same time to obtain the light-transmitting sub-layer and the metal sub-layer as shown in Figure 19. In this way, the light-transmitting film and the metal film can be patterned using the same mask, saving a preparation process step; in addition, by simultaneously patterning the light-transmitting sub-layer and the metal sub-layer, compared with the method of using two patterning methods to prepare the light-transmitting sub-layer and the metal sub-layer, the position deviation of the light-transmitting sub-layer and the metal sub-layer can be effectively reduced, and the position deviation (such as misalignment) of the light-transmitting sub-layer and the metal sub-layer can be avoided, thereby improving the accuracy of the preparation process and avoiding wiring problems (such as short circuit problems, etc.) caused by deviation in the preparation process accuracy.

[0182] In FIG. 19 , the portion of the third gate layer 12 located in the first display area AA1 and the portion of the third gate layer 12 located in the second display area AA2 have the same structure.

[0183] 20A and 20B are schematic cross-sectional structural diagrams of the first display area AA1 and the second display area AA2 corresponding to the top view shown in FIG. 19 , respectively.

[0184] In order to obtain a second display area AA2 with high light transmittance, the metal sublayer of the third gate layer 12 in the second display area AA2 is etched away, leaving only the light-transmitting sublayer. The following is an illustration of the etching process of the metal sublayer of the third gate layer 12 in the second display area AA2:

[0185] S14, forming a photoresist film PR film, the photoresist film PR film covering the metal sublayer;

[0186] The photoresist film PR film covers the first display area AA1 and the second display area AA2.

[0187] S15. Patterning the photoresist film PR film using a first mask to obtain a photoresist pattern PR mask as shown in FIG21 . In FIG21 , the photoresist pattern PR mask covers a portion of the metal sublayer located in the first display area AA1 and a portion of the metal sublayer located in the second light-emitting area KK2 of the second display area AA2 (it should be noted that, to avoid ambiguity in FIG21 , the portion of the photoresist pattern PR mask covering the second light-emitting area KK2 of the second display area AA2 is not drawn);

[0188] S16 , using the photoresist pattern PR mask as a second mask, etching the portion of the metal sublayer located in the second non-luminous area FKK2 of the second display area AA2 to obtain the third gate layer 12 as shown in FIG. 22 .

[0189] 22 is a simplified top view of the third gate layer 12 , FIG23A is a schematic cross-sectional view of the third gate layer 12 in the first display area AA1 , and FIG23B is a schematic cross-sectional view of the third gate layer 12 in the second display area AA2 .

[0190] In at least one method for preparing a display panel provided in an embodiment of the present application, the method for forming the first gate layer 6, the second gate layer 8 and the third gate layer 12 is the same, and the first mask used to form the first gate layer 6, the second gate layer 8 and the third gate layer 12 is the same mask.

[0191] Among them, the first mask is a mask used when patterning the photoresist film PR film. When the portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the first display area AA1 and the portions located in the second light-emitting area KK2 of the second display area AA2 all include a stacked light-transmitting sub-layer and a metal sub-layer, and the portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 include a light-transmitting sub-layer, the same first mask can be used to pattern the photoresist film PR film to obtain a photoresist pattern PR mask as shown in FIG. 21 , which covers the portion of the metal sub-layer located in the first display area AA1 and the portion of the metal sub-layer located in the second light-emitting area KK2 of the second display area AA2.

[0192] In the subsequent etching process, the photoresist pattern PR mask protects the portion of the metal sublayer located in the first display area AA1 and the portion of the metal sublayer located in the second light-emitting area KK2 of the second display area AA2, thereby etching away the portion of the metal sublayer of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2, so that the portion of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second non-light-emitting area FKK2 of the second display area AA2 includes a light-transmitting sublayer.

[0193] In this way, when preparing the first gate layer 6 , the second gate layer 8 and the third gate layer 12 , the same first mask can be shared, thereby greatly saving the manufacturing cost of the display panel.

[0194] Of course, in some embodiments, the above-mentioned preparation method provided in the embodiments of the present application can also be used to prepare the first source-drain conductive layer 14 and the second source-drain conductive layer 16. When the first source-drain conductive layer 14 and the second source-drain conductive layer 16 located in the first display area AA1 and the second source-drain conductive layer 16 located in the second light-emitting area KK2 of the second display area AA2 both include stacked transparent sub-layers and metal sub-layers, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-light-emitting area FKK2 of the second display area AA2 include transparent sub-layers, similar preparation methods can also be used, so that the same first mask can be used in the preparation of the first source-drain conductive layer 14 and the second source-drain conductive layer 16, further saving the preparation cost of the display panel.

[0195] The preparation process of the above-mentioned display panel may also include other processes and steps. Only the steps related to the invention are introduced here. For other preparation processes and steps of the display panel, please refer to the introduction in the relevant technology and will not be repeated here.

[0196] An embodiment of the present application provides a pixel circuit, as shown in FIG13 to FIG16 , wherein the pixel circuit in the nth row includes:

[0197] a driving sub-circuit M1 electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and configured to, under the control of the voltage of the first node N1, conduct a path between the second node N2 and the third node N3, and generate a current in the path for causing the light-emitting device Q to emit light;

[0198] a first reset sub-circuit M2, electrically connected to the first node N1, the first reset signal line Reset(n) or Reset1(n), and the first initialization signal line Vinit1, and configured to write the first initialization signal transmitted by the first reset signal line Reset(n) or Reset1(n) into the first node N1 under the control of the first reset signal transmitted by the first reset signal line Reset(n) or Reset1(n);

[0199] a second reset sub-circuit M3 electrically connected to the second node N2 and the data signal line Data(m), and configured to reset the voltage of the second node N2;

[0200] The third reset sub-circuit M4 is electrically connected to the fourth node N4, the anode of the light-emitting device Q, and the second initialization signal line Vinit2, and is configured to write the second initialization signal transmitted by the second initialization signal line Vinit2 into the anode; the fourth node N4 is electrically connected to the anode of the light-emitting device Q;

[0201] The light-emitting control sub-circuit M5 is electrically connected to the light-emitting control signal line EM(n), the first power signal line ELVDD or VDD, the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to transmit a current for causing the light-emitting device Q to emit light to the anode under the control of the light-emitting control signal transmitted by the light-emitting control signal line EM(n); wherein the anode is electrically connected to the fourth node N4, and the cathode of the light-emitting device is electrically connected to the second power signal line ELVSS or VSS;

[0202] The storage sub-circuit M6 is electrically connected to the first power signal line ELVDD or VDD and the first node N1, and is configured to store the voltage of the first node N1; wherein m and n are positive integers.

[0203] In an exemplary embodiment, as shown in FIG13 to FIG16 , the first reset sub-circuit M2 includes a first transistor T1 and a second transistor T2; a gate of the first transistor T1 is electrically connected to a first reset signal line Reset(n) or Reset1(n), and a second electrode of the first transistor T1 is electrically connected to a first initialization signal line Vinit1; a gate of the second transistor T2 is electrically connected to a first scan signal line Scan(n) or Scan1(n), a first electrode of the second transistor T2 is electrically connected to a first node N1, and a second electrode of the second transistor T2 is electrically connected to a third node N3;

[0204] As shown in FIG13 and FIG14 , the first electrode of the first transistor T1 is electrically connected to the first node N1 ; or, as shown in FIG15 and FIG16 , the first electrode of the first transistor T1 is electrically connected to the third node N3 .

[0205] In an exemplary embodiment, as shown in Figures 13 to 16, the second reset sub-circuit M3 includes a fourth transistor T4; a first electrode of the fourth transistor T4 is electrically connected to the second node N2, and a second electrode of the fourth transistor T4 is electrically connected to the data signal line Data(m); wherein, as shown in Figures 13 and 14, a gate of the fourth transistor T4 is electrically connected to the first scan signal line Scan(n) or Scan1(n); or, as shown in Figures 15 and 16, a gate of the fourth transistor T4 is electrically connected to the second scan signal line Scan2(n).

[0206] In an exemplary embodiment, as shown in Figures 14 and 16, the second reset sub-circuit M3 further includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the second reset signal line Reset2(n), a first electrode of the eighth transistor T8 is electrically connected to the third initialization signal line Vinit3, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0207] In an exemplary embodiment, as shown in Figures 13 to 16, the third reset sub-circuit M4 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2; wherein, as shown in Figure 13, the gate of the seventh transistor T7 is electrically connected to the first scan signal line Scan(n); or, as shown in Figures 14 to 16, the gate of the seventh transistor T7 is electrically connected to the second reset signal line Reset2(n).

[0208] In an exemplary embodiment, as shown in FIG. 13 to FIG. 16 , the light emitting control subcircuit M5 includes a fifth transistor T5 and a sixth transistor T6 ;

[0209] The gate of the fifth transistor T5 and the gate of the sixth transistor T6 are both electrically connected to the light emitting control signal line EM(n), the first electrode of the fifth transistor T5 is electrically connected to the first power supply signal line ELVDD or VDD, the second electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0210] In an exemplary embodiment, as shown in FIG13 to FIG16 , the driving sub-circuit M1 includes a third transistor T3 , wherein a gate of the third transistor T3 is electrically connected to the first node N1 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the third node N3 ;

[0211] The storage sub-circuit M6 includes a storage capacitor Cst. One end of the storage capacitor Cst is electrically connected to the first power signal line ELVDD or VDD, and the other end of the storage capacitor Cst is electrically connected to the first node N1.

[0212] In an exemplary embodiment, as shown in Figures 13 and 15 , the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. As shown in Figures 14 and 16 , the pixel circuit further includes an eighth transistor T8. The third transistor T3 is a polysilicon transistor, and the other transistors are oxide transistors.

[0213] In an exemplary embodiment, the third transistor T3 is a P-type transistor, and the other transistors are all N-type transistors.

[0214] 4A to 11 , the transistor located below the anode 21 is a first type transistor (ie, a third transistor, a driving transistor), and the transistor electrically connected to the anode 18 of the light emitting device Q is a sixth transistor T6 .

[0215] The first display area AA1 and the second display area AA2 may simultaneously use one of the four pixel circuits ( FIG. 13 to FIG. 16 ).

[0216] In addition, Figures 17 and 18 illustrate the layout of the shift register and driver chip (IC) in the peripheral area of ​​the display panel. In Figure 17, the display panel includes a set of EM shift registers (EM GOA, EOA), a set of NMOS TFT GOAs (N Reset & N Gate), and a set of PMOS TFT GOAs (P Gate). Figure 18 omits one set of GOAs compared to Figure 17. The design and layout of the GOAs in the display panel can be referred to in the relevant art and will not be repeated here.

[0217] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display panel, wherein: The display panel includes a first display area and at least one second display area, the transmittance of the second display area is greater than the transmittance of the first display area; the first display area includes a plurality of first sub-pixels arranged in an array, and the second display area includes a plurality of second sub-pixels arranged in an array; The first sub-pixel includes a first pixel circuit, and the second sub-pixel includes a second pixel circuit, and the transmittance of the second pixel circuit is greater than the transmittance of the first pixel circuit.

2. The display panel according to claim 1, wherein: The first sub-pixel includes a first light-emitting area and a first non-light-emitting area except the first light-emitting area, and the second sub-pixel includes a second light-emitting area and a second non-light-emitting area except the second light-emitting area; The transmittance of the second light-emitting area is greater than or equal to the transmittance of the first light-emitting area, and the transmittance of the second non-light-emitting area is greater than the transmittance of the first non-light-emitting area.

3. The display panel according to claim 2, wherein: The first pixel circuit and the second pixel circuit each include a first type transistor and a plurality of second type transistors, the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor; the orthographic projection of the first type transistor on the substrate of the display panel at least partially falls into the light emitting area, and the orthographic projection of the second type transistor on the substrate at least partially falls into the non-light emitting area; The transmittance of the first type transistor is less than or equal to the transmittance of the second type transistor.

4. The display panel according to claim 3, wherein: The first sub-pixel and the second sub-pixel each include a gate line, a light emitting control signal line, a reset signal line, an initialization signal line, a data signal line and a first power signal line; The transmittance of at least one of the data signal line and the first power signal line is less than or equal to the transmittance of the gate line, the light emitting control signal line, the reset signal line and the initialization signal line.

5. The display panel according to claim 4, wherein: The display panel comprises: a first semiconductor layer on the substrate, the first semiconductor layer comprising an active portion of the first type transistor; A first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor; A second gate layer, located on a side of the first gate layer away from the substrate, comprising a second electrode of the storage capacitor and at least a portion of the first gate of the second type transistor; A second semiconductor layer, located on a side of the second gate layer away from the substrate, including an active portion of each of the second type transistors; A third gate layer, located on a side of the second semiconductor layer away from the substrate, including at least a portion of the second gate of the second type transistor; A first source-drain conductive layer, located on a side of the third gate layer away from the substrate, comprising a source and a drain of each transistor; Among them, the gate line, the light-emitting control signal line, the reset signal line and the initialization signal line are respectively located on at least one layer among the first gate layer, the second gate layer and the third gate layer, and the data signal line and the first power signal line are respectively located on at least one layer among the first source-drain conductive layer and the second source-drain conductive layer.

6. The display panel according to claim 5, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include a first sublayer and a second sublayer; The material of one of the first sub-layer and the second sub-layer includes a light-transmitting conductive material, and the material of the other sub-layer includes a metal.

7. The display panel according to claim 6, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include the first sublayer and the second sublayer; The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer, and the material of the third sublayer includes a light-transmitting conductive material.

8. The display panel according to claim 6, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area all include a fourth sublayer; Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include a third sublayer; Wherein, the materials of the third sub-layer and the fourth sub-layer both include light-transmitting conductive materials.

9. The display panel according to claim 5, wherein: The first gate layer, the second gate layer, and the third gate layer in the first display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal; the first source-drain conductive layer and the second source-drain conductive layer in the first display area both include a metal; The first gate layer, the second gate layer, and the third gate layer located in the second non-luminescent area of ​​the second display area all include light-transmitting conductive materials; the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area all include metals; The first source-drain conductive layer and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area both include metal.

10. The display panel according to claim 9, wherein: The first gate layer, the second gate layer, and the third gate layer located in the second light-emitting area of ​​the second display area all include a first sublayer and a second sublayer; the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes a metal.

11. The display panel according to claim 9, wherein: Portions of the first gate layer, the second gate layer, and the third gate layer located in the second light emitting area of ​​the second display area all include metal.

12. The display panel according to claim 5, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the first display area all include metal.

13. The display panel according to claim 12, wherein: Portions of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second display area all include a light-transmitting conductive material.

14. The display panel according to claim 12, wherein: Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second non-luminescent area of ​​the second display area include a light-transmitting conductive material; Parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include metal; or, parts of the first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer located in the second light-emitting area of ​​the second display area include a first sublayer and a second sublayer, and the material of one of the first sublayer and the second sublayer includes a light-transmitting conductive material, and the material of the other includes metal.

15. The display panel according to claim 12, wherein: The first gate layer, the second gate layer, the third gate layer, the first source-drain conductive layer, and the second source-drain conductive layer are all located in the second light-emitting area of ​​the second display area and include metal; The first gate layer, the second gate layer and the third gate layer located in the second non-luminous area of ​​the second display area all include light-transmitting conductive materials, and the first source-drain conductive layer and the second source-drain conductive layer located in the second non-luminous area of ​​the second display area all include metals.

16. The display panel according to any one of claims 10, 11 and 14, wherein: The display panel further includes a passivation layer and a first planarization layer located between the first source-drain conductive layer and the second source-drain conductive layer and sequentially arranged in a direction away from the substrate, and a light-transmitting conductive layer located between the passivation layer and the first planarization layer; Partial line segments of the data signal line and partial line segments of the first power signal line are arranged on the light-transmitting conductive layer.

17. The display panel according to any one of claims 6 to 15, wherein: In the case where the materials of the first gate layer, the second gate layer and the third gate layer include light-transmitting conductive materials, the portions of the first gate layer, the second gate layer and the third gate layer used as gates of transistors include a light-transmitting sublayer and a light-shielding sublayer, and the light-shielding sublayer is located on a side of the light-transmitting sublayer away from the active portion of the transistor.

18. A display device, wherein: The invention comprises the display panel according to any one of claims 1 to 17.

19. A method for preparing a display panel according to any one of claims 6 to 17, wherein: The method comprises: forming a first gate layer; forming a second gate layer; A third gate layer is formed; the first gate layer, the second gate layer, and the portion of the third gate layer located in the first display area and the portion located in the second light-emitting area of ​​the second display area all include a stacked light-transmitting sub-layer and a metal sub-layer, and the first gate layer, the second gate layer, and the portion of the third gate layer located in the second non-light-emitting area of ​​the second display area include the light-transmitting sub-layer.

20. The method for preparing a display panel according to claim 19, wherein: The forming of the third gate layer comprises: forming a light-transmitting film; Forming a metal film; Performing patterning on the light-transmitting film and the metal film to obtain a light-transmitting sub-layer and a metal sub-layer; forming a photoresist film, wherein the photoresist film covers the metal sublayer; Using a first mask to pattern the photoresist film to obtain a photoresist pattern, wherein the photoresist pattern covers a portion of the metal sublayer located in the first display area and a portion of the metal sublayer located in the second light-emitting area of ​​the second display area; The portion of the metal sublayer located in the second non-luminous area of ​​the second display area is etched using the photoresist pattern as a second mask to obtain the third gate layer.

21. The method for preparing a display panel according to claim 20, wherein: The methods for forming the first gate layer, the second gate layer and the third gate layer are the same, and the first mask used to form the first gate layer, the second gate layer and the third gate layer is the same mask.

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