An adaptive electronic filter

Abstract

An adaptive electronic filter (200) comprising a memristive-based filter circuit (201) for filtering an electrical input signal to obtain a filtered electrical signal. The adaptive electronic filter (200) further comprises a memristive-based subtractor circuit (202) for obtaining an error signal based on the filtered electrical signal and a reference signal and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristive-based filter circuit (201) based on the error signal to minimize the error signal.

Description

[0001] AN ADAPTIVE ELECTRONIC FILTER

[0002] TECHNICAL FIELD

[0003] The embodiments herein relate to an adaptive electronic filter and a method for filtering electrical signals. A corresponding computer program and a computer program carrier are also disclosed.

[0004] BACKGROUND

[0005] Traditional electronic filters with fixed filter coefficients are generally designed for a certain goal such as attenuation of all frequencies above a particular “cutoff” frequency within the input signal. In contrast, adaptive electronic filters have filter coefficients which are allowed to vary over time. Therefore, adaptive filters have self-adjusting characteristics such that the filter may adjust its filter coefficients automatically to adapt to the changes in its input signal via an adaptive algorithm. Adaptive filters work generally for the adaptation of signal-changing environments. Adaptive filters are usually used in the following contexts:

[0006] • when there is a spectral overlap between the signal and noise,

[0007] • in scenarios where it is necessary for the filter characteristics to be variable, adapted to changing conditions, and

[0008] • if the frequency band, which is occupied by the noise is unknown or varies with time.

[0009] For example, when the level of interference noise is strong and the noise spectrum overlaps with that of the desired signal, elimination of the interference using a conventional filter with fixed filter coefficients will fail to preserve the desired signal spectrum.

[0010] Applications of adaptive filters include the following:

[0011] • System Identification o Adaptive filters may be used to solve the general problem of system identification. For an unknown system, the quantities inside the system are not observable from the outside. In order to identify the impulse response / functionality of the unknow system, a known signal x(n) is sent to the unknown system and an adaptive filter. Then, the difference between the output signals of the unknown signal and the adaptive filter is obtained by a subtractor, which is called an error signal. The error signal is fed back to the adaptive filter to adjust the filter coefficients. This process is repeated for multiple iterations to lower the error signal until a certain level of error signal is reached. Finally, the frequency response of the filter converges to that of the unknown system, meaning that the unknown system may be identified.

[0012] • Wireless Channel Estimation o Nonidealities of a wireless channel distort transmitted signals. In cases where the effects of the distortion can be modeled as a linear filter, an adaptive filter may be used to model the effects of the channel. The basics behind this idea are like the previous use case, i.e. , “system identification”.

[0013] • Echo Cancellation for Long-Distance Transmission o In voice communication across telephone networks, an adaptive filter may be used to cancel the echoes caused by the junction boxes called hybrids near either end of the network link.

[0014] • Acoustic Echo Cancellation o A problem which is related to echo cancellation in telephone transmission systems is that of acoustic echo cancellation for conference-style speakerphones. Having considered a speakerphone, a caller would like to turn up the amplifier gains of both the microphone and the audio loudspeaker to transmit and hear the voice signals more clearly and with a high quality.

[0015] • Adaptive Noise Cancellation o Adaptive filters are used for adaptive noise cancelling in several applications including electroencephalogram (EEG) systems.

[0016] • Adaptive Equalization o A common problem in wireless communications is that signals are distorted by a communication channel. The adaptive filter may create an inverse response of the distortion to remove distortions from a received signal.

[0017] • Jammer Suppression o Adaptive filtering is a powerful tool for rejection of narrowband interference in a direct sequence spread spectrum receiver.

[0018] Linear Predictor o The linear predictor estimates the values of a signal at a future time. This scheme is widely used in speech processing applications such as speech coding in cellular telephony, speech enhancement, and speech recognition.

[0019] • Adaptive Speech Enhancement

[0020] • Adaptive Feedback Cancellation in Hearing Aids

[0021] A challenge with adaptive filters is that due to the feedback path within the structure of the adaptive filter, a level of parallelism may be limited. For example, to parallelize and increase the processing rate of a digital circuit, some registers are usually inserted within a long computational path. This increases the level of pipelining in that circuit, which improves the throughput. However, due to timing mismatch, this technique doesn’t work properly if the digital circuit includes a feedback path in its structure.

[0022] Also, as described before, the procedure of adaptive filtering is an iterative process, which degrades the throughput and latency of the adaptive filter. On the other hand, in order to achieve a high-performance adaptive filter, large number of iterations is needed. As a result, a trade-off between the throughput and performance of the adaptive filter becomes a very challenging task.

[0023] Further, high performance adaptive filters require high-performance FIR / IIR filters, which are generally realized by a large number of filter taps. This increases the hardware complexity of such filters significantly.

[0024] Moreover, as the filter order increases, a critical path of the circuit, i.e. a path between an input and an output with a maximum delay, will be increased as well. Thus, the latency and throughput of the filter will be constrained, which leads to some challenges in high-throughput and low-latency applications. As a result, design of a high throughput and low power digital filter is a bottleneck, especially for a large number of filter taps.

[0025] Moreover, another challenge in the design of the adaptive filter is about the selection of the error minimization algorithm, which is used to adapt the filter coefficients. Some of these algorithms are good in terms of performance / accuracy while they are very complex and expensive from hardware implementation perspective. Simpler algorithms usually suffer from low performance. Thus, the trade-off between complexity and performance of these algorithms is an issue in the context of adaptive filter design.

[0026] SUMMARY Embodiments herein disclose an adaptive electronic filter and a method for filtering electrical signals.

[0027] Specifically, embodiments herein disclose a memristive-based adaptive electronic filter and a method for filtering electrical signals with the memristive-based adaptive electronic filter. The disclosed memristive-based adaptive electronic filter uses Processing In Memory (PIM) techniques. All the functional blocks within the memristive-based adaptive electronic filter may be realized using analog crossbar arrays. However, in some embodiments a mixture of analog crossbar arrays and circuits without memristors, such as digital circuits, may be used to implement different functions of the memristive-based adaptive electronic filter, such as the error minimization.

[0028] An analog crossbar array, such as a 2-dimensional array, consists of M*N memristive devices, each of which can be programmed to represent an m-bit binary value.

[0029] According to a first aspect, the object is achieved by an adaptive electronic filter comprising a memristive-based filter circuit for filtering an electrical input signal to obtain a filtered electrical signal. The adaptive electronic filter further comprises a memristive- based subtractor circuit for obtaining an error signal based on the filtered electrical signal and a reference signal and an error minimization circuit configured to provide adapted filter coefficients of the memristive-based filter circuit based on the error signal to minimize the error signal.

[0030] According to a second aspect, the object is achieved by a method for filtering electrical signals with an adaptive electronic filter comprising a memristive-based filter circuit, a memristive-based subtractor circuit and an error minimization circuit configured to provide adapted filter coefficients of the memristive-based filter circuit based on an error signal to minimize the error signal.

[0031] The method comprises filtering an electrical input signal with the memristive-based filter circuit to obtain a filtered electrical signal.

[0032] The method further comprises obtaining an error signal with a memristive-based subtractor circuit based on the filtered electrical signal and a reference signal.

[0033] The method further comprises adapting filter coefficients of the memristive-based filter circuit based on the error signal. According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor, causes the processor to perform actions according to any of the aspects above.

[0034] According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0035] The memristive-based adaptive electronic filter is a fully parallel architecture, which can achieve an ultra-high throughput without the need for additional intermediate registers or buffers to increase the speed. Since the adaptive electronic filter comprises the memristive-based filter circuit, which comprises the analog crossbar array of memristive devices the adaptive electronic filter is able to fully process the electronic signal in parallel. The crossbar arrays according to embodiments herein enable performing massive multiply-accumulate (MAC) operations in parallel. More specifically, the crossbar arrays may compute matrix-vector multiplication (MVM) by calculating a dot-product of the input vector applied to crossbar rows (i.e. , word lines) and every column of the crossbar (i.e. , bit lines). This reduces the latency and increases throughput.

[0036] Since the adaptive electronic filter comprises the memristive-based filter circuit different filter coefficients may be efficiently updated by re-programming the memristive devices of the memristive-based filter circuit based on the error signal from the memristive-based subtractor circuit.

[0037] Since the adaptive electronic filter comprises the memristive-based filter circuit and the memristive-based subtractor circuit there is no need for analog-to-digital nor digital-to- analog conversion between the filter circuit and the subtractor circuit.

[0038] Since the adaptive electronic filter comprises the memristive-based filter circuit and the memristive-based subtractor circuit and since the memristive devices consume much less power compared to traditional multiply accumulate (MAC) modules, such as digital MAC modules, the proposed PIM-based filter has the potential of low power / energy consumption, which is a critical demand in many use cases (e.g., loT devices). The lower power consumption may in turn lead to increased battery life for battery-powered devices such as mobile phones. The latency of the memristive-based adaptive electronic filter is only limited by the read cycle of the crossbar array of the memristive-based filter circuit, and it is not limited by the filter order, type, etc.

[0039] The memristive-based adaptive electronic filter is computationally efficient since the computational complexity of the filter circuit and other required components is reduced from O(N) to 0(1), where N is the number of filter taps. This results in a significant reduction in hardware complexity of the adaptive filter.

[0040] The memristive-based adaptive electronic filter is fully flexible in terms of order of the filter as well as the filter coefficients.

[0041] The memristive-based adaptive electronic filter supports processing of complexvalued input samples as well as complex-valued filter coefficients without any degradation in the throughput and performance of the filter.

[0042] The memristive-based adaptive electronic filter enables realization of large adaptive filter banks, which include multiple filters with different filter orders and filtering characteristics.

[0043] The memristive-based adaptive electronic filter enables realization of an arbitrary frequency response. As a result, all above-mentioned advantages may be achieved regardless of the impulse response of the filter.

[0044] The memristive-based adaptive electronic filter enables efficient implementation of various algorithm functions like wireless channel estimation, system identification, noise cancellation, etc. which have been listed above.

[0045] BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In the figures, features that appear in some embodiments are indicated by dashed lines.

[0047] The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

[0048] Figure 1 is a block diagram schematically illustrating a crossbar array of memristors,

[0049] Figure 2 is a block diagram schematically illustrating a memristive-based adaptive filter according to embodiments herein,

[0050] Figure 3(a) is a block diagram schematically illustrating a part of a memristive-based error minimization circuit according to embodiments herein,

[0051] Figure 3(b) is a block diagram schematically illustrating a part of a memristive-based error minimization circuit according to embodiments herein, Figure 3(c) is a block diagram schematically illustrating a part of a memristive-based error minimization circuit according to embodiments herein,

[0052] Figure 3(d) is a block diagram schematically illustrating a memristive-based error minimization circuit according to embodiments herein,

[0053] Figure 4 is a flowchart illustrating embodiments of a method for filtering an electrical signal with a memristive-based adaptive filter,

[0054] Figure 5a is a further flowchart illustrating embodiments of a method for filtering an electrical signal with a memristive-based adaptive filter,

[0055] Figure 5b is a further flowchart illustrating embodiments of a method for adapting filter coefficients for a memristive-based adaptive filter,

[0056] Figure 6 is a further block diagram schematically illustrating a memristive-based adaptive filter according to embodiments herein,

[0057] Figure 7 is a block diagram schematically illustrating a system setup for system identification,

[0058] Figure 8 is a block diagram schematically illustrating a memristive-based filter circuit according to embodiments herein,

[0059] Figure 9 is a further block diagram schematically illustrating a memristive-based adaptive filter according to embodiments herein,

[0060] Figure 10 is a further block diagram schematically illustrating a memristive-based filter circuit according to embodiments herein,

[0061] Figure 11 is a further block diagram schematically illustrating a memristive-based adaptive filter according to embodiments herein,

[0062] Figure 12 is a further block diagram schematically illustrating a memristive-based adaptive filter according to embodiments herein,

[0063] Figure 13 is a block diagram schematically illustrating a baseband processor in which embodiments herein may be implemented,

[0064] Figure 14 is a block diagram schematically illustrating a network node.

[0065] Figure 15 is a block diagram schematically illustrating a wireless communications device.

[0066] Figure 16 is a block diagram schematically illustrating a wireless communication system.

[0067] DETAILED DESCRIPTION

[0068] Embodiments herein relate to adaptive electronic filters. An adaptive filter may for example include a finite impulse response (FIR) or an infinite impulse response (HR) filter, a subtractor circuit for obtaining an error signal, and a circuit to minimize the error signal. In this way, filter coefficients of the filter will be adapted, and the desired filter responses with a target characteristic will be achieved.

[0069] The FIR filter may be mathematically expressed as and the HR filter may be represented as where [n] is the input sequence, T[n] is the output of the filter, aitbit are the coefficients of the corresponding filter, and N and M is the filter length, i.e., number of filter taps.

[0070] In many use cases, characteristics of a filter should be changed and adapted under different system or environment conditions. Adaptive filters are widely used in many applications as listed above. In such applications, the filter coefficients may be determined during a training sequence where a known data pattern is transmitted.

[0071] Unlike many analog filters, filter characteristics of digital filters may easily be changed by varying the filter coefficients. This makes digital filters attractive in adaptive filtering applications. An important part of digital filter design is the appropriate selection of the filter coefficients as well as specifying the number of taps to realize the desired frequency response (i.e., transfer function).

[0072] However, digital adaptive filters may not be computationally efficient since the computational complexity of the filter circuit may be high. Furthermore, latency and power consumption may be high.

[0073] More specifically, embodiments herein relate to memristive-based adaptive electronic filters, i.e. to adaptive electronic filters implemented with crossbar arrays of memristors. A memristor may also be referred to as a memristive device. Analog memristive devices have emerged as a new technology for storing and processing information in analog domain. These devices make it possible to perform computations in a place where data is stored. This concept is called in-memory computing (or processing in memory), which eliminates the need for moving data from a memory to a processing unit. There are different types of memristive devices, which are differentiated with respect to the used materials, switching principles, device endurance, retention, etc. The main types of memristive devices include phase change memory (PCM), resistive randomaccess memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric memristive devices (FeRAM). Memristive devices may support a limited bit precision, attributed to the limited number of conductance levels that may be reliably programmed in the device. For example, a PCM device may support around 50 conductance levels, meaning that it may represent around 6 bits.

[0074] A number of memristor devices may be organized to form an analog crossbar array. Figure 1 illustrates an electronic device 301, such as a baseband signal processor, comprising a memristor crossbar array 310 which computes MVM by calculating a dotproduct of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines). The memristor crossbar array 310 is a two-dimensional array that comprises an M*N array of memristors 311, 312, 321, 322, each of which may be programmed to represent an m-bit binary value. A memristor is a tunable and programmable. The memristor may comprise a dielectric layer sandwiched by two electrodes. A unique feature of memristors is that the conductance depends on historical electrical signals, making them capable of working as nonvolatile memory. In addition, memristors may store multibit information with continuously tunable conductance, in contrast to binary states “0” and “1” in traditional digital storage systems, equipping them with higher bit density. Thus, the m-bit binary value of the memristor may be set or programmed by applying a current to the memristor. The binary value may depend on the amplitude of the current. Thus, an M x M matrix of binary words, G, may be represented by the memristor crossbar array 310 comprising M x M memristors. The input to the memristor crossbar array 310 is an electronic input signal of multiple samples, such as a vector of M analog voltages, e.g., V, which correspond to M binary values.

[0075] Analog crossbar arrays comprise parallel conductors, such as metal lines, termed word lines and bit lines, respectively, as electrodes of the memristors. The word lines and bit lines may be perpendicular to each other. The memristors are formed at the intersections of word and bit lines. In embodiments herein input conductors 331 of the analog crossbar array 310 corresponds to the word lines and output conductors 332 of the analog crossbar array 310 corresponds to the bit lines.

[0076] The analog crossbar array 310 computes MVM by calculating the dot-product of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e. , bit lines), all performed in analog domain using Ohm’s law for multiplication and Kirchhoff’s law for accumulation.

[0077] In Figure 1 the entries of a matrix G (an MxM matrix) are programmed to the memristive devices 311, 312, 321, 322 of the MxM crossbar array 310 while the input vector V (an Mxl vector) is applied to the crossbar rows. Note that, the vector V corresponds to the actual input vector (Input 1, ... , Input M), which may be converted to analog voltages using one or more DAC modules 304 illustrated in Figure 1. As a result, the following MVM may be realized using the illustrated crossbar array 310, where an output vector I is the output current of crossbar columns, which is equal to the result of matrix-vector multiplication, i.e., I = G- V. The output vector I may be converted to the corresponding binary words using one or more ADC modules 305 as shown in Figure 1. This conversion may be done either separately for each crossbar column (i.e., one ADC for each binary word) or in a time-multiplexed fashion and hence reduce ADC overhead (i.e., multiple bit lines may share one ADC 305).

[0078] In this disclosure vectors and matrices are represented using capital boldface letters while their entries are shown using normal letters.

[0079] Thus, when the electronic input signal is digital then the electronic device 301 further comprises the one or more DACs 304 adapted to convert the input signal of multiple samples to corresponding analog voltages Vi, V2, ... VN.

[0080] In other words, when the input signal of the multiple samples is digital, the electronic device 301 may further comprise the DACs 304 configured to convert the digital input signal of the multiple samples to the analog voltages.

[0081] There may be one DAC 304 per input sample. In some other embodiments there may be less than one DAC 304 per input sample as one DAC 304 may be shared among several input samples by multiplexing. For example, two input samples may share the same DAC 304. Output signals will be extracted from the bit lines (columns in Figure 1) of the crossbar array 310. If digital output values of the crossbar array 310 are needed then the outputs of the crossbar array 310 may be converted to digital values. Thus, the electronic device 301 may further comprise the one or more ADCs 305 adapted to convert the output samples, comprising analog output current, to corresponding digital output values. In other words, the electronic device 301 may further comprise ADCs 305 configured to convert the output from the respective output conductor to a digital signal.

[0082] If analog signals are needed in a next block in the processing chain then the ADCs 305 in the electronic device 301 may not be needed.

[0083] Further, if the analog outputs are sent to another crossbar array then they may be converted to voltage signals, which may be done by a resistor.

[0084] Embodiments of a PIM-based adaptive filter 200 will be presented in relation to Figure 2. Embodiments of the adaptive filter 200 will be exemplified with an adaptive FIR filter. However, other types of filters, such as HR filters, may also be implemented in a corresponding way which will be further explained below.

[0085] The goal of the adaptive filter 200 is to filter the input signal, X[n], such that the filtered signal, Y[n], matches the desired / target signal, Z[n],

[0086] The adaptive electronic filter 200 comprises a memristive-based filter circuit 201 for filtering an electrical input signal to obtain a filtered electrical signal. In detail, the memristive-based filter circuit 201 may comprise one or more crossbar arrays 210 of memristors 211, 212. Each memristor 211 , 212 of the one or more crossbar arrays 210 is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix.

[0087] The adaptive electronic filter 200 further comprises a memristive-based subtractor circuit 202 for obtaining an error signal based on the filtered electrical signal and a reference signal. The subtraction is based on memristors. The memristive-based subtractor circuit 202, may also be referred to as an error calculation circuit 202.

[0088] The adaptive electronic filter 200 further comprises an error minimization circuit

[0089] 203 configured to provide adapted filter coefficients of the memristive-based filter circuit

[0090] (201) based on the error signal to minimize the error signal. The error minimization circuit 203 may be memristive-based, i.e., the error minimization may be performed by memristors.

[0091] Thus, the adaptive electronic filter 200 may further comprise a memristive-based error minimization circuit 203 to minimize the error signal. The error minimization circuit 203 may be adapted to generate an updated set of filter coefficients of the filter function.

[0092] Details of the memristive-based error minimization circuit 203 are illustrated in Figures 3(a)-(d). Figure 3(d) illustrates a complete error minimization circuit 203.

[0093] The error minimization circuit 203 may be adapted to minimize the error signal by computing updated filter coefficients from previous filter coefficients. Then the error minimization circuit 203 may comprise at least one memristor-based multiplier 203a, 203b, illustrated in Figures 3(a) and 3(b), for multiplying the error signal with the input signal and a convergence factor. Thus, the error minimization circuit 203 may provide adapted filter coefficients of the memristive-based filter circuit 201 based on the error signal and further based on the input signal.

[0094] The at least one memristor-based multiplier 203a, 203b may comprise a multiplying memristor 203a, 203b. The memristor-based multiplier 203a, 203b is for example suitable for least-mean-square (LMS) error minimization algorithms.

[0095] The error minimization circuit 203 may further comprise an analog adder circuit 203c, illustrated in Figure 3(c), for computing an updated filter coefficient by adding the multiplied error signal to a previous filter coefficient and at least one current-to-voltage converter 203d, 203e operatively arranged between the at least one memristor-based multiplier 203a, 203b and the adder circuit 203c such that the multiplied error signal is converted to a voltage signal by the current-to-voltage converter 203d, 203e.

[0096] In some embodiments herein the adder circuit 203c is memristive-based. That is, the adding function may be performed by memristors.

[0097] In some embodiments herein the adaptive electronic filter 200 further comprises a first current-to-voltage converter 204 operatively arranged between the memristive- based filter circuit 201 and the memristive-based subtractor circuit 202 such that a filtered current signal is converted to a filtered voltage signal by the first current-to-voltage converter 204. The filtered voltage signal is input to the memristive-based subtractor circuit 202.

[0098] The adaptive electronic filter 200 may further comprise a second current-to- voltage converter 205 operatively arranged between the memristive-based subtractor circuit 202 and the memristive-based error minimization circuit 203 such that a current error signal is converted to a voltage error signal by the second current-to-voltage converter 205. The error voltage signal is input to the memristive-based error minimization circuit 203.

[0099] All the above-mentioned current-to-voltage converters may be implemented as resistors.

[0100] If a digital version of the filtered signal is needed as output from the adaptive filter 200, an analog to digital converter (ADC) 208 may be used as depicted by dashed lines in Figure 2.

[0101] Figure 4 illustrates a flowchart of a method for filtering electrical signals according to embodiments herein. The method actions below may be taken in any suitable order.

[0102] Action 400

[0103] The quantized filter coefficients corresponding to the targeted frequency response may be extracted. A frequency response of the targeted filter may be extracted, e.g., by means of fast Fourier transform (FFT), Z-Transform, etc., to calculate the corresponding quantized filter coefficients.

[0104] A structure of the required crossbar arrays to realize the filter may be specified. For example, the number of filter coefficients may be specified.

[0105] Action 401

[0106] The method may further comprise configuring the memristive devices of the adaptive electronic filter 200. The memristive devices of the memristive-based filter circuit 201 may be configured according to the matrix coefficients, i.e. , according to the filter coefficients. Thus, the vector / matrix of filter coefficients will be programmed to the memristors of the filter circuit 201.

[0107] Action 402

[0108] Then, the input samples may be sent to delay elements 206 and digital to analog converters (DACs) 207 of the adaptive electronic filter 200. The delay elements 206 and the DACs 207 may be part of the memristive-based filter circuit 201. The output voltage of the DACs 207 will be applied to the crossbar rows. Note that in Figure 2 there is no delay element for the first filter coefficient. The delay elements 206 may be implemented as registers. When the input is digital the delay elements 206 may be digital delay elements, such as digital registers.

[0109] The adaptive electronic filter 200 filters an electrical input signal with the memristive-based filter circuit 201 to obtain the filtered electrical signal.

[0110] The input signal, X[n], will be filtered by using the PIM-based filter circuit 201 and the filtered signal, Y[n], is generated as: where N defines the filter length / order. As mentioned before, other filter types with different frequency responses may be used in a corresponding way. For example, as described above an HR filter may be represented as:

[0111] Action 403

[0112] An analog filtered signal, which is generated at the crossbar column will be sent to the error calculation circuit 202.

[0113] Action 404

[0114] The error signal is calculated by comparing the filtered signal and the desired signal. That is, the desired signal, Z[n], is subtracted from the filtered signal, Y[n], to generate an error signal. This error signal will be used as a reference to update the filter coefficients and generate a new set of coefficients. To this end, if the desired signal is a digital signal, it will be converted to the corresponding analog signal using a DAC module 509 which may be part of the memristive-based subtractor circuit 202 (error calculation circuit 202). Then, the subtraction will be performed in analog domain using the memristive-based subtractor circuit 202.

[0115] Action 405

[0116] The filter coefficients will be updated based on the calculated error. The error signal represents the difference between the filtered signal and the desired signal. The error signal may be minimized using several methods, such as the least-mean-square (LMS), recursive-least-squares (RLS) algorithms. As a result, new filter coefficients will be generated, which will be programmed to the PIM-based filter circuit 201, as illustrated by double arrows in Figure 2. This process will be repeated until the error signal is lower than a certain threshold, which is specified according to the application.

[0117] Action 406

[0118] When the error has been minimized, the samples of the filtered signal may be converted to binary values using an analog-to-digital converter (ADC) 208. The conversion to the digital domain is optional, which is shown by dashed rectangle in Figure 2, and it depends on the application, i.e. , if a analog or digital filtered signal is needed.

[0119] This procedure may be repeated for the next sequence of input samples. If the size and type of the filter remain fixed, there is no need to reprogram the crossbar array of the filter circuit 201. However, if the filter coefficients are changed because of any reason such as changing the filtering scheme, etc., then the crossbar of the filter circuit 201 may be programmed with the new vector / matrix of coefficients.

[0120] Figure 5a illustrates a flowchart of a method for filtering electrical signals with the adaptive electronic filter 200 comprising the memristive-based filter circuit 201 , the memristive-based subtractor circuit 202 and the error minimization circuit 203 according to embodiments herein. The method may be performed by the adaptive electronic filter 200 or an electronic device comprising the adaptive electronic filter 200. The method actions below may be taken in any suitable order.

[0121] Action 501

[0122] The method may comprise configuring the memristive devices of the adaptive electronic filter 200. The memristive devices of the memristive-based filter circuit 201 may be configured according to the matrix coefficients, i.e., according to the filter coefficients.

[0123] Action 502

[0124] The adaptive electronic filter 200 filters an electrical input signal with the memristive-based filter circuit 201 to obtain the filtered electrical signal.

[0125] Action 503

[0126] In some embodiments herein the filtered electrical signal is a current signal and then the method may further comprise converting the filtered current signal to the filtered voltage signal by the first current-to-voltage converter 204 operatively arranged between the memristive-based filter circuit 201 and the memristive-based subtractor circuit 202.

[0127] The filtered voltage signal is input to the memristive-based subtractor circuit 202.

[0128] Action 504

[0129] An error signal is obtained with the memristive-based subtractor circuit 202 based on the filtered electrical signal and a reference signal.

[0130] Action 505

[0131] In some embodiments herein the error signal is a current signal and then the method may further comprise converting the current error signal to the voltage error signal by the second current-to-voltage converter 205 operatively arranged between the memristive-based subtractor circuit 202 and the memristive-based error minimization circuit 203. The error voltage signal is input to the memristive-based error minimization circuit 203.

[0132] Action 506

[0133] The filter coefficients of the memristive-based filter circuit 201 are adapted based on the error signal. The filter coefficients of the memristive-based filter circuit 201 are adapted such that the error signal is minimized. In some embodiments herein the filter coefficients of the memristive-based filter circuit 201 are adapted, and the error signal is minimized, with the memristive-based error minimization circuit 203.

[0134] Figure 5b is a flowchart which illustrates details of action 506.

[0135] Action 506a

[0136] When the filter coefficients of the memristive-based filter circuit 201 are adapted with the memristive-based error minimization circuit 203 then minimizing the error signal may comprise multiplying the error signal with the input signal and a convergence factor by the at least one memristor-based multiplier 203a, 203b.

[0137] Action 506b

[0138] Adapting the filter coefficients of the memristive-based filter circuit 201 may then further comprise converting the multiplied error signal to a voltage signal by the current-to- voltage converter 203d, 203e operatively arranged between the at least one memristor- based multiplier 203a, 203b and the analog adder circuit 203c. Action 506c

[0139] Adapting the filter coefficients of the memristive-based filter circuit 201 may further comprise computing an updated filter coefficient by adding the multiplied error signal to a previous filter coefficient by the adder circuit 203c.

[0140] The above actions may be repeated until the error signal is lower than a certain threshold, which may be predefined according to the target application. When the error is acceptable, the filter is adapted, and the coefficients have converged to a solution. At this state, the filter output, Y[n], is then said to match very closely to the desired signal, Z[n], If the input data characteristics, environment conditions, etc. are changed, the filter will adapt to the new conditions by generating a new set of coefficients.

[0141] Error Minimization

[0142] In the context of adaptive filters, the adaptation of the filter coefficient may be based on minimizing the mean squared error (MSE) between the filtered signal and the desired / target signal. The error signal, may be mathematically expressed as

[0143] E(n) = Z(n) - Y(n) (5) where Z(n) is the desired / target signal and Y(n) is the filtered signal. Several algorithms have been proposed in the literature to perform the error minimization. The most common adaptation algorithms are, Recursive Least Square (RLS), and the Least Mean Square (LMS). RLS algorithm may achieve a higher convergence speed compared to the LMS algorithm, but it has a high computation complexity. On the other hand, the LMS algorithm has the advantage of low complexity and a relatively good performance. Due to the lower computational complexity, the LMS algorithm is most commonly used in the design and hardware implementation of adaptive filters.

[0144] The LMS algorithm works based on the gradient search. The update process for the filter coefficients is performed via the following equation

[0145] Ci(n + 1) = Ci(n) +JuE(n)X(n) (6) where (n + 1) is the updated version of the coefficient (n), and . is the convergence factor, which has a value much less than 1 (it is directly proportional to the convergence speed and set offline). In embodiments herein the error minimization may be performed in the analog domain using the memristive-based error minimization circuit 203. However, it is also possible to realize hardware to implement equation (6) using a digital adder and multiplier. To this end, the computation in (6) may be rewritten as

[0146] Q(n + l) = Q(n) + W(n) (7) where W(n) = .. V(n) and 7(n) = E(n)X(n). As a result, the equation (7) may be realized using the two memristive-based multipliers 203a, 203b to calculate 7(n) = E(n)X(n) and W(n) = .. V(n), respectively, and the memristive-based adder 203c to compute the updated coefficient Q(n + 1) = Q(n) + W(n). All these small modules may be connected together via the current to voltage convertors 203d, 203e to realize the presented error minimization block 203.

[0147] Analog Input Signal

[0148] In some applications, the input signal of the adaptive filter 200 and consequently the desired / target signal are analog-domain signals. In such cases, a simple solution is to use one additional ADC to convert the input signal to the digital domain and then send it to the filter shown in Figure 2 to perform the filtering as described before. Also, the DAC module in the Error calculation block will then be removed, if the desired signal (Z) is in analog domain.

[0149] Some other embodiments of the adaptive filter 200 will now be shown in Figure 6 in case of an analog-domain input signal. The processing flow for the architecture in Figure 6 is very similar to the processing flow for the architecture of Figure 2. A difference is that in the architecture shown in Figure 5, “shifting the samples in time” is performed by using analog-domain delay elements 215 instead of digital delays. As a result, since the input signal and the desired / target signals are already in the analog domain, all the DAC modules may be removed from the adaptive filter 200, as in Figure 6.

[0150] Different realizations of analog-domain delays have been proposed. In some embodiments herein the analog-domain delay elements 215 comprises a one-period timedelay (OPTD), which may be created using a simple analog circuit. The OPTD block gets the input sample [n] and produces X[n - 1] (i.e., [n] which is delayed by one cycle). Thus, by connecting a series of such modules and applying [n] to the input of the first module, all the required delayed versions of X[n] will be generated. The output signal of the architecture in Figure 6 is generated in analog domain. But, if for any reason the digital-domain output signal of the filter is needed, an ADC may be used for this purpose, which is shown by dashed lined in Figure 6.

[0151] It is worth to mention that even if the input signal and the desired / target signal of the adaptive filter are in digital domain, it is still possible to employ the proposed architecture in Figure 6 instead of the one in Figure 2. The only thing which should be considered is that two DAC modules should be used to convert the input signal and the desired / target signal from digital domain to analog domain.

[0152] Thus, the architecture in Figure 6 supports realization of an adaptive filter for all possible scenarios: digital input-signal, analog input-signal, digital output-signal, and analog output-signal.

[0153] System Identification: Wireless Channel Estimation, Adaptive Equalization, etc.

[0154] Adaptive filters are used in many applications as mentioned above. One of the most important use cases of the adaptive filter is “system identification”.

[0155] The system identification is an approach to model the functionality of an unknown system. To this end, a system setup, which is illustrated in Figure 7 may be used. In this setup, an adaptive filter 701 is used in parallel with an unknown system 702, where both of them receive the same signal, X(n), as their inputs. The output signal of the unknown system to be identified is Z(n) and the output signal of the adaptive filter is Y(n). The goal is to find (i.e. , estimate) the frequency response of the unknown system (i.e. , functionality of the unknown system). To this end, the coefficients of the adaptive filter should be adjusted such that the error between these two signals, E(n) = Z(n) - Y(n), is lower than a certain threshold. The threshold is defined depending on the application.

[0156] Having considered the setup in Figure 7, when the magnitude of the error signal is minimized (e.g., when the mean square error (MSE) is minimized), it means that the filter represents the functionality of the unknown system, and the filter frequency response is matched to the frequency response of the unknown system.

[0157] The presented setup in Figure 7 enables to perform several complicated tasks like wireless channel estimation and adaptive equalization, which are essential blocks in wireless communication systems.

[0158] PIM-based Filter Bank There are some use cases, which may benefit from employment of multiple filters with different frequency responses. This is due to the fact that depending on the environmental and system conditions, different filtering characteristics are required. Moreover, there are other use cases, which receive multiple streams of data / information in parallel and process them simultaneously. Therefore, in such cases, multiple filters with the same or different coefficients may be implemented in parallel.

[0159] Some embodiments herein are directed to filter banks, such as multidimensional filter banks, using processing in memory approach. Let’s consider an N x M-dimensional filter bank, which includes M filters and N is the length of the largest filter within the filter bank. In order to realize such a filter bank using processing in memory, first, a matrix of coefficients may be created. To this end, the quantized coefficients corresponding to each filter will be considered as a separate column of this matrix. Thus, an N x M matrix of coefficients will be obtained in which m-th column (m = 1, represents the coefficients of m-th filter of the filter bank.

[0160] Note that, the proposed scheme enables implementation of filters with different lengths / orders. For example, if the m-th filter has the length of L (L < N), the first L entries of m-th column of the matrix will represent L filter coefficients and the rest of the entries in the m-th column will be considered as zero. As a result, filtering operation will be performed for M separate streams in parallel, in which the length, order, and coefficients of these M filters may be the same or different.

[0161] Finally, the coefficient matrix will be programmed to the memristors of a crossbar array of size N x M. The rest of the procedure is similar the one, which is explained in the flowchart of Figure 4. The output of each filter is generated via a corresponding crossbar column in a parallel manner.

[0162] A feature of the proposed filter bank is that it has a fixed throughput and latency. This means that the output samples of all filters in the filter bank will be generated in parallel and the throughput and latency of each filter is independent of the order and length of the other ones.

[0163] An example of this concept is illustrated in Figure 8, which shows a filter bank to realize four different FIR filters. The output samples of j-th filter of the filter bank may be mathematically expressed as

[0164] In some embodiments herein the filter circuit 201 is adapted to operate as a filter bank and then the one or more crossbar arrays 510 of memristors comprises a first column 201-1 of memristors and a second column 201-2 of memristors. The columns of memristors may be on the same crossbar array or on different crossbar arrays.

[0165] Each memristor of the first column 201-1 of memristors is configured to represent a respective filter coefficient of a first filter function implemented as a filter matrix and each memristor of the second column 201-2 of memristors is configured to represent a respective filter coefficient of a second filter function implemented as a filter matrix. The second filter function may differ from the first filter function.

[0166] In some embodiments herein a second number of filter coefficients of the second filter function differs from a first number of filter coefficients of the first filter function such that the second number of filter coefficients is larger than the first number of filter coefficients. However, the first column 201-1 of memristors 211, 212 may still comprise a first number of memristors which equal a second number of memristors of the second column 201-2. Then at least one memristor of the first column 201-1 of memristors 211, 212 may be configured with a value that equals zero.

[0167] This may be the case if the first column 201-1 and the second column 201-2 are two columns within one crossbar array, which means that the first column 201-1 and the second column 201-2 are connected together.

[0168] But, if the first column 201-1 and the second column 201-2 are realized using two separate crossbars, then the first column 201-1 and the second column 201-2 may have different sizes (i.e. , number of memristors).

[0169] Another feature of the filter bank according to embodiments herein is that only one set of delay elements and one set of DACs are needed. This means that the hardware cost resulting from the delay line and DACs is the same in a single filter and a filter bank with multiple filters.

[0170] Hardware Sharing in the Filter Bank In order to reduce the hardware cost of the filter bank even more, the ADCs in Figure 8 may be shared between multiple columns. For example, in case of a filter bank with M filters, 1, ...,M ADCs may be used to generate all the output samples of the filter bank in M, 1 read cycles.

[0171] Figure 9 illustrates the adaptive filter 200 comprising an adaptive filter bank 901 according to embodiments herein. The proposed adaptive filter bank 901 consists of a filter bank of size N x M, in which each crossbar column is programmed by multiple coefficients. As shown in Figure 9, depending on the required characteristic of the target adaptive filter, the proper output signal is selected using a multiplexer 216, which may be implemented with analog switches, as described below.

[0172] An important advantage of employing the filter bank 901 instead of a single filter within the adaptive filter is to have a more accurate initialization step as follows. In the first iteration of the adaptive filtering procedure, multiple versions of the filtered signal will be generated. These signals will be subtracted from the desired / target signal and the corresponding error signals will be generated accordingly. In this way, it may be seen which set of filter coefficients (corresponding to a crossbar column) results in a lower error. Consequently, for the rest of the filtering procedure the selected crossbar column will be used, and its coefficients will be updated as explained before.

[0173] As a result, the filtering procedure starts with a more accurate set of filter coefficients. This reduces the number of required iterations and the convergence time to match the filtered signal with the desired / target signal. The rest of the procedure is like the one described above, for example in relation to Figure 2.

[0174] Note that everything about the usage of digital / analog delay elements, the number of required DACs / ADCs, and the type of input / output signals, which have been described above is still valid and may be applied to the context of adaptive filter banks as well.

[0175] Thus in some embodiments herein the adaptive electronic filter 200 further comprises the multiplexer 216 operatively arranged between the filter circuit 201 and the subtractor circuit 202. The multiplexer 216 is adapted to multiplex filtered electrical signals from the filter circuit 201 adapted to operate as a filter bank such that a single filtered electrical signal is obtained from the filter circuit 201. PIM-based filter with real or complex input samples and real or complex coefficients

[0176] Embodiments described below enable fully parallel implementation of PIM-based filters for real and complex input samples as well as real and complex coefficients. Figure 10 illustrates an embodiments in which the memristive-based filter circuit 201 is adapted for real and complex input samples as well as real and complex coefficients. This is the most general case. The memristive-based filter circuit 201 may comprise an / V-tap FIR filter with the complex coefficients Co, In the embodiment of Figure 10 the input samples [n] are complex-valued. In order to realize this filter using PIM, a crossbar array of size N x 4 may be used. Thus, the crossbar array of memristors may comprise four columns. Note that these four columns may be in four separate crossbars or within two crossbars, as shown in Figure 10. Two of the four columns are programmed with the real part of the coefficients, while the other two columns are programmed with the imaginary part of the coefficients. In Figure 10 a first crossbar 221 comprising two columns of memristors, programmed with the real and imaginary part of the coefficients respectively, receives the real part of the input and a second crossbar 222 comprising two columns of memristors, programmed with the real and imaginary part of the coefficients respectively, receives the imaginary part of the input.

[0177] In Figure 10 first and third columns are programmed with the real part of the coefficients, which will receive and process the real and imaginary part of the input samples respectively. As shown in Figure 10 second and fourth columns are programmed with the imaginary parts of coefficient and these two columns will process the real and imaginary part of the input samples respectively. Thus, in the embodiment of Figure 10 a first column 201 -RR of memristors is programmed with the real part of the coefficients and receives and processes the real part of the input samples. A second column 201 -Rl of memristors is programmed with the imaginary part of the coefficients and receives and processes the real part of the input samples. A third column 201 -IR of memristors is programmed with the real part of the coefficients and receives and processes the imaginary part of the input samples. A fourth column 201-11 of memristors is programmed with the imaginary part of the coefficients and receives and processes the imaginary part of the input samples. If the input samples are only real or complex and the coefficients are complex only two of the columns are needed, either the first and second columns or the third and fourth columns. If the coefficients are only real or imaginary and the input samples are complex only two of the columns are needed, either the first and third columns or the second and fourth columns. The embodiment of Figure 10 is able to handle all cases.

[0178] The filtering operation may be performed following any of the flowcharts in Figures 4, 5a and 5b. Thus, in the most general case illustrated in Figure 10 four current signals will be generated and then they may be converted to voltage signals (e.g., using resistors).

[0179] As shown in Figure 10, two memristor-based circuits (adder circuits) are designed to combine the output signals of the crossbars and generate outputs of the filter circuit 201. A current-to-voltage converter may convert the output from the memristor-based adder circuits.

[0180] As further shown in Figure 10 the adaptive filter 200 may comprise two multiplexers (e.g., analog switches) to select the proper output signal.

[0181] Thus, in some embodiments herein the filter circuit 201 is adapted to filter a complex electrical signal or the filter coefficients are complex or both are complex. Then the filter circuit 201 comprises at least two columns 201-RR, 201 -Rl, 201 -I R, 201-11 of memristors and may further comprise two multiplexers 231, 232 for selecting electrical signals from the at least two columns 201 -RR, 201 -Rl, 201 -I R, 201-11 of memristors as the filtered electrical signal.

[0182] A first multiplexer 231 may select electrical signals with a first selector Sei 1 based on outputs from the second column 201 -Rl and the third column 201 -I R, while a second multiplexer 232 may select electrical signals with a second selector Sei 2 based on outputs from the first column 201-RR and the fourth column 201-11. The first multiplexer 231 may have 3 inputs: signals from the second column 201 -Rl and the third column 201- IR respectively and a combination of the signals from the second column 201 -Rl and the third column 201 -I R. The second multiplexer 232 may have 2 inputs: signals from the first column 201-RR and a combination of the signals from the first column 201-RR and the fourth column 201-11. Table 1 below shows all four possible configurations of the multiplexers. Which configuration to choose is dependent on whether the coefficients and / or input samples are real or complex.

[0183] Table 1. Different configuration of the multiplexers to support both real and complex inputs and coefficients.

[0184] Sei 2

[0185] Sei 1

[0186] To combine the outputs from the different columns the adaptive electronic filter 200 may further comprise two memristive-based adder circuits 241, 242 operatively arranged between the at least two columns 201 -RR, 201 -Rl, 201 -I R, 201-11 of memristors and the two multiplexers 231 , 232.

[0187] In some embodiments herein the adaptive electronic filter 200 further comprises a plurality of current-to-voltage converters 251, 252, 253, 254 operatively arranged between the at least two columns 201-RR, 201 -Rl , 201-IR, 201-11 of memristors and the two memristive-based adder circuits 241 , 242 and a respective current-to-voltage converter 261, 262 operatively arranged between the respective adder circuit 241 , 242 of the two memristive-based adder circuits 241 , 242 and the two multiplexers 231 , 232.

[0188] An advantage of the above embodiments is that the output of the crossbars are combined in the analog domain rather than converting them to the digital values and then performing addition / subtraction. This reduces the hardware cost and number of required ADCs from four in case of combining the crossbar outputs in digital domain, to two ADCs in embodiments disclosed above. Besides, these two ADCs may be removed if for any reason an analog output signal is requested at the output of the filter.

[0189] PIM-based Filter with Large Lengths

[0190] Although the size of practical crossbars is large enough to implement many filtering schemes, sometimes the filter length is large such that it cannot be realized using a single crossbar array. In such cases, the coefficient matrix may be divided into multiple smaller matrices, which may be programmed to multiple crossbar arrays.

[0191] An example of this concept is shown in Figure 11 for a FIR filter with length of 64, in which the generator matrix is divided into two parts each of size 32 and then they are programmed into two smaller crossbar arrays. In the embodiment of Figure 11 , an integrator block is used to add multiple current signals, which are generated in different crossbars. However, other hardware may be used to add the current signals. The output signal of the integrator block may be sent to an ADC module to generate binary-valued samples of the filtered signal.

[0192] PIM-based Filter with Bit-Serial Inputs

[0193] The input samples to the adaptive filter 200 may be represented by multiple bits, meaning that high-resolution ADCs and DACs may be needed. A supported bit resolution of ADCs determines the quantization error; the higher supported bit resolution the lower the quantization error and hence the better performance. Therefore, in case that either the ADC 208 do not support the required resolution or in order to improve the performance, each input sample, which is a binary word, may be sent to the DAC 207 in a bit-serial manner. Thus, at each time instance, which corresponds to the read cycle of the crossbar array, one bit of all input binary-words is applied to the corresponding DAC 207.

[0194] An example embodiment is illustrated for a FIR filter circuit 201 in Figure 12. In Figure 12 flip flops (FF) 271 are used as the delay elements. Also, due to the fact that the input is bit-serial, 1 -bit DACs are used, which reduces the hardware cost.

[0195] After W read cycles, the computation is completed where W is the number of bits per input binary-word (input sample). To calculate a final result in the bit-serial scheme, the adaptive filter 200 may comprise a shift and add circuit 281 operatively arranged after the ADC 208.

[0196] PIM-based filter with coefficients slicing

[0197] In order to improve the performance of the filter circuit 201 and / or to reduce the hardware cost by using simpler and cheaper memristive devices, it is possible to assign more than one memristor of the filter circuit 201 to every coefficient. In other words, each filter coefficient may be divided into multiple parts, which may be programmed to multiple memristive devices in a crossbar row of the filter circuit 201. Thus, each part of the filter coefficient may be programmed to a respective memristor.

[0198] For example, let’s consider each filter coefficient is represented by 8 bits, i.e. , q = c c c c c c Ci cf . As explained above, the coefficient q is programmed into one memristor. However, in a coefficient slicing scenario, the coefficient q is programmed into more than one memristor. Assuming two memristors per coefficient, c c c c is programmed to a first memristor and cfc c^cf may be programmed to a second memristor. Similar to the bit-serial input scenario, a shift & add circuit is employed to calculate the output samples of the filter circuit 201 by combining the outputs of the corresponding crossbar columns.

[0199] As mentioned above, adaptive filters may be used in many applications. In particular, the adaptive filter 200 according to embodiments herein may be used in different electronic devices. Figure 13 illustrates a baseband processor 1300, for example for wireless communications signals, comprising the adaptive filter 200. The adaptive filter 200 may for example filter the wireless communications signals. The baseband signal processor 1300 may comprise further baseband signal-processing circuits 1302 and the adaptive filter 200 may be adapted to be operatively coupled to the further signal processing circuits 1302 of the baseband signal processor 1300. Thus, an electronic device may comprise the adaptive electronic filter 200.

[0200] Figure 14 illustrates a network node 601 of a wireless communications network 170, the network node 601 comprising an electronic device comprising the adaptive filter 200.

[0201] Figure 15 illustrates a wireless communications device 602 comprising an electronic device comprising the adaptive filter 200.

[0202] The network node 601 and the wireless device 602 may be configured to perform the method actions of Figures 4, 5a and 5b above.

[0203] The embodiments herein may be implemented through a processor or one or more processors, such as the processor 1504, 1604 of a processing circuitry in the network node 601 and the wireless device 602 respectively, and depicted in Figure 15 and 16 together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computer program code for performing the embodiments herein when being loaded into the network node 601 and the wireless device 602 respectively. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server and downloaded to the network node 601 and the wireless device 602 respectively.

[0204] The network node 601 and the wireless device 602 respectively may further comprise a memory 1502, 1602 comprising one or more memory units. The memory comprises instructions executable by the processor in the network node 601 and the wireless device 602 respectively.

[0205] The respective memory 1502, 1602 is arranged to be used to store e.g. information, data, configurations, and applications to perform the methods herein when being executed in the network node 601 and the wireless device 602 respectively.

[0206] In some embodiments, a computer program 1503, 1603 comprises instructions, which when executed by the at least one processor, cause the at least one processor of the network node 601 and the wireless device 602 respectively to perform the actions above.

[0207] In some embodiments, a carrier 1505, 1605 comprises the computer program, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0208] The network node 601 and the wireless device 602 respectively may further comprise an input and output interface, I / O, 1506, 1606 configured to communicate with other devices. The input and output interface 1206, 1606 may comprise a receiver, such as a wireless receiver, (not shown) and a transmitter, such as a wireless transmitter, (not shown).

[0209] Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configured with software and / or firmware, e.g. stored in the network node 601 and the wireless device 602 respectively, that when executed by the respective one or more processors such as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application-Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0210] Figure 16 illustrates a wireless communications network 170 in which embodiments herein may be implemented. The wireless communications network 170 may use a number of different technologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems such as e.g. WCDMA and LTE and in future wireless communication systems, such as 6G systems.

[0211] Network nodes operate in the wireless communications network 170 such as the network node 601. The network node 601 provides radio coverage over a geographical area, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar. There may be more than one cell. For example, there may be a second cell 16 as well. The network node 601 may be a NR-RAN node, transmission and reception point e.g. a base station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless device within the service area depending e.g. on the radio access technology and terminology used. The respective network node 601 may be referred to as a serving radio access node and communicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE.

[0212] A number of wireless communications devices operate in the wireless communication network 170, such as the wireless communications device 602.

[0213] The wireless communications device 602 may be a mobile station, a non-access point (non-AP) STA, a STA, a user equipment and / or a wireless terminal, that communicate via one or more Access Networks (AN), e.g. RAN, e.g. via the network node 601 to one or more core networks (CN) e.g. comprising a CN node 13, for example comprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g. smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell.

[0214] When using the word "comprise" or “comprising” it shall be interpreted as nonlimiting, i.e. meaning "consist at least of".

[0215] The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1. An adaptive electronic filter (200) comprising: a memristive-based filter circuit (201) for filtering an electrical input signal to obtain a filtered electrical signal; and a memristive-based subtractor circuit (202) for obtaining an error signal based on the filtered electrical signal and a reference signal; and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristive-based filter circuit (201) based on the error signal to minimize the error signal.

2. The adaptive electronic filter (200) according to claim 1, wherein the error minimization circuit (203) is memristive-based.

3. The adaptive electronic filter (200) according to claim 2, wherein the error minimization circuit (203) is adapted to minimize the error signal by computing updated filter coefficients from previous filter coefficients and wherein the error minimization circuit (203) comprises: at least one memristor-based multiplier (203a, 203b) for multiplying the error signal with the input signal and a convergence factor; an analog adder circuit (203c) for computing an updated filter coefficient by adding the multiplied error signal to a previous filter coefficient; and at least one current-to-voltage converter (203d, 203e) operatively arranged between the at least one memristor-based multiplier (203a, 203b) and the adder circuit (203c) such that the multiplied error signal is converted to a voltage signal by the current-to-voltage converter (203d, 203e).

4. The adaptive electronic filter (200) according to claim 3, wherein the adder circuit (203c) is memristive-based.

5. The adaptive electronic filter (200) according to any of the claims 1-4, further comprising a first current-to-voltage converter (204) operatively arranged between the memristive-based filter circuit (201) and the memristive-based subtractor circuit (202) such that a filtered current signal is converted to a filtered voltage signal by the first current-to-voltage converter (204) which filtered voltage signal is input to the memristive-based subtractor circuit (202).

6. The adaptive electronic filter (200) according to any of the claims 2-5, further comprising a second current-to-voltage converter (205) operatively arranged between the memristive-based subtractor circuit (202) and the memristive-based error minimization circuit (203) such that a current error signal is converted to a voltage error signal by the second current-to-voltage converter (205) which error voltage signal is input to the memristive-based error minimization circuit (203).

7. The adaptive electronic filter (200) according to any of claims 1-6, wherein the memristive-based filter circuit (201) comprises one or more crossbar arrays (210) of memristors (211 , 212), wherein each memristor (211 , 212) of the one or more crossbar arrays (210) is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix.

8. The adaptive electronic filter (200) according to claim 7, wherein the filter circuit (201) is adapted to operate as a filter bank and wherein the one or more crossbar arrays (210) of memristors comprises a first column (201-1) of memristors and a second column (201-2) of memristors, wherein each memristor of the first column (201-1) of memristors is configured to represent a respective filter coefficient of a first filter function implemented as a filter matrix and wherein each memristor of the second column (201-2) of memristors is configured to represent a respective filter coefficient of a second filter function implemented as a filter matrix, wherein the second filter function differs from the first filter function.

9. The adaptive electronic filter (200) according to claim 8, wherein a second number of filter coefficients of the second filter function differs from a first number of filter coefficients of the first filter function such that the second number of filter coefficients is larger than the first number of filter coefficients, and wherein the first column (201-1) of memristors (211 , 212) comprises a first number of memristors which equal a second number of memristors of the second column (201-2).

10. The adaptive electronic filter (200) according to claim 9, wherein at least one memristor of the first column (201-1) of memristors (211 , 212) is configured with a value that equals zero.

11. The adaptive electronic filter (200) according to any of claims 7-10, further comprising a multiplexer (216) operatively arranged between the filter circuit (201) and the subtractor circuit (202), wherein the multiplexer (216) is adapted to multiplex filtered electrical signals from the filter circuit (201) adapted to operate as a filter bank such that a single filtered electrical signal is obtained from the filter circuit (201).

12. The adaptive electronic filter (200) according to any of claims 1-11, wherein the filter circuit (201) is adapted to filter a complex electrical signal or wherein the filter coefficients are complex or both, and wherein the filter circuit (201) comprises at least two columns (201 -RR, 201 -Rl, 201 -I R, 201-11) of memristors and further comprises two multiplexers (231 , 232) for selecting electrical signals from the at least two columns (201 -RR, 201 -Rl, 201 -I R, 201-11) of memristors as the filtered electrical signal.

13. The adaptive electronic filter (200) according to claim 12, further comprising: two memristive-based adder circuits (241 , 242) operatively arranged between the at least two columns (201 -RR, 201 -Rl, 201 -I R, 201-11) of memristors and the two multiplexers (231 , 232).

14. The adaptive electronic filter (200) according to claim 13, further comprising: a plurality of current-to-voltage converters (251 , 252, 253, 254) operatively arranged between the at least two columns (201 -RR, 201 -Rl, 201 -I R, 201-11) of memristors and the two memristive-based adder circuits (241, 242); and a respective current-to-voltage converter (261 , 262) operatively arranged between the respective adder circuit (241 , 242) of the two memristive-based adder circuits (241 , 242) and the two multiplexers (231, 232).

15. The adaptive electronic filter (200) according to any of claims 2-14, wherein the error minimization circuit (203) is adapted to generate an updated set of filter coefficients of the filter function.

16. An electronic device (400) comprising the adaptive electronic filter (200) according to any of the claims 1-15.

17. A network node (601) of a wireless communications network (170), the network node (601) comprising the electronic device () of claim 16.

18. A wireless communications device (602) comprising the electronic device () of claim 16.

19. A method (200) for filtering electrical signals with an adaptive electronic filter (200) comprising a memristive-based filter circuit (201), a memristive-based subtractor circuit (202) and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristive-based filter circuit (201) based on an error signal to minimize the error signal, the method comprising: filtering (502) an electrical input signal with the memristive-based filter circuit (201) to obtain a filtered electrical signal; and obtaining (504) an error signal with a memristive-based subtractor circuit (202) based on the filtered electrical signal and a reference signal; and adapting (506) filter coefficients of the memristive-based filter circuit (201) based on the error signal.

20. The method according to claim 19, wherein adapting (506) the filter coefficients of the memristive-based filter circuit (201) is performed with a memristive-based error minimization circuit (203).21 . The method according to claim 19 or 20, wherein minimizing (805) the error signal comprises: multiplying (805a) the error signal with the input signal and a convergence factor by at least one memristor-based multiplier (203a, 203b); converting (805b) the multiplied error signal to a voltage signal by a current-to- voltage converter (203d, 203e) operatively arranged between the at least one memristor-based multiplier (203a, 203b) and an analog adder circuit (203c); and computing (805c) an updated filter coefficient by adding the multiplied error signal to a previous filter coefficient by the adder circuit (203c).

22. The method according to any of claims 19-21 , further comprising: converting (802) a filtered current signal to a filtered voltage signal by a first current-to-voltage converter (204) operatively arranged between the memristive-based filter circuit (201) and thememristive-based subtractor circuit (202), which filtered voltage signal is input to the memristive-based subtractor circuit (202).

23. The method according to any of claims 19-22, further comprising: converting (804) a current error signal to a voltage error signal by a second current-to-voltage converter (205) operatively arranged between the memristive-based subtractor circuit (202) and the memristive-based error minimization circuit (203), which error voltage signal is input to the memristive-based error minimization circuit (203).

24. A computer program (1503, 1603), comprising computer readable code units which when executed on a computer causes the computer to perform the method according to any one of claims 19-23.

25. A carrier (1505, 1605) comprising the computer program according to the preceding claim, wherein the carrier (1505, 1605) is one of an electronic signal, an optical signal, a radio signal and a computer readable medium.

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