Method for producing a semiconductor component, and semiconductor component

Abstract

The invention relates to a method for producing a semiconductor component (10), the method comprising applying (S100) a semiconductor buffer layer (120) over a structured growth surface (101) of a substrate (100), wherein interconnected cavities (115) are formed in the region of an interface between the substrate (100) and the semiconductor buffer layer (120) and are closed in the growth direction. The method furthermore comprises forming (S110) a semiconductor layer (130, 140) over the semiconductor buffer layer (120) and detaching (S120) the semiconductor buffer layer (120) from the substrate (100) in the region of the interface.

Description

[0001] METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT

[0002] DESCRIPTION

[0003] In the manufacture of semiconductor components, semiconductor layers grown epitaxially on a substrate, such as a growth substrate, are often removed at the wafer level using so-called lift-off processes. In general, concepts are being sought that enable an improved lift-off process.

[0004] The present invention is based on the object of providing an improved method for producing a semiconductor component. Furthermore, it is the object of providing an improved semiconductor component.

[0005] According to embodiments, the problem is solved by the subject matter of the present patent claims. Further developments are defined in the dependent patent claims.

[0006] A method for producing a semiconductor component comprises applying a semiconductor buffer layer over a structured growth surface of a substrate, wherein interconnected cavities are formed in the region of an interface between the substrate and the semiconductor buffer layer and are closed in the growth direction. The method further comprises forming a semiconductor layer and detaching the semiconductor buffer layer from the substrate in the region of the interface.

[0007] For example, the semiconductor buffer layer can be applied by sputtering. The method can further comprise a temperature treatment step after forming the semiconductor buffer layer and before detaching the substrate.

[0008] According to further embodiments, the semiconductor buffer layer can also be grown epitaxially.

[0009] For example, the substrate may be selected from Si, SiC or sapphire.

[0010] The semiconductor buffer layer may, for example, contain AIN or GaN or consist of AIN or GaN.

[0011] According to embodiments, the growth surface can be structured into columns. According to further embodiments, the growth surface can be structured into truncated cones or pyramids. For example, the columns or truncated cones or pyramids can be at least partially hollow.

[0012] According to embodiments, a sacrificial layer may be disposed over a main surface of the substrate. A material of the sacrificial layer may be different from the substrate material. The growth surface and the interface may correspond to a surface of the sacrificial layer.

[0013] According to embodiments, the detachment may comprise introducing an etching liquid into the cavities, thereby separating the substrate from the semiconductor buffer layer.

[0014] According to further embodiments, the detachment may comprise heating the substrate, thereby separating the substrate from the semiconductor buffer layer. Applying a semiconductor layer may comprise applying semiconductor layers to form an optoelectronic semiconductor component having an active zone for generating or absorbing radiation.

[0015] According to embodiments, the method may further comprise structuring the growth surface of the substrate. For example, structural elements are formed in the growth surface during structuring. In this case, a structural size of the structural elements as well as the growth conditions during application of the semiconductor buffer layer can be adjusted such that a roughness and an angle for light extraction are adjusted in the region of a first main surface of the semiconductor buffer layer.

[0016] Further embodiments relate to a semiconductor component that can be produced by the described method. The semiconductor component can, for example, be an LED (light-emitting diode).

[0017] The accompanying drawings are intended to provide an understanding of embodiments of the invention. The drawings illustrate embodiments and, together with the description, serve to explain the same. Further embodiments and many of the intended advantages will be readily apparent from the following detailed description. The elements and structures shown in the drawings are not necessarily to scale. Like reference numerals refer to like or corresponding elements and structures.

[0018] Fig. 1A to 1E illustrate examples of process steps in structuring a growth surface of a

[0019] Substrate. Fig. 2A illustrates a method for manufacturing a semiconductor device according to embodiments.

[0020] Fig. 2B is a perspective view illustrating a method of manufacturing a semiconductor device according to further embodiments.

[0021] Fig. 2C is a perspective view illustrating a method according to embodiments.

[0022] Figs. 2D and 2E are perspective views illustrating a method of manufacturing a semiconductor device according to further embodiments using hollow structural elements.

[0023] Fig. 3 shows an example of a semiconductor device according to embodiments.

[0024] Fig. 4 summarizes a method according to embodiments.

[0025] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which specific embodiments are shown for purposes of illustration. In this context, directional terminology such as "top", "bottom", "front", "back", "over", "on", "in front of", "behind", "fore", "rear", etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology is for the purpose of explanation and is not in any way limiting. The description of the embodiments is not limiting, since other embodiments exist and structural or logical changes may be made without departing from the scope defined by the claims.In particular, elements of embodiments described below may be combined with elements of other described embodiments, unless the context indicates otherwise.

[0026] The terms "wafer" or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure having a semiconductor surface. Wafer and structure are to be understood as including doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base support, and other semiconductor structures. For example, a layer of a first semiconductor material can be grown on a growth substrate of a second semiconductor material, for example a GaAs substrate, a GaN substrate, or a Si substrate, or of an insulating material, for example a sapphire substrate.

[0027] Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of semiconductor materials particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, which can be used to generate ultraviolet, blue or longer-wavelength light, for example, such as GaN, InGaN, AlN, AlGaN, AlGaNN, AlGaNBN, phosphide semiconductor compounds, which can be used to generate green or longer-wavelength light, for example, such as GaAsP, AlGaNP, GaP, AlGaP, as well as other semiconductor materials such as GaAs, AlGaAs, InGaAs, AlInGaAs, SiC, ZnSe, ZnO, Ga2Oa, diamond, hexagonal BN and combinations of the materials mentioned. The stoichiometric ratio of the compound semiconductor materials can vary. Further examples of semiconductor materials can include silicon, silicon-germanium and germanium.

[0028] The term "substrate" generally includes insulating, conductive, or semiconductor substrates.

[0029] The term "vertical," as used in this description, is intended to describe an orientation that is substantially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction may, for example, correspond to a growth direction during layer growth.

[0030] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation or alignment that is substantially parallel to a first surface of a substrate or semiconductor body. This can be, for example, the surface of a wafer or a chip (die).

[0031] The horizontal direction can, for example, lie in a plane perpendicular to a growth direction when growing layers.

[0032] Figs. 1A to IE illustrate method steps for structuring a growth surface 101 of a substrate, for example before carrying out and in preparation for the method according to the invention.

[0033] Fig. 1A shows a cross-sectional view of a substrate 100. The substrate 100 may be, for example, a growth substrate or any other substrate, for example, with a sacrificial layer 103 disposed thereover. Examples of the substrate 100 include, for example, sapphire, Si, SiC, AlN, and others. The sacrificial layer 103 may be any layer over which a subsequently deposited semiconductor buffer layer can be grown.

[0034] As shown in Fig. 1B, for example, first a hard mask layer 109 and subsequently a photoresist layer 110 are applied over the growth surface 101 of the substrate 100. The growth surface 101 can, for example, be the surface of the substrate 100 or the sacrificial layer 103. The hard mask layer 109 can contain a material that is selectively etchable with respect to the material of the substrate 100 and, optionally, the sacrificial layer 103. For example, a material of the hard mask layer 109 can be silicon nitride.

[0035] As shown in Fig. 1C, the photoresist layer 110 may be patterned in a suitable manner. For example, the photoresist layer 110 may be patterned photolithographically. According to embodiments, the photoresist layer 110 may also be patterned by nanoimprinting or other methods.

[0036] The pattern of the structured photoresist layer 110 is transferred into the hard mask layer 109, for example, by etching the hard mask layer 109 at the locations not covered with photoresist material. Subsequently, after the residues of the photoresist material have been removed, the substrate 100, or the sacrificial layer 103 applied over the substrate 100, is etched using the structured photoresist layer 110 (Fig. 1D). For example, the etching process 102 can be a dry etching process, for example an RIE (reactive ion etching process) or ICP (plasma-assisted etching, "inductively coupled plasma reactive ion etching"). As a result, as shown in Fig. 1E, a plurality of structural elements 105 are formed in the region of the growth surface 101. According to embodiments, a minimum diameter d of the structural elements 105 may be at least 50 nm, for example more than 100 nm.The diameter d can be less than 3 pm. The distance between adjacent structural elements can be greater than 100 nm. The distance between adjacent structural elements 105 can be less than 3 pm. For example, the distance can be in a range between 300 and 900 nm.

[0037] As shown in Fig. 2A, a semiconductor buffer layer 120 is subsequently applied over the structured growth surface 101. A method for producing the semiconductor buffer layer 120 can, for example, include a sputtering method. For example, the semiconductor buffer layer 120 can have a partial layer that is applied by sputtering. This partial layer can be treated in a subsequent high-temperature annealing step at a temperature of more than 1000°C, for example more than 1700°C. At such a high temperature, the material of the semiconductor buffer layer 120, for example AIN, recrystallizes, resulting in a very good crystal quality. Subsequently, an MOVPE method can be carried out, by means of which a further partial layer of the semiconductor buffer layer 120 is grown. Subsequently, further layers of the semiconductor layer stack 132 can be grown using MOVPE.

[0038] The buffer layer is epitaxially overgrown. As a result, cavities 115 are formed in the region of an interface between the substrate 100 and the semiconductor buffer layer 120. These cavities 115 are closed in the growth direction, i.e., for example, a vertical or z-direction, by coalescence. The cavities 115 are interconnected. The growth process for growing the semiconductor buffer layer 120 is carried out such that the layer 120 grows together after a certain layer thickness and thus forms a closed surface.

[0039] Alternatively or additionally, the semiconductor buffer layer 120 can also be grown epitaxially.

[0040] For example, the semiconductor buffer layer 120 may contain AlN. For example, a layer thickness of the semiconductor buffer layer 120 may be greater than 1 μm, for example, 1 to 2 μm. The term "in the region of an interface between the substrate and the semiconductor buffer layer" is intended to include the case where a sacrificial layer 103 is formed over the substrate 100. In this case, the term "interface between the substrate" refers to the interface between the sacrificial layer 103 and the semiconductor buffer layer 120.

[0041] For example, a height h of the resulting cavities 115, measured in the vertical direction, can be at least 200 nm, for example, 300 to 350 nm. A minimum height of the cavities 115 ensures a minimum volume of the etching liquid in a subsequent etching step, if this is carried out with an etching liquid. The diameter and spacing of the structural elements in the region of the first main surface of the semiconductor buffer layer 120 are determined by dimensioning the diameter and spacing of the structural elements 105.

[0042] Subsequently, an epitaxial growth process can be performed, for example, MOVPE (metalorganic chemical vapor phase epitaxy). For example, semiconductor layers can be grown epitaxially to form a semiconductor layer stack (not shown in Fig. 2A, shown in Fig. 3). In a subsequent process step, the semiconductor buffer layer 120 is detached from the substrate 100 in the region of the cavities.

[0043] This can be done, for example, by introducing an etching liquid 123 in the region of the cavities. For example, a suitable etchant can be introduced which etches the substrate 100. Accordingly, the substrate 100 can be separated from the semiconductor buffer layer 120 by etching. For example, during the etching process, a detachment process can take place between the first and the second partial layer of the semiconductor buffer layer 120, i.e., the separation between substrate 100 and semiconductor buffer layer 120 takes place between the partial layer applied by sputtering and the partial layer grown by MOVPE. KOH-based etchants, for example, can be used as the etching agent.

[0044] When structuring the growth surface of the substrate, the distance and diameter of the structural elements 105 can be determined as a function of the etching liquid 123 or the selectivity of the etching liquid 123. If, for example, the vertical etching rate is equal to or greater than the horizontal rate, the lateral dimensions of the structural elements between the cavities are not selected to be too large, since otherwise too much of the functional semiconductor layers will be removed vertically. For example, with a vertical to horizontal etching rate ratio of 1:1, a lateral layer thickness between the cavities 115 can be approximately 1 pm or approximately the vertical layer thickness of the semiconductor buffer layer 120. Accordingly, with a larger ratio, the lateral layer thickness between the cavities 115 must be reduced or the diameter of the structural elements must be reduced.As a result of the wet-chemical etching process, a roughening of the substrate side can also be achieved. For example, when using KOH-based etchants, the nitrogen polarity can be attacked while the metal polarity is not attacked. In this way, in addition to the already produced structural elements, inclined side flanks can result from the etching. According to further embodiments, however, other etchants suitable for etching the material of the semiconductor buffer layer or the substrate can also be used.

[0045] For example, when structuring the growth surface of the substrate 100, as illustrated in Figs. 1A to 1E, the parameters for generating the structural elements 105 can be adjusted such that a desired roughness as well as angles for light extraction are set in the region of the first main surface 122 of the semiconductor buffer layer 120. In general, wet-chemical etchants that dissolve the semiconductor material in the vicinity of the cavities 107 leave the detached or first main surface of the semiconductor buffer layer 120 in a rough state, the basic structure of which is predetermined by the previous structural elements 105.

[0046] As shown in Fig. 2A, the individual structural elements 105 may be truncated cone-shaped or truncated pyramid-shaped. More specifically, a diameter of the structural elements 105 may vary in the vertical direction.

[0047] Fig. 2B shows a further example of a workpiece 15 in which, in contrast to the view shown in Fig. 2A, the structural elements 105 are columnar. For example, a diameter of the structural elements 105 may be constant or nearly constant in the vertical direction. As further shown in Fig. 2B, the structural elements formed in the semiconductor buffer layer 120 may increase in size in the vertical direction. Accordingly, the structural elements in the semiconductor buffer layer 120 may be truncated cones or truncated pyramids.

[0048] According to further embodiments, the semiconductor buffer layer 120 and the substrate 100 can separate from each other due to mechanical forces. For example, mechanical shear forces can be applied between the semiconductor buffer layer 120 and the substrate 100 and lead to detachment. The shear forces can arise, for example, due to the different thermal expansion coefficients of the substrate 100 and the semiconductor buffer layer 120.

[0049] For example, after fabricating the semiconductor buffer layer 120 and further layers of the semiconductor layer stack 132, a thermal heating step can be performed. Due to its temporal stress profile, this step can lead to a targeted tearing or breaking of the semiconductor columns between the predetermined breaking points defined by the cavities 115.

[0050] According to further embodiments, a strain component can be introduced via a lattice mismatch between the semiconductor buffer layer 120 and other semiconductor layers of the semiconductor layer stack 132. For example, the composition and layer thickness of the semiconductor layers of the semiconductor layer stack 132 can be adjusted to achieve the highest possible strain.

[0051] According to further embodiments, cavities 107 can be arranged within the structural elements 105 in the region of the growth surface of the substrate. This is illustrated in Figs. 2D and 2E. If cavities 107 are arranged in the region of the structural elements 105, they are initially overgrown during the growth of the semiconductor buffer layer 120. However, the cavities 107 in the region of the structural elements 105 reduce the amount of material to be etched laterally and the lift-off process can be completed more quickly. This structure can also be used for a mechanical lift-off since the adhesion between the substrate and the semiconductor buffer layer 120 is reduced due to the cavities 107.

[0052] If the applied semiconductor layer stack 132 comprises layers for generating or absorbing radiation, the presence of the cavities 107 can prevent the active region from being impaired during etching.

[0053] Fig. 3 shows a perspective view of an example of a resulting semiconductor device 10. The semiconductor device 10 comprises the semiconductor buffer layer 120 and further layers, for example a semiconductor layer stack 132. For example, the semiconductor layer stack 132 may comprise a first semiconductor layer 130 of a first conductivity type, for example n-conducting, and a second semiconductor layer 140 of a second conductivity type, for example p-conducting. An active zone 135 for generating or receiving radiation may be arranged between the first semiconductor layer 130 and the second semiconductor layer 140.

[0054] For example, an active zone 135 can be arranged between the first and second semiconductor layers 130, 140. The active zone 135 can, for example, have a pn junction, a double heterostructure, a single quantum well structure (SQW), or a multiple quantum well structure (MQW) for generating radiation. The term "quantum well structure" has no significance with regard to the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires, and quantum dots, as well as any combination of these layers. As further shown in Fig. 3, a backside structuring 121 is present on the side of the semiconductor buffer layer 120 that has been detached from the substrate 100.The backside structuring 121 corresponds to the region that was formed by growing the semiconductor buffer layer 120 over the structured growth surface and was subsequently etched according to the exemplary embodiments with chemical stripping. The side of the semiconductor buffer layer 120 facing away from the first semiconductor layer 130 is thus structured without performing an additional structuring step. Accordingly, the light extraction from a resulting semiconductor component can be increased without requiring additional process steps.

[0055] For example, the semiconductor component 10 shown in Fig. 3 can be an optoelectronic semiconductor component, for example an LED (light emitting diode). However, it is obvious that the described method is applicable to any semiconductor components. Accordingly, the manufactured semiconductor component can also be a non-optoelectronic semiconductor component, for example a transistor or the like.

[0056] The semiconductor layers of the semiconductor layer stack 132 may contain, for example, GaN, for example AlGaN or InGaAlN or others.

[0057] As has been described, a method is provided with which a lift-off process can be carried out without using a laser in order to remove a semiconductor layer stack from a substrate 100. Accordingly, the laser lift-off process to be carried out, that is to say in particular the optical transmittance for the laser beam, no longer has to be taken into account when selecting the semiconductor materials. Due to the described structuring of the growth surface of the substrate, detachment can, for example, be carried out by etching without further structuring to produce fluid channels for the etchant being necessary. When carrying out the described method, a back-side structuring 121 can be produced in the region of the first main surface of the semiconductor buffer layer 120, which increases the coupling-out efficiency for generated electromagnetic radiation.Accordingly, a thin-film chip is provided which can be operated at significantly higher currents and which has a higher light extraction efficiency compared to an LED chip emitting through the unstructured sapphire substrate.

[0058] If only a sacrificial layer is etched over the substrate 100 during the etching to detach the semiconductor buffer layer from the substrate, this substrate 100 can be used for further processes.

[0059] Fig. 4 summarizes a method according to embodiments. A method for producing a semiconductor component comprises applying (S 100 ) a semiconductor buffer layer over a structured growth surface of a substrate, wherein interconnected cavities are formed in the region of an interface between the substrate and the semiconductor buffer layer and are closed in the growth direction. The method further comprises forming (S 110 ) a semiconductor layer over the semiconductor buffer layer and detaching (S 120 ) the semiconductor buffer layer from the substrate in the region of the cavities.

[0060] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is limited only by the claims and their equivalents.

[0061] LIST OF REFERENCE SYMBOLS

[0062] 10 semiconductor components

[0063] 15 Workpiece

[0064] 100 substrate

[0065] 101 Growth surface

[0066] 102 Etching processes

[0067] 103 Sacrificial Layer

[0068] 105 Structural element

[0069] 107 Cavity

[0070] 110 Photoresist material

[0071] 115 Cavity

[0072] 120 semiconductor buffer layer

[0073] 121 Back structuring

[0074] 122 first main surface of the semiconductor buffer layer

[0075] 123 Etching fluid

[0076] 130 first semiconductor layer

[0077] 132 semiconductor layer stacks

[0078] 135 active zone

[0079] 140 second semiconductor layer

Claims

CLAIMS 1. A method for producing a semiconductor device (10), comprising: Applying (S100) a semiconductor buffer layer (120) over a structured growth surface (101) of a substrate, wherein interconnected cavities (115) are formed in the region of an interface between the substrate (100) and the semiconductor buffer layer (120) and are closed in the growth direction, wherein the application of the semiconductor buffer layer (120) comprises a sputtering process; Forming (S110) a semiconductor layer (130, 140) over the semiconductor buffer layer (120), and Detaching (S120) the semiconductor buffer layer (120) from the substrate (100) in the region of the interface, further comprising a temperature treatment step to a temperature greater than 1000°C after carrying out the sputtering method and before forming (S110) the semiconductor layer (130, 140).

2. The method of claim 1, wherein the substrate (100) is selected from Si, SiC or sapphire.

3. The method of claim 1 or 2, wherein the semiconductor buffer layer (120) contains AlN or GaN.

4. Method according to one of the preceding claims, wherein the growth surface (101) is structured into columns.

5. The method according to any one of claims 1 to 3, wherein the growth surface (101) is structured into truncated cones or pyramids.

6. The method according to claim 4 or 5, wherein the columns or Truncated cones or pyramids are at least partially hollow.

7. The method according to any one of the preceding claims, wherein a sacrificial layer is disposed over a main surface of the substrate and the growth surface and the interface correspond to a surface of the sacrificial layer.

8. The method according to any one of the preceding claims, wherein the detaching comprises introducing an etching liquid (123) into the cavities (115), thereby separating the substrate (100) from the semiconductor buffer layer (120).

9. The method according to any one of claims 1 to 7, wherein the detaching comprises heating the substrate (100), thereby separating the substrate (100) from the semiconductor buffer layer (120).

10. The method according to any one of the preceding claims, wherein the application of a semiconductor layer comprises the application of semiconductor layers (130, 140) for forming an optoelectronic semiconductor component having an active zone (135) for generating or receiving radiation.

11. The method according to claim 10, further comprising structuring the growth surface of the substrate, wherein during structuring, structural elements (105) are formed in the growth surface (101) and a structural size of the structural elements (105) and the growth conditions during application of the semiconductor buffer layer (120) are adjusted such that a roughness and an angle for light extraction are adjusted in the region of a first main surface (122) of the semiconductor buffer layer (120).

12. Semiconductor component (10) which can be produced by the method according to one of the preceding claims.

13. Semiconductor component (10) according to claim 12, which is an LED.

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