Semiconductor device, production method therefor, and power conversion device

Abstract

The present disclosure relates to a semiconductor device comprising a semiconductor layer that is constituted from a gallium oxide semiconductor of a first conductivity type, a first main electrode that is formed on a first main surface of the semiconductor layer, and an electric field relaxation layer of a second conductivity type that is formed on the semiconductor layer outside of the first main electrode, wherein the electric field relaxation layer includes a first region on the first main electrode side thereof and a second region on the opposite side from the first main electrode, and the second region has a smaller acceptor surface density than the first region.

Description

Semiconductor device, manufacturing method thereof, and power conversion device

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices that use gallium oxide semiconductors.

[0002] In semiconductor devices such as vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and vertical SBDs (Schottky Barrier Diodes), a method of providing a p-type electric field relaxation layer around a main electrode on an n-type semiconductor substrate to maintain a breakdown voltage is widely known.

[0003] For example, Patent Document 1 discloses a technique for alleviating the concentration of an electric field by providing a p-type oxide semiconductor layer around a Schottky electrode on an n-type oxide semiconductor layer.

[0004] Japanese Patent Application Laid-Open No. 2017-112126

[0005] In FIGS. 3 and 4 of Patent Document 1, a continuous p-type oxide semiconductor layer or a discontinuous p-type oxide semiconductor layer is provided around the Schottky electrode. However, with such a simple arrangement of the p-type oxide semiconductor layer, there is a possibility that an electric field will concentrate at the edge of the Schottky electrode and the outer peripheral edge of the p-type oxide semiconductor layer.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that suppresses the concentration of an electric field at at least one of the end of a main electrode and the outer peripheral end of an electric field relaxation layer.

[0007] The semiconductor device according to the present disclosure comprises a semiconductor layer made of a gallium oxide semiconductor of a first conductivity type, a first main electrode formed on a first major surface of the semiconductor layer, and an electric field relaxation layer of a second conductivity type formed on the semiconductor layer outside the first main electrode, wherein the electric field relaxation layer includes a first region on the side of the first main electrode and a second region on the opposite side of the first main electrode, and the second region has a smaller areal density of acceptors than the first region.

[0008] According to the semiconductor device of the present disclosure, the area density of acceptors in the electric field relaxation layer decreases toward the outside, thereby mitigating electric field concentration at at least one of the end of the first main electrode and the outer peripheral end of the electric field relaxation layer.

[0009] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. FIG. 2 is a conceptual diagram illustrating the extent of a depletion layer in the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a configuration of a first modification of the semiconductor device according to the first embodiment. FIG. 4 is a conceptual diagram illustrating the extent of a depletion layer in the first modification of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view showing a configuration of a second modification of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a third modification of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a configuration of a fourth modification of the semiconductor device according to the first embodiment. FIG. 8 is a conceptual diagram illustrating the extent of a depletion layer in the fourth modification of the semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view showing a configuration of a fifth modification of the semiconductor device according to the first embodiment. FIG. 10 is a conceptual diagram illustrating the extent of a depletion layer and equipotential lines in the fifth modification of the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view showing a configuration of a sixth modification of the semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view showing a configuration of a seventh modification of the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view showing a configuration of a eighth modification of the semiconductor device according to the first embodiment. FIG. 14 is a cross-sectional view showing a configuration of a second embodiment. FIG. 15 is a cross-sectional view showing a configuration of a first modification of the semiconductor device according to the second embodiment. 1 is a cross-sectional view illustrating a configuration of a modified example 2 of the semiconductor device of the second embodiment. FIG. 2 is a cross-sectional view illustrating a manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 3 is a cross-sectional view illustrating a manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 4 is a cross-sectional view illustrating a manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 5 is a cross-sectional view illustrating a manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 6 is a cross-sectional view illustrating another manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 7 is a cross-sectional view illustrating another manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 8 is a cross-sectional view illustrating another manufacturing method of a modified example 1 of the semiconductor device of the second embodiment. FIG. 9 is a cross-sectional view illustrating a configuration of a modified example 3 of the semiconductor device of the second embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a modified example 4 of the semiconductor device of the second embodiment.10 is a cross-sectional view showing the configuration of Modified Example 5 of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing the configuration of Modified Example 6 of the semiconductor device of Embodiment 2. FIG. 12 is a cross-sectional view showing the configuration of Modified Example 7 of the semiconductor device of Embodiment 2. FIG. 13 is a cross-sectional view illustrating a method for manufacturing Modified Example 7 of the semiconductor device of Embodiment 2. FIG. 14 is a cross-sectional view illustrating a method for manufacturing Modified Example 7 of the semiconductor device of Embodiment 2. FIG. 15 is a cross-sectional view illustrating a method for manufacturing Modified Example 7 of the semiconductor device of Embodiment 2. FIG. 16 is a cross-sectional view illustrating a method for manufacturing Modified Example 7 of the semiconductor device of Embodiment 2. FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device of Embodiment 3. FIG. 18 is a conceptual diagram showing equipotential lines formed in the semiconductor device of Embodiment 3. FIG. 19 is a cross-sectional view showing the configuration of Modified Example 1 of the semiconductor device of Embodiment 3. FIG. 19 is a cross-sectional view showing the configuration of Modified Example 2 of the semiconductor device of Embodiment 3. FIG. 19 is a cross-sectional view showing the configuration of Modified Example 3 of the semiconductor device of Embodiment 3. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor device of Embodiment 4. FIG. 19 is a cross-sectional view showing the configuration of a modified example of the semiconductor device of Embodiment 4.

[0010] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0011] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0012] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0013] In the following description, the term "outside" refers to the direction toward the outer periphery of the semiconductor substrate, and the term "inside" refers to the opposite direction to the "outside." Here, the semiconductor substrate may be a plate-shaped substrate cut from a block, an ingot, or the like, or a layer formed by peeling off a semiconductor layer formed on a specific substrate, and may further include a drift layer having an impurity concentration lower than the impurity concentration of the semiconductor substrate formed by epitaxial growth, or other semiconductor layers that constitute semiconductor devices such as diodes and transistors.

[0014] 1 is a cross-sectional view showing the configuration of an SBD 100, which is a semiconductor device according to a first embodiment of the present disclosure. The SBD 100 is a vertical SBD in which a main current flows in the thickness direction of a semiconductor substrate 1 (semiconductor layer), and is made of gallium oxide (Ga ２ O ３ A surface electrode D1 (first main electrode) is provided as a Schottky electrode on the surface (first main surface) of a semiconductor substrate 1 configured as a semiconductor substrate 1, and a back electrode D2 (second main electrode) is provided as an ohmic electrode on the back surface (second main surface) of the semiconductor substrate 1. The surface electrode D1 is made of a metal that forms a Schottky junction with the semiconductor substrate 1, such as platinum (Pt) or nickel (Ni). A metal such as aluminum (Al) or copper (Cu), or an aluminum alloy such as silicon (Al-Si), may also be laminated. The back electrode D2 is made of a metal such as titanium (Ti), nickel (Ni), aluminum (Cu), gold (Au), or silver (Ag), either singly or in a laminated form. While FIG. 1 shows a vertical semiconductor device in which a main current flows in the thickness direction of the semiconductor substrate 1, the present disclosure is also applicable to horizontal semiconductor devices in which a main current flows in the planar direction of the semiconductor substrate 1.

[0015] A p-type semiconductor layer 2 (first semiconductor layer) is provided on the semiconductor substrate 1 outside the surface electrode D1 as an electric field relaxation layer, and a p-type semiconductor layer 3 (second semiconductor layer) is provided further outside the semiconductor layer 2 as an electric field relaxation layer. The region including the semiconductor layer 2 can be referred to as a p-region R1 (first region), and the region including the semiconductor layer 3 can be referred to as a p-region R2 (second region). The semiconductor layers 2 and 3 can be made of, for example, NiO, Cu, ２ A hetero semiconductor layer having an oxide semiconductor using a material different from gallium oxide, such as O or ZnO, can be used, and N (nitrogen), Na (sodium), Li (lithium), etc. can be used as a dopant. Here, the use of a second conductivity type gallium oxide semiconductor layer in place of the hetero semiconductor layer is not prohibited.

[0016] The semiconductor layer 2 and the semiconductor layer 3 are formed so as to have different areal densities of acceptors, and the areal density of the semiconductor layer 2 is formed so as to be higher than the areal density of the semiconductor layer 3. When there is no n-type impurity in the semiconductor layer or the amount of n-type impurity is negligible compared to the amount of p-type impurity, the areal density of the acceptors is determined by the product of the impurity concentration of the p-type impurity and the film thickness of the semiconductor layer. Therefore, when the thicknesses of the semiconductor layers 2 and 3 are the same, the areal density of the acceptors in each layer is determined by the impurity concentration of the p-type impurity. For example, when the thicknesses of the semiconductor layers 2 and 3 are 100 nm, the impurity concentrations of the p-type impurities in the semiconductor layers 2 and 3 are set to 5×10 １７ ~2 x 10 １８ cm －３ By setting the acceptor surface density of the semiconductor layers 2 and 3 to be different within the range of 5×10 １２ ~2 x 10 １３ cm －２ As an example, the surface density of the acceptors in the semiconductor layer 2 can be set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ Let's say.

[0017] By setting it in this way, the depletion layer spreads appropriately in the p-regions R1 and R2, and the concentration of the electric field can be effectively alleviated.

[0018] 2 is a conceptual diagram illustrating the extent of the depletion layer in the SBD 100. As shown in FIG. 2, the depletion layer DP is formed in almost the entire semiconductor layer 3, and extends from there to the interface between the semiconductor layer 2 and the semiconductor substrate 1.

[0019] 1 shows an SBD, but a pn junction diode can also be formed by providing a p-type semiconductor layer below the surface electrode D1. This also applies to the second and third embodiments described later.

[0020] <Modification 1> Figure 3 is a cross-sectional view showing the configuration of an SBD 101 that is a modification 1 of the first embodiment according to the present disclosure. Note that the same components as those in the SBD 100 shown in Figure 1 are designated by the same reference numerals, and redundant description will be omitted. The SBD 101 shown in Figure 3 has a stepped structure in which the film thickness of the p-type semiconductor layer 2 provided on the semiconductor substrate 1 outside the surface electrode D1 gradually decreases outward, resulting in a structure in which the areal density of acceptors in the semiconductor layer 2 changes depending on the film thickness. In the SBD 101, a region including a thick portion of the semiconductor layer 2 can be designated as a p-region R1, and a region including a thin portion of the semiconductor layer 2 can be designated as a p-region R2.

[0021] For example, the thickness of the semiconductor layer 2 in the p-region R1 is 200 nm, the thickness of the semiconductor layer 2 in the p-region R2 is 50 nm, and the impurity concentration of the p-type impurity is 1×10 １８ cm －３ Then, the area density of the acceptor in the p region R1 is set to 2×10 １３ cm －２ , the areal density of acceptors in the p region R2 is 5×10 １２ cm －２ It can be said that:

[0022] By setting it in this way, the depletion layer spreads appropriately in the p-regions R1 and R2, and the concentration of the electric field can be effectively alleviated.

[0023] 4 is a conceptual diagram illustrating the spread of the depletion layer in the SBD 101. As shown in FIG. 4, the depletion layer DP is formed in almost the entire p region R2 and extends from there to the interface between the p region R1 and the semiconductor substrate 1.

[0024] <Manufacturing Method> Next, a method for manufacturing the SBD 101 will be described with reference to cross-sectional views of FIGS. 5 to 8 showing the manufacturing steps in order.

[0025] First, in the process shown in FIG. 5, a semiconductor substrate 1 made of gallium oxide containing n-type impurities is prepared, and NiO, Cu, etc. are deposited by, for example, a sputtering method. ２ An oxide semiconductor layer of O, ZnO, or the like is formed. During film formation by sputtering, N is introduced to form a p-type semiconductor layer 2. The method for forming a p-type oxide semiconductor layer is not limited to sputtering. This also applies to the method for forming a p-type oxide semiconductor layer, which will be described later. Next, a resist film is formed on the semiconductor layer 2 and patterned by photolithography to form a resist mask RM1 that covers the desired portion of the semiconductor layer 2. A novolac-based resin or the like can be used as the resist material. Then, the resist mask RM1 is used as an etching mask to remove the semiconductor layer 2 that is not covered by the resist mask RM1 by etching, thereby leaving the semiconductor layer 2 in the desired region and removing the resist mask RM1, as shown in FIG. 6 .

[0026] 7, a resist film is formed on the semiconductor substrate 1 including the remaining semiconductor layer 2, and is patterned by photolithography to form a resist mask RM2 that covers the areas that do not need to be etched and the semiconductor substrate 1. Thereafter, using the resist mask RM2 as an etching mask, the semiconductor layer 2 that is not covered by the resist mask RM2 is removed by half etching until a predetermined thickness is reached. In the half etching, etching is performed with an adjusted etching amount, and a portion of the semiconductor layer 2 remains.

[0027] 8, the resist mask RM2 is removed to obtain the semiconductor layer 2 that is thick in the p region R1 and thin in the p region R2. In this way, the SBD 101 in which the areal density of acceptors changes outward can be obtained by performing two etching steps.

[0028] For etching the semiconductor layer 2, hydrofluoric acid, acetic acid, etc. can be used in wet etching, and SF 1 can be used in dry etching by RIE (Reactive Ion Etching). ６ etc. can be used.

[0029] 9 is a cross-sectional view showing the configuration of an SBD 102 according to a second modification of the first embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 102 shown in FIG. 9 is the same as the SBD 101 shown in FIG. 3 in that the p-type semiconductor layer provided on the semiconductor substrate 1 outside the surface electrode D1 has a stepped structure in which the film thickness gradually decreases outward. However, the p-type semiconductor layer 2 and the semiconductor layer 3 are stacked in the p-region R1.

[0030] That is, the semiconductor layer 2 is provided below the semiconductor layer 3 in the p region R1, and the p region R1 includes the semiconductor layer 2 and the semiconductor layer 3. The p region R2 has a single-layer structure including the semiconductor layer 2 that is continuous with the p region R1.

[0031] In the semiconductor layer 2 and the semiconductor layer 3, the impurity concentration of the p-type impurity is 5×10 １７ ~2 x 10 １８ cm －３ Therefore, the surface density of the acceptors in the semiconductor layers 2 and 3 is set to be 5×10 １２ ~2 x 10 １３ cm －２ For example, the surface density of the acceptors in the semiconductor layer 2 can be set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ It can be said that:

[0032] With this setting, the area density of acceptors in p region R1 becomes higher than the area density of acceptors in p region R2, and the depletion layer spreads appropriately in p region R1 and p region R2, thereby effectively alleviating the concentration of the electric field.

[0033] In the above, an example has been shown in which the areal density of the acceptors in semiconductor layer 2 is higher than the areal density of the acceptors in semiconductor layer 3 (semiconductor layer 2 > semiconductor layer 3). However, there is no restriction on the magnitude relationship between the areal densities of the acceptors in semiconductor layer 2 and semiconductor layer 3, and the areal densities may be the same, i.e., semiconductor layer 2 = semiconductor layer 3, or the magnitude relationship may be reversed, i.e., semiconductor layer 2 < semiconductor layer 3.

[0034] Regardless of the setting of the areal density of the acceptors in the semiconductor layers 2 and 3, the areal density of the acceptors in the p region R1 is higher than the areal density of the acceptors in the p region R2, so that the depletion layer spreads appropriately in the p region R1 and the p region R2, thereby effectively alleviating the concentration of the electric field.

[0035] However, in the p-region R1, by making the layer with the higher impurity concentration of p-type impurities the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is enhanced.

[0036] 10 is a cross-sectional view showing the configuration of an SBD 103 according to a third modification of the first embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 103 shown in FIG. 10 is the same as the SBD 101 shown in FIG. 3 in that the p-type semiconductor layer provided on the semiconductor substrate 1 outside the surface electrode D1 has a stepped structure in which the film thickness gradually decreases outward. However, the p-type semiconductor layer 2 and the semiconductor layer 3 are stacked in the p-region R1.

[0037] That is, the semiconductor layer 2 is provided only below the semiconductor layer 3 in the p region R1, and the p region R1 includes the semiconductor layer 2 and the semiconductor layer 3. The p region R2 has a single-layer structure including the semiconductor layer 3 that is continuous from above the semiconductor layer 2 in the p region R1.

[0038] In the semiconductor layer 2 and the semiconductor layer 3, the impurity concentration of the p-type impurity is 5×10 １７ ~2 x 10 １８ cm －３ Therefore, the surface density of the acceptors in the semiconductor layers 2 and 3 is set to be 5×10 １２ ~2 x 10 １３ cm－２ For example, the surface density of the acceptors in the semiconductor layer 2 can be set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ It can be said that:

[0039] With this setting, the area density of acceptors in p region R1 becomes higher than the area density of acceptors in p region R2, and the depletion layer spreads appropriately in p region R1 and p region R2, thereby effectively alleviating the concentration of the electric field.

[0040] As with the SBD 102 shown in FIG. 9, there is no restriction on the relationship in the surface density of acceptors between the semiconductor layer 2 and the semiconductor layer 3. Also, in the p-region R1, by placing the layer with a higher impurity concentration of p-type impurities as the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is also increased.

[0041] 11 is a cross-sectional view showing the configuration of an SBD 104 according to a fourth modification of the first embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 104 shown in FIG. 11 includes a p-type semiconductor layer 2 provided on a semiconductor substrate 1 outside a surface electrode D1, and a p-type semiconductor layer 3 and a p-type first high-concentration semiconductor layer 21 having a higher acceptor areal density than the semiconductor layer 3 provided alternately outside the semiconductor layer 2.

[0042] The region including the semiconductor layer 2 can be defined as a p-region R1, and the region including the semiconductor layer 3 and the first heavily doped semiconductor layer 21 can be defined as a p-region R2. The first heavily doped semiconductor layer 21 can be made of, for example, NiO, Cu, ２ The semiconductor layer 2, the semiconductor layer 3, and the first high-concentration semiconductor layer 21 can be formed by depositing NiO, Cu, or the like by sputtering, for example. ２ After forming an oxide semiconductor layer of O, ZnO, or the like, the dose of the dopant can be changed by ion implantation, thereby allowing the concentration of each impurity to be set, which makes it easy to manufacture the first high-concentration semiconductor layer 21 having a high area density of acceptors.

[0043] The area density of acceptors in the first high-concentration semiconductor layer 21 can be set higher than that in the semiconductor layer 3, for example, 1×10 １３ cm －２ It can be about.

[0044] By setting in this way, the first heavily doped semiconductor layer 21 is not completely depleted, and the semiconductor layer 3, which has a lower areal density of acceptors than the first heavily doped semiconductor layer 21, is almost depleted, so that the semiconductor layer 3 serves as an exit for the equipotential lines formed in the semiconductor substrate 1. Therefore, an excessive potential gradient in the p region R2 can be suppressed.

[0045] 12 is a conceptual diagram illustrating the expansion of the depletion layer and equipotential lines in the SBD 104. As shown in Fig. 12, the depletion layer DP is formed almost entirely in the semiconductor layer 3, but the first heavily doped semiconductor layer 21 is not completely depleted, and the equipotential lines EP exit to the outside through the semiconductor layer 3, which reduces the potential gradient in the p region R2 and suppresses excessive potential gradients.

[0046] <Modification 5> Figure 13 is a cross-sectional view showing the configuration of an SBD 105 according to Modification 5 of the first embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in Figure 1 are designated by the same reference numerals, and redundant description will be omitted. The SBD 105 shown in Figure 13 has a p-type semiconductor layer 2 provided on a semiconductor substrate 1 outside a surface electrode D1. The semiconductor layer 2 includes a thick film region 22 with a large thickness and a thin film region 23 with a small thickness. The portion adjacent to the surface electrode D1 forms a p-region R1 in which the thick film region 22 is continuous, while the area outside the p-region R1 forms a p-region R2 in which the thin film region 23 and the thick film region 22 are alternately provided.

[0047] In the thick film region 22, by increasing the film thickness of the semiconductor layer 2, the surface density of the acceptors can be made higher than that of the thin film region 23. For example, the surface density of the acceptors in the thin film region 23 can be increased to 5×10 １２ cm －２ In the thick film region 22, １３ cm －２ It can be about.

[0048] By setting in this way, the thick film region 22 is not completely depleted, and the thin film region 23, which has a lower area density of acceptors than the thick film region 22, is almost depleted, so that the thin film region 23 serves as an exit for the equipotential lines formed in the semiconductor substrate 1. Therefore, an excessive potential gradient in the p region R2 can be suppressed.

[0049] 14 is a conceptual diagram illustrating the expansion of the depletion layer and equipotential lines in the SBD 105. As shown in Fig. 14, the depletion layer DP is formed almost entirely in the thin film region 23, but the thick film region 22 is not completely depleted, and the equipotential lines EP exit to the outside through the thin film region 23, which reduces the potential gradient in the p region R2 and suppresses excessive potential gradients.

[0050] 15 is a cross-sectional view showing the configuration of an SBD 106 according to a sixth modification of the first embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 106 shown in FIG. 15 has a layered structure in which a p-type semiconductor layer 2 is provided on a semiconductor substrate 1 outside a surface electrode D1, and a semiconductor layer 3 is provided on the semiconductor layer 2. However, the SBD 106 has a region where the semiconductor layer 3 is provided continuously and a region where the semiconductor layer 3 is provided discontinuously.

[0051] The continuous semiconductor layer 3 is provided adjacent to the surface electrode D1, and together with the semiconductor layer 2 forms a thick film region 31 of a laminated structure with a large film thickness. This region becomes the p region R1. The discontinuous semiconductor layer 3 is provided outside the p region R1, but the portion where the semiconductor layer 3 is provided and the semiconductor layer 2 form a thick film region 31 of a partial laminated structure with a large film thickness, and the thick film regions 31 exist alternately. This region becomes the p region R2.

[0052] In the p-region R1, the semiconductor layer 2 and the semiconductor layer 3 are stacked, so that the area density of the acceptors in the semiconductor layer 2 is 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２In this case, the area density of the acceptors can be made higher than that of the semiconductor layer 2. Therefore, the area density of the acceptors can be made higher than that of the single-layer portion of the semiconductor layer 2 in the p region R2.

[0053] By setting in this way, the portion where the semiconductor layer 2 and the semiconductor layer 3 are stacked is not completely depleted, and the portion of the single-layer semiconductor layer 2, which has a lower area density of acceptors than that, is almost depleted, and this portion becomes the exit of the equipotential lines formed in the semiconductor substrate 1. Therefore, an excessive potential gradient in the p region R2 can be suppressed.

[0054] The equipotential lines in SBD 106 are in the same state as those in SBD 105 shown in Figure 14, and the equipotential lines exit to the outside through the single-layer semiconductor layer 2 portion of p region R2, making the potential gradient within p region R2 gentler and suppressing excessive potential gradients.

[0055] In the above, an example has been shown in which the areal density of the acceptors in semiconductor layer 2 is higher than the areal density of the acceptors in semiconductor layer 3 (semiconductor layer 2 > semiconductor layer 3). However, there is no restriction on the magnitude relationship between the areal densities of the acceptors in semiconductor layer 2 and semiconductor layer 3, and the areal densities may be the same, i.e., semiconductor layer 2 = semiconductor layer 3, or the magnitude relationship may be reversed, i.e., semiconductor layer 2 < semiconductor layer 3.

[0056] However, in the p-region R1, by making the layer with the higher impurity concentration of p-type impurities the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is enhanced.

[0057] 16 is a cross-sectional view showing the configuration of an SBD 107 according to a seventh modification of the first embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 107 shown in FIG. 16 includes a p-type semiconductor layer 2 provided on the semiconductor substrate 1 outside the surface electrode D1, adjacent to the surface electrode D1, and a p-type semiconductor layer 3 provided thereon, forming a thick film region 31 having a thick stacked structure. This region serves as a p-region R1.

[0058] A discontinuous semiconductor layer 2 is provided on the semiconductor substrate 1 outside the p region R1, and a semiconductor layer 3 is provided to cover the discontinuous semiconductor layer 2. The portion where the semiconductor layer 2 is provided and the semiconductor layer 3 form thick film regions 31 with a partially laminated structure having a thick film thickness, and the thick film regions 31 exist alternately, with a single layer of semiconductor layer 3 between the thick film regions 31. This region becomes the p region R2.

[0059] In the p-region R1, the semiconductor layer 2 and the semiconductor layer 3 are stacked, so that the area density of the acceptors in the semiconductor layer 2 is 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors can be made higher than that of the single semiconductor layer 3. Therefore, the area density of acceptors can be made higher than that of the single semiconductor layer 3 in the p region R2.

[0060] By setting in this way, the portion where the semiconductor layer 2 and the semiconductor layer 3 are stacked is not completely depleted, and the portion of the single-layer semiconductor layer 3, which has a lower area density of acceptors than that, is almost depleted, and this portion becomes the exit of the equipotential lines formed in the semiconductor substrate 1. Therefore, an excessive potential gradient in the p region R2 can be suppressed.

[0061] The equipotential lines in SBD 107 are in the same state as those in SBD 105 shown in Figure 14, and the equipotential lines exit to the outside through the single-layer semiconductor layer 3 portion of p region R2, making the potential gradient within p region R2 gentler and suppressing excessive potential gradients.

[0062] As with the SBD 106 of the sixth modification, there is no limitation on the magnitude relationship between the area densities of the acceptors in the semiconductor layer 2 and the semiconductor layer 3.

[0063] However, in the p-region R1, by making the layer with the higher impurity concentration of p-type impurities the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is enhanced.

[0064] <Variation 8> FIG. 17 is a cross-sectional view illustrating the configuration of an SBD 108 according to Variation 8 of the first embodiment of the present disclosure. Note that the same components as those in the SBD 100 illustrated in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. In the SBD 108 illustrated in FIG. 17 , a continuous p-type semiconductor layer 2 is provided adjacent to the surface electrode D1 on the semiconductor substrate 1 outside the surface electrode D1 to form a p-region R1. A continuous p-type semiconductor layer 3 is provided outside the p-region R1 to form a p-region R2. Further outside the p-region R2, a separation region RX is formed in which discontinuous semiconductor layers 32 are provided. Note that the discontinuous semiconductor layers 32 are separated from each other and can therefore be referred to as separation semiconductor layers. The separation region RX is not limited to that illustrated in FIG. 17 , and can be provided further outside the p-region R2 of any of the SBDs 101 to 107.

[0065] In the separation region RX, multiple semiconductor layers 32 are arranged at intervals of, for example, 1 μm, and the spaces between the semiconductor layers 32 serve as outlets for the equipotential lines, making the potential gradient gentler and suppressing excessive potential gradients, thereby mitigating the electric field concentration in the outermost periphery outside the p region R2.

[0066] The impurity concentration of the semiconductor layer 32 in the separation region RX can be the same as the impurity concentration of the semiconductor layer 2 in the p region R1 or the impurity concentration of the semiconductor layer 3 in the p region R2. By making the impurity concentration the same as that of the semiconductor layer 3 in the p region R2, it can be formed in the same process as the p region R2, and by forming them simultaneously, it is possible to reduce misalignment of the resist mask used for etching.

[0067] The spacing between the semiconductor layers 32 in the separation region RX can be the same, but the spacing can also be increased toward the outside.

[0068] Second Embodiment Figure 18 is a cross-sectional view showing the configuration of an SBD 200, which is a semiconductor device according to a second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in Figure 1 are designated by the same reference numerals, and redundant description will be omitted. The SBD 200 shown in Figure 18 includes a p-type semiconductor layer 2 (first semiconductor layer) provided on a semiconductor substrate 1 outside a surface electrode D1, a p-type semiconductor layer 3 (second semiconductor layer) provided outside the semiconductor layer 2, and a p-type semiconductor layer 4 (third semiconductor layer) provided further outside as an electric field relaxation layer. The region including the semiconductor layer 2 can be referred to as a p-region R1 (first region), the region including the semiconductor layer 3 as a p-region R2 (second region), and the region including the semiconductor layer 4 as a p-region R3 (third region).

[0069] The semiconductor layers 2, 3, and 4 are formed so that the areal densities of acceptors are different from each other, and the areal density of the semiconductor layer 2 is formed higher than the areal densities of the semiconductor layers 3 and 4, but the magnitude relationship between the areal densities of the semiconductor layers 3 and 4 is not limited.

[0070] As an example, the surface density of the acceptors in the semiconductor layer 2 is set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ , the surface density of the acceptors in the semiconductor layer 4 is 1×10 １２ cm －２ It can be said that:

[0071] In this way, by reducing the areal density of acceptors in the semiconductor layers 3 and 4, the depletion layer spreads from the outside to the inside within the semiconductor layers, and electric field concentration can be effectively alleviated.

[0072] 19 is a cross-sectional view showing the configuration of an SBD 201 that is a first modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0073] In the SBD 201 shown in FIG. 19, the p-type semiconductor layer provided on the semiconductor substrate 1 outside the surface electrode D1 has a stacked structure in which semiconductor layer 2 and semiconductor layer 3 are stacked in the p region R1, a single layer structure of semiconductor layer 2 in the p region R2, and a single layer structure of semiconductor layer 3 in the p region R3.

[0074] That is, semiconductor layer 2 is provided below semiconductor layer 3 in p region R1, and p region R1 includes semiconductor layer 2 and semiconductor layer 3. p region R2 includes semiconductor layer 2 that continues from p region R1, but semiconductor layer 2 is not provided in p region R3. That is, semiconductor layer 3 is provided from the edge portion of semiconductor layer 2 in p region R2 to the top of semiconductor substrate 1 in p region R3.

[0075] In the semiconductor layer 2 and the semiconductor layer 3, the impurity concentration of the p-type impurity is 5×10 １７ ~2 x 10 １８ cm －３ Therefore, the surface density of the acceptors in the semiconductor layer 2 is set to be 1×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors increases in the order of p region R1, p region R2, and p region R3.

[0076] By setting it in this way, the areal density of acceptors in the p regions R1 to R3 is gradually reduced from the inside to the outside, which causes the depletion layer to spread from the outside to the inside in the semiconductor layer, thereby effectively alleviating the electric field concentration.

[0077] Furthermore, if the area density of the acceptors in the p region R1 is made the highest, the electric field concentration can be effectively alleviated without being restricted by the magnitude relationship between the area densities of the acceptors in the p regions R2 and R3.

[0078] However, in the p-region R1, by making the layer with the higher impurity concentration of p-type impurities the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is enhanced.

[0079] 20 is a cross-sectional view showing the configuration of an SBD 202 that is a second modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0080] In the SBD 202 shown in FIG. 20, the p-type semiconductor layer provided on the semiconductor substrate 1 outside the surface electrode D1 has a stacked structure in which a semiconductor layer 2 is stacked on a semiconductor layer 3 in the p region R1, a single-layer structure of the semiconductor layer 2 in the p region R2, and a single-layer structure of the semiconductor layer 3 in the p region R3.

[0081] That is, semiconductor layer 3 is provided below semiconductor layer 2 in p region R1, and p region R1 includes semiconductor layer 3 and semiconductor layer 2. p region R2 has a single-layer structure of semiconductor layer 2 continuing from p region R1, and semiconductor layer 2 is provided from p region R2 to the edge portion of semiconductor layer 3 in p region R3.

[0082] As in the SBD 201 shown in FIG. 19, the surface density of the acceptors in the semiconductor layer 2 is set to 1×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors increases in the order of p region R1, p region R2, and p region R3.

[0083] By setting it in this way, the areal density of acceptors in the p regions R1 to R3 is gradually reduced from the inside to the outside, which causes the depletion layer to spread from the outside to the inside in the semiconductor layer, thereby effectively alleviating the electric field concentration.

[0084] Furthermore, if the area density of the acceptors in the p region R1 is made the highest, the electric field concentration can be effectively alleviated without being restricted by the magnitude relationship between the area densities of the acceptors in the p regions R2 and R3.

[0085] However, in the p-region R1, by making the layer with the higher impurity concentration of p-type impurities the lower layer, the effect of suppressing the concentration of the electric field at the lower end of the surface electrode D1 is enhanced.

[0086] <Manufacturing Method> Next, a method for manufacturing the SBD 201 will be described with reference to cross-sectional views of FIGS. 21 to 24 showing the manufacturing steps in order.

[0087] First, in the step shown in FIG. 21, a semiconductor substrate 1 made of gallium oxide containing n-type impurities is prepared, and NiO, Cu, etc. are deposited by, for example, a sputtering method. ２ An oxide semiconductor layer of O, ZnO, or the like is formed. During film formation by sputtering, N is introduced to form a p-type semiconductor layer 2. Next, a resist film is formed on the semiconductor layer 2 and patterned by photolithography to form a resist mask RM1 that covers the portion of the semiconductor layer 2 that is to remain. Novolac resin or the like can be used as the resist material. Thereafter, the resist mask RM1 is used as an etching mask to remove the semiconductor layer 2 that is not covered by the resist mask RM1 by etching, thereby removing the resist mask RM1 and leaving the semiconductor layer 2 in the desired region, as shown in FIG. 22 .

[0088] 23, a p-type semiconductor layer 3 is formed on the semiconductor substrate 1, including on the remaining semiconductor layer 2, through a process similar to that for the semiconductor layer 2. In this process, the amount of N introduced is set so that the concentration is different from that of the semiconductor layer 2. Next, a resist film is formed on the semiconductor layer 3 and patterned by photolithography to form a resist mask RM2 that covers the portion of the semiconductor layer 3 that is to be left. Thereafter, the resist mask RM2 is used as an etching mask, and the semiconductor layer 3 that is not covered by the resist mask RM2 is removed by etching.

[0089] 24, the resist mask RM2 is removed to obtain the SBD 201. In this manner, the SBD 201 can be obtained in which the areal density of acceptors can be reduced stepwise from the inside to the outside by two patterning steps.

[0090] For etching the semiconductor layers 2 and 3, hydrofluoric acid, acetic acid, etc. can be used in wet etching, and SF 6 can be used in dry etching by RIE. ６ etc. can be used.

[0091] Next, another example of a method for manufacturing the SBD 201 will be described with reference to cross-sectional views of FIGS. 25 to 28 showing the manufacturing steps in order.

[0092] 25, a semiconductor substrate 1 made of gallium oxide containing n-type impurities is prepared, a resist film is formed on the semiconductor substrate 1, and a resist mask RM3 is formed by patterning the resist film by photolithography, with openings at the portions where the semiconductor layer 2 is to be formed. This resist mask RM3 is formed thicker than the semiconductor layer 2. Next, a resist mask RM3 made of NiO, Cu, or the like is deposited by, for example, sputtering on the semiconductor substrate 1 on which the resist mask RM3 has been formed. ２ An oxide semiconductor layer such as O or ZnO is formed and N is introduced to form a p-type semiconductor layer 2 .

[0093] Thereafter, the resist mask RM3 is lifted off, leaving the semiconductor layer 2 in the desired region, as shown in Fig. 26. When lifting off the resist mask RM3, a remover for the resist mask RM3 penetrates into the semiconductor layer 2 from the corners and the like, thereby removing the semiconductor layer 2 together with the resist mask RM3.

[0094] 27, a resist mask RM4 is formed with openings in areas where the semiconductor layer 3 is to be formed. This resist mask RM4 is formed thicker than the semiconductor layer 3. Next, a resist mask RM4 is formed on the semiconductor substrate 1 on which the resist mask RM4 has been formed, by, for example, sputtering. ２ An oxide semiconductor layer such as O or ZnO is formed and N is introduced to form a p-type semiconductor layer 3 .

[0095] 28, the resist mask RM4 is lifted off to obtain the SBD 201 in which the semiconductor layer 3 remains in the desired region. When the resist mask RM4 is lifted off, a remover for the resist mask RM4 penetrates into the corners of the semiconductor layer 3, thereby removing the semiconductor layer 3 together with the resist mask RM4.

[0096] 29 is a cross-sectional view showing the configuration of an SBD 203 according to a third modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0097] 29 has a p-type semiconductor layer 2 provided on a semiconductor substrate 1 outside a surface electrode D1, a p-type semiconductor layer 3 provided outside the semiconductor layer 2, and p-type semiconductor layers 4 and p-type second highly-doped semiconductor layers 33 provided alternately outside the semiconductor layer 2. The region including the semiconductor layer 2 can be called a p-region R1, the region including the semiconductor layer 3 can be called a p-region R2, and the region including the semiconductor layer 4 and the second highly-doped semiconductor layer 33 can be called a p-region R3 (third region).

[0098] The semiconductor layers 2, 3, and 4 are formed so as to have different areal densities of acceptors, with the areal density of the semiconductor layer 2 being higher than that of the semiconductor layer 3, and the areal density of the semiconductor layer 3 being higher than that of the semiconductor layer 4.

[0099] As an example, the surface density of the acceptors in the semiconductor layer 2 is set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ , the surface density of the acceptors in the semiconductor layer 4 is 1×10 １２ cm －２ The surface density of the second high-concentration semiconductor layer 33 may be higher than or equal to that of the semiconductor layer 3, or may be equal to that of the semiconductor layer 2.

[0100] By setting it in this way, the second heavily doped semiconductor layer 33 is less likely to be depleted, the semiconductor layer 4 having a low surface density of acceptors becomes the exit of the equipotential lines, the potential gradient becomes gentler, an excessive potential gradient is suppressed, and the electric field concentration in the outermost periphery outside the p region R2 can be alleviated.

[0101] The semiconductor layer 2, the semiconductor layer 3, the second high concentration semiconductor layer 33 and the semiconductor layer 4 are formed by depositing NiO, Cu, ２After forming an oxide semiconductor layer of O, ZnO, or the like, the dose of dopants N, Na, and Li can be changed by ion implantation to set the impurity concentration of each dopant, which makes it easy to manufacture the second high-concentration semiconductor layer 33 having a high area density of acceptors.

[0102] 30 is a cross-sectional view showing the configuration of an SBD 204 according to a fourth modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0103] 30 , a p-type semiconductor layer 2 is provided on a semiconductor substrate 1 outside a surface electrode D1. The p-type semiconductor layer 2 is provided continuously in p regions R1 and R2, but discontinuously in p region R3. In p region R1, a continuous semiconductor layer 3 is provided on the semiconductor layer 2, and together with the semiconductor layer 2, it forms a laminated structure, forming a thick film region 31 with a large thickness. In p region R2, no semiconductor layer 3 is provided, and in p region R3, where a discontinuous semiconductor layer 2 is provided, the semiconductor layer 3 extending from the edge of the semiconductor layer 2 in p region R2 covers the semiconductor layer 2, forming a thick film region 31 with a partially laminated structure where the semiconductor layer 3 and the semiconductor layer 2 are thick. The thick film regions 31 alternate, and a single semiconductor layer 3 is formed between the thick film regions 31.

[0104] In the p-region R1, the semiconductor layer 2 and the semiconductor layer 3 are stacked, so that the area density of the acceptors in the semiconductor layer 2 is 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors can be made higher in the thick film region 31 than in the single-layer semiconductor layer 2 portion in the p region R2.

[0105] In the p region R3, the thick film region 31 with a high acceptor areal density is not completely depleted, and the single-layer portion of the semiconductor layer 3 with a lower acceptor areal density is almost depleted, which serves as an exit for the equipotential lines formed in the semiconductor substrate 1. This makes it possible to suppress an excessive potential gradient in the p region R3.

[0106] 31 is a cross-sectional view showing the configuration of an SBD 205 according to a fifth modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0107] In the SBD205 shown in FIG. 31 , a p-type semiconductor layer 2 provided on a semiconductor substrate 1 outside a surface electrode D1 has a laminated structure in which a semiconductor layer 2 is laminated on a semiconductor layer 3 in a p region R1, a single-layer structure of the semiconductor layer 2 in a p region R2, and a thick-film region 22 having a partially laminated structure in which the semiconductor layer 2 is discontinuously provided on the semiconductor layer 3 and the semiconductor layer 3 have a thick film thickness in the portion where the semiconductor layer 2 is provided, and the thick-film regions 22 are alternately present, with a single-layer semiconductor layer 3 being formed between the thick-film regions 22.

[0108] In the p-region R1, the semiconductor layer 2 and the semiconductor layer 3 are stacked, so that the area density of the acceptors in the semiconductor layer 2 is 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors can be made higher in the thick film region 31 than in the single-layer semiconductor layer 2 portion in the p region R2.

[0109] In the p region R3, the thick film region 22 with a high acceptor areal density is not completely depleted, and the single-layer portion of the semiconductor layer 3 with a lower acceptor areal density is almost depleted, which serves as an exit for the equipotential lines formed in the semiconductor substrate 1. This makes it possible to suppress an excessive potential gradient in the p region R3.

[0110] 32 is a cross-sectional view showing the configuration of an SBD 206 according to a sixth modification of the second embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0111] In the SBD 206 shown in FIG. 32 , a p-type semiconductor layer 2 is provided on a semiconductor substrate 1 outside a surface electrode D1. A p-type semiconductor layer 3 is provided outside the semiconductor layer 2, and a p-type semiconductor layer 4 is provided further outside. The region including the semiconductor layer 2 can be referred to as a p-region R1, the region including the semiconductor layer 3 as a p-region R2, and the region including the semiconductor layer 4 as a p-region R3. Further outside the p-region R3 is a separation region RX in which a semiconductor layer 41 is provided discontinuously. The discontinuous semiconductor layers 41 are separated from each other and can be referred to as separation semiconductor layers. The separation region RX is not limited to that shown in FIG. 32 , and can be provided further outside the p-region R3 of any of the SBDs 201 to 205. The separation region RX can surround the p-region R3 in a plan view.

[0112] The semiconductor layers 2, 3, and 4 are formed so as to have different areal densities of acceptors, with the areal density of the semiconductor layer 2 being higher than that of the semiconductor layer 3, and the areal density of the semiconductor layer 3 being higher than that of the semiconductor layer 4.

[0113] As an example, the surface density of the acceptors in the semiconductor layer 2 is set to 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ , the surface density of the acceptors in the semiconductor layer 4 is 1×10 １２ cm －２ It can be said that:

[0114] In this way, by gradually decreasing the areal density of acceptors from the inside to the outside in the semiconductor layers 2 to 4, a depletion layer spreads from the outside to the inside in the semiconductor layers, and electric field concentration can be effectively alleviated.

[0115] Furthermore, in the separation region RX, multiple semiconductor layers 41 are arranged at intervals of, for example, 1 μm, and the spaces between the semiconductor layers 41 serve as outlets for the equipotential lines, making the potential gradient gentler and suppressing excessive potential gradients, thereby mitigating the electric field concentration in the outermost periphery outside the p region R2.

[0116] The impurity concentration of semiconductor layer 41 in separation region RX can be the same as the impurity concentration of any of semiconductor layer 2 in p region R1, semiconductor layer 3 in p region R2, and semiconductor layer 4 in p region R3. By making the impurity concentration the same as that of semiconductor layer 4 in p region R3, it can be formed in the same process as p region R3, and by forming them simultaneously, it is possible to reduce misalignment of the resist mask used for etching.

[0117] The spacing between the semiconductor layers 41 in the separation region RX can be the same, but the spacing can also be increased toward the outside.

[0118] 33 is a cross-sectional view showing the configuration of an SBD 207 according to a seventh modification of the second embodiment of the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 207 shown in FIG. 33 has a layered structure in which a p-type semiconductor layer 2 is provided on a semiconductor substrate 1 outside a surface electrode D1, and a semiconductor layer 3 is provided on the semiconductor layer 2. However, the SBD 207 has a region where the semiconductor layer 3 is provided continuously and a region where the semiconductor layer 3 is provided discontinuously.

[0119] The continuous semiconductor layer 3 is provided adjacent to the surface electrode D1, and together with the semiconductor layer 2 forms a thick film region 31. This region becomes the p region R1. The discontinuous semiconductor layer 3 is provided outside the p region R1, but the portion where the semiconductor layer 3 is provided and the semiconductor layer 2 form a thick film region 31, and the thick film regions 31 exist alternately. This region becomes the p region R2.

[0120] A discontinuous semiconductor layer 2 is provided on the semiconductor substrate 1 outside the p region R2, and a semiconductor layer 3 is provided to cover the discontinuous semiconductor layer 2. The portions where the semiconductor layer 2 is provided and the semiconductor layer 3 form thick film regions 31, and the thick film regions 31 exist alternately, with a single layer of semiconductor layer 3 between the thick film regions 31. This region becomes the p region R3. Further outside the p region R3 is a separation region RX where the semiconductor layer 3 is provided discontinuously.

[0121] In the p-region R1, the semiconductor layer 2 and the semiconductor layer 3 are stacked, so that the area density of the acceptors in the semiconductor layer 2 is 2×10 １３ cm －２ , the surface density of the acceptors in the semiconductor layer 3 is 5×10 １２ cm －２ In this case, the area density of acceptors can be made higher than that of the single semiconductor layer 3. Therefore, the area density of acceptors can be made higher than that of the single semiconductor layer 2 in the p region R2.

[0122] In the p region R3, the thick film region 31 of the partial laminated structure in which the semiconductor layer 2 and the semiconductor layer 3 are laminated is not completely depleted, and the portion of the single-layer semiconductor layer 3 having a lower area density of acceptors than that is almost depleted, and this portion becomes the exit of the equipotential lines formed in the semiconductor substrate 1. Therefore, an excessive potential gradient in the p region R3 can be suppressed.

[0123] Furthermore, in the separation region RX, multiple semiconductor layers 3 are arranged at intervals of, for example, 1 μm, and the spaces between the semiconductor layers 3 serve as outlets for the equipotential lines, making the potential gradient gentler and suppressing excessive potential gradients, thereby mitigating electric field concentration in the outermost periphery outside the p region R3.

[0124] <Manufacturing Method> Next, a method for manufacturing the SBD 207 will be described with reference to cross-sectional views of FIGS. 34 to 38 showing the manufacturing steps in order.

[0125] First, in the step shown in FIG. 34, a semiconductor substrate 1 made of gallium oxide containing n-type impurities is prepared, and NiO, Cu, etc. are deposited by, for example, a sputtering method. ２ An oxide semiconductor layer of O, ZnO, or the like is formed. For example, N is introduced during film formation by sputtering to form a p-type semiconductor layer 2. Next, a resist film is formed on the semiconductor layer 2 and patterned by photolithography to form a resist mask RM5 that covers the portion of the semiconductor layer 2 that is to remain. Novolac resin or the like can be used as the resist material. Thereafter, the resist mask RM5 is used as an etching mask to remove the semiconductor layer 2 that is not covered by the resist mask RM5 by etching, thereby removing the resist mask RM5 and leaving the semiconductor layer 2 in the desired region, as shown in FIG. 35 .

[0126] 36, a p-type semiconductor layer 3 is formed on the semiconductor substrate 1 including the remaining semiconductor layer 2 through the same process as for the semiconductor layer 2. In this process, the amount of N introduced is set so that the concentration is different from that of the semiconductor layer 2.

[0127] 37, a resist film is formed on the semiconductor layer 3 and patterned by photolithography to form a resist mask RM6 that covers the desired portion of the semiconductor layer 3. Thereafter, the resist mask RM6 is used as an etching mask to remove the semiconductor layer 3 not covered by the resist mask RM6 by etching, thereby leaving the semiconductor layer 3 in the desired region. Finally, the resist mask RM6 is removed to obtain the SBD207 shown in FIG.

[0128] In the first and second embodiments described above, for example, in FIGS. 19, 20, 30, etc., there are portions where the semiconductor layer 3 climbs up onto the semiconductor layer 2 at the boundary between the p region R1 and the p region R2, and there are also portions near the boundary where the areal density of the acceptors is not as set, but these portions are small, and the areal density of the acceptors is as set in the entire region of each semiconductor layer.

[0129] Third Embodiment Figure 39 is a cross-sectional view showing the configuration of an SBD300 that is a semiconductor device according to a third embodiment of the present disclosure. Note that the same components as those in the SBD 100 shown in Figure 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 300 shown in Figure 39 has a p-type semiconductor layer 2 (first semiconductor layer) provided on a semiconductor substrate 1 extending from the inside to the outside of a surface electrode D1, a p-type semiconductor layer 3 (second semiconductor layer) provided outside the semiconductor layer 2, and a portion of the surface electrode D1 extending over the semiconductor layer 2.

[0130] By making the surface density of the acceptors in semiconductor layer 2 higher than the surface density of the acceptors in semiconductor layer 3, the depletion layer spreads appropriately in p region R1 and p region R2, and the electric field concentration can be effectively alleviated, which is the same as in SBD 100 of embodiment 1. However, by configuring the surface electrode D1 so that a portion thereof extends onto semiconductor layer 2, the electric field concentration in p region R1 can be alleviated even if the surface density of the acceptors in semiconductor layer 2 is small.

[0131] 40 is a conceptual diagram showing equipotential lines formed in SBD 300. A depletion layer spreads from the pn junction between semiconductor substrate 1 and semiconductor layers 2 and 3 toward surface electrode D1, which has a potential of 0 V. However, as shown in FIG. 40, surface electrode D1 runs over semiconductor layer 2, shifting the position of the potential of 0 V toward the periphery, thereby suppressing excessive depletion of semiconductor layer 2. As a result, equipotential lines EP do not become dense at position A in FIG. 40, and electric field concentration is alleviated.

[0132] 41 is a cross-sectional view showing the configuration of an SBD301 that is a first modification of the third embodiment according to the present disclosure. The same components as those in the SBD 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The SBD 301 shown in FIG. 41 has a p-type semiconductor layer 2 provided on a semiconductor substrate 1 from the inside to the outside of a surface electrode D1, and a portion of the surface electrode D1 extends over the semiconductor layer 2.

[0133] The semiconductor layer 2 has a step structure in which the film thickness of the semiconductor layer 2 outside the surface electrode D1 becomes thinner in stages outward, and a change in film thickness changes the surface density of acceptors in the semiconductor layer 2. The semiconductor layer 2 also has a step structure in which the film thickness of the semiconductor layer 2 inside the surface electrode D1 becomes thinner in stages inward, and a change in the surface density of acceptors in the semiconductor layer 2 also inside the surface electrode D1.

[0134] In SBD301, the region including the thick portion of the semiconductor layer 2 can be referred to as p region R1, the region including the outer thin portion of the semiconductor layer 2 can be referred to as p region R2, and the region including the inner thin portion of the semiconductor layer 2 can be referred to as inner p region RY.

[0135] By providing p region R1 and p region R2, the depletion layer is appropriately spread within p region R1 and p region R2, and electric field concentration can be effectively alleviated, which is the same as SBD101 of variant 1 of embodiment 1. However, by configuring the surface electrode D1 so that a portion thereof extends onto the semiconductor layer 2 of the inner p region RY and p region R1, electric field concentration at the lower end of the surface electrode D1 can be suppressed.

[0136] Fig. 42 is a conceptual diagram showing equipotential lines formed on the SBD 301. As shown in Fig. 42, the surface electrode D1 rides on the semiconductor layer 2, so that the position of the potential 0 V varies stepwise, and compared to the case where the position of the potential 0 V is shifted by one position as shown in Fig. 41, the equipotential lines EP change smoothly at three positions, i.e., positions A, B, and C, which are the lower ends of the surface electrode D1, thereby mitigating electric field concentration.

[0137] <Modification 2> Figure 43 is a cross-sectional view showing the configuration of an SBD302 which is modification 2 of embodiment 3 according to the present disclosure. Note that the same components as those of SBD300 shown in Figure 39 are assigned the same reference numerals, and redundant description will be omitted. The SBD 302 shown in Figure 43 is provided with a protective film PF that covers from above the outer edge of the semiconductor layer 2 to above a portion of the semiconductor substrate 1 outside the semiconductor layer 3. A portion of the surface electrode D1 extends over the semiconductor layer 2 and the protective film PF so as to cover from above the inner edge of the semiconductor layer 2 to above the inner edge of the protective film PF.

[0138] By covering the semiconductor layers 2 and 3 with the surface electrode D1 and the protective film PF in this manner, it is possible to suppress changes in the film characteristics of the semiconductor layers 2 and 3 over time, such as deterioration due to external influences, and a stable high breakdown voltage can be obtained.

[0139] The protective film PF is SiO ２ , SiN, or other insulating films can be used. ２ , ZnO ２ , TiO ２ and BaTiO ３ Silicon oxide (SiO ２ By using a high-dielectric-constant (high-k) material having a higher relative dielectric constant than the dielectric constant of the conductive material, the electric field concentration at the periphery can be effectively alleviated.

[0140] <Modification 3> Figure 44 is a cross-sectional view showing the configuration of an SBD303 that is Modification 3 of Embodiment 3 according to the present disclosure. Note that the same components as those of the SBD301 shown in Figure 41 are denoted by the same reference numerals, and redundant description will be omitted. The SBD303 shown in Figure 44 is provided with a protective film PF that covers almost the entire semiconductor layer 2 in the p region R1, the entire semiconductor layer 2 in the p region R2, and a portion of the semiconductor substrate 1 outside the p region R2. The surface electrode D1 is configured so that a portion of the surface electrode D1 extends over the semiconductor layer 2 and the protective film PF so as to cover the semiconductor layer 2 in the inner p region RY and from the edge of the semiconductor layer 2 in the p region R1 to the inner edge of the protective film PF.

[0141] By covering the semiconductor layer 2 with the surface electrode D1 and the protective film PF in this manner, the position of the potential 0 V changes in stages, the equipotential lines change smoothly at the lower end of the surface electrode D1, and changes in the film characteristics of the semiconductor layers 2 and 3 over time, such as deterioration due to external influences, can be suppressed, thereby enabling a stable high breakdown voltage to be obtained.

[0142] 45 is a cross-sectional view showing the configuration of a MOSFET 400 which is a semiconductor device according to a fourth embodiment of the present disclosure. The MOSFET 400 shown in FIG. 45 is a vertical MOSFET in which a main current flows in the thickness direction of a semiconductor substrate 1, and is made of gallium oxide (Ga) containing n-type impurities. ２ O ３ A front surface electrode D1 serving as a source electrode (first main electrode) is provided on a front surface (first main surface) of a semiconductor substrate 1 configured as a semiconductor substrate 1, and a back surface electrode D2 serving as a drain electrode (second main electrode) is provided on a back surface (second main surface) of the semiconductor substrate 1. The front surface electrode D1 and the back surface electrode D2 are made of a material selected from metals such as Ti, Ni, Al, Cu, Au, and Ag, either singly or in a laminated state.

[0143] A p-type semiconductor layer 2 (first semiconductor layer) is provided on the semiconductor substrate 1 outside the surface electrode D1 as an electric field relaxation layer, and a p-type semiconductor layer 3 (second semiconductor layer) is provided further outside the semiconductor layer 2. The region including the semiconductor layer 2 can be referred to as a p-region R1 (first region), and the region including the semiconductor layer 3 can be referred to as a p-region R2 (second region). The semiconductor layers 2 and 3 can be made of, for example, NiO, Cu, ２ O, ZnO, etc. can be used, and N, Na, Li, etc. can be used as a dopant.

[0144] The semiconductor layer 2 and the semiconductor layer 3 are formed so that the areal density of acceptors differs, and the areal density of the semiconductor layer 2 is formed so that it is higher than the areal density of the semiconductor layer 3 .

[0145] In the upper layer portion on the surface side of the semiconductor substrate 1, a plurality of p-type semiconductor layers made of an oxide semiconductor or a plurality of high resistance layers formed by nitrogen ion implantation or the like are selectively provided, and in the upper layer portion of the well 11, a high concentration of n-type impurities (n ＋ Two source layers 12 included in the semiconductor layer 2 are provided at a distance from each other. A well 11 may be provided below the boundary between the semiconductor layer 2 and the surface electrode D1, and the source layer 12 may not be provided in the well 11, but the source layer 12 may be provided in the well 11.

[0146] A gate electrode 14 is provided above adjacent wells 11 via a gate insulating film 13. The gate insulating film 13 is provided so as to straddle the source layers 12 of the adjacent wells 11, and an interlayer insulating film 15 is provided so as to cover the gate insulating film 13 and the gate electrode 14. The gate insulating film 13, the gate electrode 14, and the interlayer insulating film 15 are also provided on edge portions of the wells 11 where no source layer 12 is provided.

[0147] In this way, by providing the semiconductor layer 2 and the semiconductor layer 3 as electric field relaxation layers outside the surface electrode D1 of the MOSFET 400, the depletion layer spreads appropriately within the p region R1 and the p region R2, thereby effectively relaxing the concentration of the electric field.

[0148] 46 is a cross-sectional view showing a configuration of a MOSFET 401 that is a modification of the fourth embodiment according to the present disclosure. Note that the same components as those in MOSFET 400 shown in FIG. 45 are denoted by the same reference numerals, and redundant description will be omitted.

[0149] 46 has a stepped structure in which the thickness of the p-type semiconductor layer 2 provided on the semiconductor substrate 1 outside the surface electrode D1 becomes thinner in stages outward, and the change in thickness changes the areal density of acceptors in the semiconductor layer 2. In the SBD 101, the region including the thick portion of the semiconductor layer 2 can be defined as a p-region R1, and the region including the thin portion of the semiconductor layer 2 can be defined as a p-region R2.

[0150] For example, the thickness of the semiconductor layer 2 in the p-region R1 is 200 nm, the thickness of the semiconductor layer 2 in the p-region R2 is 50 nm, and the impurity concentration of the p-type impurity is 1×10 １８ cm －３ Then, the area density of the acceptor in the p region R1 is set to 2×10 １３ cm －２ , the areal density of acceptors in the p region R2 is 5×10 １２ cm －２ It can be said that:

[0151] By setting it in this way, the depletion layer spreads appropriately in the p region R1 and the p region R2, and the concentration of the electric field can be effectively alleviated. Note that the MOSFET can be applied with the electric field relaxation layer configurations described in the first to third embodiments instead of the configuration of the electric field relaxation layer described in the fourth embodiment, and the configuration of the MOSFET can be changed as desired depending on the specifications and design of the MOSFET, manufacturing requirements, issues, etc.

[0152] Although the fourth embodiment shows MOSFET 401 in which well 11 is formed in the surface layer of semiconductor substrate 1, a MOSFET may be used which has a semiconductor layer of a first conductivity type epitaxially grown on semiconductor substrate 1, i.e., an n-type drift layer, and has well 11 formed in the surface layer of the drift layer. Furthermore, the fourth embodiment shows an example in which the present disclosure is applied to a MOSFET with a planar gate electrode, but the present disclosure can also be applied to a MOSFET with a trench gate electrode, and can also be applied to an IGBT (Insulated Gate Bipolar Transistor).

[0153] <Fifth Embodiment> A power conversion device according to the fifth embodiment will be described. In the fifth embodiment, the semiconductor device according to the first to fourth embodiments is applied to a power conversion device, and in the following description, the semiconductor device according to the fourth embodiment will be used as an example.

[0154] <Configuration of Power Conversion Device> The power conversion device to which the present invention is applied is not limited to a specific application, but the following description will be given of a case where the present invention is applied to a three-phase inverter.

[0155] FIG. 47 is a block diagram schematically showing the configuration of a power conversion system including a power conversion device 2200 according to the fifth embodiment.

[0156] The power conversion system shown in FIG. 47 includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery. The power supply 2100 can also be configured from a rectifier circuit or an AC-DC converter connected to an AC system. The power supply 2100 can also be configured from a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0157] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power supply 2100 into AC power and supplies the AC power to the load 2300.

[0158] As shown in FIG. 47 , the power conversion device 2200 includes a conversion circuit 2201 that converts DC power into AC power and outputs it, a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202.

[0159] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0160] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0161] There are various specific circuit configurations for the conversion circuit 2201, but the conversion circuit 2201 according to the fifth embodiment is a two-level three-phase full-bridge circuit, and can be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element.

[0162] The semiconductor device according to the fourth embodiment is applied to each of the switching elements in the conversion circuit 2201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the conversion circuit 2201, are connected to the load 2300.

[0163] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit 2202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements.

[0164] When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is less than the threshold voltage of the switching element.

[0165] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (on time) that each switching element of the conversion circuit 2201 should be in the on state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching element according to the voltage to be output.

[0166] Then, the control circuit 2203 outputs a control command (control signal) to the drive circuit 2202 so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0167] In the power conversion device 2200 according to the fifth embodiment, the MOSFET 400 or 401 of the semiconductor device according to the fourth embodiment described above is applied as the switching element of the conversion circuit 2201, thereby effectively alleviating the concentration of the electric field at the periphery of the semiconductor device.

[0168] Although a two-level power conversion device has been described in the fifth embodiment, the semiconductor device of the fourth embodiment can be applied to a three-level or multi-level power conversion device. When power is supplied to a single-phase load, the semiconductor device of the fourth embodiment can be applied to a single-phase inverter.

[0169] Furthermore, when power is supplied to a DC load or the like, the semiconductor device of the fourth embodiment can also be applied to a DC-DC converter or an AC-DC converter.

[0170] In the above example, the semiconductor device according to the fourth embodiment is used as the switching element of the conversion circuit 2201, but the semiconductor device according to any of the first to third embodiments can also be used as the free wheel diode connected in antiparallel to the switching element. In this case as well, the concentration of the electric field at the outer periphery of the semiconductor device can be effectively alleviated.

[0171] Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure to the above. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

[0172] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

Claims

1. A semiconductor device comprising: a semiconductor layer composed of a gallium oxide semiconductor of a first conductivity type; a first main electrode formed on a first main surface of the semiconductor layer; and an electric field relaxation layer of a second conductivity type formed on the semiconductor layer outside the first main electrode, wherein the electric field relaxation layer includes a first region on the first main electrode side and a second region on the side opposite to the first main electrode, and the acceptor surface density of the second region is smaller than that of the first region.

2. The semiconductor device according to claim 1, wherein the first region has a stacked structure in which a first semiconductor layer of a second conductivity type and a second semiconductor layer of a second conductivity type are stacked, and the second region has a single-layer structure of the first semiconductor layer or the second semiconductor layer.

3. The semiconductor device according to claim 1, wherein in the first region, a first semiconductor layer of a second conductivity type is continuous, and in the second region, a first high-concentration semiconductor layer having a higher impurity concentration than a second semiconductor layer separated from the first region via the second semiconductor layer of a second conductivity type is provided, and the acceptor surface density of the second semiconductor layer is smaller than those of the first semiconductor layer and the first high-concentration semiconductor layer.

4. The semiconductor device according to claim 1, wherein in the first region, a first semiconductor layer of a second conductivity type having a first film thickness is continuous, and in the second region, a first semiconductor layer separated from the first region via a second semiconductor layer having a second film thickness smaller than the first film thickness is provided.

5. The semiconductor device according to claim 1, wherein the first region has a stacked structure in which a first semiconductor layer of a second conductivity type and a second semiconductor layer of a second conductivity type are stacked to have a first film thickness, and in the second region, a plurality of semiconductor layers of one of the first semiconductor layer and the second semiconductor layer are discontinuously formed, and the other semiconductor layer is continuously formed, and a plurality of partial stacked structures in which the plurality of semiconductor layers of one and the other semiconductor layer are stacked to have the first film thickness are provided, and between the plurality of partial stacked structures, the first semiconductor layer or the second semiconductor layer having a second film thickness smaller than the first film thickness is formed.

6. The semiconductor device according to any one of claims 1 to 5, wherein the electric field relaxation layer further includes a third region having a separated semiconductor layer of a second conductivity type separated from the second region outside the second region.

7. The semiconductor device according to claim 1, wherein the electric field relaxation layer further includes a third region that is in contact with the second region outside the second region and has a different acceptor surface density from that of the second region.

8. The first region has a stacked structure in which a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type are stacked. The second region is formed of either the first semiconductor layer or the second semiconductor layer, and an opening is formed in the other. The third region is formed of the one different from the second region among the first semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 7.

9. The third region has a second high-concentration semiconductor layer having a higher impurity concentration than the third semiconductor layer spaced apart from the second region through a third semiconductor layer of the second conductivity type. The acceptor surface density of the third semiconductor layer is smaller than that of the second high-concentration semiconductor layer. The semiconductor device according to claim 7.

10. The first region has a stacked structure in which the first semiconductor layer and the second semiconductor layer are stacked to have a first film thickness. The second region is formed of either the first semiconductor layer or the second semiconductor layer. The third region has a plurality of partial stacked structures in which a plurality of semiconductor layers of one of the first semiconductor layer and the second semiconductor layer are discontinuously formed and the other semiconductor layer is continuously formed, and the plurality of semiconductor layers of one and the other semiconductor layer are stacked to have the first film thickness. Between the plurality of partial stacked structures, it is formed of the first semiconductor layer or the second semiconductor layer having a second film thickness thinner than the first film thickness. The semiconductor device according to claim 8.

11. The semiconductor device according to claim 10, wherein the plurality of semiconductor layers of one are formed of the first semiconductor layer formed discontinuously, and the other semiconductor layer is formed of the second semiconductor layer formed continuously.

12. The semiconductor device according to any one of claims 7 to 11, wherein the electric field relaxation layer further includes a separated region having a separated semiconductor layer of the second conductivity type spaced apart from the third region outside the third region.

13. The semiconductor device according to any one of claims 2, 5, 8, and 10, wherein in the stacked structure, the second semiconductor layer is stacked on the first semiconductor layer, and the impurity concentration of the second conductivity type in the first semiconductor layer is greater than the impurity concentration of the second conductivity type in the second semiconductor layer.

14. The semiconductor device according to claim 1, wherein in the first region, the first semiconductor layer of the second conductivity type is continuous with a first film thickness, and in the second region, the first semiconductor layer is continuous with a second film thickness that is thinner than the first film thickness.

15. The semiconductor device according to claim 1, wherein a part of the first main electrode is formed so as to ride on the upper part of the electric field relaxation layer in the first region.

16. The semiconductor device according to claim 15, wherein the electric field relaxation layer further includes an inner region located inside the first main electrode rather than in the first region. In the first region, the first semiconductor layer of the second conductivity type is continuous with a first film thickness. In the second region, the first semiconductor layer is continuous with a second film thickness that is thinner than the first film thickness. In the inner region, the first semiconductor layer is continuous with a third film thickness that is thinner than the first film thickness. The first main electrode covers the first semiconductor layer in the inner region and a part of the first semiconductor layer in the first region.

17. The semiconductor device according to claim 15 or 16, further comprising a protective film that covers the surface of the electric field relaxation layer in the second region from the outer edge portion outside the electric field relaxation layer in the first region. The first main electrode is formed so as to ride on a part of the upper part of the protective film.

18. The semiconductor device according to claim 17, wherein the protective film is formed of a material having a higher relative dielectric constant than silicon oxide.

19. A method for manufacturing a semiconductor device according to claim 8, comprising: (a) a step of patterning the first semiconductor layer on the semiconductor layer using a first etching mask; and (b) a step of patterning the stacked structure in which the second semiconductor layer is stacked on the first semiconductor layer in the first region using a second etching mask, defining the second region with the first semiconductor layer, and forming the third region with the second semiconductor layer.

20. A method of manufacturing a semiconductor device according to claim 14, comprising: (a) a step of patterning the first semiconductor layer having the first film thickness on the semiconductor layer using a first etching mask; (b) a step of patterning the first semiconductor layer in the second region to a second film thickness thinner than the first film thickness using a second etching mask. A method of manufacturing a semiconductor device.

21. A method of manufacturing a semiconductor device according to claim 3, comprising a step of forming the first high-concentration semiconductor layer by ion implantation. A method of manufacturing a semiconductor device.

22. A method of manufacturing a semiconductor device according to claim 9, comprising a step of forming the second high-concentration semiconductor layer by ion implantation. A method of manufacturing a semiconductor device.

23. A power conversion device comprising: a conversion circuit that has the semiconductor device according to any one of claims 1 to 18 and converts and outputs input power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

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