Method for producing thin film transistor

Abstract

Provided is a method for producing a top-gate type thin film transistor, said method comprising: a patterning step for patterning, by photolithography, an oxide semiconductor film that is formed on a substrate; a first pre-annealing step for subjecting, to an annealing process, the oxide semiconductor film after the patterning; a pre-processing step for subjecting, to a plasma process, a surface of the oxide semiconductor film after the annealing; and a gate insulating film formation step for forming a gate insulating film on the oxide semiconductor film after the plasma process.

Description

Thin film transistor manufacturing method

[0001] The present invention relates to a method for manufacturing a thin film transistor.

[0002] In recent years, active development has been made of thin-film transistors that use an In—Ga—Zn—O (IGZO) oxide semiconductor for the semiconductor layer (channel layer). For example, Patent Document 1 describes a method for manufacturing a top-gate thin-film transistor in which a channel layer, a gate insulating layer, and a gate electrode are stacked in this order from the substrate side.

[0003] Japanese Patent Application Publication No. 2018-195610

[0004] In the above-described method for manufacturing a top-gate thin-film transistor, a post-annealing treatment may be performed at the final stage of the manufacturing process in order to improve field-effect mobility. However, this post-annealing treatment may result in a negative shift in the gate threshold voltage Vth of the thin-film transistor obtained.

[0005] The present invention has been made in view of the above problems, and its main object is to provide a method for manufacturing a top-gate thin film transistor that can suppress a negative shift in threshold voltage after post-annealing.

[0006] That is, the method for manufacturing a thin film transistor of the present invention is a method for manufacturing a top-gate thin film transistor, and is characterized by including: a patterning step of patterning an oxide semiconductor film formed on a substrate by photolithography; a first pre-annealing step of annealing the oxide semiconductor film after the patterning; a pre-treatment step of plasma-treating the surface of the oxide semiconductor film after the annealing; and a gate insulating film formation step of forming a gate insulating film on the oxide semiconductor film after the plasma treatment.

[0007] In such a manufacturing method, the oxide semiconductor film after the photolithography process is annealed before the gate insulating film is formed, and the surface is further subjected to plasma treatment, thereby making it possible to remove carbon-based impurities (CO) contained in the photoresist remaining on the surface of the oxide semiconductor film, thereby suppressing a negative shift in the threshold voltage after post-annealing and obtaining a stable threshold voltage (Vth).

[0008] Specific embodiments of the pretreatment step include: ２ Gas, N ２ For example, a plasma treatment may be performed using plasma generated from a gas or a mixed gas of these as a process gas.

[0009] It is preferable that the gate insulating film forming step forms the gate insulating film by a plasma CVD method, in which after plasma is generated using a plasma processing apparatus and plasma processing is performed, the gate insulating film can be formed by simply changing the type of process gas supplied without turning off the generated plasma, thereby shortening the processing time.

[0010] The gate insulating film forming step includes forming the gate insulating film by a plasma CVD method, and then ２ It is preferable to include a second pre-annealing step of annealing the oxide semiconductor film in a plasma atmosphere. In this way, defects in the oxide semiconductor film caused by the plasma treatment or film formation by plasma CVD can be repaired by the annealing step, and the oxide semiconductor film can easily obtain the resistance required for TFT operation.

[0011] Furthermore, it is preferable that the gate insulating film formation step forms the gate insulating film using plasma generated by applying high-frequency power to an antenna, and includes a first film formation step of forming the gate insulating film by applying a first high-frequency power of a predetermined magnitude to the antenna, and a second film formation step of forming the gate insulating film by applying a second high-frequency power greater than the first high-frequency power to the antenna after the first film formation step. In this way, in the first film formation step in which the high-frequency power applied is relatively small, plasma damage to the underlying oxide semiconductor film can be suppressed and the resistance of the oxide semiconductor film can be suppressed from decreasing, and in the second film formation step in which the high-frequency power applied is relatively large, a film with excellent insulating properties can be obtained.

[0012] From the viewpoint of efficiently forming the gate insulating film while suppressing plasma damage to the oxide semiconductor film, it is preferable to make the thickness of the gate insulating film formed by the second film formation step larger than the thickness of the gate insulating film formed by the first film formation step.

[0013] According to the present invention configured as described above, it is possible to provide a method for manufacturing a top-gate thin film transistor that can suppress a negative shift in threshold voltage after post-annealing.

[0014] 1 is a longitudinal sectional view schematically showing the configuration of a thin film transistor obtained by the manufacturing method of this embodiment; FIG. 2 is a diagram schematically showing the configuration of a plasma processing apparatus used in the manufacturing method of the same embodiment; FIG. 3 is a diagram explaining the configuration of a thin film transistor used in an experimental example; FIG. 4 is a graph showing TFT transfer characteristics of the thin film transistor used in experimental example 1 (without post-annealing); FIG. 5 is a graph showing the relationship between the gate threshold voltage of the thin film transistor used in experimental example 1 and the post-annealing temperature; FIG. 6 is a graph showing the relationship between the gate threshold voltage of the thin film transistor used in experimental example 2 and the plasma pretreatment time; FIG. 7 is a graph showing the relationship between the thickness of the first layer of the gate insulating layer of the thin film transistor used in experimental example 3 and the semiconductor layer sheet resistance; and FIG. 8 is a graph showing the relationship between the thickness of the first layer of the gate insulating layer of the thin film transistor used in experimental example 3 and the leakage current density.

[0015] A thin film transistor 1 according to one embodiment of the present invention and a method for manufacturing the same will be described below.

[0016] 1. Thin-Film Transistor 1 The thin-film transistor 1 of this embodiment is a so-called top-gate TFT that uses an oxide semiconductor for the channel. As shown in FIG. 1 , the thin-film transistor 1 includes a semiconductor layer 3 serving as a channel layer, a gate insulating layer 4, and a gate electrode 5, which are stacked in this order from the substrate 2 side, and a source electrode 6 and a drain electrode 7 provided on either side of the semiconductor layer 3.

[0017] The substrate 2 is made of any material that can transmit light, and may be made of, for example, a resin material such as plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, etc., or a glass material.

[0018] The semiconductor layer 3 (channel layer) allows current to pass between the source electrode 6 and the drain electrode 7. The semiconductor layer 3 of this embodiment is made of an oxide semiconductor and contains, as a main component, an oxide of at least one element selected from, for example, In, Ga, Zn, Sn, Al, Ti, etc. Specific examples of materials that may constitute the semiconductor layer 3 include In—Ga—Zn—O (IGZO), In—Al—Mg—O, In—Al—Zn—O, and In—Hf—Zn—O. The semiconductor layer 3 is made of an amorphous oxide semiconductor film. While the semiconductor layer 3 of this embodiment has a single-layer structure, it is not limited thereto and may have a stacked structure formed by stacking multiple layers having different compositions and crystallinity.

[0019] The gate insulating layer 4 is made of any insulating material having high insulating properties. In this example, SiO ２ The gate insulating layer 4 is made of an insulating film (gate insulating film) containing SiN as a main component. ｘ , SiON, Al ２ O ３ , Y ２ O ３ , Ta ２ O５ , Hf ２ The gate insulating layer 4 may be an insulating film containing one or more oxides selected from the following: a single layer structure of these insulating films or a laminated structure of two or more layers.

[0020] The gate electrode 5 controls the carrier density in the semiconductor layer 3 by the gate voltage applied to the thin film transistor 1. The gate electrode 5 is made of any material having high conductivity, and may be made of, for example, one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc. Alternatively, the gate electrode 5 may be made of a conductive film of a metal oxide such as Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), or In—Ga—Zn—O (IGZO). The gate electrode 5 may be made of a single layer structure of these conductive films or a laminate structure of two or more layers.

[0021] The source electrode 6 and the drain electrode 7 are formed apart from each other so as to partially cover the surface of the semiconductor layer 3. Like the gate electrode 5, the source electrode 6 and the drain electrode 7 are made of a highly conductive material so as to function as electrodes. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which multiple layers made of different materials are stacked.

[0022] 2. Manufacturing Method of Thin Film Transistor 1 Next, a manufacturing method of the thin film transistor 1 having the above-described structure will be described. The manufacturing method of the thin film transistor 1 of this embodiment includes (1) a semiconductor layer forming step, (2) a gate insulating layer forming step, (3) a gate electrode forming step, (4) a source / drain electrode forming step, and (5) a post-annealing step. Each step will be described below.

[0023] (1) Semiconductor Layer Forming Step The semiconductor layer forming step includes: (1-1) a film forming step of forming an oxide semiconductor film; (1-2) a patterning step of patterning the formed oxide semiconductor film; and (1-3) a first pre-annealing step of annealing the patterned oxide semiconductor film.

[0024] (1-1) Film Forming Step (Oxide Semiconductor Film Forming Step) First, an oxide semiconductor film is formed on the substrate 2. The oxide semiconductor film may be formed by a known method, for example, by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma. However, the method is not limited to this, and the oxide semiconductor film may be formed by other methods.

[0025] (1-2) Patterning Step Next, the oxide semiconductor film formed on the substrate 2 is patterned by a photolithography process. Specifically, after applying a photoresist to the surface of the oxide semiconductor film, exposure and development are performed so that the resist remains only in the area that will later become the channel layer. The area where the resist is not applied is then removed by etching to form the semiconductor layer 3. The etching method is CF ４ Dry etching using gas or the like may be performed, or wet etching using acid such as HCl may be performed.

[0026] (1-3) First Pre-Annealing Step The first pre-annealing step is an annealing treatment of the oxide semiconductor film after the patterning step (after the photolithography process) to remove carbon-based impurities (such as CO) contained in the photoresist remaining on the surface of the oxide semiconductor film. The first pre-annealing step is preferably performed, for example, in an oxygen atmosphere at a temperature of 300° C. or higher and 450° C. or lower for 0.5 hours or longer and 3 hours or shorter, and is preferably performed, for example, in an oxygen atmosphere at about 350° C. for about 2 hours.

[0027] (2) Gate insulating layer forming step After the first pre-annealing step, a gate insulating layer 4 is formed on the semiconductor layer 3 made of an oxide semiconductor film. The gate insulating layer forming step includes: (2-1) a pre-treatment step of performing a plasma treatment on the surface of the oxide semiconductor film; (2-2) a film forming step of forming a gate insulating film on the oxide semiconductor film; and (2-3) a second pre-annealing step of annealing the oxide semiconductor film after forming the gate insulating film.

[0028] (2-1) Pretreatment Step Before the film formation step, the surface of the oxide semiconductor film is subjected to plasma treatment (specifically, plasma ashing), whereby carbon-based impurities (such as CO) contained in the photoresist remaining on the surface of the oxide semiconductor film can be further removed.

[0029] The plasma processing may be performed using an inductively coupled plasma processing apparatus 100 as shown in Fig. 2. Specifically, the plasma processing apparatus 100 includes a vacuum vessel 20 having a processing chamber 10 formed therein that is evacuated and into which a process gas G is introduced, an antenna 30 provided inside the processing chamber 10, and a high-frequency power supply 40 that applies a high-frequency wave (13.56 MHz) to the antenna 30. When a high-frequency wave is applied from the high-frequency power supply 40 to the antenna 30, a high-frequency magnetic field generated from the antenna 30 is formed in the processing chamber 10, thereby generating an inductive electric field, and thereby generating an inductively coupled plasma P.

[0030] Specifically, in this step, oxygen gas is supplied as the process gas into the processing chamber 10, and in this state, high frequency power is applied to the antenna 30 to generate an inductively coupled plasma, thereby performing plasma processing. The plasma processing time is preferably 5 seconds or more. The process gas may be nitrogen gas or a mixture of oxygen gas and nitrogen gas. In this embodiment, the process gas supply flow rate is 400 sccm, the high frequency power (RF power) applied to the antenna 30 is 1.3 kW, the processing chamber pressure is 2.7 Pa, the processing time is 10 seconds, and the substrate temperature is 180°C. However, these settings may be changed as appropriate.

[0031] (2-2) Film Forming Step (Gate Insulating Film Forming Step) After the plasma treatment, a gate insulating film is formed on the oxide semiconductor film. In this embodiment, a SiO ２ This film formation step is preferably performed continuously from the pre-treatment step while maintaining the plasma generated in the treatment chamber 10 of the plasma treatment apparatus 100 in the pre-treatment step (i.e., without turning off the plasma).

[0032] In this film formation process, silane gas (SiH ４A mixed gas of a nitrogen gas (a nitrogen gas) and oxygen gas is supplied as a process gas into the processing chamber 10, and in this state, high frequency power is applied to the antenna 30 to generate an inductively coupled plasma. The film formation process of this embodiment includes a first film formation process and a second film formation process in which different high frequency powers are applied to the antenna 30.

[0033] First, a first film formation process is performed. In this first film formation process, a first high-frequency power of a predetermined magnitude is applied to the antenna 30 to generate an inductively coupled plasma and form a film. The magnitude of the applied first high-frequency power is preferably the same as the magnitude of the high-frequency power applied to the antenna 30 in the pre-processing process, for example, 1.3 kW, but is not limited to this. In this embodiment, the supply flow rates of the process gases are 150 sccm for silane gas and 400 sccm for oxygen gas, the pressure in the processing chamber is 2.7 Pa, the film formation time is 5 seconds, and the substrate temperature is 180° C. However, these may be changed as appropriate.

[0034] The second film formation process is performed consecutively (i.e., without turning off the plasma) after the first film formation process. In the second film formation process, a second high-frequency power greater than the first high-frequency power is applied to the antenna 30 to generate an inductively coupled plasma, thereby forming a film. Here, the second high-frequency power is set to 1.9 kW, but is not limited thereto. In this embodiment, the process gas supply flow rates are 150 sccm for silane gas and 200 sccm for oxygen gas, the processing chamber pressure is set to 2.7 Pa, the film formation time is set to 65 seconds, and the substrate temperature is set to 180°C. However, these may be changed as appropriate. Furthermore, in the second film formation process, the film formation time is preferably longer than that of the first film formation process (e.g., 65 seconds). Other conditions, such as the processing chamber pressure and substrate temperature, are preferably the same as those of the first film formation process.

[0035] Furthermore, the thickness of the gate insulating film (second layer) formed in the second film formation process is preferably greater than the thickness of the gate insulating film (first layer) formed in the first film formation process. In this case, the film thickness of the first layer is preferably 10 nm or less. The first layer can suppress plasma damage to the underlying semiconductor layer (IGZO film) and suppress the semiconductor layer from becoming low in resistance. On the other hand, the second layer can provide a film with excellent insulating properties. Furthermore, the amount of oxygen gas (O ２ ) flow rate of silane gas (SiH ４ ) is preferably set to be larger than the same flow rate ratio in the first film formation step.

[0036] (2-3) Second Pre-Annealing Step The second pre-annealing step is an annealing process of the oxide semiconductor film after the gate insulating film is formed by the plasma CVD method, thereby recovering defects in the oxide semiconductor film caused by the plasma and making it easier to obtain the resistance of the oxide semiconductor film required for TFT operation. The second pre-annealing step is preferably performed, for example, in an oxygen atmosphere at a temperature of 300° C. or higher and 450° C. or lower for 0.5 hours or higher and 3 hours or lower, and is preferably performed, for example, in an oxygen atmosphere at about 350° C. for about 2 hours.

[0037] (3) Gate Electrode Forming Step After the second pre-annealing step, the gate electrode 5 is formed on the gate insulating film. The method for forming the gate electrode 5 is not particularly limited, and may be a known method such as vacuum deposition.

[0038] (4) Source / Drain Electrode Formation Step Then, the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 3. The formation of the source electrode 6 and the drain electrode 7 is not particularly limited, and may be performed by any known method.

[0039] (5) Post-annealing Step After all components are formed, post-annealing (heat treatment) is performed. This post-annealing may be performed, for example, in a nitrogen atmosphere at atmospheric pressure. The furnace temperature during post-annealing is not particularly limited, and is, for example, 150°C to 350°C, and preferably 200°C or higher. The heat treatment time is also not particularly limited, and is, for example, 1 hour to 3 hours.

[0040] In this manner, the thin film transistor 1 of this embodiment can be obtained.

[0041] <3. Effects of this embodiment> In the method for manufacturing the thin-film transistor 1 of this embodiment configured as described above, the oxide semiconductor film after the photolithography process is annealed before the gate insulating film is formed, and the surface is further subjected to plasma treatment, thereby making it possible to remove carbon-based impurities (CO) contained in the photoresist remaining on the surface of the oxide semiconductor film, and thereby making it possible to suppress a negative shift in the threshold voltage after post-annealing and obtain a stable threshold voltage (Vth).

[0042] The effects of the method for manufacturing the thin film transistor 1 of this embodiment were confirmed by experiments.

[0043] Experimental Example 1: The semiconductor layer was made of IGZO, and the gate insulating layer 4 was made of SiO ２ A number of top-gate thin-film transistors (see FIG. 3) were fabricated under different manufacturing conditions, each with a gate electrode 5 formed of a laminate of Pt and Mo, and their transfer characteristics were evaluated. The results are shown in FIGS. 4 to 6.

[0044] As can be seen from FIGS. 4 to 6, after the semiconductor layer made of IGZO is patterned by a photolithography process, a gate insulating layer 4 (SiO ２ It was confirmed that in the sample in which an annealing treatment (first pre-annealing treatment) was performed before the formation of the semiconductor layer, and then the surface of the semiconductor layer was subjected to plasma treatment, the negative shift of the gate threshold voltage Vth after post-annealing was suppressed compared to the sample in which the first pre-annealing treatment was not performed.

[0045] Experimental Example 2 In Experimental Example 2, the semiconductor layer was made of IGZO, and the gate insulating layer 4 was made of SiO ２A plurality of top-gate thin-film transistors (see FIG. 3 ) were fabricated, each having a gate electrode 5 formed of a Pt and Mo laminate, with the duration of plasma treatment varied (no plasma treatment, 5 seconds, 10 seconds, and 15 seconds), and their transfer characteristics were evaluated. The results are shown in FIG. 7 . As can be seen from FIG. 7 , samples that underwent plasma treatment (pretreatment) for 5 seconds or more were confirmed to have a more stable threshold voltage (Vth) than samples that did not undergo plasma treatment (pretreatment).

[0046] In Experimental Example 3, the semiconductor layer was made of an IGZO film, and the gate insulating layer 4 was made of SiO ２ A plurality of top-gate thin-film transistors (see FIG. 3 ) were fabricated, each having a first layer of two layers (first and second layers) made of Pt and Mo, and a gate electrode 5 made of a laminate of Pt and Mo. The thickness of the first layer was varied, and the sheet resistance and leakage current density of the semiconductor layer were evaluated. The results are shown in FIG.

[0047] As can be seen from Fig. 8, it was confirmed that the sample with the second layer formed can suppress the decrease in resistance of the semiconductor layer (IGZO film) compared to the sample without the first layer. Also, as shown in Fig. 9, the leakage current density can be reduced by making the thickness of the first layer smaller than that of the second layer, and the leakage current density can be reduced to 1 × 10 by making the thickness of the first layer 10 nm or less. －６ (A / cm ２ ) I was able to confirm that the following can be done:

[0048] 4. Other Modified Embodiments The present invention is not limited to the above-described embodiment. For example, in the manufacturing method of the above-described embodiment, the gate insulating film deposition process includes a first film deposition process and a second film deposition process, but is not limited to this. In other embodiments, the gate insulating film deposition process may be performed without changing the high-frequency power applied to the antenna 30 during the process.

[0049] In the manufacturing method of the above embodiment, the gate insulating layer forming step includes the second pre-annealing step, but this is not limiting. In the manufacturing method of other embodiments, the gate insulating layer forming step does not need to include the second pre-annealing step.

[0050] Furthermore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible without departing from the spirit of the present invention.

[0051] The above-described method for manufacturing a thin film transistor of the present invention can provide a top-gate thin film transistor capable of suppressing a negative shift in threshold voltage after post-annealing.

[0052] REFERENCE SIGNS LIST 1 thin film transistor 2 substrate 3 semiconductor layer 4 gate insulating layer 5 gate electrode 6 source electrode 7 drain electrode

Claims

1. A method for manufacturing a top-gate type thin film transistor, comprising: a patterning step of patterning an oxide semiconductor film formed on a substrate by photolithography; a first pre-annealing step of annealing the oxide semiconductor film after the patterning; a pre-treatment step of plasma treating a surface of the oxide semiconductor film after the annealing; and a gate insulating film formation step of forming a gate insulating film on the oxide semiconductor film after the plasma treatment.

2. The pretreatment step is ２ Gas, N ２ 2. The method for producing a thin film transistor according to claim 1, wherein the plasma treatment is performed using plasma generated by using a gas or a mixture of gases thereof as a process gas.

3. The method for producing a thin film transistor according to claim 1, wherein the gate insulating film forming step forms the gate insulating film by a plasma CVD method.

4. The gate insulating film forming step includes forming the gate insulating film by a plasma CVD method, and then performing O ２ The method for manufacturing a thin film transistor according to claim 3 , further comprising a second pre-annealing step of annealing the oxide semiconductor film in an atmosphere.

5. A method for manufacturing a thin film transistor as described in claim 3, wherein the gate insulating film formation process forms the gate insulating film using plasma generated by applying high frequency power to an antenna, the method comprising: a first film formation process for forming the gate insulating film by applying a first high frequency power of a predetermined magnitude to the antenna; and a second film formation process for forming the gate insulating film by applying a second high frequency power greater than the first high frequency power to the antenna after the first film formation process.

6. The method for manufacturing a thin film transistor according to claim 5, wherein the thickness of the gate insulating film formed in the second film forming step is greater than the thickness of the gate insulating film formed in the first film forming step.

7. The method for manufacturing a thin film transistor according to claim 6, wherein the gate insulating film formed in the first film formation step has a thickness of 10 nm or less.

8. The method for producing a thin film transistor according to claim 1, wherein the plasma treatment in the pretreatment step is carried out for 5 seconds or more.

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