Electronic device, control method, and program

Abstract

This electronic device includes: a shared terminal connected to an external device; a plurality of signal processing units connected to the shared terminal; one or more first switches for switching the shared terminal and one or more signal processing units among the plurality of signal processing units to a connected state or an unconnected state; and control means for controlling operation states of the plurality of signal processing units and open and closed states of the first switches. The plurality of signal processing units include a first signal processing unit that is connected to the shared terminal without the first switches and that processes a first signal, and one or more signal processing units that are connected to the shared terminal via the first switches and that process a signal having a lower transmission rate than the first signal. In a state where the first signal processing unit is to process the first signal, the control means sets the first switches to the unconnected state.

Description

Electronic device, control method, and program

[0001] The present invention relates to a technique for sharing terminals with different signaling methods.

[0002] Electronic devices such as digital video cameras are equipped with multiple terminals (interfaces) compatible with various signal formats (signal standards), such as terminals for inputting and outputting analog and digital signals in serial or parallel formats. Because each of these terminals has its own dedicated shape, the type and number of terminals installed in an electronic device affect the size of the housing that makes up the external appearance of the electronic device.

[0003] Furthermore, since miniaturization of electronic devices is desirable, there are techniques for sharing multiple terminals to reduce the housing size (Patent Documents 1 and 2). Patent Document 1 describes a configuration in which multiple signal processing units are connected in parallel to a shared terminal and a switch circuit switches between the signal processing units. Patent Document 2 describes a configuration in which multiple switch elements switch the path from the shared terminal to the signal processing units.

[0004] Japanese Patent No. 4182672 Japanese Patent Application Laid-Open No. 2012-239011

[0005] In Patent Document 1, there is a concern that the input signal to the shared terminal may be degraded because it passes through a switch circuit, and Patent Document 2 does not take into consideration sharing a low-speed transmission signal terminal and a high-speed transmission signal terminal.

[0006] The present invention has been made in view of the above-mentioned problems, and realizes a technology that can reduce the degradation of high-speed transmission signals and enable terminals with different signaling methods to be shared.

[0007] In order to solve the above problem, the electronic device of the present invention has a shared terminal connected to an external device, a plurality of signal processing units connected to the shared terminal, one or more first switches that switch one or more of the plurality of signal processing units to a connected state or a disconnected state and the shared terminal, and a control means that controls the operating states of the plurality of signal processing units and the open / closed state of the first switches, wherein the plurality of signal processing units include a first signal processing unit that is connected to the shared terminal without going through the first switch and that processes a first signal, and one or more signal processing units that are connected to the shared terminal via the first switch and that process a signal having a lower transmission speed than the first signal, and the control means puts the first switch into a disconnected state when the first signal processing unit is in a state where it is processing the first signal.

[0008] According to the present invention, it is possible to reduce the degradation of high-speed transmission signals and to share terminals for different signal systems.

[0009] Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which the same or similar elements are designated by the same reference numerals.

[0010] The accompanying drawings are incorporated in and constitute a part of the specification, illustrate embodiments of the present invention, and together with the description, serve to explain the principles of the present invention. Figure 1 is a diagram illustrating the configuration of an electronic device according to a first embodiment. Figure 2 is a diagram illustrating the configuration of an electronic device according to a second embodiment. Figure 3 is a diagram illustrating the configuration of an electronic device according to a third embodiment.

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0012] In this embodiment, an example is described in which the electronic device is an imaging device such as a digital video camera that captures video and other images, but the electronic device is not limited to an imaging device and may also be a video device that records, plays back, and edits video.

[0013] First Embodiment First, the configuration and functions of an electronic device according to a first embodiment will be described with reference to FIG.

[0014] The electronic device 100a of the first embodiment is provided with one shared terminal 1 and multiple (three in FIG. 1 ) external output terminals 2, 3, and 4. The shared terminal 1 and the external output terminals 2, 3, and 4 are provided in a housing that forms the external shape of the electronic device 100a, and are connected to a signal processing circuit via a signal transmission path inside the electronic device 100a.

[0015] The shared terminal 1 is configured as a shared input terminal for signals that are input from external devices and have different signal formats (signal standards), such as analog, digital, serial, or parallel, and that have different transmission speeds and frequency bands.

[0016] The external output terminals 2, 3, and 4 are connected to video input terminals of external devices via cables or the like, and output video signals to the external devices.

[0017] The external device may be an imaging device that captures video or other images, or video equipment that records, plays back, or edits video.

[0018] The electronic device 100 a includes a control unit 40 a, an imaging unit 50, an image processing unit 60, a recording unit 70, a display unit 80, and a video output unit 90.

[0019] The control unit 40a includes a microcomputer that controls the entire electronic device 100a, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), etc. The microcomputer includes a processor (CPU, MPU) that performs arithmetic and control processing of the electronic device 100a, a volatile memory (ROM) that stores programs executed by the processor, and a work memory (RAM) into which programs read from the non-volatile memory and constants and variables for executing the programs are loaded. The control unit 40a controls each component of the electronic device 100a by loading the programs stored in the ROM into the RAM and executing them.

[0020] The imaging unit 50 has an image sensor, such as a CCD or CMOS, that converts a subject image into an electrical signal, and an A / D converter that converts an analog video signal output from the image sensor into a digital signal. The imaging unit 50 performs imaging operations including resetting each pixel of the image sensor, accumulating signals (exposure), and reading out signals based on a timing signal from the control unit 40a, and performs noise reduction processing on the generated analog video signal for each frame to output a digital video signal.

[0021] The image processing unit 60 performs digital signal processing on the video signal output from the imaging unit 50. The digital signal processing includes de-Bayer processing, development processing, gamma processing, encoding processing, etc. The video data generated by the image processing unit 60 is output to the display unit 80 and the video output unit 90, and is also stored in the recording unit 70 as a video file such as H.264 / MPEG-4. The image processing unit 60 is configured with a GPU (Graphics Processing Unit), ASIC, FPGA, etc.

[0022] The recording unit 70 is a memory card, a hard disk, an SSD (Solid State Drive), or the like that stores the video file generated by the image processing unit 60 .

[0023] The display unit 80 includes a display device such as a liquid crystal display or an organic electroluminescence (EL) display that displays live view images, playback video, and a GUI (Graphical User Interface) for configuring various settings for the electronic device 100a. The display unit 80 also includes an integrated touch panel that accepts user operations and is capable of detecting user touch operations on the GUI. The various settings for the electronic device 100a include, for example, settings for image capture, recording, display, video output, and settings for functions assigned to the shared terminal 1. The settings for functions assigned to the shared terminal 1 include settings for synchronization with an external device (external synchronization settings), such as settings for inputting or outputting analog signals and settings for inputting or outputting digital signals. The control unit 40a changes settings and controls the operation of the electronic device 100a in response to user operations via the touch panel. The electronic device 100a may also include an operation unit other than a touch panel that accepts user operations, such as a push button, a rotary dial, or a slide switch.

[0024] The video output unit 90 converts the video data output from the image processing unit 60 into a video signal in a format that complies with a predetermined standard and outputs the video signal to an external device via the external output terminals 2, 3, and 4. The video output unit 90 is configured using an ASIC, FPGA, or the like, and may be configured on the same IC chip as the control unit 40a and the image processing unit 60. The external output terminals 2, 3, and 4 are, for example, a connector that outputs a video signal that complies with HDMI (registered trademark) (High-Definition Multimedia Interface) and two coaxial connectors that output a video signal that complies with SDI (Serial Digital Interface). The coaxial connectors are BNC connectors with an impedance of 75 Ω that correspond to, for example, 12G-SDI corresponding to a video signal transmission speed of 12 Gbps or 3G-SDI corresponding to 3 Gbps.

[0025] The shared terminal 1 is connected to a first signal processing unit 30 and a second signal processing unit 31. The first signal processing unit 31 is connected to the shared terminal 1 without going through the first switch 20, and the second signal processing unit 32 is connected to the shared terminal 1 via the first switch 20. The first signal processing unit 30 and the second signal processing unit 31 process signals of different signaling systems (signal standards) and with different transmission speeds, frequency bands, etc. The second signal processing unit 31 processes signals with a narrower frequency band and lower transmission speeds and frequencies than the signals processed by the first signal processing unit 30.

[0026] The shared terminal 1 is a coaxial connector into which a synchronization signal is input from an external device, such as a BNC connector or DIN1.0 / 2.3 connector with an impedance of 75 Ω. These synchronization signals are transmitted over a 75 Ω transmission line and terminated by a termination unit 10 consisting of a 75 Ω termination resistor placed between the transmission line and GND to reduce signal degradation due to reflection noise. Video cameras synchronize with external devices using either analog or digital signals. When synchronizing with analog signals, analog synchronization signals such as black burst signals and tri-level synchronization signals are used. When synchronizing with digital signals, digital synchronization signals such as SD-SDI (Standard Definition-SDI) signals, HD-SDI (High Definition-SDI) signals, and 3G-SDI signals are used. The SDI signal is a video signal corresponding to return video, which is video captured by a separate imaging device.

[0027] Analog synchronous signals and digital synchronous signals have different signaling systems (signal standards), transmission speeds, frequency bands, etc., and therefore require signal processing circuits suited to each signal.

[0028] In the case of a digital synchronization signal, the synchronization signal is input to the first signal processing unit 30. The first signal processing unit 30 performs equalization processing on the SDI signal, detects the horizontal synchronization signal H and the vertical synchronization signal V, and generates a clock signal for synchronizing the control unit 40a with an external device. The first signal processing unit 30 is configured with an equalizer IC for equalization processing, an ASIC or FPGA for detecting the horizontal synchronization signal H and the vertical synchronization signal V, and a PLL (Phase Locked Loop) for generating the clock signal. The ASIC or FPGA may be configured on the same IC chip as the control unit 40a and the image processing unit 60. Note that return video input from an external device to the first signal processing unit 30 via the shared terminal 1 can be equalized and then displayed on the display unit 80 via the image processing unit 60, and can also be output to an external device via the video output unit 90 and external output terminals 2, 3, and 4.

[0029] In the case of an analog synchronizing signal, the synchronizing signal is input to the second signal processing unit 31 via the first switch 20. The second signal processing unit 31 detects the horizontal synchronizing signal H and the vertical synchronizing signal V and generates a clock signal for synchronizing the control unit 40a with an external device. The second signal processing unit 31 is composed of a sync separator circuit and an ASIC or FPGA for detecting the horizontal synchronizing signal H and the vertical synchronizing signal V, and a PLL for generating the clock signal. Note that a dedicated sync separator IC may be used instead of the sync separator circuit and the ASIC or FPGA. The ASIC or FPGA may be configured on the same IC chip as the control unit 40a, the image processing unit 60, and the first signal processing unit 30.

[0030] The clock signal generated by the first signal processing unit 30 or the second signal processing unit 31 is input to the control unit 40a. The control unit 40a synchronizes the imaging operation of the imaging unit 50 with the external device based on the clock signal input from the first signal processing unit 30 or the second signal processing unit 31. The control unit 40a controls the first signal processing unit 30 and the second signal processing unit 31, such as powering them down, in accordance with the external synchronization setting of the electronic device 100a.

[0031] Here, the physical layer specifications for SD-SDI signals, HD-SDI signals, and 3G-SDI signals are defined by the Society of Motion Picture and Television Engineers (SMPTE) 259M, SMPTE 292M, and SMPTE 424M, respectively. One of the specifications is return loss, which for 3G-SDI signals requires a return loss of 15 dB or more (5 MHz to 1.485 GHz) and 10 dB or more (1.485 to 2.97 GHz). To meet this requirement, it is necessary to match the impedances of the shared terminal 1 and the signal processing units 30 and 31. However, in this embodiment, an impedance mismatch occurs because the transmission path branches into the first signal processing unit 30 and the second signal processing unit 31 at position A in FIG. 1 .

[0032] Therefore, in this embodiment, in order to reduce the influence of signal reflection in the second signal processing unit 31 when an SDI signal is input from the shared terminal 1, the first switch 20 is switched to an open state, thereby disconnecting the shared terminal 1 from the second signal processing unit 31. This causes the impedance of the first switch 20 seen from the shared terminal 1 to be high, thereby reducing impedance mismatch at branch point A of the transmission path from the shared terminal 1 to the first signal processing unit 30. Furthermore, because there is no switch in the transmission path between the shared terminal 1 and the first signal processing unit 30, impedance mismatch does not occur when the signal passes through the inside of the switch circuit.

[0033] To further reduce impedance mismatch, first switch 20 may be placed near branch point A so that the stub length at branch point A is minimized, or first switch 20 may be placed on the opposite side to the transmission path from shared terminal 1 to first signal processing unit 30. Furthermore, it is desirable that first switch 20 have an input capacitance that is sufficiently small relative to the frequency of the signal input from shared terminal 1.

[0034] The control unit 40a controls the operating states of the first signal processing unit 30 and the second signal processing unit 31 and the open / closed state of the first switch 20 in accordance with the external synchronization setting of the electronic device 100a. When the external synchronization setting is a setting for inputting a digital synchronization signal, the control unit 40a sets the first signal processing unit 30 to a state where it processes the input signal and switches the first switch 20 to a closed state. When the external synchronization setting is a setting for inputting an analog synchronization signal, the control unit 40a sets the second signal processing unit 31 to a state where it processes the input signal and switches the first switch 20 to a closed state.

[0035] The signal processing unit may automatically determine the type of synchronization signal input from the shared terminal 1 and control the opening and closing of the first switch 20 according to the determination result. In this case, the opening and closing state of the first switch 20 may be changed to input the synchronization signal to the first signal processing unit 30 and the second signal processing unit 31 in a time-division manner, and the opening and closing state of the first switch 20 may be controlled so that the synchronization signal is input to the signal processing unit according to the determination result. In this case, the opening and closing control of the first switch 20 may be performed by the first signal processing unit or the second signal processing unit 31. Alternatively, a cable detection function installed in the equalizer IC of the first signal processing unit 30 may be used to open the first switch 20 when the equalizer IC detects the synchronization signal. In this case, the opening and closing control of the first switch 20 may be performed by the first signal processing unit. Alternatively, the amplitude voltage, frequency, and other signal characteristics of the synchronization signal may be analyzed to determine the type of synchronization signal, and the opening and closing of the first switch 20 may be controlled.

[0036] Although the example of FIG. 1 shows two signal processing units, three or more signal processing units may be provided. In this case, switches are not provided in the transmission path of the signal processing unit with the highest signal transmission speed and frequency and strictest impedance matching requirements, but are provided in the transmission paths of the other signal processing units. Furthermore, although the example of FIG. 1 shows only the second signal processing unit 31 downstream of the first switch 20, multiple signal processing units may be provided. In this case, an additional switch may be provided between the first switch 20 and the signal processing unit to isolate the multiple signal processing units. In this case, the location of the switches may be determined according to the required impedance matching specifications and the signal transmission speed and frequency. The opening and closing control of these switches may also be performed by the control unit 40a.

[0037] In this embodiment, the shared terminal 1 is a synchronization signal with an external device, and an example has been described in which terminals for signals with different signal methods (signal standards), transmission speeds, frequency bands, etc. are shared, but this is not limited to synchronization signals.

[0038] As described above, according to the first embodiment, the shared terminal 1 and the plurality of signal processing units 30 and 31 are connected via a transmission line, and a switch is provided to switch the shared terminal 1 and the signal processing units between a connected state and a disconnected state according to the required impedance matching specifications. This reduces degradation of high-speed transmission signals, enables terminals with different signaling methods to be shared, and allows the electronic device 100a to be miniaturized.

[0039] Second Embodiment Next, the configuration and functions of an electronic device according to a second embodiment will be described with reference to FIG.

[0040] In FIG. 2, among the configurations and functions of the electronic device 100b of the second embodiment, the parts that are common to the first embodiment are denoted by the same reference numerals.

[0041] The electronic device 100b of the second embodiment differs from the electronic device 100a of the first embodiment in the control processing of the control unit 40b, and a second switch 21 and a third signal processing unit 32 are added.

[0042] In the second embodiment, the shared terminal 1 is configured as a shared input / output terminal for signals that are input / output from external devices and have different signal formats (signal standards), such as analog, digital, serial, or parallel, and that have different transmission speeds and frequency bands.

[0043] The control unit 40b outputs a clock signal synchronized with the imaging operation of the imaging unit 50 to the third signal processing unit 32. The third signal processing unit 32 generates a synchronization signal synchronized with the imaging operation of the imaging unit 50 based on the synchronization clock signal from the control unit 40a, and outputs the synchronization signal to the external device via the shared terminal 1. The control unit 40b controls the power-down and other operations of the first signal processing unit 30, the second signal processing unit 31, and the third signal processing unit 32 in accordance with the external synchronization setting of the electronic device 100b.

[0044] The third signal processing unit 32 is configured with an ASIC or FPGA for generating a synchronization signal, a video driver for outputting the synchronization signal to an external device, etc. The video driver may be configured as a discrete component using transistors and operational amplifiers, or a dedicated video driver IC may be used.

[0045] The signal processing units 30 and 31 in the first embodiment are circuits that process signals input from the shared terminal 1, and therefore require a 75 Ω termination unit 10 for impedance matching. However, when the input signal terminal and the output signal terminal are shared as in the second embodiment, the 75 Ω termination unit 10 is not required when a signal is output from the shared terminal 1.

[0046] Therefore, in this embodiment, a second switch 21 is disposed between the termination unit 10 and GND, and the second switch 21 is switched to an open state when a signal is output from the shared terminal 1. This separates the termination unit 10 from the transmission path from the third signal processing unit 32, which is a signal output circuit, to the shared terminal 1.

[0047] The control unit 40b controls the opening and closing of the second switch 21 in accordance with the external synchronization setting of the electronic device 100b. The control unit 40b switches the second switch 21 to a closed state when the external synchronization setting is a setting for inputting a signal, and switches the second switch 21 to an open state when the external synchronization setting is a setting for outputting a signal.

[0048] Furthermore, when the external synchronization setting is a setting to input an analog synchronization signal or a setting to output a signal, the control unit 40b switches the first switch 20 to a closed state, and when the external synchronization setting is a setting to input a digital synchronization signal, the control unit 40b switches the first switch 20 to an open state. When the external synchronization setting is a setting to output a signal, the control unit 40b puts the third signal processing unit 32 into a state to process the output signal and switches the first switch 20 to a closed state.

[0049] In order to further reduce impedance mismatching, termination unit 10 and second switch 21 may be placed near branch point B so that the stub length at branch point B with termination unit 10 is minimized, or termination unit 10 and second switch 21 may be placed on the opposite side of the transmission path from shared terminal 1 to first signal processing unit 30. Furthermore, termination unit 10 and second switch 21 may be placed in reverse so that the stub length at branch point B is minimized. Furthermore, it is desirable that second switch 21 have an input capacitance that is sufficiently small relative to the frequency of the signal input from shared terminal 1.

[0050] In this embodiment, the shared terminal 1 is a synchronization signal with an external device, and an example has been described in which terminals for signals with different signal methods (signal standards), transmission speeds, frequency bands, etc. are shared, but this is not limited to synchronization signals.

[0051] As described above, according to the second embodiment, in addition to the effects of the first embodiment, the termination unit 10 of the transmission path connecting the shared terminal 1 and the third signal processing unit 32 is switched between a connected state and a disconnected state by a switch depending on whether a signal is input or output from the shared terminal 1. This reduces degradation of high-speed transmission signals, enables terminals with different signaling methods to be shared, and allows the electronic device 100b to be made smaller.

[0052] Third Embodiment Next, the configuration and functions of an electronic device according to a third embodiment will be described with reference to FIG.

[0053] In FIG. 3, among the configurations and functions of the electronic device 100c of the third embodiment, the parts that are common to the first embodiment are denoted by the same reference numerals.

[0054] The electronic device 100c of embodiment 3 differs from the electronic device 100a of embodiment 1 in the control processing of the control unit 40c, and a first termination unit 10a, a second termination unit 10b, a third switch 21a, a fourth switch 21b, and a third signal processing unit 32 are added.

[0055] Furthermore, in the electronic device 100a of the first embodiment, the termination units 10a and 10b are arranged near the first signal processing unit 30 and the second signal processing unit 31 in order to ensure signal quality.

[0056] In embodiment 3, the shared terminal 1 is configured as a shared input / output terminal for signals that are input / output from external devices and have different signal formats (signal standards), such as analog, digital, serial, or parallel, and that have different transmission speeds and frequency bands.

[0057] When the control unit 40c determines that the setting of the shared terminal 1 has been changed by a user operation, it closes the third switch 21a and the fourth switch 21b, connecting the shared terminal 1 to the first signal processing unit 30 and the second signal processing unit 31. This reduces the signal amplitude value of the transmission path of the shared terminal 1. In this embodiment, the combined resistance value of the first termination unit 10a and the second termination unit 10b is 75Ω. For example, if the termination resistances are both 75Ω, the combined resistance value on the termination side is 75 / 2 = 37.5Ω, and the signal amplitude value is approximately 687% of that of a normal 75Ω circuit.

[0058] Next, after a predetermined time has elapsed, the control unit 40c switches all switches other than the switch that realizes the function selected by the user to the closed state. For example, if the setting is to use the first signal processing unit 30, the control unit 40c switches the fourth switch 21b to the closed state. If the setting is to use the third signal processing unit 32, the control unit 40c switches the third switch 21a and the fourth switch 21b to the closed state. Note that in this embodiment, control does not need to be limited to the time during processing after the predetermined time has elapsed, but may also be performed after determining that the signal amplitude value is smaller than a predetermined value. For example, if the first signal processing unit 30, the second signal processing unit 31, and the third signal processing unit 32 can detect the signal amplitude value, the determination may be performed by each signal processing unit, or a circuit configuration for determining the signal amplitude value may be added. If a circuit configuration is added, signal quality can be ensured by arranging a signal processing unit with a lower signal frequency than the first signal processing unit 30 (on the signal processing units 31 and 32 side of the first switch 20).

[0059] Furthermore, when there are multiple signal processing units, termination units, and switches as in embodiment 3, the third switch 21a and the fourth switch 21b can be controlled to close the switches other than the switches that realize the functions set by the user so that the combined resistance value of the termination units increases in stages. In this case, combinations of multiple termination units and multiple switches are stored in advance, and the control unit 40c calculates the combined resistance value and controls the opening and closing of the switches.

[0060] In this case, the second termination unit 10b can also be disconnected by the first switch 20. In the example of Fig. 3, the second termination unit 10b, which is located after the first switch 20, can be brought into the same state as when the fourth switch 21b is closed, as seen from the shared terminal 1, by disconnecting the first switch 20.

[0061] Furthermore, if the control unit 40c determines that there is no input signal even though the setting of the shared terminal 1 has been changed to the input setting, it is possible to avoid circuit destruction of the electronic device 100c by temporarily opening the third switch 21a and the fourth switch 21b and repeating the series of control sequences of embodiment 3.

[0062] As described above, according to the third embodiment, when a plurality of termination units 10a, 10b are arranged near a plurality of signal processing units 30, 31 to ensure signal quality, the open / closed state of the plurality of termination units 10a, 10b can be controlled by the third switch 21a and the fourth switch 21b in response to a change in the setting of the shared terminal 1, thereby suppressing the signal amplitude value and preventing circuit destruction of the electronic device.

[0063] The present invention can also be realized by a process in which a program that realizes one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., an ASIC) that realizes one or more of the functions.

[0064] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention.

[0065] This application claims priority based on Japanese Patent Application No. 2023-207171, filed December 7, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. An electronic device comprising: a shared terminal connected to an external device; a plurality of signal processing units connected to the shared terminal; one or more first switches that switch one or more of the plurality of signal processing units to a connected or unconnected state and the shared terminal; and control means for controlling the operating states of the plurality of signal processing units and the open / closed states of the first switches, wherein the plurality of signal processing units include a first signal processing unit that is connected to the shared terminal without passing through the first switch and that processes a first signal, and one or more signal processing units that are connected to the shared terminal via the first switch and that process a signal having a lower transmission speed than the first signal, and wherein the control means sets the first switch to a unconnected state when the first signal processing unit is in a state where it is processing the first signal.

2. An electronic device as described in claim 1, further comprising a setting means for setting a function to be assigned to the shared terminal, and wherein the control means controls the state of the plurality of signal processing units to a first state in which a signal is processed or a second state in which a signal is not processed depending on the function assigned to the shared terminal.

3. The electronic device described in claim 2, characterized in that the multiple signal processing units include a second signal processing unit that processes a signal having a lower frequency than the first signal, the frequency of the first signal is higher than the frequency of a second signal processed by the second signal processing unit, and the first switch switches between a connected state and a disconnected state between the second signal processing unit and the shared terminal.

4. The electronic device described in claim 3, characterized in that the control means sets the first signal processing unit to the first state and the second signal processing unit to the second state in response to the first signal being input to the shared terminal, and sets the first signal processing unit to the second state and the first signal processing unit to the first state in response to the second signal being input to the shared terminal.

5. The electronic device according to claim 3 or 4, characterized in that the control means sets the first switch to a non-connected state when the first signal processing section is in the first state.

6. The electronic device according to any one of claims 1 to 5, further comprising a termination section for terminating a signal input to the shared terminal.

7. The electronic device according to claim 3, wherein the plurality of signal processing sections include a third signal processing section that is connected to the shared terminal via the first switch and outputs a signal to the shared terminal.

8. The electronic device according to claim 7, characterized in that the control means brings the first switch into a connected state when the third signal processing unit is in the first state and the first signal processing unit and the second signal processing unit are in the second state.

9. An electronic device as described in claim 7 or 8, comprising: a termination section which terminates a signal input to the shared terminal; and a second switch which switches between a connected state and a non-connected state between the termination section and GND, wherein when a signal is input from the shared terminal, the second switch is set to a connected state, and when a signal is output from the shared terminal, the second switch is set to a non-connected state.

10. The electronic device according to claim 9, wherein the control means switches the second switch between a connected state and a disconnected state depending on a function assigned to the shared terminal.

11. The electronic device according to claim 3, further comprising: a first termination section provided downstream of a position where the shared terminal branches off to the first signal processing section and the second signal processing section, between said position and the first signal processing section, terminating a signal input to the shared terminal; a second termination section provided downstream of said position, between the first switch and the second signal processing section, terminating a signal input to the shared terminal; a third switch that switches the first termination section and GND between a connected state and a non-connected state; and a fourth switch that switches the second termination section and GND between a connected state and a non-connected state.

12. The electronic device described in claim 11, characterized in that when the function assigned to the shared terminal is changed, the control means brings the third switch and the fourth switch into a connected state, and after a predetermined time has elapsed, switches other than the switch that realizes the function assigned to the shared terminal into a closed state.

13. The electronic device described in claim 11, characterized in that when the function assigned to the shared terminal is changed, the control means switches the switches other than the switch that realizes the function assigned to the shared terminal to a closed state when the signal amplitude value of the shared terminal is smaller than a predetermined value after switching the third switch and the fourth switch to a connected state.

14. The electronic device according to claim 11, characterized in that the control means switches the second termination section and GND between a connected state or a disconnected state by setting the first switch to a disconnected state when the fourth switch is in a connected state.

15. The electronic device described in claim 13, characterized in that when the function assigned to the shared terminal is set to input a signal, if the control means determines that no signal is being input, it disconnects the third switch and the fourth switch and redoes control when the function assigned to the shared terminal has been changed.

16. A control method for an electronic device, the electronic device having: a shared terminal connected to an external device; a plurality of signal processing units connected to the shared terminal; and one or more first switches for switching one or more of the plurality of signal processing units to a connected state or a disconnected state with the shared terminal, the plurality of signal processing units including a first signal processing unit connected to the shared terminal without going through the first switch and processing a first signal, and one or more signal processing units connected to the shared terminal via the first switch and processing a signal having a lower transmission speed than the first signal, the control method comprising a step of controlling the operating states of the plurality of signal processing units and the open / closed state of the first switch, the control step being characterized in that the first switch is brought into a disconnected state when the first signal processing unit is processing the first signal.

17. A program for causing a computer to function as an electronic device according to any one of claims 1 to 15.

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