Slew boost circuit and method for controlling slew boost circuit

Abstract

The present invention relates to a slew boost circuit comprising: a comparator that compares a first differential input voltage and a second differential input voltage and generates a dynamic current; a first boosting current supply terminal which, when the dynamic current is generated, mirrors the generated dynamic current and supplies same to a main source-amplifying circuit; and a second boosting current supply terminal which supplies additional dynamic current to the main source-amplifying circuit unit on the basis of the operation of a timing controller.

Description

Slew boost circuit and slew boost circuit control method

[0001] The present invention relates to a slew boost circuit and a slew boost circuit control method.

[0002] Display panels, especially OLED displays, typically require high resolution and fast response times. To achieve this, display driver ICs play a crucial role in accurately processing input signals and transmitting them to the display panel as output signals. During this process, the rise and fall speeds of the output signals, or slew rate, significantly impact display performance.

[0003] Existing technologies have proposed various circuit designs that detect and compensate for differences between input and output signals to reduce slew rate deviation. However, these technologies suffer from reduced signal detection capabilities in low slew rate situations, where the input signal changes slowly, resulting in insufficient compensation effectiveness of the slew boost circuit. In particular, in situations where the output signal has a long transmission distance and a high load, such as the edge channel of a display, the signal's rise and fall speeds can slow down, degrading output quality.

[0004] Therefore, there is a need to develop a slew boost circuit that can solve these problems.

[0005] The present invention aims to provide a novel circuit and control method for compensating for slew rate deviation occurring in each channel of a display driver IC. In particular, the present invention aims to effectively compensate for low slew rate signals occurring in the edge channel, thereby shortening settling time and improving display output quality.

[0006] The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0007] A slew boost circuit according to one embodiment of the present invention may include a slew boost circuit that supplies current to a main source amplifier circuit, the slew boost circuit comprising: a comparator that compares a first differential input voltage and a second differential input voltage and generates a current; a first boosting current supply terminal that mirrors the generated current when the current is generated and supplies the current to the main source amplifier circuit; and a second boosting current supply terminal that additionally supplies current to the main source amplifier circuit based on the operation of a timing controller.

[0008] In at least one embodiment of the present invention, the comparator includes first and second comparison transistors, the first differential input voltage being connected to a gate and the second differential input voltage being connected to a source, and when the first differential input voltage rises, current can flow to the first comparison transistor, and when the first differential input voltage falls, current can flow to the second comparison transistor.

[0009] In at least one embodiment of the present invention, the first boosting current supply terminal includes a mirror circuit that generates a mirroring current by mirroring the current flowing to the first and second comparison transistors, and can supply the mirroring current to a common source terminal and / or a common gate terminal of the main source amplifier circuit unit.

[0010] In at least one embodiment of the present invention, the timing controller is synchronized to a change point in time of the first differential input voltage, and can set a current supply time of the second boosting current supply terminal differently for each channel position of the display drive IC.

[0011] In at least one embodiment of the present invention, the second boosting current supply stage includes first and second current source transistors, and the timing controller can control the amount of current supplied to the common source stage of the main source amplifier circuit by applying a bias to the gate nodes of the first and second current source transistors.

[0012] In at least one embodiment of the present invention, the current supply time can be set within a range of 50 ns to 500 ns.

[0013] In at least one embodiment of the present invention, a toggle circuit in which an N-type transistor and a P-type transistor are connected in parallel may be arranged between a terminal to which the first differential input voltage is input and the gates of the first and second comparison transistors.

[0014] A method for controlling a slew boost circuit according to embodiments of the present invention may include a step of comparing a first differential input voltage and a second differential input voltage and generating a current, a step of mirroring the generated current when the current is generated and supplying the current to the main source amplifier circuit, and a step of additionally supplying current to the main source amplifier circuit based on an operation of a timing controller.

[0015] In the method of at least one embodiment of the present invention, the step of generating the current may include a step of causing current to flow to the first comparison transistor when the first differential input voltage rises, and a step of causing current to flow to the second comparison transistor when the first differential input voltage falls.

[0016] In at least one embodiment of the method of the present invention, the step of mirroring the generated current and supplying the current to the main source amplifier circuit may include the step of supplying the mirrored current to a common source terminal and / or a common gate terminal of the main source amplifier circuit.

[0017] In at least one embodiment of the method of the present invention, the timing controller is synchronized to a change point in time of the first differential input voltage and can set a current supply time of the second boosting current supply terminal differently for each channel position of the display drive IC.

[0018] In at least one embodiment of the method of the present invention, the current supply time can be set within a range of 50 ns to 500 ns.

[0019] The present invention, according to at least one embodiment, can effectively compensate for slew rate deviation between the Center channel and the Edge channel of a display driver IC. This can improve the overall signal transmission characteristics of a display by maintaining uniform signal quality in both the Center and Edge channels of the display driver IC.

[0020] The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary skill in the art to which the present invention belongs from the description below.

[0021] FIG. 1 is a drawing of a display device configuration according to one embodiment of the present invention.

[0022] FIG. 2 is a diagram of a data drive device configuration according to one embodiment of the present invention.

[0023] FIG. 3 is a block diagram of a differential amplifier according to one embodiment of the present invention.

[0024] FIG. 4 is a diagram of a main source amplifier circuit configuration according to one embodiment of the present invention.

[0025] FIG. 5 is a diagram of a slew boost circuit according to one embodiment of the present invention.

[0026] FIG. 6 is a diagram showing the effect of a slew boost circuit according to one embodiment of the present invention.

[0027] The present invention is susceptible to various modifications and embodiments. Specific embodiments are illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0028] The suffixes "module" and "part" used in this specification are used only for nominal distinction between components and should not be construed as implying that they are or can be physically or chemically distinguished or separated.

[0029] Terms containing ordinal numbers, such as "first" and "second," may be used to describe various components, but these components are not limited by these terms. These terms may only be used in a nominal sense to distinguish one component from another, and their ordinal meaning is determined not from the names but from the context of the description.

[0030] The term "and / or" is used to include any combination of the multiple items it refers to. For example, "A and / or B" means all three cases, "A," "B," "A and B."

[0031] When it is said that a component is "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0032] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0033] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0034] Additionally, the terms unit, control unit, control device, or controller are merely terms widely used to name devices that control the corresponding function, and do not imply a generic function unit. For example, a device by these names may include a communication device that communicates with other controllers or sensors to control the corresponding function, a computer-readable recording medium that stores an operating system or logic commands and input / output information, and one or more processors that perform judgments, calculations, decisions, etc. necessary for controlling the corresponding function.

[0035] Meanwhile, a processor may include semiconductor integrated circuits and / or electronic components that perform at least one or more of comparison, judgment, calculation, and decision-making to achieve a programmed function. For example, the processor may be any one or a combination of a computer, a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), and electronic circuitry (logic circuits).

[0036] The processor may be electrically connected to memory, and the processor may be able to retrieve and write data from the memory. The memory and processor may be integrated or physically separate.

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0038] FIG. 1 is a drawing of a display device configuration according to one embodiment of the present invention.

[0039] Referring to FIG. 1, the display device (100) may include a display panel (120), a data processing device (130), a gate driving device (140), and a data driving device (110).

[0040] The display panel (120) may be a liquid crystal display (LCD) panel or a self-light emitting element panel such as an organic light emitting diode (OLED) panel.

[0041] When the display panel (120) is a liquid crystal display panel, the display panel (120) may include a backlight, a liquid crystal, and a common electrode, and a pixel electrode and a driving transistor may be arranged in each pixel. When a scan signal is supplied to the gate of the driving transistor, the driving transistor may be turned on, and a data voltage may be supplied to the pixel electrode. Then, an electric field is formed between the pixel electrode and the common electrode according to the data voltage, and the alignment direction of the liquid crystal is changed, and accordingly, the transmittance of light supplied from the backlight is changed, and the brightness of the pixel may be adjusted.

[0042] A plurality of data lines (DL) and a plurality of gate lines (GL) may be arranged in a matrix form on the display panel (120). The data lines (DL) may be connected to the source terminal of the driving transistor of each pixel, and the gate lines (GL) may be connected to the gate terminal of the driving transistor of each pixel. When a scan signal (SCN) is supplied to the gate lines (GL), the driving transistor is turned on, allowing the data voltage (VD) supplied through the data lines (DL) to be transmitted to the pixel electrode.

[0043] A parasitic capacitor may be formed on the data line (DL). The parasitic capacitor may be formed between the data line (DL) and the common electrode or between the data line (DL) and the pixel electrode. From the perspective of the data driving device (110) that supplies the data voltage (VD), the parasitic capacitor may be recognized as a load. The larger the capacity of the parasitic capacitor, the more power the data driving device (110) must supply to the data line (DL).

[0044] The display panel (120) may be a self-luminous element panel, such as an OLED panel. In addition to an OLED panel, the self-luminous element panel may also utilize other types of self-luminous elements, such as a micro LED panel.

[0045] Each pixel of an OLED panel may include a scan transistor, a driving transistor, and an OLED. When a scan signal (SCN) is supplied to the gate of the scan transistor, the scan transistor is turned on, and a data voltage (VD) can be supplied to the driving transistor through the scan transistor. In an OLED panel, the data voltage (VD) can be supplied to the gate of the driving transistor. Depending on the size of the data voltage (VD), the size of the conduction current of the driving transistor is determined, and depending on the size of the conduction current of the driving transistor, the brightness of the OLED connected to the driving transistor can be controlled.

[0046] A plurality of data lines (DL) and a plurality of gate lines (GL) may be arranged in a matrix form on the display panel (120). The data lines (DL) may be connected to the source terminal of the scan transistor of each pixel, and the gate lines (GL) may be connected to the gate terminal of the source transistor of each pixel. When a scan signal (SCN) is supplied to the gate lines (GL), the scan transistor is turned on, allowing the data voltage (VD) supplied through the data lines (DL) to be transmitted to the driving transistor.

[0047] A parasitic capacitor may be formed on the data line (DL). The parasitic capacitor may be formed between the data line (DL) and the cathode electrode of the OLED, or between the data line (DL) and the anode electrode of the OLED. From the perspective of the data driving device (110) that supplies the data voltage (VD), the parasitic capacitor may be recognized as a load. The larger the capacity of the parasitic capacitor, the more power the data driving device (110) must supply to the data line.

[0048] The data processing device (130) can receive image data from an external device, for example, a host or a device called an AP (Application Processor). Then, the data processing device (130) can convert the image data in the format of the external device into image data (RGB) in a format that the data driving device (110) can process. Then, the data processing device (130) can transmit the converted image data (RGB) to the data driving device (110).

[0049] Image data (RGB) may include pixel data representing a grayscale value for each pixel (P). The pixel data for one pixel (P) may be, for example, data having 8 bits and may express a grayscale value from 0 to 255. The data processing device (130) may generate pixel data for each pixel and include the pixel data in the image data (RGB) to transmit it to the data driving device (110).

[0050] The data processing device (130) can transmit control signals to devices involved in driving the display panel, for example, the data driving device (110) and the gate driving device (140). The data processing device (130) can transmit a data control signal (DCS) to the data driving device (110) and a gate control signal (GCS) to the gate driving device (140).

[0051] Control signals (DCS, GCS) may include configuration information for each device. For example, the data processing unit (130) may receive configuration information from an external device, confirm the configuration information for each device, and then transmit the configuration information by including it in the corresponding control signal (DCS or GCS).

[0052] Control signals (DCS, GCS) may include timing signals for controlling each device. The timing signals may be, for example, vertical synchronization signals (Vsync), horizontal synchronization signals (Hsync), etc. The data driving device (110) or gate driving device (140) may distinguish frames and each horizontal time according to the timing signals. In terms of controlling the timing of each device, the data processing device (130) is also referred to as a timing controller.

[0053] The gate driving device (140) can supply a scan signal (SCN) to pixels (P) arranged on the display panel (120). Then, pixels supplied with a scan signal (SCN) indicating turn-on can be selected, and a data voltage (VD) can be supplied to the selected pixels.

[0054] The gate driving device (140) can supply a scan signal (SCN) through a gate line (GL). A plurality of gate lines (GL) can be arranged on the display panel (120). And, each gate line (GL) can be connected to pixels (P) arranged in a row in one direction—for example, a horizontal direction. The gate driving device (140) can supply a scan signal (SCN) that instructs to turn on one of the plurality of gate lines (GL), and pixels (P) connected to the corresponding gate line (GL) can be selected. The gate driving device (140) can supply a scan signal (SCN) that instructs to turn on while changing the gate line (GL) every horizontal time.

[0055] The data driving device (110) can drive pixels (P) arranged on the display panel (120).

[0056] The data driving device (110) can receive image data (RGB) from the data processing device (130). In addition, the data driving device (110) can check pixel data for each pixel (P) included in the image data (RGB), generate a data voltage (VD) corresponding to the pixel data, and supply the data voltage (VD) to each pixel (P).

[0057] Pixel data can represent a grayscale value for each pixel (P), and the data driving device (110) can generate a data voltage (VD) corresponding to this grayscale value.

[0058] Pixel data is stored in the latch circuit of the data driving device (110) and can be output in the form of a digital signal. In addition, the data driving device (110) can convert the digital signal into an analog voltage using gamma reference voltages.

[0059] There is a difference between the gradation corresponding to physical brightness and the gradation corresponding to brightness perceived by humans. Correcting this difference is called gamma conversion. When the data driving device (110) converts a digital signal into an analog voltage, it can also apply gamma conversion simultaneously. For example, the data driving device (110) can apply digital-to-analog conversion and gamma conversion simultaneously by using the voltages used for digital-to-analog conversion as voltages to which gamma conversion is applied—gamma reference voltages.

[0060] The analog voltage may not be suitable for driving the pixel (P) due to its low power level. Therefore, the data driving device (110) can amplify the analog voltage to generate a data voltage (VD) and supply the data voltage (VD) with a relatively high power level to the pixel (P).

[0061] FIG. 2 is a diagram of a data drive device configuration according to one embodiment of the present invention.

[0062] Referring to FIG. 2, the data driving device (110) may include a channel circuit (210) and a gamma reference voltage generation circuit (230).

[0063] The channel circuit (210) may include a latch circuit (211), a level shifter (212), a digital-to-analog converter (DAC, 213), and a buffer circuit (214), and may receive pixel data (PXD) corresponding to the grayscale value of a pixel, generate a data voltage (VD), and supply the data voltage (VD) to a data line connected to the pixel.

[0064] The latch circuit (211) can sequentially store pixel data (PXD) received through the data bus line.

[0065] The latch circuit (211) may have two latches inside. The first latch may store pixel data to be output at the next horizontal time, and the second latch may store pixel data to be output at the current horizontal time. When the next horizontal time arrives, the first latch may store pixel data to be output at the next horizontal time, and the pixel data stored in the first latch may be moved to and stored in the second latch.

[0066] The output timing of the latch circuit (211) can be determined based on the latch output signal generated at each horizontal time. The latch output signal can be synchronized with the horizontal synchronization signal. Alternatively, the latch output signal can be a signal with a different phase from the horizontal synchronization signal but the same period length.

[0067] The latch circuit (211) can transfer pixel data (PXD) stored in the latch circuit (211) to the level shifter (212) according to the latch output signal.

[0068] The level shifter (212) can convert pixel data (PXD) into a digital signal (DS). The level shifter (212) can increase the signal level while converting pixel data (PXD) into a digital signal (DS).

[0069] Pixel data (PXD) may be a signal with a low voltage or power level. The level shifter (212) may convert the pixel data (PXD) into a digital signal (DS) with a high voltage or power level.

[0070] The DAC (213) can receive a digital signal (DS) and drive the gates of the internal switches. In addition, the DAC (213) can convert the digital signal (DS) into an analog voltage (AS) by driving the gates of the switches.

[0071] The DAC (213) may include a plurality of switches. Depending on the on / off state of the switches, the switches may selectively connect one of a plurality of gamma reference voltage lines, from which a plurality of gamma reference voltages are supplied, to an output. The voltage formed on the selected gamma reference voltage line may be an analog voltage (AS). A digital signal (DS) may be supplied to the gates of the switches to change the on / off states of the switches.

[0072] A digital signal (DS) can be supplied to drive the gates of the switches. The digital signal (DS) is output by the level shifter (212), and from this perspective, the gate load of the switches can become part of the output load of the level shifter (212).

[0073] The data drive device (110) may include a gamma reference voltage generation circuit (230) that supplies gamma reference voltages (VGM) to the DAC (213).

[0074] The channel circuit (210) may include a buffer circuit (214) placed between the output of the DAC (213) and the pixel.

[0075] The buffer circuit (214) can amplify the output of the DAC (213) and supply it to a data line connected to a pixel. The buffer circuit (214) can amplify an analog voltage (AS) to generate a data voltage (VD) and supply the data voltage (VD) to the data line.

[0076] The buffer circuit (214) may include a differential amplifier for amplifying the analog voltage (AS) into a data voltage (VD).

[0077] The differential amplifier may be a rail-to-rail Class-A type amplifier. The buffer circuit (214) may generate a data voltage (VD) by amplifying an analog voltage (AS) using such a differential amplifier.

[0078] Differential amplifiers can be configured with a buffer structure, allowing their input and output to be connected. For example, the output terminal of a differential amplifier can be connected to the negative input terminal of the differential amplifier. Furthermore, an analog voltage (AS) can be supplied to the positive input terminal of the differential amplifier.

[0079] FIG. 3 is a block diagram of a differential amplifier according to one embodiment of the present invention.

[0080] Referring to FIG. 3, the differential amplifier may include a main source amplification circuit (300) and a boosting circuit (400).

[0081] The boosting circuit (400) may include a comparator (420), a first boosting current supply terminal (430), a second boosting current supply terminal (440), and a timing control terminal (450).

[0082] The comparator (420) receives the analog voltage (AS), which is the output voltage of the DAC, as an input signal, and receives the output value, which is the voltage generated by amplification, as another input signal, and can compare the voltage levels of the two signals. If there is a difference in the voltage levels of the two signals, current flows to the first boosting current supply terminal (430), and this current can be mirrored by the first and second mirror circuits of the first boosting current supply terminal (430) and supplied to the main source amplification circuit unit (300).

[0083] The second boosting current supply terminal (440) is connected in parallel with the first boosting current supply terminal (430) and can supply current to the main source amplifier circuit (300) based on the operation of the timing control terminal (450).

[0084] The timing control unit (450) can control the operating time of the second boosting current supply unit (440) by synchronizing with the timing of the input signal fluctuation. In addition, the operating time can be set according to the position of each channel of the display drive IC.

[0085] Details of the main source amplification circuit (300) and the boosting circuit (400) will be described with reference to FIGS. 4 and 5.

[0086] FIG. 4 is a diagram of a main source amplifier circuit configuration according to one embodiment of the present invention.

[0087] Referring to FIG. 4, the main source amplifier circuit (300) may include a first circuit stage (310), a second circuit stage (321), a third circuit stage (322), a fourth circuit stage (330), and a fifth circuit stage (340).

[0088] The first circuit stage (310) is a circuit that generates differential currents according to differential input voltages and may be referred to as an input circuit stage. Hereinafter, the first circuit stage (310) will be referred to as an input circuit stage (310) and an embodiment will be described.

[0089] The second circuit stage (321) may be a circuit that controls the gate voltage of the first output stage transistor (MPO) according to the first differential currents generated in the input circuit stage (310), and the third circuit stage (322) may be a circuit that controls the gate voltage of the second output stage transistor (MNO) according to the second differential currents generated in the input circuit stage (310). The second circuit stage (321) and the third circuit stage (322) have the form of current mirror circuits, so that the two circuits may be combined and referred to as current mirror circuit stages (321, 322), and the second circuit stage (321) may be referred to as the first current mirror circuit, and the third circuit stage (322) may be referred to as the second current mirror circuit. Hereinafter, an embodiment will be described while referring to the second circuit stage (321) as the first current mirror circuit (321), and the third circuit stage (322) as the second current mirror circuit.

[0090] The fourth circuit unit (330) is a circuit that provides bias current and may be referred to as a bias circuit unit. Hereinafter, the fourth circuit unit (330) will be referred to as a bias circuit unit (330) and an embodiment will be described.

[0091] The fifth circuit stage (340) may include a first output stage transistor (MPO) positioned between the first voltage rail (DDVDH) and the output stage (OT) and a second output stage transistor (MNO) positioned between the second voltage rail (AVSS) and the output stage (OT). The fifth circuit stage (340) may be referred to as an output circuit stage as a circuit including the output stage (OT). Hereinafter, the fifth circuit stage (340) will be described in an embodiment while referring to it as an output circuit stage (340).

[0092] In the main source amplifier circuit (300), the input circuit stage (310), current mirror circuit stage (321, 322), bias circuit stage (330), and output circuit stage (340) can form a rail-to-rail Class-A amplifier.

[0093] The main source amplifier circuit (300) may include a first voltage rail to which a high driving voltage (DDVDH) is supplied and a second voltage rail to which a low driving voltage (AVSS) is supplied. In addition, the input circuit (310), the current mirror circuit (321, 322), and the output circuit (340) may have one side connected to the first voltage rail and the other side connected to the second voltage rail.

[0094] The main source amplifier circuit (300) can receive differential input voltages (IP, IM) and supply an output voltage (OT) to the outside. In the main source amplifier circuit (300), a first differential input voltage (IP) can be input through a first input terminal, and a second differential input voltage (IM) can be input through a second input terminal. In addition, an output voltage (OT) can be supplied to the outside through an output terminal from the main amplifier (300). For convenience of explanation, the reference symbol IP can be used to refer to the first differential input voltage and can be used to refer to the first input terminal. In addition, the reference symbol IM can be used to refer to the second differential input voltage and can be used to refer to the second input terminal. In addition, the reference symbol OT can be used to refer to the output voltage and can be used to refer to the output terminal. And, the first differential input voltage (IP) may be referred to as a positive input voltage, and the first input terminal may be referred to as a positive input terminal. The second differential input voltage (IM) may be referred to as a negative input voltage, and the second input terminal may be referred to as a negative input terminal.

[0095] When the main source amplifier circuit (300) functions as a buffer, the minus input terminal can be connected to the output terminal. And, the output voltage (OT) can follow the waveform of the first differential input voltage (IP).

[0096] The speed at which the output voltage (OT) follows the waveform of the first differential input voltage (IP) may vary depending on the slew rate of the main source amplifier circuit (300). According to one embodiment, the main source amplifier circuit (300) can improve the slew rate of the main source amplifier circuit (300) by additionally supplying dynamic current through the boosting circuit (400). The dynamic current may be generated in response to fluctuations in differential input voltages (particularly, the first differential input voltage (IP)). For example, the dynamic current may be generated when the first differential input voltage (IP) has a rising waveform or a falling waveform. The dynamic current may not be generated when the differential input voltages (particularly, the first differential input voltage (IP)) are in a static state. For example, the dynamic current may not be generated when the first differential input voltage (IP) is maintained at a constant level. According to this structure, the main source amplifier circuit (300) can improve the slew rate without additionally consuming static power.

[0097] The output circuit unit (340) may include a first output stage transistor (MPO) arranged between the first voltage rail and the output stage, and a second output stage transistor (MNO) arranged between the second voltage rail and the output stage, and the slew rate of the main source amplifier circuit unit (300) may be greatly affected by the magnitude of the current that charges and discharges the gates of the first output stage transistor (MPO) and the second output stage transistor (MNO). For example, when the voltage of the gate is increased or decreased in order to adjust the magnitude of the current flowing to the first output stage transistor (MPO) and the second output stage transistor (MNO) in response to the dynamic waveform of the first differential input voltage (IP), if the current that charges and discharges the gate is large, the fluctuation of the current flowing to the first output stage transistor (MPO) and the second output stage transistor (MNO) may increase, so that the slew rate may be improved.

[0098] According to one embodiment, the main source amplifier circuit (300) may have a structure in which an additional dynamic current is supplied in response to fluctuations in differential input voltages, and this dynamic current increases the current that charges and discharges the gates of the first output stage transistor (MPO) and the second output stage transistor (MNO).

[0099] The current for charging and discharging the first output stage transistor (MPO) and the second output stage transistor (MNO) can be affected by the current of the input circuit stage (310) and the current of the current mirror circuit stage (321, 322), and the main source amplifier circuit unit (300) can increase the current for charging and discharging the first output stage transistor (MPO) and the second output stage transistor (MNO) by additionally supplying dynamic current to the input circuit stage (310) and / or the current mirror circuit stage (321, 322).

[0100] The input circuit (310) may include a first differential amplifier circuit (311) and a second differential amplifier circuit (312).

[0101] The first differential amplifier circuit (311) may include a first N-type transistor (MN1) and a second N-type transistor (MN2) having a common source structure. In addition, the sources of the first N-type transistor (MN1) and the second N-type transistor (MN2) may be connected to a second voltage rail to which a driving low voltage (AVSS) is supplied through a third N-type transistor (MN3).

[0102] A bias voltage can be supplied to the gate of the third N-type transistor (MN3), and depending on this bias voltage, the third N-type transistor (MN3) can function as a bias current source.

[0103] A first differential input voltage (IP) can be supplied to the gate of the first N-type transistor (MN1), and a second differential input voltage (IM) can be supplied to the gate of the second N-type transistor (MN2).

[0104] When the first differential input voltage (IP) increases, more current can flow to the first N-type transistor (MN1). When more current flows to the first N-type transistor (MN1), more current can flow to the first output transistor (MPO) and less current can flow to the second output transistor (MNO), causing the output voltage (OT) to increase. In addition, when the first input voltage (IP) decreases, less current can flow to the first N-type transistor (MN1). When less current flows to the first N-type transistor (MN1), less current can flow to the first output transistor (MPO) and more current can flow to the second output transistor (MNO), causing the output voltage (OT) to decrease.

[0105] The second differential amplifier circuit (312) may include a first P-type transistor (MP1) and a second P-type transistor (MP2) having a common source structure. In addition, the sources of the first P-type transistor (MP1) and the second P-type transistor (MP2) may be connected to a first voltage rail to which a driving high voltage (DDVDH) is supplied through a third P-type transistor (MP3).

[0106] A bias voltage can be supplied to the gate of the third P-type transistor (MP3), and depending on this bias voltage, the third P-type transistor (MP3) can function as a bias current source.

[0107] A first differential input voltage (IP) can be supplied to the gate of the first P-type transistor (MP1), and a second differential input voltage (IM) can be supplied to the gate of the second P-type transistor (MP2).

[0108] When the first differential input voltage (IP) increases, less current may flow to the first P-type transistor (MP1). When less current flows to the first P-type transistor (MP1), more current may flow to the first output transistor (MPO) and less current may flow to the second output transistor (MNO), causing the output voltage (OT) to increase. In addition, when the first input voltage (IP) decreases, more current may flow to the first P-type transistor (MP1). When more current flows to the first P-type transistor (MP1), less current may flow to the first output transistor (MPO) and more current may flow to the second output transistor (MNO), causing the output voltage (OT) to decrease.

[0109] The current mirror circuit (321, 322) may include a first current mirror circuit (321) and a second current mirror circuit (322).

[0110] The first current mirror circuit (321) may include a first reference current transistor (MP4) and a first mirroring current transistor (MP5).

[0111] The first current mirror circuit (321) may have a common gate structure. The gate of the first reference current transistor (MP4) may be connected to the gate of the first mirroring current transistor (MP5).

[0112] The first current mirror circuit (321) may be connected on one side to a first voltage rail to which a driving high voltage (DDVDH) is supplied. The source of the first reference current transistor (MP4) and the source of the first mirroring current transistor (MP5) may be connected to the first voltage rail.

[0113] A first reference current can flow through the first reference current transistor (MP4), and a mirroring current for the first reference current can flow through the first mirroring current transistor (MP5).

[0114] A first additional transistor circuit having a common gate structure may be arranged on the drain of the first reference current transistor (MP4) and the drain of the first mirroring current transistor (MP5).

[0115] The first additional transistor circuit may include a first additional transistor (MP6) connected to the drain of the first reference current transistor (MP4) and a second additional transistor (MP7) connected to the drain of the first mirroring current transistor (MP5). The first additional transistor (MP6) may perform an additional function, such as limiting the amount of current flowing to the first reference current transistor (MP4), and the second additional transistor (MP7) may perform an additional function, such as limiting the amount of current flowing to the first mirroring current transistor (MP5).

[0116] To form a current mirror circuit, the gate and drain of the first reference current transistor (MP4) may be electrically connected. In normal operation, the first additional transistor (MP6) and the second additional transistor (MP7) may operate as a bypass circuit, so the gate of the first reference current transistor (MP4) and the drain of the first additional transistor (MP6) may be connected.

[0117] In the first differential amplifier circuit (311) of the input circuit (310), the drain of the first N-type transistor (MN1) may be connected to the drain of the first mirroring current transistor (MP5). In addition, in the first differential amplifier circuit (311), the drain of the second N-type transistor (MN2) may be connected to the drain of the first reference current transistor (MP4).

[0118] The second current mirror circuit (322) may include a second reference current transistor (MN4) and a second mirroring current transistor (MN5). The second current mirror circuit (322) may have a common gate structure. The gate of the second reference current transistor (MN4) may be connected to the gate of the second mirroring current transistor (MN5).

[0119] The second current mirror circuit (322) may be connected on one side to a second voltage rail to which a driving low voltage (AVSS) is supplied. The source of the second reference current transistor (MN4) and the source of the second mirroring current transistor (MN5) may be connected to the second voltage rail.

[0120] A second reference current can flow through the second reference current transistor (MN4), and a mirroring current for the second reference current can flow through the second mirroring current transistor (MN5).

[0121] A second additional transistor circuit having a common gate structure may be arranged on the drain of the second reference current transistor (MN4) and the drain of the second mirroring current transistor (MN5).

[0122] The second additional transistor circuit may include a third additional transistor (MN6) connected to the drain of the second reference current transistor (MN4) and a fourth additional transistor (MN7) connected to the drain of the second mirroring current transistor (MN5). The third additional transistor (MN6) may perform an additional function, such as limiting the amount of current flowing to the second reference current transistor (MN4), and the fourth additional transistor (MN7) may perform an additional function, such as limiting the amount of current flowing to the second mirroring current transistor (MN5).

[0123] To form a current mirror circuit, the gate and drain of the second reference current transistor (MN4) may be electrically connected. In normal operation, the third additional transistor (MN6) and the fourth additional transistor (MN7) may operate as a bypass circuit, so the gate of the second reference current transistor (MN4) and the drain of the third additional transistor (MN6) may be connected.

[0124] In the second differential amplifier circuit (312) of the input circuit (310), the drain of the first P-type transistor (MP1) may be connected to the drain of the second mirroring current transistor (MN5). In addition, in the second differential amplifier circuit (312), the drain of the second P-type transistor (MP2) may be connected to the drain of the second reference current transistor (MN4).

[0125] A bias circuit (330) may be placed between the first current mirror circuit (321) and the second current mirror circuit (322).

[0126] The bias circuit (330) may include a first bias circuit and a second bias circuit.

[0127] The first bias circuit may have a structure in which one N-type transistor (MN8) and one P-type transistor (MP8) are connected in parallel. The bias current supplied by the first bias circuit may be determined according to the bias voltage supplied to the gates of one N-type transistor (MN8) and one P-type transistor (MP8).

[0128] The second bias circuit may have a structure in which another N-type transistor (MN9) and another P-type transistor (MP9) are connected in parallel. The bias current supplied by the second bias circuit may be determined depending on the bias voltage supplied to the gates of the other N-type transistor (MN9) and the other P-type transistor (MP9).

[0129] The first bias circuit can form a single current path by being electrically connected to the first reference current transistor (MP4) of the first current mirror circuit (321) and the second reference current transistor (MN4) of the second current mirror circuit (322). This path can be called a reference current path. In the reference current path, the first bias current basically formed by the first bias circuit can flow through the first voltage rail, the first reference current transistor (MP4) and the first bias circuit to the second voltage rail through the second reference current transistor (MN4).

[0130] The second bias circuit may be electrically connected to the first mirroring current transistor (MP5) of the first current mirror circuit (331) and the second mirroring current transistor (MN5) of the second current mirror circuit (322) to form another current path. This path may be referred to as a mirroring current path. In the mirroring current path, the second bias current basically formed by the second bias circuit may flow through the first voltage rail, the first mirroring current transistor (MP5), and the second bias circuit to the second voltage rail through the second mirroring current transistor (MN5).

[0131] In the output circuit (340), the first output transistor (MPO) may have a source connected to the first voltage rail and a drain connected to the output terminal (OT). In addition, the gate of the first output transistor (MPO) may be connected to the contact node of the second bias circuit and the first current mirror circuit (321) in the mirroring current path.

[0132] In the output circuit (340), the second output transistor (MNO) may have a source connected to the second voltage rail and a drain connected to the output terminal (OT). In addition, the gate of the second output transistor (MNO) may be connected to the contact node of the second bias circuit and the second current mirror circuit (322) in the mirroring current path.

[0133] The input circuit (310) can generate differential currents according to differential input voltages (IP, IM). In addition, the current mirror circuit (321, 322) can control the gate voltages of the first output transistor (MPO) and the second output transistor (MNO) according to the differential currents. In addition, the boosting circuit (400) can supply additional dynamic current to the input circuit (310) or additional dynamic current to the current mirror circuit (321, 322) in response to changes in the differential input voltages (IP, IM), thereby improving the slew rate of the main source amplifier circuit (300).

[0134] The boosting circuit unit (400) can supply dynamic current to the input circuit unit (310). The input circuit unit (310) can include differential amplifier circuits having a common source structure and having differential input voltages (IP, IM) input to the gates, and the boosting circuit unit (400) can supply dynamic current to the common source terminal of these differential amplifier circuits. For example, the boosting circuit unit (400) can supply dynamic current to the common source terminal (CSN) of the first differential amplifier circuit (311) or to the common source terminal (CSP) of the second differential amplifier circuit (312).

[0135] The boosting circuit unit (400) can supply dynamic current to the current mirror circuit units (321, 322). The current mirror circuit units (321, 322) can include current mirror circuits having a common gate structure, and the boosting circuit unit (400) can supply dynamic current to the common gate terminal of these current mirror circuits. For example, the boosting circuit unit (400) can supply dynamic current to the common gate terminal (HPC) of the first current mirror circuit (321) or the common gate terminal (HNC) of the second current mirror circuit (322).

[0136] The current mirror circuit (321, 322) may include a reference current path through which a reference current flows and a mirroring current path through which a mirroring current flows, and the boosting circuit (400) may supply current. For example, the boosting circuit (400) may supply a dynamic current to the common gate terminal (HPC) of the first current mirror circuit (321), and this dynamic current may flow into the reference current path through the drain of the first reference current transistor (MP4). As another example, the boosting circuit (400) may supply a dynamic current to the common gate terminal (HNC) of the second current mirror circuit (322), and this dynamic current may flow into the reference current path through the drain of the second reference current transistor (MN4).

[0137] FIG. 5 is a diagram of a slew boost circuit according to one embodiment of the present invention.

[0138] Referring to FIG. 5, the boosting circuit unit (400) includes a toggle circuit unit (410), a comparator (420), a first boosting current supply unit (430), a second boosting current supply unit (440), and a timing control unit (450).

[0139] The comparator (420) may include a first comparison transistor (TN2) and a second comparison transistor (TP2) having a first differential input voltage (IP) connected to a gate and a second differential input voltage (IM) connected to a source.

[0140] The boosting circuit (400) can generate and supply dynamic current according to the current flowing through the first comparison transistor (TN2) and the second comparison transistor (TP2).

[0141] The first comparison transistor (TN2) may be an N-type transistor. If the first differential input voltage (IP) and the second differential input voltage (IM) maintain similar voltage levels, current may not flow to the first comparison transistor (TN2). Then, if the first differential input voltage (IP) rises (has a rising waveform), current may flow to the first comparison transistor (TN2). The first comparison transistor (TN2) may be connected to the first boosting current supply terminal (430).

[0142] The first boosting current supply terminal (430) can mirror the current flowing to the first comparison transistor (TN2) through the first mirror circuit (431) and supply the mirrored current to the common source terminal (CSP) of the second differential amplifier circuit (312) and / or the common gate terminal (HNC) of the second current mirror circuit (322).

[0143] In the first mirror circuit (431), the current flowing in the first comparison transistor (TN2) flows to the P-type transistor (TP3), and the current flowing in the P-type transistor (TP3) can be mirrored to the other P-type transistor (TP4) and the other P-type transistor (TP5). In addition, the current flowing in the other P-type transistor (TP4) can be supplied to the common source terminal (CSP) of the second differential amplifier circuit (312), and the current flowing in the other P-type transistor (TP5) can be supplied to the common gate terminal (HNC) of the second current mirror circuit.

[0144] The second comparison transistor (TP2) may be a P-type transistor. When the first differential input voltage (IP) and the second differential input voltage (IM) maintain similar voltage levels, current may not flow to the second comparison transistor (TP2). Then, when the first differential input voltage (IP) decreases (has a falling waveform), current may flow to the second comparison transistor (TP2). The second comparison transistor (TP2) may be connected to the first boosting current supply terminal (430).

[0145] The first boosting current supply terminal (430) can mirror the current flowing to the second comparison transistor (TP2) through the second mirror circuit (432) and supply the mirrored current to the common source terminal (CSN) of the first differential amplifier circuit (311) and / or the common gate terminal (HPC) of the first current mirror circuit.

[0146] In the second mirror circuit (432), the current flowing in the second comparison transistor (TP2) flows to the N-type transistor (TN3), and the current flowing in the N-type transistor (TN3) can be mirrored to the other N-type transistor (TN4) and the other N-type transistor (TN5). In addition, the current flowing in the other N-type transistor (TN4) can be supplied to the common gate terminal (HPC) of the first current mirror circuit, and the current flowing in the other N-type transistor (TN5) can be supplied to the common source terminal (CSN) of the first differential amplifier circuit.

[0147] The boosting circuit (400) may further include a second boosting current supply terminal (440) and a timing control terminal (450).

[0148] The second boosting current supply terminal (440) is connected in parallel with the first boosting current supply terminal (430), and can supply current to the common source terminal (CSN) of the first differential amplifier circuit of the main source amplifier circuit (300) or the common source terminal (CSP) of the second differential amplifier circuit based on the operation of the timing control terminal (450).

[0149] The second boosting current supply terminal (440) may include a first current source transistor (TP6), which is a P-type transistor capable of generating current, and a second current source transistor (TN6), which is an N-type transistor, and the current generated from the first current source transistor (TP6) may be supplied to a common source terminal (CSP) of a second differential amplifier circuit of the main source amplifier circuit unit (300), and the current generated from the second current source transistor (TN6) may be supplied to a common source terminal (CSN) of a first differential amplifier circuit of the main source amplifier circuit unit (300).

[0150] The timing control unit (450) controls the operating time of the second boosting current supply unit (440) in synchronization with the change timing of the first differential input voltage (IP) signal, and can set the operating time according to the position of each channel of the display driver IC. In addition, the timing control unit (450) can save energy and improve signal quality by supplying current through the second boosting current supply unit only at the necessary timing according to the rising / falling signal.

[0151] The timing control unit (450) controls a switch included in the second boosting current supply unit according to the position of each channel of the display drive IC, and applies a bias to the gate nodes of the first current source transistor (TP6) and the second current source transistor (TN6) to control the amount of current while supplying current to the main source amplifier circuit unit (300). This enables a stable output waveform to be obtained even at a low slew rate.

[0152] The boosting circuit (400) may further include a toggle circuit (410) in which an N-type transistor (TN1) and a P-type transistor (TP1) are connected in parallel. The toggle circuit (410) may be arranged between a terminal to which a first differential input voltage (IP) is input and the gates of the comparison transistors (TN2, TP2). The boosting circuit (400) may control the voltage supplied to the gate of the toggle circuit (410) to turn off the toggle circuit (410) and prevent dynamic current from being supplied.

[0153] FIG. 6 is a diagram showing the effect of a slew boost circuit according to one embodiment of the present invention.

[0154] Referring to Fig. 6 (a), these are waveforms of an input signal and an output signal when the input voltage rises (rising) in the Edge channel of the display driver IC. The x-axis represents time (us), and the y-axis represents voltage (V). It can be seen that when the input voltage rises (rising) in the Edge channel of the display driver IC, the output signal rises later than the input signal. It can be seen that the output signal of the present invention is output closer to the input signal than the output signal of the comparative example. (Here, the comparative example refers to the case of a conventional slew boost circuit.) This shows that the stability of the output waveform can be secured in the conventional slew boost circuit even at a low slew rate in the Edge channel of the display driver IC.

[0155] Referring to Fig. 6 (b), this is a voltage graph when the input voltage falls (falling) in the Edge channel of the display driver IC. The x-axis represents time (us), and the y-axis represents voltage (V). It can be seen that when the input voltage falls (falling) in the Edge channel of the display driver IC, the output signal falls later than the input signal. It can be seen that the output signal of the present invention is generated closer to the input signal than the output signal of the comparative example. (Here, the comparative example refers to the case of the existing slew boost circuit.) This shows that the stability of the output waveform can be secured in the existing slew boost circuit even at a low slew rate in the Edge channel of the display driver IC.

[0156] It will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential characteristics thereof. Therefore, the above detailed description should not be construed as limiting in any respect, but rather as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the scope of equivalents of the present invention are intended to be included within the scope of the present invention.

[0157] The method according to the above-described embodiment can be produced as a program to be executed on a computer, and the program can be stored in a computer-readable recording medium, examples of which include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc., and also includes one implemented in the form of a carrier wave (e.g., transmission via the Internet).

[0158] Computer-readable recording media can be distributed across network-connected computer systems, allowing computer-readable code to be stored and executed in a distributed manner. Furthermore, functional programs, codes, and code segments for implementing the above-described method can be readily inferred by programmers skilled in the art to which the embodiments pertain.

[0159] It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit and essential characteristics of the present invention.

[0160] Accordingly, the above detailed description should not be construed as limiting in all respects, but rather as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are intended to be included within the scope of the present invention.

Claims

1. In a slew boost circuit that supplies current to the main source amplification circuit, A comparator that compares the first differential input voltage and the second differential input voltage and generates a current; A first boosting current supply unit that mirrors the generated current when the current is generated and supplies the current to the main source amplifier circuit; and A slew boost circuit comprising a second boosting current supply terminal for additionally supplying current to the main source amplifier circuit based on the operation of the timing controller.

2. In paragraph 1, The above comparator, It includes first and second comparison transistors, wherein the first differential input voltage is connected to the gate and the second differential input voltage is connected to the source, A slew boost circuit in which current flows to the first comparison transistor when the first differential input voltage rises, and in which current flows to the second comparison transistor when the first differential input voltage falls.

3. In paragraph 2, The first boosting current supply stage is It includes a mirror circuit that generates a mirroring current by mirroring the current flowing through the first and second comparison transistors, A slew boost circuit that supplies the above mirroring current to the common source terminal and / or the common gate terminal of the main source amplifier circuit.

4. In paragraph 1, The above timing controller, A slew boost circuit that is synchronized to the change point of the first differential input voltage and sets the current supply time of the second boosting current supply stage differently for each channel position of the display driver IC.

5. In paragraph 1, The above second boosting current supply unit is, A slew boost circuit comprising first and second switches, and supplying current to a common source terminal of the main source amplifier circuit section when the first and second switches are turned on.

6. In paragraph 1, The above second boosting current supply unit is, Contains first and second current source transistors, The above timing controller, A slew boost circuit that controls the amount of current supplied to the common source terminal of the main source amplifier circuit by applying a bias to the gate nodes of the first and second current source transistors.

7. In paragraph 4, The above current supply time is, Slew boost circuit configurable within the range of 50ns to 500ns.

8. In paragraph 2, A toggle circuit in which an N-type transistor and a P-type transistor are connected in parallel, A slew boost circuit arranged between a terminal to which the first differential input voltage is input and the gates of the first and second comparison transistors.

9. A control method for a slew boost circuit that supplies dynamic current to a main source amplifier circuit, A step of comparing a first differential input voltage and a second differential input voltage and generating a current; When the above current is generated, a step of mirroring the generated current and supplying the current to the main source amplifier circuit; and A slew boost circuit control method, comprising the step of additionally supplying current to the main source amplifier circuit based on the operation of the timing controller.

10. In paragraph 9, The step of generating the above current is: A slew boost circuit control method, comprising a step of causing current to flow to the first comparison transistor when the first differential input voltage rises, and causing current to flow to the second comparison transistor when the first differential input voltage falls.

11. In paragraph 9, The step of supplying the current to the main source amplifier circuit by mirroring the generated current is as follows. A slew boost circuit control method, comprising a step of supplying the mirrored current to a common source terminal and / or a common gate terminal of the main source amplifier circuit.

12. In paragraph 9, The above timing controller, A slew boost circuit control method, which is synchronized to the change point of the first differential input voltage and sets the current supply time of the second boosting current supply stage differently for each channel position of the display driver IC.

13. In paragraph 12, The above current supply time is, Slew boost circuit control method that can be set within the range of 50ns to 500ns.

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