Display device and manufacturing method therefor

Abstract

A display device and a manufacturing method therefor are provided. This display device includes a display panel and a circuit board bonded to the display panel. The display panel includes a substrate, a circuit layer, and an element layer. The circuit layer includes: first power lines disposed in a display area of the substrate; a power sensing line disposed in a non-display area of the substrate, extending from a first side of the edge of the display area to a sub-area of the substrate, and electrically connected to one of the first power lines; and a power sensing extension line electrically connected to the power sensing line and contacting one side of the edge of the sub-area.

Description

Display device and method for manufacturing the same

[0001] The present invention relates to a display device and a method for manufacturing the same.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, a light emitting display device, etc. Here, the light emitting display device may include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device including an ultra-small light emitting element.

[0004] Organic light-emitting diode (OLED) displays images using light-emitting elements, each containing a light-emitting layer of organic light-emitting material. Because OLED displays utilize self-luminous elements to display images, they can exhibit superior performance compared to other display devices in terms of power consumption, response speed, luminance efficiency, brightness, and viewing angle.

[0005] One side of the display device may include a display area where an image is displayed and a non-display area surrounding the display area. The display area may have light-emitting areas arranged therein that emit light with respective brightnesses and colors.

[0006] A method of manufacturing a display device may include a step of checking whether light-emitting elements arranged in light-emitting areas of a display area light up normally.

[0007] During the lighting inspection process, static electricity can be introduced through the pads connected to the test device's connectors. This can lead to a potential problem: the charge can be concentrated in relatively high-resistance areas of the wiring adjacent to the pads, potentially leading to short circuits.

[0008] In addition, there is a problem that the lifespan of the display device may be reduced because the insulating layers including inorganic insulating materials are lifted off at the point where a short circuit defect due to static electricity occurs, thereby causing a path for oxygen or moisture to penetrate.

[0009] Accordingly, the problem to be solved by the present invention is to provide a display device and a manufacturing method thereof capable of reducing short-circuit defects caused by static electricity introduced during lighting inspection.

[0010] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] A display device according to embodiments for solving the above problem includes a display panel and a circuit board bonded to the display panel. The display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate includes a main region and a sub-region protruding from one side of the main region. The main region includes a display region in which light-emitting regions are arranged and a non-display region disposed around the display region. The element layer includes light-emitting elements disposed in each of the light-emitting regions. The circuit layer includes light-emitting pixel drivers arranged in parallel in a first direction and a second direction and electrically connected to the light-emitting elements, first power wires arranged in the display area and extending in the second direction and transmitting first power to the light-emitting pixel drivers, a power detection wire arranged in the non-display area, facing the sub-area among the edges of the display area and extending from a first side adjacent to the sub-area to the sub-area, and electrically connected to one of the first power wires, and a power detection extension wire electrically connected to the power detection wire and in contact with one side of the edge of the sub-area.

[0012] The circuit layer may further include pads arranged in the sub-region and to which the circuit board is connected. The pads may include a power detection transmission pad electrically connected to the power detection wiring. The power detection wiring may be connected to one side of the power detection transmission pad. The power detection extension wiring may extend from the other side of the power detection transmission pad to one side of an edge of the sub-region.

[0013] The circuit layer may further include a power detection additional wiring that is disposed in the non-display area and extends from a second side of the edge of the display area opposite the first side to the sub-area and is electrically connected to another first power wire among the first power wires. The pads may further include a power detection additional pad that is electrically connected to the power detection additional wiring.

[0014] The display device may further include a sealing layer disposed on the element layer; and at least one dam portion disposed in a dam region surrounding the display area among the non-display areas. The circuit layer may include a first gate insulating layer disposed on the substrate, a first gate conductive layer disposed on the first gate insulating layer, a second gate insulating layer covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer, a first interlayer insulating layer covering the second gate conductive layer, a third gate insulating layer disposed on the first interlayer insulating layer, a third gate conductive layer disposed on the third gate insulating layer, a second interlayer insulating layer covering the third gate conductive layer, a first source-drain conductive layer disposed on the second interlayer insulating layer, a first planarization layer covering the first source-drain conductive layer, a second source-drain conductive layer disposed on the first planarization layer, and a second planarization layer covering the second source-drain conductive layer. Among the power sensing wirings, a bypass portion overlapping the dam region may be disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer. Among the power sensing wirings, a first main portion disposed between the bypass portion and the one first power wiring may be disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer. Among the power sensing wirings, a second main portion disposed between the bypass portion and the power sensing transmission pad may be disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

[0015] The above-mentioned bypass portion may be of a form including jig portions whose extension direction is variable.

[0016] A portion of the first main section of the power detection wiring adjacent to the bypass section may be in the form of a jig section having a variable extension direction.

[0017] The total extension length of the above jigs can correspond to the width of the above bypass section.

[0018] The sealing layer may include a first sealing layer disposed on the element layer, a second sealing layer disposed on the first sealing layer, and a third sealing layer disposed on the first sealing layer and covering the second sealing layer. Each of the first sealing layer and the third sealing layer may include an inorganic insulating material. The second sealing layer may include an organic insulating material disposed within an area surrounded by the at least one dam portion. The third sealing layer may be in contact with the first sealing layer at an outer edge of the dam area.

[0019] The substrate may further include a test pad region connected to one side of an edge of the sub-region. The circuit layer may further include test connection pads disposed in the test pad region and to which a connector of a test device supplying test signals for lighting tests is connected, and test connection wires disposed in the test pad region and extending from one side of an edge of the sub-region. The test connection wires may include a power detection dummy wire connected to the power detection extension wire.

[0020] The above inspection connection pads may include dummy pads electrically connected to the power detection dummy wiring.

[0021] The circuit layer may further include a first power supply wire disposed in the non-display area and transmitting the first power, and a first power extension wire electrically connected to the first power supply wire and in contact with one side of an edge of the sub-area. The inspection connection wires may further include a first power connection wire connected to the first power extension wire. The inspection connection pads may further include a first power supply pad electrically connected to the first power connection wire. The power detection dummy wire may be electrically connected to the first power connection wire.

[0022] A method for manufacturing a display device according to embodiments for solving the above problem includes the steps of: providing an inspection panel; performing a lighting inspection on the inspection panel using an inspection device connected to inspection connection pads of an inspection pad area of ​​the inspection panel; removing the inspection pad area of ​​the inspection panel to provide a display panel; and bonding a circuit board to pads of a sub-area of ​​the display panel. In the step of providing the inspection panel, the inspection panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate includes a main area including a display area in which light-emitting areas are arranged and a non-display area disposed around the display area, and a sub-area protruding from one side of the main area and having one side connected to the inspection pad area. The element layer includes light-emitting elements disposed in each of the light-emitting areas. The circuit layer includes light-emitting pixel drivers arranged in parallel in a first direction and a second direction and electrically connected to the light-emitting elements, first power wires arranged in the display area and extending in the second direction and transmitting a first power to the light-emitting pixel drivers, a power detection wire arranged in the non-display area, extending from a first side of an edge of the display area facing the sub-area and adjacent to the sub-area to the sub-area, and electrically connected to one of the first power wires, a power detection extension wire electrically connected to the power detection wire and in contact with one side of the edge of the sub-area, test connection pads arranged in the test pad area, and test connection wires arranged in the test pad area and extending from one side of the edge of the sub-area. The test connection wires include a power detection dummy wire electrically connected to the power detection extension wire.

[0023] In the step of providing the above inspection panel, the circuit layer may further include pads arranged in the sub-region and to which the circuit board is connected. The pads may include a power detection transmission pad electrically connected to the power detection wiring. The power detection wiring may be connected to one side of the power detection transmission pad. The power detection extension wiring may extend from the other side of the power detection transmission pad to one side of the edge of the sub-region.

[0024] The above inspection connection pads may include dummy pads electrically connected to the power detection dummy wiring.

[0025] In the step of providing the above inspection panel, the circuit layer may further include a first power supply wire arranged in the non-display area and transmitting the first power, and a first power extension wire electrically connected to the first power supply wire and in contact with one side of the edge of the sub-area. The inspection connection wires may further include a first power connection wire connected to the first power extension wire. The inspection connection pads may further include a first power supply pad electrically connected to the first power connection wire.

[0026] The above power detection dummy wiring can be electrically connected to the first power connection wiring.

[0027] In the step of providing the inspection panel, the circuit layer may further include a power detection additional wiring that is arranged in the non-display area and extends from a second side of the edge of the display area opposite the first side to the sub-area and is electrically connected to another first power wiring among the first power wirings. The pads may further include a power detection additional pad that is electrically connected to the power detection additional wiring.

[0028] In the step of providing the inspection panel, the inspection panel may further include at least one dam portion arranged in a dam area surrounding the display area among the non-display areas. The circuit layer may include a first gate insulating layer arranged on the substrate, a first gate conductive layer arranged on the first gate insulating layer, a second gate insulating layer covering the first gate conductive layer, a second gate conductive layer arranged on the second gate insulating layer, a first interlayer insulating layer covering the second gate conductive layer, a third gate insulating layer arranged on the first interlayer insulating layer, a third gate conductive layer arranged on the third gate insulating layer, a second interlayer insulating layer covering the third gate conductive layer, a first source-drain conductive layer arranged on the second interlayer insulating layer, a first planarization layer covering the first source-drain conductive layer, a second source-drain conductive layer arranged on the first planarization layer, and a second planarization layer covering the second source-drain conductive layer. Among the power sensing wirings, a bypass portion overlapping the dam region may be disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer. Among the power sensing wirings, a first main portion disposed between the bypass portion and the one first power wiring may be disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer. Among the power sensing wirings, a second main portion disposed between the bypass portion and the power sensing transmission pad may be disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

[0029] The above-mentioned bypass portion may be of a form including jig portions whose extension direction is variable.

[0030] A portion of the first main section of the power detection wiring adjacent to the bypass section may be in the form of a jig section having a variable extension direction.

[0031] Specific details of other embodiments are included in the detailed description and drawings.

[0032] A display device according to embodiments may include a display panel and a circuit board. The display panel may include a substrate, a circuit layer, and a component layer. The circuit layer may include first power lines, a power detection line extending from a first side of a display area to a sub-area and electrically connected to one of the first power lines, and a power detection extension line electrically connected to the power detection line and contacting one side of an edge of the sub-area.

[0033] In the step of preparing the inspection panel prior to the step of performing the lighting inspection, the circuit layer of the inspection panel may further include a power detection dummy wire disposed in the inspection pad area and extending from one side of the edge of the sub area and connected to the power detection extension wire.

[0034] In this way, as the circuit layer includes the power detection extension wiring and the power detection dummy wiring, the static electricity introduced around the power detection transmission pad can be distributed to the power detection extension wiring and the power detection dummy wiring, rather than being introduced only to the power detection wiring side.

[0035] This can reduce bursting and short circuiting of the power sensing wire due to overheating of a portion of the power sensing wire caused by concentration of static electricity.

[0036] Accordingly, the life of the display device can be improved because the occurrence of an oxygen or moisture path due to bursting of the power detection wire can be prevented.

[0037] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0038] Figures 1 and 2 are plan views showing display devices according to embodiments.

[0039] Figure 3 is a cross-sectional view showing A-A' of Figure 2.

[0040] Figure 4 is a layout diagram showing part B of Figure 2.

[0041] Fig. 5 is an equivalent circuit diagram showing the light emitting pixel driver of Fig. 4.

[0042] FIG. 6 is a cross-sectional view showing the first transistor, the second transistor, the fourth transistor, and the sixth transistor of FIG. 5, and the light-emitting element.

[0043] FIG. 7 is a layout diagram showing part A of FIG. 1 according to embodiments.

[0044] FIG. 8 is a plan view showing portion D of FIG. 7 according to one embodiment.

[0045] Fig. 9 is a cross-sectional view showing E-E' of Fig. 8.

[0046] FIG. 10, FIG. 11 and FIG. 12 are plan views showing portion D of FIG. 7 according to each of the embodiments.

[0047] Fig. 13 is a flowchart showing a method of manufacturing a display device according to embodiments.

[0048] FIG. 14 is a plan view showing an inspection panel during a step of preparing the inspection panel of FIG. 13 according to embodiments.

[0049] FIG. 15 is a layout diagram showing part F of FIG. 14 according to one embodiment.

[0050] FIG. 16 and FIG. 17 are process diagrams showing steps for performing the lighting test of FIG. 13 according to one embodiment.

[0051] Fig. 18 is a process diagram showing the steps for performing the lighting test of Fig. 13 according to a comparative example.

[0052] FIG. 19 is a layout diagram showing part F of FIG. 14 according to another embodiment.

[0053] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0054] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0055] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0056] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0057] Specific embodiments are described below with reference to the attached drawings.

[0058] Figures 1 and 2 are plan views showing display devices according to embodiments. Figure 3 is a cross-sectional view showing line A-A' of Figure 2. Figure 4 is a layout diagram showing part B of Figure 2.

[0059] Referring to FIGS. 1 and 2, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc.

[0060] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an organic light-emitting display device, but the present invention can be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0061] The display device (10) may be formed flat, but is not limited thereto. For example, the display device (10) may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device (10) may be formed flexibly so as to be able to be bent, curved, folded, or rolled.

[0062] The display device (10) may include a substrate (110), a display driving circuit (300), and a circuit board (200).

[0063] The substrate (110) may include a main area (MA) arranged on one side (hereinafter referred to as a display surface) on which an image is displayed, and a sub area (SBA) protruding from one side of the main area (MA).

[0064] The main area (MA) may include a display area (DA) in which light-emitting areas (EA of FIG. 4) emitting light with each color and brightness for image display are arranged, and a non-display area (NDA) arranged around the display area (DA).

[0065] The edge of the display area (DA) may include a first side (SD1) and a second side (SD2) extending in a first direction (DR1) and facing each other, and a third side (SD3) and a fourth side (SD4) extending in a second direction (DR2) and connecting the first side (SD1) and the second side (SD2) and facing each other.

[0066] For example, the first side (SD1) and the second side (SD2) may be shorter than the third side (SD3) and the fourth side (SD4). In this case, the display area (DA) may be formed as a rectangular plane.

[0067] As another example, the corners where the first side (SD1) and the second side (SD2) and the third side (SD3) and the fourth side (SD4) meet can be formed rounded to have a predetermined curvature or formed at a right angle.

[0068] As another example, the planar shape of the display area (DA) is not limited to a square, but may be formed into another polygon, circle, or ellipse.

[0069] The non-display area (NDA) may be positioned at the edge of the main area (MA) and may surround the periphery of the display area (DA).

[0070] The non-display area (NDA) may include a dam area (DMA) surrounding the display area (DA) and spaced apart from the display area (DA). At least one dam section (DM1, DM2 of FIGS. 8 and 9) having a ring shape surrounding the display area (DA) may be arranged in the dam area (DMA).

[0071] The sub-area (SBA) may face and be adjacent to the first side (SD1) of the display area (DA).

[0072] The sub-area (SBA) may include a bending area (BA) that is deformed into a bendable shape, and a first sub-area (SB1) and a second sub-area (SB2) that are in contact with both sides of the bending area (BA).

[0073] The first sub-area (SB1) is an area positioned between the main area (MA) and the bending area (BA). One side of the first sub-area (SB1) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the first sub-area (SB1) may be in contact with the bending area (BA).

[0074] The second sub-area (SB2) is separated from the main area (MA) by the first sub-area (SB1) and the bending area (BA).

[0075] When the bending area (BA) is deformed into a bent shape, the second sub-area (SB2) can be arranged on the lower surface of the substrate (110). That is, due to the bending area (BA) deformed into a bent shape, the second sub-area (SB2) can overlap with the main area (MA) in the thickness direction (i.e., the third direction (DR3)) of the substrate (110).

[0076] Figure 1 illustrates a state in which the sub-area (SBA) is spread out parallel to the main area (MA). In contrast, Figures 2 and 3 illustrate a state in which the bending area (BA) of the sub-area (SBA) is bent.

[0077] Referring to FIG. 3, a display device (10) according to embodiments may include a display panel (100) that emits light for displaying an image, and a circuit board (200) bonded to the display panel (100).

[0078] The display device (10) may further include a display driving circuit (300) mounted on a circuit board (200).

[0079] The display panel (100) may include a substrate (110), a circuit layer (120) disposed on the substrate (110), and a device layer (130) disposed on the circuit layer (120).

[0080] The display panel (100) may further include a sealing layer (140) disposed on the element layer (130), and a touch sensor layer (150) disposed on the sealing layer (140).

[0081] As illustrated in FIGS. 1 and 2, the substrate (110) includes a main area (MA) corresponding to a display surface and a sub area (SBA) protruding from one side of the main area (MA), and the main area (MA) may include a display area (DA) in which light-emitting areas (EA of FIG. 4) are arranged, and a non-display area (NDA) arranged around the display area (DA).

[0082] The substrate (110) may be made of an insulating material such as a polymer resin. For example, the substrate (110) may be made of polyimide. The substrate (110) may be a flexible substrate capable of bending, folding, rolling, etc.

[0083] Alternatively, the substrate (110) may be made of an insulating material such as glass.

[0084] The element layer (130) may include light-emitting elements (LEs of FIGS. 5 and 6) arranged in each light-emitting area (EA).

[0085] The circuit layer (120) may include light-emitting pixel drivers (EPDs of FIGS. 4 and 5) that are electrically connected to the light-emitting elements (LEs) of the element layer (130).

[0086] The sealing layer (140) is placed on the element layer (130) and may have a structure in which two or more inorganic films and at least one organic film are alternately laminated.

[0087] The touch sensor layer (150) may include touch electrodes for detecting a signal that varies depending on the touch of a person or object, and sensing the point where the touch of a person or object occurs in the main area (MA).

[0088] The polarizing layer (160) is intended to prevent the deterioration of image visibility due to external light reflection by blocking external light reflected from the touch sensor layer (150), sealing layer (140), element layer (130), and circuit layer (120) and their interfaces.

[0089] The display device (10) may further include a cover window (not shown) disposed on the polarizing layer (160). The cover window may be attached to the polarizing layer (160) by a transparent adhesive material such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be an inorganic material such as glass, or an organic material such as plastic or a polymer material. By such a cover window, the touch sensor layer (150), the sealing layer (140), the element layer (130), and the circuit layer (120) may be protected from electrical and physical shocks on the display surface.

[0090] The circuit board (200) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0091] The circuit board (200) can be bonded to pads (PD of FIG. 7) arranged in the second sub-area (SB2) of the board (110) using a low-resistance, high-reliability material such as anisotropic conductive film or SAP.

[0092] The display driving circuit (300) can be provided as an integrated circuit chip (IC).

[0093] According to embodiments, the display driving circuit (300) can be attached to the circuit board (200) in a COF (chip on film) manner.

[0094] The display driving circuit (300) can output data signals to the data wiring (DL of FIG. 5) of the circuit layer (120).

[0095] The display device (10) may further include a touch driving circuit (400) for driving the touch sensor layer (150).

[0096] Referring to FIG. 4, the display area (DA) of the display device (10) may include light-emitting areas (EA). In addition, the display area (DA) may further include a non-light-emitting area disposed in a space between the light-emitting areas (EA).

[0097] The light emitting elements (LEs) of the light emitting areas (EA) and the light emitting pixel drivers (EPDs) electrically connected to each other can be arranged in parallel in the first direction (DR1) and the second direction (DR2) in the main area (MA).

[0098] The light-emitting pixel drivers (EPDs) can be electrically connected to the light-emitting elements (LE of FIG. 5) of the element layers (130) respectively arranged in the light-emitting areas (EA).

[0099] The light-emitting areas (EA) may have a rhombus-shaped planar shape or a rectangular planar shape. However, this is merely an example, and the planar shape of the light-emitting areas (EA) according to one embodiment is not limited to that illustrated in FIG. 4. That is, the light-emitting areas (EA) may have a polygonal shape, such as a square, pentagon, or hexagon, or a circular or oval planar shape including curved edges.

[0100] The light-emitting areas (EA) may include first light-emitting areas (EA1) that emit light of a first color by a predetermined wavelength band, second light-emitting areas (EA2) that emit light of a second color by a lower wavelength band than the first color, and third light-emitting areas (EA3) that emit light of a third color by a lower wavelength band than the second color.

[0101] For example, the first color may be red with a wavelength range of approximately 600 nm to 750 nm. The second color may be green with a wavelength range of approximately 480 nm to 560 nm. The third color may be blue with a wavelength range of approximately 370 nm to 460 nm.

[0102] The first light-emitting areas (EA1) and the third light-emitting areas (EA3) can be arranged alternately in at least one of the first direction (DR1) and the second direction (DR2).

[0103] The second light-emitting areas (EA2) can be arranged parallel to each other in at least one of the first direction (DR1) and the second direction (DR2).

[0104] And, the second light-emitting areas (EA2) can be adjacent to the first light-emitting areas (EA1) and the third light-emitting areas (EA3) in diagonal directions (DR4, DR5) intersecting the first direction (DR1) and the second direction (DR2).

[0105] Among these light-emitting areas (EA), pixels (PX) that display each brightness and color can be provided by the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) that are adjacent to each other.

[0106] In other words, pixels (PX) can be basic units that display various colors, including white, at a given brightness.

[0107] Each of the pixels (PX) may include at least one first light-emitting area (EA1), at least one second light-emitting area (EA2), and at least one third light-emitting area (EA3) that are adjacent to each other. Accordingly, each of the pixels (PX) may display various colors through mixing of lights emitted from the adjacent first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3).

[0108] Fig. 5 is an equivalent circuit diagram showing the light emitting pixel driver of Fig. 4.

[0109] Referring to FIG. 5, the light-emitting pixel drivers (EPDs) are electrically connected to a first power source (ELVDD), and one of the light-emitting elements (LEs) of the element layer (130) can be electrically connected between one of the light-emitting pixel drivers (EPDs) of the circuit layer (120) and a second power source (ELVSS).

[0110] That is, the anode electrode of the light-emitting element (LE) is electrically connected to the light-emitting pixel driver (EPD), and a second power supply (ELVSS) having a lower voltage level than the first power supply (ELVDD) can be applied to the cathode electrode of the light-emitting element (LE).

[0111] A capacitor (Cel) connected in parallel with the light emitting element (LE) represents the parasitic capacitance between the anode and cathode electrodes.

[0112] The circuit layer (120) may further include a first power line (VDL) that transmits a first power supply (ELVDD), a gate initialization voltage line (VGIL) that transmits a gate initialization voltage (VGINT), and an anode initialization voltage line (VAIL) that transmits an anode initialization voltage (VAINT).

[0113] The circuit layer (120) may further include a scan write wiring (GWL) that transmits a scan write signal (GW), a scan initialization wiring (GIL) that transmits a scan initialization signal (GI), an emission control wiring (ECL) that transmits an emission control signal (EC), a gate control wiring (GCL) that transmits a gate control signal (GC), and a bias control wiring (GBL) that transmits a bias control signal (GB).

[0114] One light-emitting pixel driver (EPD) of the circuit layers (120) may include a first transistor (T1) that generates a driving current for driving the light-emitting element (LE), two or more transistors (T2 to T7) electrically connected to the first transistor (T1), and at least one capacitor (PC1).

[0115] A first transistor (T1) can be electrically connected between a first node (N1) and a second node (N2). The first node (N1) is electrically connected to a first electrode (e.g., a source electrode) of the first transistor (T1). The second node (N2) is electrically connected to a second electrode (e.g., a drain electrode) of the first transistor (T1).

[0116] The first node (N1) can be electrically connected to the first power line (VDL) through the fifth transistor (T5).

[0117] The second node (N2) can be electrically connected to the anode electrode of the light emitting element (LE) through the sixth transistor (T6).

[0118] A first capacitor (PC1) can be electrically connected between a first power line (VDL) and a third node (N3). The third node (N3) is electrically connected to a gate electrode of a first transistor (T1).

[0119] That is, the gate electrode of the first transistor (T1) can be electrically connected to the first power line (VDL) through the first capacitor (PC1).

[0120] Accordingly, the potential of the gate electrode of the first transistor (T1) can be maintained at the voltage charged in the first capacitor (PC1).

[0121] A second transistor (T2) can be electrically connected between the data line (DL) and the first node (N1).

[0122] The second transistor (T2) can be electrically connected between the first electrode of the first transistor (T1) and the data line (DL).

[0123] That is, the first electrode of the first transistor (T1) can be electrically connected to the data line (DL) through the second transistor (T2).

[0124] The second transistor (T2) can be turned on by a scan write signal (GW) of a scan write wiring (GWL).

[0125] The fifth transistor (T5) can be electrically connected between the first node (N1) and the first power line (VDL).

[0126] The sixth transistor (T6) can be electrically connected between the second node (N2) and the fourth node (N4). The fourth node (N4) is electrically connected to the anode electrode of the light emitting element (LE).

[0127] That is, the fifth transistor (T5) can be electrically connected between the first electrode of the first transistor (T1) and the first power line (VDL).

[0128] The sixth transistor (T6) can be electrically connected between the second electrode of the first transistor (T1) and the anode electrode of the light emitting element (LE).

[0129] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the emission control signal (EC) of the emission control line (ECL).

[0130] When the data signal (Vdata) of the data line (DL) is transmitted to the first electrode of the first transistor (T1) through the turned-on second transistor (T2), the voltage difference between the gate electrode of the first transistor (T1) and the first electrode of the first transistor (T1) can become the voltage difference between the first power source (ELVDD) and the data signal (Vdata).

[0131] At this time, when the voltage difference between the gate electrode of the first transistor (T1) and the first electrode of the first transistor (T1), i.e., the voltage difference between the gate and the source, becomes greater than the threshold voltage, the first transistor (T1) is turned on, so that a current between the drain and the source of the first transistor (T1) corresponding to the data signal (Vdata) can be generated.

[0132] Next, when the fifth transistor (T5) and the sixth transistor (T6) are turned on, the first power source (ELVDD), the first transistor (T1), the light-emitting element (LE), and the second power source (ELVSS) can be connected in series. Accordingly, the drain-source current of the first transistor (T1) corresponding to the data signal (Vdata) can be supplied as a driving current of the light-emitting element (LE).

[0133] Accordingly, the light emitting element (LE) can emit light with a brightness corresponding to the data signal (Vdata).

[0134] The third transistor (T3) can be electrically connected between the second node (N2) and the third node (N3). That is, the third transistor (T3) can be electrically connected between the gate electrode of the first transistor (T1) and the second electrode of the first transistor (T1).

[0135] The third transistor (T3) can be turned on by a gate control signal (GC) of a gate control wiring (GCL).

[0136] Through the turned-on third transistor (T3), the voltage difference between the second node (N2) and the third node (N3) can be initialized.

[0137] The fourth transistor (T4) can be electrically connected between the gate initialization voltage wiring (VGIL) and the third node (N3). That is, the fourth transistor (T4) can be connected between the gate electrode of the first transistor (T1) and the gate initialization voltage wiring (VGIL).

[0138] The fourth transistor (T4) can be turned on by the scan initialization signal (GI) of the scan initialization wiring (GIL).

[0139] Through the turned-on fourth transistor (T4), the potential of the third node (N3) can be initialized.

[0140] The third transistor (T3) and the fourth transistor (T4) can be provided as N-type MOSFETs.

[0141] The seventh transistor (T7) can be electrically connected between the fourth node (N4) and the anode initialization voltage wiring (VAIL). That is, the seventh transistor (T7) can be electrically connected between the anode electrode of the light emitting element (LE) and the anode initialization voltage wiring (VAIL).

[0142] The seventh transistor (T7) can be turned on by a bias control signal (GB) of a bias control line (GBL).

[0143] Through the turned-on seventh transistor (T7), the potential of the fourth node (N4) can be initialized.

[0144] According to embodiments, among the first to seventh transistors (T1 to T7), the third transistor (T3) and the fourth transistor (T4) may be provided as N-type MOSFETs, and the remaining transistors (T1, T2, T5 to T7) excluding the third transistor (T3) and the fourth transistor (T4) may be provided as P-type MOSFETs.

[0145] Accordingly, according to embodiments, the circuit layer (120) may include a first semiconductor layer for providing a P-type MOSFET and a second semiconductor layer for providing an N-type MOSFET.

[0146] FIG. 6 is a cross-sectional view showing the first transistor, the second transistor, the fourth transistor, and the sixth transistor of FIG. 5, and the light-emitting element.

[0147] Referring to FIG. 6, a display panel (100) of a display device (10) according to embodiments may include a substrate (110), a circuit layer (120) on the substrate (110), and an element layer (130) on the circuit layer (120).

[0148] The display panel (100) of the display device (10) according to the embodiments may further include a sealing layer (140) on the element layer (130), a touch sensor layer (150) on the sealing layer (140), and a polarizing layer (160) on the touch sensor layer (150).

[0149] The circuit layer (120) includes a first semiconductor layer (CH1, E11, E21, CH2, E12, E22, CH6, E16, E26) disposed on a substrate (110), a first gate insulating layer (123) covering the first semiconductor layer, a first gate conductive layer (G1, G2, G6) disposed on the first gate insulating layer (123), a second gate insulating layer (124) covering the first gate conductive layer, a second gate conductive layer (CAE, LB2) disposed on the second gate insulating layer (124), a first interlayer insulating layer (125) covering the second gate conductive layer, a second semiconductor layer (CH4, E14, E24) disposed on the first interlayer insulating layer (125), a third gate insulating layer (126) covering the second semiconductor layer, a third gate conductive layer (G4) disposed on the third gate insulating layer (126), and a second interlayer insulating layer covering the third gate conductive layer. It may include an insulating layer (127), a first source-drain conductive layer (ANCE1, VGIL, DCE) disposed on a second interlayer insulating layer (127), a first planarization layer (128) covering the first source-drain conductive layer, a second source-drain conductive layer (DL, ANCE2) disposed on the first planarization layer (128), and a second planarization layer (129) covering the second source-drain conductive layer.

[0150] According to embodiments, the circuit layer (120) may further include a barrier layer (121) disposed on the substrate (110), a first light-blocking layer (LB1) disposed on the barrier layer (121), and a buffer layer (122) covering the first light-blocking layer (LB1). In this case, the first semiconductor layers (CH1, E11, E21, CH2, E12, E22, CH6, E16, E26) may be disposed on the buffer layer (122).

[0151] The circuit layer (120) may include light-emitting pixel drivers (EPDs) corresponding to each light-emitting area (EA).

[0152] Each of the light-emitting pixel drivers (EPDs) may include a first transistor (T1), second to seventh transistors (T2 to T7 in FIG. 5) electrically connected to the first transistor (T1), and at least one capacitor (PC1 in FIG. 5).

[0153] FIG. 6 illustrates the first transistor (T1), the second transistor (T2), the fourth transistor (T4), and the sixth transistor (T6) among the transistors (T1 to T7 of FIG. 5) of the emission pixel driver (EPD).

[0154] The barrier layer (121) and the buffer layer (122) may include different inorganic insulating materials.

[0155] The first semiconductor layer on the buffer layer (122) may include channel portions (CH1, CH2, CH6), first electrode portions (E11, E12, E16) and second electrode portions (E21, E22, E26) of each of the first transistor (T1), the second transistor (T2), the fifth transistor (T5 in FIG. 5), the sixth transistor (T6) and the seventh transistor (T7), which are formed as P-type MOSFETs.

[0156] The first gate conductive layer on the first gate insulating layer (123) may include gate electrodes (G1, G2, G6) of each of the first transistor (T1), the second transistor (T2), the fifth transistor (T5 in FIG. 5), the sixth transistor (T6), and the seventh transistor (T7), which are provided as P-type MOSFETs.

[0157] Since the fifth transistor (T5) and the seventh transistor (T7) have the same structure as the first transistor (T1), the second transistor (T2), and the sixth transistor (T6), redundant descriptions thereof are omitted below.

[0158] In each of the first transistor (T1), the second transistor (T2), and the sixth transistor (T6), the channel portions (CH1, CH2, CH6) may overlap with the gate electrodes (G1, G2, G6).

[0159] The channel portion (CH1) of the first transistor (T1) may overlap with the first light-shielding layer (LB1) under the buffer layer (122).

[0160] In each of the first transistor (T1), the second transistor (T2), and the sixth transistor (T6), the first electrode portion (E11, E12, E16) may be connected to one end of the channel portion (CH1, CH2, CH6), and the second electrode portion (E21, E22, E26) may be connected to the other end of the channel portion (CH1, CH2, CH6).

[0161] The first electrode portion (E11) of the first transistor (T1) can be connected to the second electrode portion (E22) of the second transistor (T2).

[0162] The second electrode portion (E21) of the first transistor (T1) can be connected to the first electrode portion (E16) of the sixth transistor (T6).

[0163] The second gate conductive layer on the second gate insulating layer (124) may include a capacitor electrode (CAE) and a second light-shielding layer (LB2).

[0164] The capacitor electrode (CAE) may overlap with the gate electrode (G1) of the first transistor (T1).

[0165] Accordingly, a first capacitor (PC1 in Fig. 5) can be provided by an overlapping area between the capacitor electrode (CAE) and the gate electrode (G1) of the first transistor (T1).

[0166] The second semiconductor layer on the first interlayer insulating layer (125) may include a channel portion (CH4), a first electrode portion (E14), and a second electrode portion (E24) of each of the third transistor (T3 in FIG. 5) and the fourth transistor (T4) provided as N-type MOSFETs.

[0167] The third gate conductive layer on the third gate insulating layer (126) may include a gate electrode (G4) of each of the third transistor (T3 in FIG. 5) and the fourth transistor (T4) provided as an N-type MOSFET.

[0168] In each of the third transistor (T3 in FIG. 5) and the fourth transistor (T4), the channel portion (CH4) may overlap with the second light-shielding layer (LB2) under the first interlayer insulating layer (125).

[0169] The channel portion (CH4) of the fourth transistor (T4) may overlap with the gate electrode (G4) of the fourth transistor (T4).

[0170] The first electrode portion (E14) of the fourth transistor (T4) can be connected to one end of the channel portion (CH4) of the fourth transistor (T4), and the second electrode portion (E24) of the fourth transistor (T4) can be connected to the other end of the channel portion (CH4) of the fourth transistor (T4).

[0171] Since the third transistor (T3) has the same structure as the fourth transistor (T4), any duplicate explanation will be omitted below.

[0172] The first source-drain conductive layer on the second interlayer insulating layer (127) may include a first anode connection electrode (ANCE1), a data connection electrode (DCE), a gate initialization voltage wiring (VGIL), and a node auxiliary connection electrode (NACE).

[0173] The second source-drain conductive layer on the first planarization layer (128) may include a second anode connection electrode (ANCE2) and a data wiring (DL).

[0174] The data connection electrode (DCE) can be electrically connected to the first electrode portion (E12) of the second transistor (T2) through the first data connection hole (DCH1).

[0175] The data wiring (DL) can be electrically connected to the data connection electrode (DCE) through the second data connection hole (DCH2).

[0176] In this way, the data wiring (DL) can be electrically connected to the first electrode portion (E12) of the second transistor (T2) via the data connection electrode (DCE).

[0177] The anode electrode (131) of the element layer (130) can be placed on the second planarization layer (129).

[0178] The first anode connection electrode (ANCE1) can be electrically connected to the second electrode portion (E26) of the sixth transistor (T6) through the first anode connection hole (ANCH1).

[0179] The second anode connection electrode (ANCE2) can be electrically connected to the first anode connection electrode (ANCE1) through the second anode connection hole (ANCH2).

[0180] The anode electrode (131) can be electrically connected to the second anode connection electrode (ANCE2) through the third anode connection hole (ANCH3).

[0181] In this way, the anode electrode (131) can be electrically connected to the second electrode portion (E26) of the sixth transistor (T6) through the first anode connection electrode (ANCE1) and the second anode connection electrode (ANCE2).

[0182] Each of the first data connection hole (DCH1) and the first anode connection hole (ANCH1) can penetrate the second interlayer insulating layer (127), the third gate insulating layer (126), the first interlayer insulating layer (125), the second gate insulating layer (124), and the first gate insulating layer (123).

[0183] Each of the second anode connection hole (ANCH2) and the second data connection hole (DCH2) can penetrate the first planarization layer (128).

[0184] The gate initialization voltage wiring (VGIL) can be electrically connected to the first electrode portion (E14) of the fourth transistor (T4) through the gate initialization voltage connection hole (VGCH).

[0185] The node auxiliary connecting electrode (NACE) can be electrically connected to the second electrode portion (E24) of the fourth transistor (T4) through the node auxiliary connecting hole (NACH).

[0186] Each of the gate initialization voltage connection hole (VGCH) and the node auxiliary connection hole (NACH) can penetrate the second interlayer insulating layer (127) and the third gate insulating layer (126).

[0187] The element layer (130) on the circuit layer (120) may include light-emitting elements (LEs) arranged in each of the light-emitting areas (EA1, EA2, EA3).

[0188] Each of the light emitting elements (LEs) may include a structure in which a light emitting layer (133) is disposed between an anode electrode (131) and a cathode electrode (134) that are opposite to each other.

[0189] According to embodiments, the device layer (130) may include anode electrodes (131) each disposed in the light-emitting areas (EA), a pixel-defining layer (132) disposed in the non-light-emitting area (NEA) and covering the edge of the anode electrode (131), a spacer layer (132') disposed on a portion of the pixel-defining layer (132), light-emitting layers (133) each disposed on the anode electrodes (131), and a cathode electrode (134) disposed on the pixel-defining layer (132) and the spacer layer (132') of the light-emitting layers (133).

[0190] Alternatively, each of the light emitting elements (LEs) may further include first common layers (135) disposed between the anode electrodes (131) and the light emitting layers (133), and second common layers (136) disposed between the light emitting layers (133) and the cathode electrodes (134).

[0191] The sealing layer (140) can be placed on the circuit layer (120) and cover the element layer (130).

[0192] The sealing layer (140) is intended to block the penetration of oxygen or moisture into the element layer (130) and to alleviate electrical or physical impact on the circuit layer (120) and the element layer (130).

[0193] The sealing layer (140) may include a first sealing layer (141) disposed on the circuit layer (120), covering the element layer (130), and including an inorganic insulating material, a second sealing layer (142) disposed on the first sealing layer (141), overlapping the element layer (130), and including an organic insulating material, and a third sealing layer (143) disposed on the first sealing layer (141), covering the second sealing layer (142), and including an inorganic insulating material.

[0194] The touch sensor layer (150) can be placed on the sealing layer (140).

[0195] The polarizing layer (160) can be placed on the touch sensor layer (150).

[0196] For example, the polarizing layer (160) can be attached to the touch sensor layer (150) through an adhesive layer between the polarizing layer (160) and the touch planarization layer (153).

[0197] FIG. 7 is a layout diagram showing part A of FIG. 1 according to embodiments.

[0198] Referring to FIG. 7, a display panel (100) of a display device (10) according to embodiments may include a substrate (110) and a circuit layer (120) on the substrate (110).

[0199] The substrate (110) includes a main area (MA) and a sub area (SBA) protruding from one side of the main area (MA), and the main area (MA) may include a display area (DA) in which light-emitting areas (EA of FIG. 4) are arranged, and a non-display area (NDA) arranged around the display area (DA).

[0200] As illustrated in FIGS. 4 and 5, the circuit layer (120) may include light-emitting pixel drivers (EPDs) that are arranged parallel to each other in the first direction (DR1) and the second direction (DR2) and are electrically connected to the light-emitting elements (LEs) of the element layer (130).

[0201] As illustrated in FIG. 7, the circuit layer (120) may further include first power lines (VDLs) that are arranged in the display area (DA) and extend in the second direction (DR2) and transmit a first power (ELVDD of FIG. 5) to the light-emitting pixel drivers (EPDs).

[0202] The circuit layer (120) may further include data lines (DL) that are arranged in the display area (DA) and extend in the second direction (DR2), are adjacent to the first power lines (VDL), and transmit data signals (Vdata in FIG. 5).

[0203] According to embodiments, the circuit layer (120) may include a power sensing wire (VDTL) disposed in a non-display area (NDA) and electrically connected to one of the first power wires (VDLs), and a power sensing extension wire (VDTEXL) electrically connected to the power sensing wire (VDTL) and in contact with one side of an edge of a sub-area (SBA).

[0204] The power detection line (VDTL) may extend from a first side (SD1) adjacent to the sub-area (SBA) and facing the sub-area (SBA) among the edges of the display area (DA). That is, the power detection line (VDTL) may be electrically connected to a portion of one of the first power lines (VDL) adjacent to the first side (SD1).

[0205] According to embodiments, the circuit layer (120) may further include pads (PD) disposed in the sub-area (SBA) and to which the circuit board (200) is connected.

[0206] The pads (PD) can be placed in the second sub-area (SB2). In this way, the bending area (BA) of the sub-area (SBA) is deformed into a bending shape, so that the circuit board (200) connected to the pads (PD) can be accommodated on the rear side of the display panel (100).

[0207] The pads (PD) may include a power sense transfer pad (VDTPD) electrically connected to a power sense wire (VDTL).

[0208] The power sense wire (VDTL) can extend from the first side (SD1) of the display area (DA) to the sub area (SBA) and be connected to one side of the power sense transfer pad (VDTPD).

[0209] The power sense wire (VDTL) may include a bypass section (BYP1) overlapping a dam area (DMA of FIG. 8), a first main section (MNP11) positioned between one first power wire (VDL) and the bypass section (BYP1), and a second main section (MNP21) positioned between a power sense transfer pad (VDTPD) and the bypass section (BYP1).

[0210] The power sense extension wire (VDTEXL) can extend from one side of the power sense transfer pad (VDTPD) to one side of the edge of the sub-area (SBA).

[0211] That is, the power sense transfer pad (VDTPD) can be placed between and electrically connected to the power sense wire (VDTL) and the power sense extension wire (VDTEXL).

[0212] According to embodiments, the circuit layer (120) may further include a power detection additional wiring (VDTAL) disposed in a non-display area (NDA) and electrically connected to another first power wiring (VDL) among the first power wirings (VDLs).

[0213] The power detection additional wiring (VDTAL) can extend from a second side (SD2) opposite to the first side (SD1) of the edge of the display area (DA) to the sub-area (SBA). That is, the power detection additional wiring (VDTAL) can be electrically connected to a portion of another first power wiring (VDL) adjacent to the second side (SD2).

[0214] The pads (PD) may further include a power detection additional pad (VDAPD) electrically connected to a power detection additional wiring (VDTAL).

[0215] Similar to the power sense wire (VDTL), the power sense additional wire (VDTAL) may include a bypass section (BYP2) overlapping a dam area (DMA in FIG. 8), a first main section (MNP12) positioned between another first power wire (VDL) and the bypass section (BYP2), and a second main section (MNP22) positioned between the power sense additional pad (VDAPD) and the bypass section (BYP2).

[0216] According to embodiments, a voltage level at an end adjacent to a first side (SD1) of one first power wire (VDL) can be transmitted to a circuit board (200) through a power detection wire (VDTL) and a power detection transfer pad (VDTPD). In addition, a voltage level at an end adjacent to a second side (SD2) of another first power wire (VDL) can be transmitted to the circuit board (200) through a power detection additional wire (VDTAL) and a power detection additional pad (VDAPD). Accordingly, it can be easily detected whether the voltage level of the first power (ELVDD) supplied to the light-emitting pixel drivers (EPDs) through the first power wires (VDLs) is normal. Therefore, correction of the voltage level of the first power (ELVDD) can be facilitated, so that the picture quality of the display device (10) can be improved.

[0217] The power detection additional wiring (VDTAL) extends parallel to the third side (SD3) from the second side (SD2) spaced far from the sub-area (SBA) and is connected to the power detection additional pad (VDAPD) of the sub-area (SBA).

[0218] On the other hand, the power sense wire (VDTL) is connected to the power sense transfer pad (VDTPD) of the sub-area (SBA) from the first side (SD1) facing the sub-area (SBA), and thus extends with a shorter length than the power sense auxiliary wire (VDTAL). Therefore, the power sense wire (VDTL) may be more vulnerable to electrostatic discharge (ESD) than the power sense auxiliary wire (VDTAL).

[0219] Accordingly, according to embodiments, since the circuit layer (120) includes a power sensing extension wire (VDTEXL) extending from the other side of the power sensing transfer pad (VDTPD) to one side of the edge of the sub-area (SBA), when performing a lighting test, static electricity (ESD in FIG. 17) introduced through the pads (PD) can be distributed to the power sensing extension wire (VDTEXL) rather than flowing only to the power sensing wire (VDTL) side, so that a short circuit defect of the power sensing wire (VDTL) due to concentration of static electricity (ESD) can be prevented.

[0220] In addition, according to embodiments, the circuit layer (120) may further include a first power supply line (VDSPL) disposed in the non-display area (NDA) and extending to the sub-area (SBA) and transmitting the first power (ELVDD), and a first power extension line (VDEXL) electrically connected to the first power supply line (VDSPL) and in contact with one side of the edge of the sub-area (SBA).

[0221] The pads (PD) may further include a first power pad (VDPD) electrically connected to a first power supply line (VDSPL).

[0222] A first power pad (VDPD) can be positioned and electrically connected between a first power supply wire (VDSPL) and a first power extension wire (VDEXL).

[0223] The circuit layer (120) may further include a second power supply line (VSSPL) that is arranged in the non-display area (NDA) and extends to the sub-area (SBA) and transmits a second power supply line (ELVSS), and a second power extension line (VSEXL) that is electrically connected to the second power supply line (VSSPL) and contacts one side of the edge of the sub-area (SBA).

[0224] The pads (PD) may further include a second power pad (VSPD) electrically connected to a second power supply line (VSSPL).

[0225] A second power pad (VSPD) can be positioned and electrically connected between the second power supply wire (VSSPL) and the second power extension wire (VSEXL).

[0226] The pads (PD) may further include data pads (DTPD) that transmit data signals (Vdata) of data lines (DL).

[0227] The circuit layer (120) may further include data supply lines (DTSPL) that are arranged in the non-display area (NDA) and the sub-area (SBA) and electrically connect between data lines (DL) and data pads (DTPD), and data extension lines (DTEXL) that are electrically connected to the data supply lines (DTSTL), extend from the data pads (DTPD), and contact one side of the edge of the sub-area (SBA).

[0228] Fig. 8 is a plan view showing portion D of Fig. 7 according to one embodiment. Fig. 9 is a cross-sectional view showing line E-E' of Fig. 8.

[0229] As illustrated in FIG. 8, according to one embodiment, the power sensing wiring (VDTL) may include a bypass portion (BYP1) overlapping with a dam area (DMA), a first main portion (MNP11) electrically connected to one side of the bypass portion (BYP1), and a second main portion (MNP21) electrically connected to the other side of the bypass portion (BYP1).

[0230] Referring to FIG. 9, the bypass portion (BYP1) of the power detection wiring (VDTL) may be arranged on at least one of the first gate conductive layer (G1, G2, G6 of FIG. 6) on the first gate insulating layer (123), the second gate conductive layer (CAE, LB2 of FIG. 6) on the second gate insulating layer (124), and the third gate conductive layer (G4 of FIG. 6) on the third gate insulating layer (126).

[0231] Each of the first main portion (MNP11) and the second main portion (MNP21) of the power detection wiring (VDTL) may be disposed on at least one of the first source-drain conductive layer (ANCE1, VGIL, DCE of FIG. 6) on the second interlayer insulating layer (127) and the second source-drain conductive layer (DL, ANCE2 of FIG. 6) on the first planarization layer (128).

[0232] For example, as shown in the diagram of FIG. 9, the bypass portion (BYP1) of the power sensing wiring (VDTL) may be placed on the third gate conductive layer on the third gate insulating layer (126).

[0233] The first main portion (MNP11) of the power detection wiring (VDTL) may include a first main wiring layer (MNL11) disposed on a first source-drain conductive layer on a second interlayer insulating layer (127) and electrically connected to one side of the bypass portion (BYP1) through a bypass connection hole (BYCH), and a second main wiring layer (MNL21) disposed on a second source-drain conductive layer on a first planarization layer (128) and electrically connected to the first main wiring layer (MNL11).

[0234] Similarly, the second main portion (MNP21) of the power detection wiring (VDTL) may include a first main wiring layer (MNL12) disposed on a first source-drain conductive layer on a second interlayer insulating layer (127) and electrically connected to the other side of the bypass portion (BYP1) through a bypass connection hole (BYCH), and a second main wiring layer (MNL22) disposed on a second source-drain conductive layer on a first planarization layer (128) and electrically connected to the first main wiring layer (MNL12).

[0235] As illustrated in FIG. 8, according to one embodiment, the bypass portion (BYP1) of the power sensing wire (VDTL) may have a protruding shape including jigs (ZG) whose extension direction is variable.

[0236] In each of the jigs (ZG), the extension direction of the bypass (BYP1) can be changed from the first direction (DR1) to the second direction (DR2), or from the second direction (DR2) to the first direction (DR1).

[0237] In this way, as the bypass section (BYP1) includes the jigs (ZG), the total extension length of the power sensing wire (VDTL) is increased, so that the resistance of the power sensing wire (VDTL) can be secured above the threshold for sensing the voltage level of the first power source (ELVDD).

[0238] According to embodiments, the first power supply line (VDSPL) may include, similarly to the power sensing line (VDTL), a bypass section (BYP3) overlapping the dam area (DMA), a first main section (MNP13) electrically connected to one side of the bypass section (BYP3), and a second main section (MNP23) electrically connected to the other side of the bypass section (BYP3).

[0239] The first main section (MNP13) of the first power supply wiring (VDSPL) is arranged adjacent to the first side (SD1) of the edge of the display area (DA) and can be extended to the bypass section (BYP3) of the first power supply wiring (VDSPL).

[0240] The second main section (MNP23) of the first power supply wiring (VDSPL) can be extended from the bypass section (BYP3) of the first power supply wiring (VDSPL) to the first power supply pad (VDSPD).

[0241] According to embodiments, the second power supply line (VSSPL) may include, similarly to the power sense line (VDTL), a bypass section (BYP4) overlapping the dam area (DMA), a first main section (MNP14) electrically connected to one side of the bypass section (BYP4), and a second main section (MNP24) electrically connected to the other side of the bypass section (BYP4).

[0242] The first main portion (MNP14) of the second power supply wiring (VSSPL) can be extended to the bypass portion (BYP4) of the second power supply wiring (VSSPL) surrounding the periphery of the display area (DA).

[0243] The second main section (MNP24) of the second power supply wiring (VSSPL) can be extended from the bypass section (BYP4) of the second power supply wiring (VSSPL) to the second power supply pad (VSSPD).

[0244] Each of the bypass portion (BYP3) of the first power supply wiring (VDSPL) and the bypass portion (BYP4) of the second power supply wiring (VSSPL) may be disposed on at least one of the first gate conductive layer (G1, G2, G6 in FIG. 6) on the first gate insulating layer (123), the second gate conductive layer (CAE, LB2 in FIG. 6) on the second gate insulating layer (124), and the third gate conductive layer (G4 in FIG. 6) on the third gate insulating layer (126).

[0245] Each of the first main portion (MNP13) of the first power supply wiring (VDSPL), the second main portion (MNP23) of the first power supply wiring (VDSPL), the first main portion (MNP14) of the second power supply wiring (VSSPL), and the second main portion (MNP24) of the second power supply wiring (VSSPL) may be disposed on at least one of the first source-drain conductive layer (ANCE1, VGIL, DCE in FIG. 6) on the second interlayer insulating layer (127) and the second source-drain conductive layer (DL, ANCE2 in FIG. 6) on the first planarization layer (128).

[0246] Additionally, according to embodiments, the circuit layer (120) may further include a plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) arranged in a non-display area (NDA) and a sub-area (SBA).

[0247] One of the multiple constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) can transmit the gate initialization voltage (VGINT in FIG. 5).

[0248] Another one of the multiple constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) can transmit the anode initialization voltage (VAINT in Fig. 5).

[0249] Another one of the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) can transmit one of a gate high voltage and a gate low voltage. The gate high voltage and the gate low voltage can be provided for generating at least one of a scan write signal (GW in FIG. 5), an emission control signal (EC), a gate control signal (GC), and a bias control signal (GB).

[0250] Among the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3), the first constant voltage supply line (CVSPL1) may, like the power detection line (VDTL), include a bypass section (BYP5) overlapping with a dam area (DMA), a first main section (MNP15) electrically connected to one side of the bypass section (BYP5), and a second main section (MNP25) electrically connected to the other side of the bypass section (BYP5).

[0251] Among the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3), the second constant voltage supply line (CVSPL2) may, like the power detection line (VDTL), include a bypass section (BYP6) overlapping with a dam area (DMA), a first main section (MNP16) electrically connected to one side of the bypass section (BYP6), and a second main section (MNP26) electrically connected to the other side of the bypass section (BYP6).

[0252] Among the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3), the third constant voltage supply line (CVSPL3) may, like the power detection line (VDTL), include a bypass section (BYP7) overlapping with a dam area (DMA), a first main section (MNP17) electrically connected to one side of the bypass section (BYP7), and a second main section (MNP27) electrically connected to the other side of the bypass section (BYP7).

[0253] The bypass portions (BYP5, BYP6, BYP7) of the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) may be arranged on at least one of the first gate conductive layer (G1, G2, G6 in FIG. 6) on the first gate insulating layer (123), the second gate conductive layer (CAE, LB2 in FIG. 6) on the second gate insulating layer (124), and the third gate conductive layer (G4 in FIG. 6) on the third gate insulating layer (126).

[0254] Each of the first main sections (MNP15, MNP16, MNP17) and the second main sections (MNP25, MNP26, MNP27) of the plurality of constant voltage supply lines (CVSPL1, CVSPL2, CVSPL3) may be arranged on at least one of the first source-drain conductive layer (ANCE1, VGIL, DCE in FIG. 6) on the second interlayer insulating layer (127) and the second source-drain conductive layer (DL, ANCE2 in FIG. 6) on the first planarization layer (128).

[0255] According to embodiments, in each of the first power supply wire (VDSPL), the second power supply wire (VSSPL), and the plurality of constant voltage supply wires (CVSPL1, CVSPL2, CVSPL3), protrusions (PRO) may be arranged parallel to each other at a portion of the edge of the bypass portion (BYP2, BYP3, BYP4, BYP5, BYP6, BYP7) that overlaps the dam area (DMA) but does not overlap the first main portion (MNP12, MNP13, MNP14, MNP15, MNP16, MNP17) and the second main portion (MNP22, MNP23, MNP24, MNP25, MNP26, MNP27).

[0256] In this way, the length of the gap between the bypass parts (BYP2, BYP3, BYP4, BYP5, BYP6, BYP7) provided in the first power supply wire (VDSPL), the second power supply wire (VSSPL), and the plurality of constant voltage supply wires (CVSPL1, CVSPL2, CVSPL3) and the inorganic insulating material may be further increased, so that the penetration of oxygen or moisture through the periphery of the bypass parts (BYP2, BYP3, BYP4, BYP5, BYP6, BYP7) may be delayed.

[0257] In this way, the lifespan of the display device (10) can be improved.

[0258] As shown in the illustration of FIG. 9, according to embodiments, a first dam section (DM1) surrounding the periphery of the display area (DA) and a second dam section (DM2) surrounding the periphery of the first dam section (DM1) may be arranged in the dam area (DMA).

[0259] Each of the first dam section (DM1) and the second dam section (DM2) may include two or more dam layers (DML11, DML21, DML31, DML41) (DML12, DML22, DML32).

[0260] Each of two or more dam layers (DML11, DML21, DML31, DML41) (DML12, DML22, DML32) may be arranged on the same layer as one of the first planarization layer (128), the second planarization layer (129), the pixel definition layer (132), and the spacer layer (132').

[0261] For example, the first dam section (DM1) may include a first dam layer (DML11) disposed on the same layer as the first planarization layer (128), a second dam layer (DML21) disposed on the same layer as the second planarization layer (129), a third dam layer (DML31) disposed on the same layer as the pixel definition layer (132), and a fourth dam layer (DML41) disposed on the same layer as the spacer layer (132').

[0262] In addition, the second dam portion (DM2) may include a first dam layer (DML12) disposed on the same layer as the second flattening layer (129), a second dam layer (DML22) disposed on the same layer as the pixel definition layer (132), and a third dam layer (DML32) disposed on the same layer as the spacer layer (132').

[0263] The second planarization layer (129) covers the second source-drain conductive layer (MNL21, MNL22) on the first planarization layer (128) and can be spaced apart from at least one dam portion (DM1, DM2) of the dam area (DMA).

[0264] The pixel definition layer (132) can be placed on the second planarization layer (129).

[0265] Accordingly, the second interlayer insulating layer (127) can be in contact with the first sealing layer (141) between the second flattening layer (129) and the first dam section (DM1), between the first dam section (DM1) and the second dam section (DM2), and between the second dam section (DM2) and the second flattening layer (129) in the dam area (DMA).

[0266] According to embodiments, the first sealing layer (141) of the sealing layer (140) may include an inorganic insulating material covering the element layer (130).

[0267] The first sealing layer (141) is disposed in the display area (DA) and can extend to the dam area (DMA) of the non-display area (NDA).

[0268] The second sealing layer (142) may include an organic insulating material diffused within an area surrounded by at least one dam section (DM1, DM2) disposed in a dam area (DMA).

[0269] The third sealing layer (143) may include an inorganic insulating material covering the second sealing layer (142).

[0270] The third sealing layer (143) extends to the dam area (DMA) of the non-display area (NDA) and can come into contact with the first sealing layer (141).

[0271] FIG. 10, FIG. 11 and FIG. 12 are plan views showing portion D of FIG. 7 according to each of the embodiments.

[0272] The display device (10) of one embodiment illustrated in FIG. 10 is substantially the same as the embodiment illustrated in FIGS. 7 to 9, except that the first main portion (MNP11') positioned between one first power wire (VDL) and the bypass portion (BYP1') is in a protruding shape including jig portions (ZG), rather than the bypass portion (BYP1') overlapping with the dam area (DMA) among the power detection wires (VDTL), and therefore, a redundant description thereof is omitted below.

[0273] According to one embodiment of FIG. 10, the bypass portion (BYP1') of the power detection wiring (VDTL) can be arranged in a straight line.

[0274] The bypass portion (BYP1') of the power detection wiring (VDTL) is arranged as at least one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer, and considering that it has a relatively high resistance, static electricity can easily be concentrated.

[0275] In particular, as in one embodiment of FIG. 8, when the bypass section (BYP1) of the power detection wiring (VDTL) includes jig sections (ZG), overheating may occur due to static electricity (ESD of FIG. 17) that is excessively concentrated in the jig section (ZG) of the bypass section (BYP1), which may result in bursting and short circuiting of the bypass section (BYP1). In addition, since an interfacial lifting defect may occur in the surrounding insulating layers at the point where the bursting of the bypass section (BYP1) occurs, a path for oxygen or moisture to penetrate may be created, and thus the lifespan of the display device (10) may be rapidly reduced.

[0276] On the other hand, according to one embodiment of FIG. 10, since the bypass portion (BYP1') of the power detection wiring (VDTL) is arranged in a straight line, even if static electricity (ESD of FIG. 17) is introduced into the bypass portion (BYP1'), it is not excessively dense, so that bursting and short-circuiting defects due to overheating can be reduced. As a result, the lifespan of the display device (10) can be improved.

[0277] In addition, according to one embodiment of FIG. 10, instead of the bypass portion (BYP1') of the power sensing wire (VDTL) being arranged in a straight shape, the first main portion (MNP11') of the power sensing wire (VDTL) is arranged in a protruding shape including jig portions (ZG), so that the resistance of the power sensing wire (VDTL) can be secured to be above the threshold for sensing the voltage level of the first power source (ELVDD).

[0278] According to one embodiment of FIG. 10, in the first direction (DR1), the bypass portion (BYP1') of the power sensing wire (VDTL) may be arranged with a first width (W1), and the jig portions (ZG) of the first main portion (MNP11') of the power sensing wire (VDTL) may be arranged with a first jig width (W_ZG1).

[0279] The display device (10) of one embodiment illustrated in FIG. 11 is substantially the same as the embodiment of FIG. 10, except that, in the first direction (DR1), the bypass portion (BYP1') of the power sensing wire (VDTL) is arranged with a second width (W2) greater than the first width (W1) so as to have lower resistance, and the jig portions (ZG) of the first main portion (MNP11') of the power sensing wire (VDTL) are arranged with a second jig width (W_ZG2) greater than the first jig width (W_ZG1), and thus, a duplicate description thereof is omitted below.

[0280] In this way, since the bypass part (BYP1') of the power detection wiring (VDTL) has lower resistance, the short-circuit failure of the bypass part (BYP1') due to static electricity (ESD in Fig. 17) can be further reduced.

[0281] The display device (10) of one embodiment illustrated in FIG. 12 is substantially the same as the embodiments of FIGS. 10 and 11, except that the protrusions (PRO) are arranged in parallel at a portion of the edge of the bypass portion (BYP1") of the power detection wiring (VDTL) that does not overlap with the first main portion (MNP11') and the second main portion (MNP21), and therefore, a duplicate description thereof is omitted below.

[0282] In this way, the gap between the bypass portion (BYP1") of the power sensing wire (VDTL) and the inorganic insulating material can be made longer, so that the penetration of oxygen or moisture through the periphery of the bypass portion (BYP1") of the power sensing wire (VDTL) can be delayed.

[0283] In this way, the lifespan of the display device (10) can be further improved.

[0284] Fig. 13 is a flowchart showing a method of manufacturing a display device according to embodiments.

[0285] Referring to FIG. 13, a method for manufacturing a display device (10) according to embodiments may include a step (S10) of preparing an inspection panel (100' of FIG. 14), a step (S20) of performing a lighting inspection on the inspection panel (100') using an inspection device (ACNT, BCNT of FIG. 16) connected to inspection connection pads (TPD of FIG. 15) of an inspection pad area (TPDA of FIG. 14) of the inspection panel (100'), a step (S30) of preparing a display panel (100) by removing the inspection pad area (TPDA) of the inspection panel (100'), and a step (S40) of bonding a circuit board (200) to pads (PD) of a sub-area (SBA) of the display panel (100).

[0286] Fig. 14 is a plan view showing an inspection panel during a step of preparing the inspection panel of Fig. 13 according to embodiments. Fig. 15 is a layout diagram showing part F of Fig. 14 according to one embodiment. Figs. 16 and 17 are process diagrams showing a step of performing a lighting inspection of Fig. 13 according to one embodiment.

[0287] Referring to FIG. 14, in the step (S10) of preparing an inspection panel (100' of FIG. 14), the display device (10) according to the embodiments includes an inspection panel (100'), and the inspection panel (100') may include a substrate (110), a circuit layer (120), and a device layer (130).

[0288] The substrate (110) of the inspection panel (100') may include not only a main area (MA) and a sub area (SBA), but may also include a inspection pad area (TPDA) connected to one side of an edge of the sub area (SBA).

[0289] Referring to FIG. 15, the circuit layer (120) of the inspection panel (100') may further include inspection connection pads (TPD) arranged in the inspection pad area (TPDA), and inspection connection wires (CNL) arranged in the inspection pad area (TPDA) and extending from one side of the edge of the sub-area (SBA).

[0290] At least some of the check interconnect lines (CNL) may be connected to the check connection pads (TPD).

[0291] The test connection pads (TPD) can be connected to a connector (ACNT in Fig. 16) of a test device that supplies test signals for lighting tests.

[0292] The test connection wires (CNL) may include a power sense dummy wire (VDTDL) that is connected to a power sense extension wire (VDTEXL).

[0293] The test connection pads (TPD) may include a dummy pad (DMPD) electrically connected to a power sense dummy wire (VDTDL).

[0294] According to one embodiment, the test connection wires (CNL) may further include a first power connection wire (VDCNL) connected to a first power extension wire (VDEXL), a second power connection wire (VSCNL) connected to a second power extension wire (VSEXL), and data connection wires (DTCNL) connected to data extension wires (DTEXL).

[0295] In addition, the test connection pads (TPD) may further include a first power supply pad (VDSPD) electrically connected to the first power connection wire (VDCNL), a second power supply pad (VSSPD) electrically connected to the second power connection wire (VSCNL), and test data supply pads (DTSPD) electrically connected to the data connection wires (DTCNL).

[0296] The first power connection wire (VDCNL) is connected to the first power extension wire (VDEXL) at the boundary between the sub-area (SBA) and the test pad area (TPDA), and can be extended to the first power supply pad (VDSPD).

[0297] The second power connection wire (VSCNL) is connected to the second power extension wire (VSEXL) at the boundary between the sub-area (SBA) and the test pad area (TPDA), and can be extended to the second power supply pad (VSSPD).

[0298] Data connection wires (DTCNL) are connected to data extension wires (DTEXL) at the boundary between the sub-area (SBA) and the test pad area (TPDA) and can be extended to the test data supply pads (DTSPD).

[0299] According to embodiments, the power detection line (VDTL) may be provided in the circuit layer (120) to detect the voltage level of the first power (ELVDD) applied to the first side (SD1) of the display area (DA), and the power detection additional line (VDTAL) may be provided in the circuit layer (120) to detect the voltage level of the first power (ELVDD) applied to the second side (SD2) of the display area (DA). Therefore, the inspection device for lighting inspection does not need to be electrically connected to the power detection line (VDTL) and the power detection additional line (VDTAL).

[0300] According to embodiments, unlike the power detection additional wiring (VDTAL) which is arranged in a relatively long path between the second side (SD2) and the sub-area (SBA), the power detection wiring (VDTL) is arranged in a relatively short path between the first side (SD1) and the sub-area (SBA). However, since the power detection wiring (VDTL) is intended to transmit a signal rather than a power source, it can be arranged in a relatively thin width, and like the power detection additional wiring (VDTAL), it may be vulnerable to a short circuit failure due to electrostatic discharge (ESD) as it includes jigs (ZG) in order to have a resistance higher than a threshold for detecting a voltage level of the first power source (ELVDD).

[0301] Accordingly, according to embodiments, in order to prevent electrostatic discharge (ESD) from being concentrated on the power sensing wire (VDTL), the circuit layer (120) may include a power sensing extension wire (VDTEXL), a power sensing dummy wire (VDTDL), and a dummy pad (DMPD) that are electrically connected to the power sensing wire (VDTL) and the power sensing transfer pad (VDTPD). In this way, electrostatic discharge (ESD) introduced into the power sensing transfer pad (VDTPD) can be discharged toward the power sensing extension wire (VDTEXL), the power sensing dummy wire (VDTDL), and the dummy pad (DMPD).

[0302] Referring to FIG. 16, in the step (S20) of performing a lighting test, the A connector (ACNT) of the test device may be connected to the test connection pads (TPD) of the test pad area (TPDA), and the B connector (BCNT) of the test device may be connected to the pads (PD) of the second sub-area (SB2).

[0303] Accordingly, various test signals of the test device for lighting inspection can be applied to the test connection pads (TPD) connected to the A connector (ACNT) and the pads (PD) connected to the B connector (BCNT).

[0304] However, as shown in the illustration of Fig. 17, when the B connector (BCNT) of the inspection device is connected to the pads (PD) of the second sub-area (SB2), static electricity (ESD) may be introduced to the pads (PD).

[0305] Fig. 18 is a process diagram showing the steps for performing the lighting test of Fig. 13 according to a comparative example.

[0306] As in the comparative example (REF) illustrated in Fig. 18, when the power sensing transfer pad (VDTPD) is connected only to the power sensing wire (VDTL), the electrostatic discharge (ESD) introduced around the power sensing transfer pad (VDTPD) may be concentrated on the power sensing wire (VDTL) through the first electrostatic discharge path (FL1). At this time, since the bypass portion (BYP1) of the power sensing wire (VDTL) is arranged as at least one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer and has a relatively high resistance, the electrostatic discharge (ESD) of the first electrostatic discharge path (FL1) is concentrated on the bypass portion (BYP1) of the power sensing wire (VDTL), so that the bypass portion (BYP1) of the power sensing wire (VDTL) may be overheated, which may result in an open circuit failure (ERR) of the power sensing wire (VDTL).

[0307] On the other hand, as illustrated in FIG. 17, according to one embodiment, a power sensing extension wire (VDTEXL), a power sensing dummy wire (VDTDL), and a dummy pad (DMPD) are included, which are electrically connected to a power sensing wire (VDTL) and a power sensing transfer pad (VDTPD). Accordingly, electrostatic discharge (ESD) introduced around the power sensing transfer pad (VDTPD) can be transmitted to the power sensing wire (VDTL) through a first electrostatic path (FL1), and can also be distributed toward the power sensing extension wire (VDTEXL), the power sensing dummy wire (VDTDL), and the dummy pad (DMPD) through a second electrostatic path (FL2).

[0308] Accordingly, the amount of electrostatic discharge (ESD) flowing into the power sensing wire (VDTL) through the first electrostatic discharge path (FL1) can be reduced, so that the short-circuit failure of the power sensing wire (VDTL) due to electrostatic discharge (ESD) can be reduced.

[0309] FIG. 19 is a layout diagram showing part F of FIG. 14 according to another embodiment.

[0310] The display device (10) of one embodiment illustrated in FIG. 19 is substantially the same as the embodiment illustrated in FIGS. 15, 16, and 17, except that the inspection panel (100') does not include a dummy pad (DMPD) and the power detection dummy wiring (VDTDL) is electrically connected to the first power connection wiring (VDCNL), and therefore, a redundant description thereof is omitted below.

[0311] In this way, electrostatic discharge (ESD) introduced around the power sense transfer pad (VDTPD) can be distributed toward the power sense extension wire (VDTEXL), the power sense dummy wire (VDTDL), the first power connection wire (VDCNL), and the first power supply pad (VDSPD) without having a dummy pad (DMPD).

[0312] Accordingly, the structure of the inspection panel (100') can be simplified since the dummy pad (DMPD) that does not need to be connected to the inspection device can be removed.

[0313] Next, as shown in the illustration of Fig. 7, the display panel (100) can be prepared by removing the inspection pad area (TPDA) from the inspection panel (100'). (S30)

[0314] And, as shown in the illustration of Fig. 1, a display device (10) can be provided by bonding a circuit board (200) to a display panel (100). (S40)

[0315] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Display panel; and A circuit board is included that is bonded to the above display panel, The above display panel includes a substrate; a circuit layer disposed on the substrate; and a device layer disposed on the circuit layer. The above substrate includes a main region and a sub region protruding from one side of the main region, The above main area includes a display area in which light-emitting areas are arranged, and a non-display area arranged around the display area, The above element layer includes light-emitting elements respectively arranged in the light-emitting areas, The above circuit layer is, Light-emitting pixel drivers arranged parallel to each other in the first direction and the second direction and electrically connected to the light-emitting elements respectively; First power wires arranged in the above display area and extending in the second direction and transmitting first power to the light-emitting pixel drivers; A power sensing wire disposed in the non-display area, extending from a first side of the edge of the display area facing the sub-area and adjacent to the sub-area to the sub-area, and electrically connected to a first power wire of one of the first power wires; and A display device including a power detection extension wire electrically connected to the above power detection wire and contacting one side of an edge of the sub-area.

2. In paragraph 1, The circuit layer further includes pads arranged in the sub-area and to which the circuit board is connected, The above pads include a power sensing transmission pad electrically connected to the power sensing wiring, The above power detection wiring is connected to one side of the above power detection transmission pad, The above power detection extension wiring is a display device that extends from the other side of the power detection transmission pad to one side of the edge of the sub-area.

3. In paragraph 2, The circuit layer further includes a power detection additional wiring that is arranged in the non-display area and extends from a second side of the edge of the display area opposite the first side to the sub-area and is electrically connected to another first power wire among the first power wires. The above pads further include a display device including a power detection additional pad electrically connected to the power detection additional wiring.

4. In paragraph 2, a sealing layer disposed on the above element layer; and Further comprising at least one dam section arranged in a dam area surrounding the display area among the non-display areas, The above circuit layer is, A first gate insulating layer disposed on the above substrate; A first gate conductive layer disposed on the first gate insulating layer; A second gate insulating layer covering the first gate conductive layer; A second gate conductive layer disposed on the second gate insulating layer; A first interlayer insulating layer covering the second gate conductive layer; A third gate insulating layer disposed on the first interlayer insulating layer; A third gate conductive layer disposed on the third gate insulating layer; A second interlayer insulating layer covering the third gate conductive layer; A first source-drain conductive layer disposed on the second interlayer insulating layer; A first planarizing layer covering the first source drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and A second planarization layer covering the second source drain conductive layer is included, Among the power detection wiring, the bypass portion overlapping the dam region is disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer, Among the power sensing wires, the first main part, which is arranged between the bypass part and the one first power wire, is arranged on at least one of the first source-drain conductive layer and the second source-drain conductive layer, A display device in which a second main section, which is arranged between the bypass section and the power detection transmission pad among the power detection wiring, is arranged on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

5. In paragraph 4, The above-mentioned bypass part is a display device having a form including jig parts whose extension direction is variable.

6. In paragraph 4, A display device in which a portion of the first main section of the power detection wiring adjacent to the bypass section includes jig sections whose extension direction is variable.

7. In paragraph 6, The total extension length of the above jigs is an indicator device corresponding to the width of the above bypass section.

8. In paragraph 4, The above sealing layer, A first sealing layer disposed on the above element layer; A second sealing layer disposed on the first sealing layer; and A third sealing layer is disposed on the first sealing layer and covers the second sealing layer, Each of the first sealing layer and the third sealing layer comprises an inorganic insulating material, The second sealing layer comprises an organic insulating material disposed within an area surrounded by at least one dam portion, The third sealing layer is a display device that contacts the first sealing layer at the outer edge of the dam area.

9. In paragraph 2, The above substrate further includes a test pad region connected to one side of an edge of the sub-region, The above circuit layer is, Inspection connection pads arranged in the above inspection pad area and to which a connector of an inspection device supplying inspection signals for lighting inspection is connected; and Further comprising inspection connection wires arranged in the inspection pad area and extending from one side of the edge of the sub-area, The above inspection connection wires are a display device including a power detection dummy wire connected to the power detection extension wire.

10. In paragraph 9, The above inspection connection pads are a display device including dummy pads electrically connected to the power detection dummy wiring.

11. In paragraph 9, The above circuit layer is, A first power supply wiring arranged in the non-display area and transmitting the first power; and Further comprising a first power extension wire electrically connected to the first power supply wire and contacting one side of the edge of the sub-area, The above inspection connection wires further include a first power connection wire connected to the first power extension wire, The above inspection connection pads further include a first power supply pad electrically connected to the first power connection wiring, The above power detection dummy wiring is an indicator device electrically connected to the first power connection wiring.

12. Step of preparing the inspection panel; A step of performing a lighting test on the inspection panel using an inspection device connected to the inspection connection pads of the inspection pad area among the inspection panels; A step of removing the inspection pad area from the above inspection panel to prepare a display panel; and Comprising a step of bonding a circuit board to pads of a sub-area of ​​the above display panel, At the stage of preparing the above inspection panel, The above inspection panel comprises: a substrate; a circuit layer disposed on the substrate; and a device layer disposed on the circuit layer. The above substrate is, A main area including a display area in which light-emitting areas are arranged and a non-display area arranged around the display area; and It includes a sub-area protruding from one side of the above main area and having one side connected to the above inspection pad area, The above element layer includes light-emitting elements respectively arranged in the light-emitting areas, The above circuit layer is, Light-emitting pixel drivers arranged parallel to each other in the first direction and the second direction and electrically connected to the light-emitting elements respectively; First power wires arranged in the above display area and extending in the second direction and transmitting first power to the light-emitting pixel drivers; A power sensing wire disposed in the non-display area, extending from a first side of the edge of the display area facing the sub-area and adjacent to the sub-area to the sub-area, and electrically connected to a first power wire of one of the first power wires; A power sensing extension wire electrically connected to the above power sensing wire and contacting one side of the edge of the sub-area; Inspection connection pads arranged in the above inspection pad area; and Including inspection connection wires arranged in the above inspection pad area and extending from one side of the edge of the sub-area, A method for manufacturing a display device, wherein the above inspection connection wires include a power detection dummy wire electrically connected to the power detection extension wire.

13. In paragraph 12, At the stage of preparing the above inspection panel, The circuit layer further includes pads arranged in the sub-area and to which the circuit board is connected, The above pads include a power sensing transmission pad electrically connected to the power sensing wiring, The above power detection wiring is connected to one side of the above power detection transmission pad, A method for manufacturing a display device, wherein the power detection extension wiring extends from the other side of the power detection transmission pad to one side of the edge of the sub-area.

14. In paragraph 13, A method for manufacturing a display device, wherein the above inspection connection pads include dummy pads electrically connected to the power detection dummy wiring.

15. In paragraph 13, At the stage of preparing the above inspection panel, The above circuit layer is, A first power supply wiring arranged in the non-display area and transmitting the first power; and Further comprising a first power extension wire electrically connected to the first power supply wire and contacting one side of the edge of the sub-area, The above inspection connection wires further include a first power connection wire connected to the first power extension wire, A method for manufacturing a display device, wherein the above inspection connection pads further include a first power supply pad electrically connected to the first power connection wiring.

16. In paragraph 15, A method for manufacturing a display device, wherein the above power detection dummy wiring is electrically connected to the above first power connection wiring.

17. In paragraph 13, At the stage of preparing the above inspection panel, The circuit layer further includes a power detection additional wiring that is arranged in the non-display area and extends from a second side of the edge of the display area opposite the first side to the sub-area and is electrically connected to another first power wire among the first power wires. A method for manufacturing a display device, wherein the above pads further include a power detection additional pad electrically connected to the power detection additional wiring.

18. In paragraph 13, In the step of providing the above inspection panel, the inspection panel further includes at least one dam portion arranged in a dam area surrounding the display area among the non-display areas, The above circuit layer is, A first gate insulating layer disposed on the above substrate; A first gate conductive layer disposed on the first gate insulating layer; A second gate insulating layer covering the first gate conductive layer; A second gate conductive layer disposed on the second gate insulating layer; A first interlayer insulating layer covering the second gate conductive layer; A third gate insulating layer disposed on the first interlayer insulating layer; A third gate conductive layer disposed on the third gate insulating layer; A second interlayer insulating layer covering the third gate conductive layer; A first source-drain conductive layer disposed on the second interlayer insulating layer; A first planarizing layer covering the first source drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and A second planarization layer covering the second source drain conductive layer is included, Among the power detection wiring, the bypass portion overlapping the dam region is disposed on one of the first gate conductive layer, the second gate conductive layer and the third gate conductive layer, Among the power sensing wires, the first main part, which is arranged between the bypass part and the one first power wire, is arranged on at least one of the first source-drain conductive layer and the second source-drain conductive layer, A method for manufacturing a display device, wherein a second main section, which is arranged between the bypass section and the power detection transmission pad among the power detection wiring, is arranged on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

19. In paragraph 18, A method for manufacturing a display device, wherein the above-mentioned bypass section includes jig sections whose extension direction is variable.

20. In paragraph 18, A method for manufacturing a display device, wherein a portion of the first main section of the power detection wiring adjacent to the bypass section includes jig sections whose extension direction is variable.

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