Reference unit writing circuit and writing method, and STT-mram

Abstract

A reference unit writing circuit and writing method, and an STT-MRAM. The reference unit writing circuit is adapted to execute a writing operation on a reference unit in an STT-MRAM after the STT-MRAM is powered on and stabilized and before reading from or writing to the STT-MRAM. Using the scheme can reduce the power consumption required for writing to a reference unit.

Description

Reference cell writing circuit, writing method and STT-MRAM

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 11, 2023, with application number 202311701813.9 and invention name “Reference unit write circuit, write method and STT-MRAM”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of memory technology, and in particular to a reference cell writing circuit, a writing method and an STT-MRAM. Background Art

[0003] As a new type of non-volatile memory, magnetic random access memory (MRAM) has the advantages of low power consumption, high reliability, sustainable miniaturization, and compatibility with complementary metal oxide semiconductor (CMOS) processes. It combines the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM), and is considered to be one of the most promising next-generation memories.

[0004] Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a new type of MRAM that writes information via spin current. Specifically, STT-MRAM polarizes current through the fixed layer, generating a spin current. This spin torque is transferred to the magnetic moment of the free layer, causing it to rotate according to the direction of the spin current, thereby writing "0" or "1". The method for reading information is the same as MRAM, also by detecting the resistance of the memory cell to read the stored information.

[0005] Unlike traditional SRAM circuits that store data through high and low potentials, STT-MRAM circuits use spin-polarized currents flowing in different directions through the tunnel junction to drive the change in the magnetization direction of the soft magnetic material, achieving the switching of the high and low impedance states of the magnetic tunnel junction, thereby achieving the purpose of storing data. Therefore, the read operation of the MRAM circuit requires the use of a magnetic tunnel junction (MTJ) that has been written to a high-resistance state or a low-resistance state to form a reference cell. The stored result is obtained by comparing the resistance values ​​of the MTJ in the storage array and the MTJ in the reference cell. The selection and writing of the reference cell determines the accuracy of the read data, so the write circuit of the reference cell is crucial.

[0006] However, the existing reference cell writing method requires high power consumption, resulting in power waste.

[0007] Summary of the Invention

[0008] The problem to be solved by the present invention is to reduce the power consumption required for writing into a reference cell.

[0009] To solve the above problems, an embodiment of the present invention provides a reference cell write circuit suitable for performing a write operation on a reference cell in an STT-MRAM; the reference cell write circuit is suitable for performing a write operation on the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written.

[0010] Optionally, the reference cell writing circuit includes:

[0011] A power-on detection circuit, adapted to detect whether the STT-MRAM is powered on, and generate a power-on stability indication signal and an STT-MRAM start signal after the power-on is stable;

[0012] A write control circuit is connected to the power-on detection circuit and the reference cell in the STT-MRAM, and is adapted to generate a reference cell write control signal based on the power-on stability indication signal and the STT-MRAM start signal; the reference cell write control signal is adapted to perform a write operation on the reference cell in the STT-MRAM.

[0013] Optionally, the write control circuit includes:

[0014] a NOT gate circuit, connected to the power-on detection circuit, and adapted to perform an inversion operation on the STT-MRAM start-up signal output by the power-on detection circuit;

[0015] an AND gate circuit connected to the power-on detection circuit and the NOT gate circuit, and adapted to perform an AND operation on the power-on stability indication signal output by the power-on detection circuit and the output signal of the NOT gate circuit to obtain the write control signal;

[0016] A first switch tube is connected to the AND gate circuit and is adapted to apply a power supply voltage to one end of a reference cell in the STT-MRAM under the control of an output signal of the AND gate circuit;

[0017] and a second switch tube connected to the AND gate circuit, adapted to connect the ground line to one end of the reference unit in the STT-MRAM under the control of the output signal of the AND gate circuit.

[0018] Optionally, the power-on stability indication signal is converted from a low level to a high level at a first moment after power-on stabilization, and the STT-MRAM start-up signal is converted from a low level to a high level at a second moment after power-on stabilization, the first moment is earlier than the second moment, and the difference between the first moment and the second moment is greater than or equal to the pulse width of the write control signal.

[0019] An embodiment of the present invention further provides an STT-MRAM, comprising any one of the above-mentioned reference cell write circuits.

[0020] Optionally, the STT-MRAM further includes:

[0021] Storage arrays;

[0022] a plurality of reference cells connected to the reference cell writing circuit;

[0023] The timing logic circuit is connected to the memory array and the reference unit and is suitable for providing timing signals required for the memory array and the reference unit to work.

[0024] Optionally, the power-on detection circuit is connected to the sequential logic circuit and is adapted to output the STT-MRAM start-up signal to the sequential logic circuit to control the sequential logic circuit to output a corresponding timing signal.

[0025] Optionally, all reference cells in the STT-MRAM share the same reference cell write circuit.

[0026] An embodiment of the present invention further provides a reference cell writing method, which is suitable for performing a write operation on a reference cell in an STT-MRAM. The method includes:

[0027] After the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written, a write operation is performed on a reference cell in the STT-MRAM.

[0028] Optionally, after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written, performing a write operation on a reference cell in the STT-MRAM includes:

[0029] Detecting whether the STT-MRAM is powered on, and generating a power-on stability indication signal and an STT-MRAM start signal after the power-on is stable;

[0030] Based on the power-on stability indication signal and the STT-MRAM start-up signal, a reference cell write control signal is generated; the reference cell write control signal is suitable for performing a write operation on the reference cell in the STT-MRAM.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0032] By applying the solution of the present invention, the reference cell write circuit can perform a write operation on the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written. Compared with a solution in which the reference cell is written at the same time as each write operation on the storage cell, the write operation only needs to be performed on the reference cell during the power-on startup phase. When the write operation is performed on the storage cell after power-on, there is no need to perform a write operation on the reference cell at the same time. This can reduce the power consumption required for performing the write operation on the reference cell and save the time required for writing the reference cell.

[0033] Furthermore, by setting a power-on detection circuit to generate a power-on stability indication signal and an STT-MRAM start-up signal after power-on is stable, the write control circuit can generate a reference cell write control signal based on the power-on stability indication signal and the STT-MRAM start-up signal. As a result, the reference cell can be written during the power-on startup phase after the STT-MRAM is shipped from the factory. There is no need to reserve PADs and I / Os in the design phase, thereby effectively reducing the circuit area introduced by the reference cell write, and performing the write operation on the reference cell more conveniently and quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic structural diagram of a reference unit writing circuit according to an embodiment of the present invention;

[0035] FIG2 is a timing diagram of related signals in a reference unit write circuit according to an embodiment of the present invention;

[0036] FIG3 is a schematic structural diagram of an STT-MRAM according to an embodiment of the present invention;

[0037] FIG4 is a schematic structural diagram of an STT-MRAM readout circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Traditional reference cell programming is achieved through a one-time write configuration after shipment. This method requires pre-designing write pads (PADs) and input / output terminals (I / Os) during the design phase. After shipment, a one-time write configuration is performed using the PADs and I / Os to set the reference cell to the desired high-impedance or low-impedance state. Subsequently, no further write operations are performed on these PADs.

[0039] Due to the need to introduce additional PAD and I / O, even under advanced processes, the area of ​​IO and PAD still accounts for a large proportion, and the reference unit is generally composed of multiple MTJs in series and parallel. Each reference unit requires multiple IO and PAD, which adds a lot of additional area.

[0040] There is also a method of using dedicated reference cell write commands to write configurations to reference cells after leaving the factory. Although this method reduces the area of ​​the reference cell write circuit, it is time-consuming and increases system costs.

[0041] There is a reference cell writing method that selects a reference cell for a write operation based on the output of a row decoding circuit and an output of a column decoding circuit, thereby programming the reference cell while performing a write operation on the memory cell without requiring a dedicated reference cell write command.

[0042] However, this approach involves programming the reference cell simultaneously with each write operation to the memory cell. Since MRAM write operations require a large write current and take a long time, write power consumption is high. If the reference cell is programmed during each write operation, a large amount of power would be wasted.

[0043] Furthermore, because MRAM read operations require comparing the resistance of the MTJ in the storage cell with that of the reference cell, a first write pass is required before a read operation can be performed. This limits MRAM's application in areas such as physically unclonable functions (PUFs). PUFs exploit the disorder in device characteristics caused by manufacturing uncertainty / variability to produce unique and unpredictable outputs when stimulated by inputs, allowing for direct reading without requiring a write operation in applications.

[0044] To address this problem, the present invention provides a reference cell write circuit. By using this reference cell write circuit, a write operation can be performed on the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written. Since the write operation only needs to be performed on the reference cell during the power-on startup phase, when the write operation is performed on the storage cell after power-on, there is no need to perform a write operation on the reference cell at the same time. This can reduce the power consumption required to perform the write operation on the reference cell and save the time required to write the reference cell.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] 1 , an embodiment of the present invention further provides a reference cell write circuit 10 , which is suitable for performing a write operation on a reference cell in an STT-MRAM.

[0047] Different from the existing reference cell writing scheme, in the embodiment of the present invention, the reference cell writing circuit is suitable for performing a write operation on the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written.

[0048] The term "power-on stability of the STT-MRAM" refers to the state where the power supply voltage of the STT-MRAM gradually increases from a minimum value to a fixed value and then remains constant. The term "before reading or writing the STT-MRAM" refers to the state before performing a read or write operation on the first memory cell in the STT-MRAM.

[0049] In a specific implementation, the reference cell write circuit 10 may perform a write operation on the reference cell in the STT-MRAM immediately after the STT-MRAM is powered on and stabilized, or may perform a write operation on the reference cell in the STT-MRAM after a period of time has passed since the STT-MRAM was powered on and stabilized. The timing of performing the write operation on the reference cell is not limited, as long as it can be completed before performing a read or write operation on the first memory cell in the STT-MRAM.

[0050] In a specific implementation, the reference cell writing circuit 10 may have various structures, which are not limited here.

[0051] In one embodiment of the present invention, referring to FIG1 , the reference cell write circuit 10 includes: a power-on detection circuit 101 and a write control circuit 102 .

[0052] The power-on detection circuit 101 is adapted to detect whether the STT-MRAM is powered on, and generate a power-on stability indication signal pdb and an STT-MRAM start signal mram_en after the power-on is stable;

[0053] The write control circuit 102 is connected to the power-on detection circuit 101 and the reference cell in the STT-MRAM, and is adapted to generate a reference cell write control signal ref-ctrl based on the power-on stability indication signal pdb and the STT-MRAM enable signal mram_en; the reference cell write control signal ref-ctrl is adapted to perform a write operation on the reference cell in the STT-MRAM.

[0054] During the actual power-on process, the power supply voltage value of the STT-MRAM gradually increases from a low level to a high level and remains at a high level. The power-on detection circuit 101 can determine whether the STT-MRAM is powered on by detecting the power supply voltage value of the STT-MRAM. When the power-on detection circuit 101 detects that the power supply voltage value of the STT-MRAM is at a low level, it indicates that the STT-MRAM is not powered on. When the power-on detection circuit 101 detects that the power supply voltage value of the STT-MRAM gradually increases, it indicates that the STT-MRAM is powered on. When the power-on detection circuit 101 detects that the power supply voltage value of the STT-MRAM remains at a high level, it indicates that the power-on of the STT-MRAM is stable.

[0055] When the STT-MRAM is powered on and stable, the power-on detection circuit 101 can generate a power-on stability indication signal pdb and an STT-MRAM start signal mram_en. The write control circuit 102 can generate a reference cell write control signal ref-ctrl based on the power-on stability indication signal pdb and the STT-MRAM start signal mram_en.

[0056] In a specific implementation, the write control circuit 102 can adopt a variety of circuit structures to generate the reference cell write control signal ref-ctrl, as long as it can complete the write operation of the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written.

[0057] In one embodiment of the present invention, referring to FIG1 , the write control circuit 102 includes: a NOT gate circuit 102a, an AND gate circuit 102b, a first switch tube Q1, and a second switch tube Q2.

[0058] The NOT gate circuit 102a is connected to the power-on detection circuit 101 and is adapted to perform an inversion operation on the STT-MRAM enable signal mram_en output by the power-on detection circuit 101;

[0059] The AND gate circuit 102b is connected to the power-on detection circuit 101 and the NOT gate circuit 102a, and is adapted to perform an AND operation on the power-on stability indication signal pdb output by the power-on detection circuit 101 and the output signal mram_en of the NOT gate circuit 102a to obtain the write control signal ref-ctrl;

[0060] The first switch Q1 is connected to the AND gate circuit 102b and is adapted to apply the power supply voltage VDD to one end of the reference cell in the STT-MRAM under the control of the output signal ref-ctrl of the AND gate circuit 102b;

[0061] The second switch Q2 is connected to the AND gate circuit 102b and is adapted to connect the ground line GND to one end of the reference cell in the STT-MRAM under the control of the output signal ref-ctrl of the AND gate circuit 102b.

[0062] In a specific implementation, the power-on detection circuit 101 has a power supply voltage connection terminal, a ground terminal, a first output terminal, and a second output terminal.

[0063] The power supply voltage connection terminal is connected to the power supply voltage output terminal, thereby detecting the power supply voltage value output by the power supply voltage output terminal. In addition, the power supply voltage connection terminal is also connected to one end of the first switch tube Q1, so that the power supply voltage can be applied to one end of the reference unit when the first switch tube Q1 is turned on.

[0064] The ground terminal is connected to the ground wire for grounding related components in the power-on detection circuit 102. At the same time, the ground terminal is also connected to one end of the second switch tube Q2, so that one end of the reference unit can be grounded when the second switch tube Q2 is turned on.

[0065] The first output terminal outputs a power-on stability indication signal pdb, and the second output terminal outputs an STT-MRAM enable signal mram_en. The NOT gate circuit 102a inverts the STT-MRAM enable signal mram_en and inputs it to one input terminal of the AND gate circuit 102b. The other input terminal of the AND gate circuit 102b receives the power-on stability indication signal pdb. As a result, the write control signal ref-ctrl is at a high level when the power-on stability indication signal pdb is high and the STT-MRAM enable signal mram_en is low, and is at a low level otherwise.

[0066] In a specific implementation, the first switch Q1 and the second switch Q2 can both be MOS transistors, or insulated gate bipolar transistors (IGBTs), or other semiconductor devices. In an embodiment of the present invention, the first switch Q1 and the second switch Q2 are both NMOS transistors.

[0067] Regardless of the type of switching devices used by the first switching tube Q1 and the second switching tube Q2, the control ends of the first switching tube Q1 and the second switching tube Q2 are connected to the output end of the gate circuit 102b, one end is connected to the power-on circuit, and the other end is connected to the reference unit. As a result, they can be turned on or off under the control of the write control signal ref-ctrl to perform a write operation on the reference unit.

[0068] Figure 2 is a timing diagram of the relevant signals in the reference cell write circuit. Referring to Figure 2, the power-on detection circuit sets the power-on stability indicator signal (pdb) high after the STT-MRAM is powered on and stabilized. A period of time later, the STT-MRAM enable signal (mram_en) is set high. The STT-MRAM enable signal (mram_en) is inverted and then ANDed with the power-on stability indicator signal (pdb), ultimately generating the reference cell write control signal (ref-ctrl). This reference cell write control signal (ref-ctrl) is applied to the reference cell's MTJ by turning on the first and second switches (Q1, Q2), applying the power supply voltage (VDD) and ground (GND) to the reference cell's MTJ, achieving the write operation.

[0069] 2 , assuming that the power-on stability indication signal pdb is converted from a low level to a high level at a first time t1 after power-on stabilization, and the STT-MRAM enable signal mram_en is converted from a low level to a high level at a second time t2 after power-on stabilization, the first time t1 is earlier than the second time t2, and the difference between the first time t1 and the second time t2 is greater than or equal to the pulse width of the write control signal ref-ctrl, thereby allowing the write control signal ref-ctrl to have sufficient time to ensure the correct writing of the reference cell.

[0070] After the write control signal ref-ctrl is converted from a low level to a high level, the reference cell starts to be written, so that the resistance value of the reference cell has high and low changes.

[0071] In a specific implementation, the STT-MRAM enable signal mram_en can be input into the sequential logic circuit in the STT-MRAM to control the STT-MRAM's start-up, ensuring that the STT-MRAM completes writing to the reference cell before reading or writing. At the same time, operating the MRAM circuit after power-on is stable also increases circuit reliability.

[0072] By adopting the solution of the present invention, even for a complex reference cell structure, only a few MOS tubes need to be added as switches to complete writing during the power-on phase, effectively reducing the area introduced by the reference cell writing circuit, and without increasing subsequent read and write time and power consumption, it is possible to conveniently and quickly perform writing operations on the reference cell.

[0073] 3 , an embodiment of the present invention provides an STT-MRAM, which may include the reference cell write circuit 10 in the above embodiment.

[0074] In a specific implementation, the STT-MRAM may further include: a memory array 201, multiple reference cells 202, and a sequential logic circuit 203. The sequential logic circuit 203 is connected to the memory array 201 and the multiple reference cells 202 and is suitable for providing the timing signals required for the operation of the memory array 201 and the multiple reference cells 202. The memory array 201, the multiple reference cells 202, and the sequential logic circuit 203 constitute the MRAM main circuit 20 in the STT-MRAM.

[0075] In a specific implementation, the memory array 201 includes a plurality of memory cells arranged in an array. The memory cells are used to store data information. The number of reference cells 202 can be two or more. The reference cells 201 are used to provide a reference voltage (or reference current) when reading data from the memory cells.

[0076] In a specific implementation, the memory cell 11 of the STT-MRAM is mainly composed of an MTJ and an NMOS transistor connected in series. The MTJ is used to store data information, and the magnetic field polarization direction of its free layer can be flipped through the spin transfer torque (STT) effect, so that the MTJ has different resistance states. More specifically, when the relative magnetic field polarization directions of the free layer and the fixed layer are parallel, the MTJ exhibits a low resistance state. When the relative magnetic field polarization directions of the free layer and the fixed layer are antiparallel, the MTJ exhibits a high resistance state. Therefore, the MTJ can be simply regarded as a variable resistor. The NMOS transistor is used to control access to the memory cell. For example, referring to Figure 4, the memory cell 201a may include: a first MTJ R1 and a first NMOS transistor N1.

[0077] In a specific implementation, the reference cell 202 of the STT-MRAM is primarily composed of one or more MTJs and an NMOS transistor connected in series. For example, referring to FIG4 , the reference cell 202 may include a second MTJ R2 and a second NMOS transistor N2. The second MTJ R2 may be the equivalent resistance of one or more MTJs.

[0078] The STT-MRAM may also include a word line selector and a column selector, which may set the word line and column select signals connected to the storage cell to be read and the corresponding reference cell to a high level, so that the corresponding storage cell or reference cell is in a conductive state. Other word lines and column select signals are set to a low level, so that the corresponding storage cell or reference cell is in a non-conductive state and cannot perform any operation. Each storage cell and reference cell can be uniquely identified by a word line (WL) and a column select signal (cs). The storage cell to be read and the corresponding reference cell are selected by the word line and column select signals.

[0079] The timing logic circuit 2023 can provide the STT-MRAM with the timing signals required for operation, such as control signals for word line selectors and column selectors, readout circuit drive signals, precharge signals, etc. The STT-MRAM may also include a readout circuit, which can use a sense amplifier to connect to the memory array and reference cell, and obtain the stored result by comparing the resistance of the MTJ in the memory array and the reference cell.

[0080] As shown in FIG4 , one end of the storage unit 201 a and one end of the reference unit 202 are respectively connected to the symmetrical ends of the sense amplifier SA through a pair of column selection tubes. The gate of one column selection tube in the pair of column selection tubes is connected to the column selection signal cs, and the gate of the other column selection tube is connected to the inverted signal csn of the column selection signal.

[0081] When a memory cell 11 needs to be read, one end of the MTJ in the memory cell 201a and the reference cell 202 is connected to a low potential, and the other end is connected to the corresponding switch tube. The word line control signal WL of the memory cell 201a and the gate tube control signal ref-WL of the reference cell 202 are high, and the column select read control signal cs is valid. The difference between the currents on the two paths (i.e., the current value Iread on the memory cell path and the current value Iref on the reference cell path) is amplified by the sensitive amplifier to achieve the purpose of fast reading.

[0082] In a specific implementation, the reference cell write circuit 10 performs a write operation on the reference cell 21 before the read circuit performs a read or write operation on the memory cell, so that the resistance value of the reference cell is written to a desired value for subsequent comparison.

[0083] In a specific implementation, the STT-MRAM may be provided with only one reference cell write circuit 10, and the write operation of all reference cells of the STT-MRAM may be controlled by the unique reference cell write circuit 10, thereby maximally saving the circuit area introduced by the reference cell write.

[0084] In other embodiments, the STT-MRAM may also be provided with two or more reference cell write circuits 10, and each reference cell write circuit 10 performs a write operation on part of the reference cells respectively, thereby improving the reference cell write efficiency.

[0085] By using the reference cell write circuit of the embodiment of the present invention, the reference cell write operation is performed during the power-on startup phase without affecting the normal reading and writing of the subsequent MRAM circuit. The circuit design is flexible, does not increase the write power consumption, is easy to implement and has high flexibility.

[0086] In order to enable those skilled in the art to better understand and implement the present invention, the method corresponding to the reference unit writing circuit is described in detail below.

[0087] An embodiment of the present invention provides a reference cell writing method, which may include:

[0088] After the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written, a write operation is performed on a reference cell in the STT-MRAM.

[0089] In a specific implementation, after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written, performing a write operation on a reference cell in the STT-MRAM may include:

[0090] Detecting whether the STT-MRAM is powered on, and generating a power-on stability indication signal and an STT-MRAM start signal after the power-on is stable;

[0091] Based on the power-on stability indication signal and the STT-MRAM start-up signal, a reference cell write control signal is generated; the reference cell write control signal is suitable for performing a write operation on the reference cell in the STT-MRAM.

[0092] In a specific implementation, whether the power-on stability is determined by detecting the power supply voltage of the STT-MRAM, and after the power-on stability is determined, a power-on stability indication signal and an STT-MRAM start-up signal are generated, and a reference cell write control signal is generated based on the power-on stability indication signal and the STT-MRAM start-up signal.

[0093] In a specific implementation, when the power-on stability indication signal pdb is at a high level and the STT-MRAM start signal mram_en is at a low level, the write control signal ref-ctrl can be set to a high level; otherwise, the write control signal ref-ctrl can be set to a low level, thereby performing a write operation on the reference cell in the STT-MRAM after the STT-MRAM is powered on and stabilized and before the STT-MRAM is read or written.

[0094] The reference cell writing method of the present invention not only saves the extra time required for reference cell writing, but also does not increase write power consumption, and the circuit is simple and easy to implement. Furthermore, writing to the reference cell during each power-up phase eliminates the need for subsequent write operations, making it more suitable for applications in fields such as PUFs.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A reference cell writing circuit, adapted to perform a writing operation on a reference cell in an STT-MRAM; characterized in that, The reference cell writing circuit is adapted to perform a writing operation on the reference cells in the STT-MRAM after the STT-MRAM is powered on and stabilized and before reading and writing the STT-MRAM.

2. The reference cell writing circuit according to claim 1, characterized in that, The reference cell writing circuit includes: A power-on detection circuit, adapted to detect whether the STT-MRAM is powered on, and generate a power-on stabilization indication signal and an STT-MRAM enable signal after power-on stabilization; A writing control circuit, connected to the power-on detection circuit and the reference cells in the STT-MRAM, adapted to generate a reference cell writing control signal based on the power-on stabilization indication signal and the STT-MRAM enable signal; the reference cell writing control signal is adapted to perform a writing operation on the reference cells in the STT-MRAM.

3. The reference cell writing circuit according to claim 2, characterized in that, The writing control circuit includes: A NOT gate circuit, connected to the power-on detection circuit, adapted to perform an inversion operation on the STT-MRAM enable signal output by the power-on detection circuit; An AND gate circuit, connected to the power-on detection circuit and the NOT gate circuit, adapted to perform an AND operation on the power-on stabilization indication signal output by the power-on detection circuit and the output signal of the NOT gate circuit to obtain the writing control signal; A first switching transistor, connected to the AND gate circuit, adapted to apply a power supply voltage to one end of the reference cells in the STT-MRAM under the control of the output signal of the AND gate circuit; And a second switching transistor, connected to the AND gate circuit, adapted to connect the ground wire to one end of the reference cells in the STT-MRAM under the control of the output 4. The reference cell writing circuit according to claim 2, characterized in that, signal of the AND gate circuit.

5. An STT-MRAM, characterized in that, The power-on stabilization indication signal changes from a low level to a high level at a first moment after power-on stabilization, the STT-MRAM enable signal changes from a low level to a high level at a second moment after power-on stabilization, the first moment is earlier than the second moment, and the difference between the first moment and the second moment is greater than or equal to the pulse width of the writing control signal.

6. The STT-MRAM according to claim 5, characterized in that, Including the reference cell writing circuit according to any one of claims 1 to 4. The STT-MRAM further includes: A storage array; A plurality of reference cells, connected to the reference cell writing circuit; 7. The STT-MRAM according to claim 6, characterized in that, A timing logic circuit, connected to the storage array and the reference cells, adapted to provide timing signals required for the operation of the storage array and the reference cells.

8. The STT-MRAM according to claim 5, characterized in that, The power-on detection circuit is connected to the timing logic circuit, adapted to output the STT-MRAM enable signal to the timing logic circuit to control the timing logic circuit to output corresponding timing signals.

9. A reference cell writing method, adapted to perform a writing operation on a reference cell in an STT-MRAM, characterized in that, All the reference cells in the STT-MRAM share the same reference cell writing circuit. The method includes:

10. The reference cell writing method according to claim 9, characterized in that, Performing a writing operation on the reference cells in the STT-MRAM after the STT-MRAM is powered on and stabilized and before reading and writing the STT-MRAM. The performing a writing operation on the reference cells in the STT-MRAM after the STT-MRAM is powered on and stabilized and before reading and writing the STT-MRAM includes: Detect whether the STT-MRAM is powered on, and after the power-on is stable, generate a power-on stable indication signal and an STT-MRAM enable signal; Based on the power-on stable indication signal and the STT-MRAM enable signal, generate a reference cell write control signal; the reference cell write control signal is suitable for performing a write operation on the reference cell in the STT-MRAM.

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