Semiconductor integrated circuit device

Abstract

In the present invention, a standard cell comprises: an active region (2N1) that has an overlap with an active region (2P1) in plan view; power supply wiring (11) that is formed in a back surface wiring layer; and a via (61) that is formed in a region where a region serving as a source of a transistor (P1) in the active region (2P1) and the power supply wiring (11) overlap and connects the source in the active region (2P1) and the power supply wiring (11). Nanosheets (21), (22) have each a surface exposed from gate wiring (31) on a first side that is one side in a second direction, and are disposed close to an end on the first side of the standard cell.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses a standard cell using a complementary FET (CFET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device. In Patent Document 1, wiring is provided on the back surface directly below the transistor, and the source and drain of the transistor are connected to this wiring.

[0005] Patent Document 2 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a fork-shaped gate electrode, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 2 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0006] US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0246644

[0007] However, with regard to standard cells using CFETs, no specific study has yet been made on the layout structure of standard cells using fork-sheet transistors instead of nanosheet transistors as transistors.

[0008] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, with respect to standard cells using CFETs.

[0009] In a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first active region including a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding the outer periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed on the back side of the first transistor and extending in the first direction, for supplying a first power supply voltage; and a first via formed in a region where a region serving as the source of the first transistor in the first active region overlaps with the first power supply wiring, for connecting the source of the first transistor in the first active region with the first power supply wiring, wherein the first and second nanosheets have a first side surface, which is one side in the second direction, exposed from the first gate wiring, and are arranged in proximity to an end of the first side of the first standard cell.

[0010] According to the present disclosure, the first and second nanosheets have their first-side surfaces exposed from the first gate wiring and are arranged close to the first-side end of the first standard cell, thereby reducing the distance between the active region of the standard cell arranged on the first side of the first standard cell and the first and second active regions, thereby enabling a reduction in the area of ​​the semiconductor integrated circuit device.

[0011] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first active region including a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel including a second nanosheet extending in the first direction; a first gate wiring extending in a second direction forming a first gate wiring and surrounding the outer periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed on the back side of the first transistor and extending in the first direction, for supplying a first power supply voltage; and a first via formed in a region where a region serving as a source of the first transistor in the first active region overlaps with the first power supply wiring, for connecting the source of the first transistor in the first active region with the first power supply wiring, wherein a first side surface of the first and second nanosheets, which is one side in the second direction, is exposed from the first gate wiring, and the first power supply wiring is disposed in the center of the first standard cell in the second direction.

[0012] According to the present disclosure, when first standard cells are arranged in a first direction and a second direction, the first power supply wiring that is continuous in the first direction is evenly arranged in the second direction, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0013] In a third aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell and a fourth standard cell arranged side by side in a first direction, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, and the channel comprises: a first active region including a first nanosheet extending in the first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, and constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel comprising a second nanosheet extending in the first direction; and a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, and surrounding the outer periphery of the first and second nanosheets in the second direction and the depth direction; and the fourth standard cell constitutes a channel, a source, and a drain of a seventh transistor of the first conductivity type, and the channel comprises: a first active region including a first nanosheet extending in the first direction; the seventh active region including a seventh nanosheet extending in the first direction; an eighth active region formed higher than the seventh active region in the depth direction and overlapping with the seventh active region in a plan view, and constituting the channel, source, and drain of the eighth transistor of the second conductivity type, the eighth active region including an eighth nanosheet extending in the first direction as the channel; and a fifth gate wiring extending in the second direction and surrounding the outer peripheries of the seventh and eighth nanosheets in the second direction and the depth direction, wherein the first and second nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first gate wiring, and the seventh and eighth nanosheets have first-side surfaces exposed from the fifth gate wiring, wherein the width of the seventh nanosheet in the second direction is smaller than the width of the first nanosheet in the second direction, and wherein the end of the first nanosheet and the end of the seventh nanosheet on the first side are arranged at the same position in the second direction in a plan view.

[0014] According to the present disclosure, in the layout of a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, it is possible to reduce the area of ​​the semiconductor integrated circuit device, suppress a drop in power supply voltage, and increase the speed, with respect to standard cells using CFETs.

[0015] 1. A plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment. 2. A plan view showing an example of the layout structure of an inverter cell according to an embodiment. 3. A cross-sectional view of the inverter cell of FIG. 2. 4. A circuit diagram of the inverter cell of FIG. 2. 5. Another configuration example of a semiconductor integrated circuit device according to an embodiment. 6. A plan view showing an example of the layout structure of an inverter cell according to a modified example of an embodiment. 7. A plan view showing an example of the layout structure of a two-input NAND cell included in a semiconductor integrated circuit device. 8. A plan view showing an example of the layout structure of a two-input NOR cell included in a semiconductor integrated circuit device. 9. A circuit diagram of the standard cell of FIGS. 7 and 8.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include fork sheet transistors with fork-shaped gate electrodes, which are nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0017] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0018] 1A and 1B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment. Specifically, FIG. 1A shows the lower part of a cell, i.e., the part including a fork sheet transistor formed on the side closer to the substrate, and FIG. 1B shows the upper part of a cell, i.e., the part including a fork sheet transistor formed on the side farther from the substrate.

[0019] 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and in an M0 wiring layer, which is a metal wiring layer above the transistors.

[0020] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0021] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0022] In the layout of FIG. 1, a plurality of cells aligned in the X direction constitute a cell column CR (CR1 to CR3). A plurality of cell columns CR (three columns in FIG. 1) are aligned in the Y direction. The plurality of cells includes cells with logic functions such as inverters, NAND gates, and NOR gates. The plurality of cells includes, for example, inverter cells C1 and C4, two-input NAND cells C2 and C5, and two-input NOR cells C3 and C6, which will be described later.

[0023] In each cell, power supply wiring is formed in the BM0 wiring layer and the M0 wiring layer in the center of the drawing in the Y direction. Specifically, a power supply wiring (power supply wiring 11 described later) that supplies a power supply voltage VDD is formed in the BM0 wiring layer, and a power supply wiring (power supply wiring 51 described later) that supplies a power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. Each cell row CR is arranged inverted in the Y direction for every other row. In the center of the drawing of the cell row CR, the power supply wiring that supplies VDD is continuous in the X direction, and the power supply wiring that supplies VSS is continuous in the X direction. As a result, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0024] An active region 2P that forms the channel, source, and drain of a P-type transistor is formed at the bottom of each cell. An active region 2N that forms the channel, source, and drain of an N-type transistor is formed at the top of each cell. In a cell row CR, the active regions 2P are arranged side by side in the X direction, and the active regions 2N are arranged side by side in the X direction.

[0025] As will be described in more detail later, in the standard cells arranged in cell row CR1, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR2, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR3, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction not exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. That is, in the block layout of FIG. 1, in cells adjacent in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring facing each other in the Y direction, and their surfaces not exposed from the gate wiring facing each other in the Y direction. Specifically, the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR1 and the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR2 have surfaces that face each other in the Y direction exposed from the gate wiring. The nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR2 and the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR3 have surfaces that face each other in the Y direction not exposed from the gate wiring. This allows the distance d1 between the active regions 2P (2N) of the standard cells arranged in cell row CR1 and the active regions 2P (2N) of the standard cells arranged in cell row CR2 to be reduced, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced. In other words, the distance d1 between the active area 2P (2N) of the standard cell arranged in cell row CR1 and the active area 2P (2N) of the standard cell arranged in cell row CR2 is smaller than the distance d2 between the active area 2P (2N) of the standard cell arranged in cell row CR2 and the active area 2P (2N) of the standard cell arranged in cell row CR3.

[0026] Furthermore, the standard cells arranged in cell row CR1 have the lower ends of their active regions 2P (2N) arranged at the same position in the Y direction. The standard cells arranged in cell row CR2 have the upper ends of their active regions 2P (2N) arranged at the same position in the Y direction. The standard cells arranged in cell row CR3 have the lower ends of their active regions 2P (2N) arranged at the same position in the Y direction. That is, in cell row CR1, the lower ends of the active regions 2P (2N) in the Y direction are aligned. In cell row CR2, the upper ends of the active regions 2P (2N) in the Y direction are aligned. In cell row CR3, the lower ends of the active regions 2P (2N) in the Y direction are aligned. Furthermore, in the standard cells arranged in cell row CR1, the nanosheets included in the active regions 2P (2N) have the lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR2, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR3, the nanosheets included in the active region 2P (2N) have their lower surface in the Y direction exposed from the gate wiring. That is, in the standard cells arranged in cell row CR1, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. In the standard cells arranged in cell row CR2, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. In the standard cells arranged in cell row CR3, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing a structure made of an insulator between them. 1, in a cell row in which standard cells are arranged in the X direction, the position of the surface of the nanosheet exposed from the gate wiring can be aligned in the Y direction, thereby making it possible to make the shape of the structure, i.e., the size and layout area in the Y direction, constant, which facilitates the manufacture of semiconductor integrated circuit devices.

[0027] (Configuration of Inverter Cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C4 according to the embodiment, Fig. 3 is a cross-sectional view showing an example of the layout structure of the inverter cell according to the embodiment, and Fig. 4 is a circuit diagram configured in the inverter cell according to the embodiment. Specifically, Fig. 2(a) shows the lower part of inverter cell C1, Fig. 2(b) shows the upper part of inverter cell C1, Fig. 2(c) shows the lower part of inverter cell C4, Fig. 2(d) shows the upper part of inverter cell C4, Fig. 3(a) is a cross-section taken along X1-X1' in Figs. 2(a) and 2(b), Fig. 3(b) is a cross-section taken along Y1-Y1' in Figs. 2(a) and 2(b), Fig. 3(c) is a cross-section taken along Y2-Y2' in Figs. 2(a) and 2(b), and Fig. 3(d) is a cross-section taken along Y3-Y3' in Figs. 2(a) and 2(b).

[0028] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 3 and the dashed lines running vertically in cross-sectional views such as FIG. 3 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0029] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit having an input A and an output Y is configured.

[0030] 2A, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, a power supply wiring 11 extending in the X direction is formed at the center of the cell in the Y direction of the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0031] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0032] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0033] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0034] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has, as a channel, a nanosheet 22 having a structure of three overlapping sheets in a plan view and extending in the X direction.

[0035] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0036] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0037] 3(c), the gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so that part of the outer peripheries of the nanosheets 21 and 22 are exposed. Specifically, the right-hand side surfaces of the nanosheets 21 and 22 in the drawing are not covered by the gate wiring 31. That is, the right-hand side surfaces of the nanosheets 21 and 22 in the drawing are exposed from the gate wiring 31. Therefore, in FIG. 2, the lower sides of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper sides of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0038] 2, dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0039] 2A, a local interconnect (LI) 41 extending in the Y direction is formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that will become the drain of the transistor P1.

[0040] 2B, a local wiring 42 extending in the Y direction is formed above the cell. The local wiring 42 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0041] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, a power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0042] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N1 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N1 that will become the source of the transistor N1 through a via 62 and a local wiring. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N1 overlap in plan view.

[0043] The wiring 52 is disposed on the lower side in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N1 overlap in a plan view.

[0044] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64 and 65 and local wirings 41 and 42.

[0045] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0046] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0047] In the inverter cell C1 shown in FIG. 2, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row CR is arranged in a flipped orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d3 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P1 and 2N1 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0048] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d3 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P1 (2N1) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P1 (2N1) is positioned closer to the lower end of the cell frame in the Y direction, based on the center of the cell frame in the Y direction. That is, in a planar view, the center of the active region 2P1 (2N1) in the Y direction is lower than the center of the cell frame in the Y direction.

[0049] Furthermore, the power supply wiring 11, 51 is formed in the center of the cell in the Y direction in plan view. That is, the center of the active region 2P1 (2N1) in the Y direction is located below the center of the power supply wiring 11 (51) in the Y direction. By arranging the inverter cell C1 in the circuit block of FIG. 1, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in the power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0050] Furthermore, the via 61 connects the power supply wiring 11 and a portion of the active region 2P1 that serves as the source of the transistor P1. In plan view, the center of the via 61 in the Y direction is located at the same position as the center of the power supply wiring 11 in the Y direction. That is, when the center of the active region 2P1 in the Y direction is used as a reference, the via 61 is located closer to the upper end of the active region 2P1 in the Y direction (the side where the nanosheet 21 is not exposed from the gate wiring 31). In other words, the center of the via 61 in the Y direction is located above the center of the active region 2P1 in the Y direction.

[0051] Furthermore, the via 62 connects the power supply wiring 51 and a portion of the active region 2N1 that serves as the source of the transistor N1. In plan view, the center of the via 62 in the Y direction is located at the same position as the center of the power supply wiring 51 in the Y direction. That is, when the center of the active region 2N1 in the Y direction is used as a reference, the via 62 is located closer to the upper end of the active region 2N1 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31). In other words, the center of the via 62 in the Y direction is located above the center of the active region 2N1 in the Y direction.

[0052] Furthermore, the via 63 connecting the wiring 52 and the gate wiring 31 is formed lower in the Y direction than the power wiring 51 in plan view (the side where the nanosheet 22 is exposed from the gate wiring 31 and where the active region 2N1 is positioned closer to the cell frame). The via 63 is formed in the area where the wiring 52 and the active region 2N1 overlap in plan view. That is, the via 63 is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as the reference point. This reduces the distance from the wiring 52 (input A) to the portion of the gate wiring 31 that overlaps the nanosheets 21 and 22 in plan view and covers the nanosheets 21 and 22, thereby reducing the resistance from the wiring 52 to the gate wiring 31 and increasing the speed of the semiconductor integrated circuit device.

[0053] Furthermore, the wiring 53 is disposed on the upper side of the drawing in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N1 is disposed close to the cell frame). The via 64 connecting the wiring 53 to the local wiring 42 and the via 65 connecting the local wirings 41 and 42 are formed on the upper side of the drawing in the Y direction. This reduces the distance from the wiring 53 to the portion of the active region 2P1 that serves as the drain of the transistor P1 and the portion of the active region 2N1 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P1 (2N1) that serves as the drain of the transistor P1 (N1), thereby enabling an increase in the speed of the semiconductor integrated circuit device.

[0054] (Configuration of Inverter Cell C4) The inverter cell C4 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0055] As shown in Figures 2(c) and (d), compared to the inverter cell C1 shown in Figures 2(a) and (b), the inverter cell C4 has active regions 2P4 and 2N4, each having a different width in the Y direction, arranged in place of the active regions 2P1 and 2N1.

[0056] Specifically, the active regions 2P4 and 2N4 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C4.

[0057] As shown in FIG. 2, the bottom edge of the active region 2P4 (2N4) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1 (2N1). That is, the bottom edge of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P4 (2N4) of the inverter cell C4 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C4 have their lower surfaces in the Y direction exposed from the gate wiring 31. That is, the nanosheet surfaces exposed from the gate wiring of the inverter cells C1 and C4 are aligned in the Y direction. This allows the shape of the insulating structure between the opposing nanosheets exposed from the gate wiring, i.e., their size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0058] In this embodiment, two inverter cells with different active region widths are arranged in a circuit block. However, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each inverter cell can be aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0059] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0060] Fig. 5(a) shows another example of the configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0061] 5B shows a cross section of the inverter cell C1 of FIG. 3 taken along line Y1-Y1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 for supplying VDD is formed in a wiring layer provided on the surface of chip B. The power supply wiring 11 is connected to the active region 2P1 of chip A through a via 61.

[0062] This configuration example also provides the same effects as the inverter cell described above.

[0063] (Variation 1) Fig. 6(a) is a plan view showing an example of the layout structure of an inverter cell according to a variation of the embodiment. Fig. 6(a) shows the lower part of the cell. Compared to Fig. 2(a), Fig. 6(a) has a via 61a arranged in place of the via 61. In plan view, the via 61a is formed at the lower end of the power supply wiring 11 in the drawing. In other words, in plan view, the via 61a is formed closer to the center of the drawing in the Y direction of the active region 2P1.

[0064] According to the configuration of Figure 6(a), the via 61a is positioned closer to the center of the active region 2P1 in the Y direction of the drawing, so that the difference in resistance value from the via 61a to the top and bottom ends of the nanosheet 21 in the Y direction of the drawing is small, allowing current to be supplied evenly to the nanosheet 21 and increasing the speed of the semiconductor integrated circuit device.

[0065] The via 61a is preferably disposed at the center of the active region 2P1 in the Y direction in the drawing.

[0066] 6A. That is, in FIG. 2B, the via 62 may be formed at the lower end of the power supply wiring 51 in the Y direction in plan view. In other words, the via 62 may be formed closer to the center of the active region 2N1 in the Y direction in plan view.

[0067] (Modification 2) Fig. 6(b) is a plan view showing an example of a layout structure of an inverter cell according to a modification of the embodiment. Fig. 6(b) shows the lower part of the cell. Compared to Fig. 2(a), Fig. 6(b) has a via 61b arranged instead of the via 61. In plan view, the via 61b has a different shape from the via 61.

[0068] The vias 61b have a rectangular cross section in a plan view. Specifically, the length d5 ​​of each via 61b in the Y direction is longer than the length d6 of each via 61b in the X direction. The length d5 ​​of each via 61b in the Y direction is approximately the same as the length of the power supply wiring 11 from the top to the bottom of the drawing.

[0069] According to the configuration of Figure 6(b), the resistance value of the via 61b connecting the power supply wiring 11 and the portion that becomes the source of the transistor P1 in the active region 2P1 can be reduced, thereby suppressing a drop in the power supply voltage and suppressing the occurrence of electromigration.

[0070] The upper part of the cell may also be configured in the same manner as in Fig. 6B, i.e., via 61b may be disposed in place of via 62 in Fig. 2B.

[0071] 7(a) shows the lower part of a two-input NAND cell C2, FIG. 7(b) shows the upper part of a two-input NAND cell C2, FIG. 7(c) shows the lower part of a two-input NAND cell C5, FIG. 7(d) shows the upper part of a two-input NAND cell C5, FIG. 8(a) shows the lower part of a two-input NOR cell C3, FIG. 8(b) shows the upper part of a two-input NOR cell C3, FIG. 8(c) shows the lower part of a two-input NOR cell C6, FIG. 8(d) shows the upper part of a two-input NOR cell C6, FIG. 9(a) is a circuit diagram of a two-input NAND cell, and FIG. 9(b) is a circuit diagram of a two-input NOR cell.

[0072] The layout structures of FIGS. 7 and 8 can be easily inferred from the above description of the inverter cells and the circuit diagram of FIG. 9, and therefore will not be described further.

[0073] 7A, an active region 2P2 is formed in the P-type transistor region at the bottom of the two-input NAND cell C2. The active region 2P2 overlaps with the power supply wiring 11 in plan view.

[0074] Transistors P11 and P12 are configured in the active region 2P2. The transistors P11 and P12 have nanosheets 23 and 24, respectively, extending in the X direction. In the active region 2P2, the portions that become the sources of the transistors P11 and P12 are connected to the power supply wiring 11 via vias 66 and 67, respectively. The vias 66 and 67 are formed in a region where the power supply wiring 11 and the active region 2P2 overlap in a planar view.

[0075] 7B, an active region 2N2 is formed in the N-type transistor region in the upper part of the cell. The active region 2N2 overlaps with the active region 2P2 in plan view.

[0076] Transistors N11 and N12 are configured in the active region 2N2. The transistors N11 and N12 have nanosheets 25 and 26, respectively, extending in the X direction. In the active region 2N2, the portion that serves as the source of the transistor N11 is connected to the power supply wiring 51 via a via 68. The via 68 is formed in a region where the power supply wiring 51 and the active region 2N2 overlap in a plan view.

[0077] Gate wirings 34 and 35 are formed extending in the Y direction. The nanosheets 23 and 25 overlap the gate wiring 34 in a planar view. The nanosheets 24 and 26 overlap the gate wiring 35 in a planar view. The gate wiring 34 corresponds to the gates of the transistors P11 and N11. The gate wiring 35 corresponds to the gates of the transistors P12 and N12.

[0078] The gate wiring 34 covers the outer peripheries of the nanosheets 23 and 25 in the Y and Z directions so that part of the outer peripheries of the nanosheets 23 and 25 are exposed. The gate wiring 35 covers the outer peripheries of the nanosheets 24 and 26 in the Y and Z directions so that part of the outer peripheries of the nanosheets 24 and 26 are exposed. Specifically, the lower sides of the nanosheets 23 and 25 in the Y direction are exposed from the gate wiring 34, and the upper sides of the nanosheets 24 and 26 in the Y direction are covered by the gate wiring 34. The lower sides of the nanosheets 24 and 26 in the Y direction are exposed from the gate wiring 35, and the upper sides of the nanosheets 24 and 26 in the Y direction are covered by the gate wiring 35.

[0079] In the M0 wiring layer, a power supply wiring 51 and wirings 52 to 54 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VDD. The wiring 52 corresponds to input A, the wiring 53 corresponds to output Y, and the wiring 54 corresponds to input B.

[0080] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N2 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N2 that serves as the source of the transistor N11 via a via 68 and a local wiring. The via 68 is formed in the region where the power supply wiring 51 and the active region 2N2 overlap in plan view.

[0081] The wiring 52 is disposed on the lower side in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 34 through a via 69. The via 69 is formed in a region where the wiring 52 and the active region 2N2 overlap in a plan view.

[0082] The wiring 53 is disposed on the upper side of the drawing in the Y direction. The wiring 53 is connected to the portions that become the drains of the transistors P11 and P12 and the portion that becomes the drain of the transistor N12 via vias 70 and 71 and local wiring.

[0083] The wiring 54 is disposed on the lower side in the Y direction in the drawing. The wiring 54 is connected to the gate wiring 35 through a via 72. The via 72 is formed in a region where the wiring 54 and the active region 2N2 overlap in a plan view.

[0084] As described above, the two-input NAND cell C2 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and realizes a NAND circuit with inputs A and B and an output Y.

[0085] As shown in FIGS. 7A and 7B, the active regions 2P2 and 2N2 in the two-input NAND cell C2 have a width of w1 in the Y direction in plan view.

[0086] In the two-input NAND cell C2 shown in FIG. 7, the nanosheets 23 and 25 have their lower surfaces in the Y direction exposed from the gate wiring 34. The nanosheets 24 and 26 have their lower surfaces in the Y direction exposed from the gate wiring 35. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d3 from the lower end of the active region 2P2 (2N2) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P2 and 2N2 (nanosheets 23-26) can be arranged close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0087] Furthermore, the upper surfaces of the nanosheets 23 and 25 in the Y direction are not exposed from the gate wiring 34. The upper surfaces of the nanosheets 24 and 26 in the Y direction are not exposed from the gate wiring 35. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d3 from the lower end of the active region 2P2 (2N2) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P2 (2N2) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P2 (2N2) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P2 (2N2) in the Y direction is located below the center of the cell frame in the Y direction.

[0088] Furthermore, the power supply wiring 11, 51 is formed in the center of the cell in the Y direction in plan view. That is, the center of the active region 2P2 (2N2) in the Y direction is located below the center of the power supply wiring 11 (51) in the Y direction. By arranging the two-input NAND cell C2 in the circuit block of FIG. 1, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in the power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0089] Furthermore, vias 66 and 67 connect the power supply wiring 11 to the portions of the active region 2P2 that serve as the sources of transistors P11 and P12, respectively. In plan view, the Y-direction centers of the vias 66 and 67 are located at the same position as the Y-direction center of the power supply wiring 11. That is, when the center of the active region 2P2 is used as a reference, the vias 66 and 67 are located closer to the upper end of the active region 2P2 (the side where the nanosheets 23 and 24 are not exposed from the gate wirings 34 and 35, respectively). In other words, the Y-direction centers of the vias 66 and 67 are located above the Y-direction center of the active region 2P2.

[0090] Furthermore, the via 68 connects the power supply wiring 51 to a portion of the active region 2N2 that serves as the source of the transistor N11. In plan view, the center of the via 68 in the Y direction is located at the same position as the center of the power supply wiring 51 in the Y direction. That is, when the center of the active region 2N2 in the Y direction is used as a reference, the via 68 is located closer to the upper end of the active region 2N2 in the Y direction (the side where the nanosheets 25, 26 are not exposed from the gate wirings 34, 35, respectively). In other words, the center of the via 68 in the Y direction is located above the center of the active region 2N2 in the Y direction.

[0091] Furthermore, the via 69 (72) connecting the wiring 52 (54) and the gate wiring 34 (35) is formed in a plan view below the power wiring 51 in the Y direction (the side where the nanosheets 25, 26 are exposed from the gate wiring 34, 35, respectively, and where the active region 2N2 is positioned closer to the cell frame), and is formed in a region where the wiring 52 (54) and the active region 2N2 overlap in a plan view. In other words, the via 69 (72) is positioned closer to the bottom end of the cell frame when the center of the cell frame in the Y direction is used as the reference point. This reduces the distance from the wiring 52 (54) corresponding to input A (input B) to the portion of the gate wiring 34 (35) that overlaps the nanosheets 23, 25 (24, 26) in a planar view and covers the nanosheets 23, 25 (24, 26), thereby reducing the resistance from the wiring 52 (54) to the gate wiring 34 (35) and enabling the semiconductor integrated circuit device to operate at a higher speed.

[0092] Furthermore, the wiring 53 is arranged on the upper side of the drawing in the Y direction (the side where the nanosheets 25, 26 are not exposed from the gate wiring 34, 35, and opposite the side where the active region 2N2 is arranged close to the cell frame). The via 70 connects the wiring 53 to a local wiring connected to the portion that will become the drain of the transistors P11, P12 in the active region 2P2. The via 71 connects the wiring 53 to a local wiring connected to the portion that will become the drain of the transistor N12 in the active region 2N2. The vias 70, 71 are formed on the upper side of the drawing in the Y direction. This reduces the distance from the wiring 53 to the portion that will become the drain of the transistors P11, P12 in the active region 2P2 and the portion that will become the drain of the transistor N12 in the active region 2N2, thereby reducing the resistance from the wiring 53 to the portion that will become the drain of the transistors P11, P12 in the active region 2P2 and the portion that will become the drain of the transistor N12 in the active region 2N2, and thereby increasing the speed of the semiconductor integrated circuit device.

[0093] (Configuration of Two-Input NAND Cell C5) The two-input NAND cell C5 has a configuration similar to that of the two-input NAND cell C2. Specifically, the two-input NAND cell C5 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and implements a NAND circuit with inputs A and B and an output Y.

[0094] As shown in Figures 7(c) and (d), compared to the two-input NAND cell C2 shown in Figures 7(a) and (b), the two-input NAND cell C5 has active regions 2P5 and 2N5 with different widths in the Y direction arranged therein instead of the active regions 2P2 and 2N2.

[0095] Specifically, the active regions 2P5 and 2N5 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the two-input NAND cell C2 is greater than the drive capability of the two-input NAND cell C5.

[0096] As shown in FIG. 7, the bottom edge of the active region 2P5 (2N5) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P2 (2N2) in the Y direction. That is, the bottom edge of the active region 2P2 (2N2) of the two-input NAND cell C2 in the Y direction and the bottom edge of the active region 2P5 (2N5) of the two-input NAND cell C5 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 23 (25) of the two-input NAND cells C2 and C5 have their lower surfaces exposed from the gate wiring 34. The nanosheets 24 (26) of the two-input NAND cells C2 and C5 have their lower surfaces exposed from the gate wiring 35 in the Y direction. That is, the nanosheet surfaces exposed from the gate wiring of the two-input NAND cells C2 and C5 are aligned in the Y direction. This allows the shape of the insulating structure, which is exposed from the gate wiring and provided between the opposing nanosheets, i.e., the size and placement area in the Y direction, to be constant, thereby facilitating the manufacture of semiconductor integrated circuit devices.

[0097] In this embodiment, two two-input NAND cells with different active area widths are arranged in a circuit block. However, three or more two-input NAND cells with different active area widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each two-input NAND cell is simply aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0098] 8A, an active region 2P3 is formed in the P-type transistor region below the two-input NOR cell C3. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0099] Transistors P21 and P22 are configured in the active region 2P3. The transistors P21 and P22 have nanosheets 27 and 28, respectively, extending in the X direction. In the active region 2P3, the portion that serves as the source of the transistor P21 is connected to the power supply wiring 11 via a via 73. The via 73 is formed in a region where the power supply wiring 11 and the active region 2P3 overlap in a plan view.

[0100] 8B, an active region 2N3 is formed in the N-type transistor region in the upper part of the cell. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0101] The active region 2N3 includes transistors N21 and N22. The transistors N21 and N22 have nanosheets 29 and 30, respectively, that extend in the X direction.

[0102] Gate wirings 36 and 37 are formed extending in the Y direction. The nanosheets 27 and 29 overlap the gate wiring 36 in a planar view. The nanosheets 28 and 30 overlap the gate wiring 37 in a planar view. The gate wiring 36 corresponds to the gates of the transistors P21 and N21. The gate wiring 37 corresponds to the gates of the transistors P22 and N22.

[0103] The gate wiring 36 covers the outer peripheries of the nanosheets 27 and 29 in the Y and Z directions so that part of the outer peripheries of the nanosheets 27 and 29 are exposed. The gate wiring 37 covers the outer peripheries of the nanosheets 28 and 30 in the Y and Z directions so that part of the outer peripheries of the nanosheets 28 and 30 are exposed. Specifically, the lower sides of the nanosheets 27 and 29 in the Y direction are exposed from the gate wiring 36, and the upper sides of the nanosheets 27 and 29 in the Y direction are covered by the gate wiring 36. The lower sides of the nanosheets 28 and 30 in the Y direction are exposed from the gate wiring 37, and the upper sides of the nanosheets 28 and 30 in the Y direction are covered by the gate wiring 37.

[0104] In the M0 wiring layer, a power supply wiring 51 and wirings 52 to 54 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VDD. The wiring 52 corresponds to input A, the wiring 53 corresponds to output Y, and the wiring 54 corresponds to input B.

[0105] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N3 in a plan view. The power supply wiring 51 is connected to the sources of the transistors N21 and N22 in the active region 2N3 via vias 74 and 75 and local wiring. The vias 74 and 75 are formed in the region where the power supply wiring 51 and the active region 2N3 overlap in a plan view.

[0106] The wiring 52 is disposed on the lower side in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 36 through a via 76. The via 76 is formed in a region where the wiring 52 and the active region 2N3 overlap in a plan view.

[0107] The wiring 53 is disposed on the upper side of the drawing in the Y direction. The wiring 53 is connected to the portion that becomes the drain of the transistor P22 and the portions that become the drains of the transistors N21 and N22 via vias 77 and 78 and local wiring.

[0108] The wiring 54 is disposed on the lower side in the Y direction in the drawing. The wiring 54 is connected to the gate wiring 37 through a via 79. The via 79 is formed in a region where the wiring 54 and the active region 2N3 overlap in a plan view.

[0109] As described above, the two-input NOR cell C3 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and an output Y.

[0110] As shown in FIGS. 8A and 8B, the active regions 2P3 and 2N3 of the two-input NOR cell C3 have a width of w1 in the Y direction in plan view.

[0111] In the two-input NOR cell C3 shown in FIG. 8, the nanosheets 27 and 29 have their lower Y-direction surfaces exposed from the gate wiring 36. The nanosheets 28 and 30 have their lower Y-direction surfaces exposed from the gate wiring 37. Furthermore, every other cell row CR is inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their exposed surfaces (lower surfaces) from the gate wiring facing each other in the Y direction. This reduces the distance d3 from the lower Y-direction edge of the active region 2P3 (2N3) to the lower Y-direction edge of the cell frame. In other words, the active regions 2P2 and 2N2 (nanosheets 27-30) can be positioned close to the lower Y-direction edge of the cell frame. This allows for a smaller area for the semiconductor integrated circuit device.

[0112] Furthermore, the upper surfaces of the nanosheets 27 and 29 in the Y direction are not exposed from the gate wiring 36. The upper surfaces of the nanosheets 28 and 30 in the Y direction are not exposed from the gate wiring 37. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction face each other in the Y direction with the surfaces exposed from the gate wiring (the lower surfaces) facing each other, and the surfaces not exposed from the gate wiring (the upper surfaces) facing each other. Therefore, the distance d3 from the lower end of the active region 2P3 (2N3) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P3 (2N3) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P3 (2N3) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P3 (2N3) in the Y direction is located below the center of the cell frame in the Y direction.

[0113] Furthermore, the power supply wiring 11 and 51 are formed in the center of the cell in the Y direction in plan view. That is, the center of the active region 2P3 (2N3) in the Y direction is located below the center of the power supply wiring 11 (51) in the Y direction. By arranging the two-input NOR cell C3 in the circuit block of FIG. 1, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in the power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0114] Furthermore, the via 73 connects the power supply wiring 11 to a portion of the active region 2P3 that serves as the source of the transistor P21. In plan view, the center of the via 73 in the Y direction is located at the same position as the center of the power supply wiring 11 in the Y direction. That is, when the center of the active region 2P3 in the Y direction is used as a reference, the via 73 is located closer to the upper end of the active region 2P3 in the Y direction (the side where the nanosheets 27, 28 are not exposed from the gate wirings 36, 37, respectively). In other words, the center of the via 73 in the Y direction is located above the center of the active region 2P3 in the Y direction.

[0115] Furthermore, vias 74 and 75 connect the power supply wiring 51 to the portions of the active region 2N3 that serve as the sources of transistors N21 and N22, respectively. In plan view, the Y-direction centers of vias 74 and 75 are located at the same position as the Y-direction center of power supply wiring 51. That is, when the Y-direction center of the active region 2N3 is used as a reference, vias 74 and 75 are located closer to the upper end of the active region 2N3 (the side where nanosheets 29 and 30 are not exposed from gate wirings 36 and 37, respectively). In other words, the Y-direction centers of vias 74 and 75 are located above the Y-direction center of the active region 2N3.

[0116] Furthermore, via 76 (79) connecting wiring 52 (54) and gate wiring 36 (37) is formed in a plan view below power wiring 51 in the Y direction (the side where nanosheets 29, 30 are exposed from gate wiring 36, 37, respectively, and where active region 2N3 is positioned closer to the cell frame), and is formed in a region where wiring 52 (54) and active region 2N3 overlap in a plan view. In other words, via 76 (79) is positioned closer to the bottom end of the cell frame when the center of the cell frame in the Y direction is used as the reference point. This reduces the distance from the wiring 52 (54) corresponding to input A (input B) to the portion of the gate wiring 36 (37) that overlaps the nanosheets 27, 29 (28, 30) in a planar view and covers the nanosheets 27, 29 (28, 30), thereby reducing the resistance from the wiring 52 (54) to the gate wiring 36 (37) and enabling the semiconductor integrated circuit device to operate at a higher speed.

[0117] Furthermore, the wiring 53 is arranged on the upper side of the drawing in the Y direction (the side where the nanosheets 29 and 30 are not exposed from the gate wiring 36 and 37, respectively, and opposite the side where the active region 2N3 is arranged closer to the cell frame). The via 77 connects the wiring 53 to a local wiring connected to a portion that will become the drain of the transistor P22 in the active region 2P3. The via 78 connects the wiring 53 to a local wiring connected to a portion that will become the drain of the transistors N21 and N22 in the active region 2N3. The vias 77 and 78 are formed on the upper side of the drawing in the Y direction. This reduces the distance from the wiring 53 to the portion that will become the drain of the transistor P22 in the active region 2P3 and the portion that will become the drain of the transistors N21 and N22 in the active region 2N3, thereby reducing the resistance from the wiring 53 to the portion that will become the drain of the transistor P22 in the active region 2P3 and the portion that will become the drain of the transistors N21 and N22 in the active region 2N3, and thereby increasing the speed of the semiconductor integrated circuit device.

[0118] (Configuration of 2-input NOR cell C6) The 2-input NOR cell C6 has almost the same configuration as the 2-input NOR cell C3. Specifically, the 2-input NOR cell C6 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and output Y.

[0119] As shown in Figures 8(c) and (d), compared to the two-input NOR cell C3 shown in Figures 8(a) and (b), the two-input NOR cell C6 has active regions 2P6 and 2N6, which have different widths in the Y direction, arranged in place of the active regions 2P3 and 2N3.

[0120] Specifically, the active regions 2P6 and 2N6 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the two-input NOR cell C3 is greater than the drive capability of the two-input NOR cell C6.

[0121] As shown in FIG. 8 , the bottom edge of the active region 2P6 (2N6) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P3 (2N3). That is, the bottom edge of the active region 2P3 (2N3) of the two-input NOR cell C3 in the Y direction and the bottom edge of the active region 2P6 (2N6) of the two-input NOR cell C6 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 27 (29) of the two-input NOR cells C3 and C6 have their lower surfaces exposed from the gate wiring 36. The nanosheets 28 (30) of the two-input NOR cells C3 and C6 have their lower surfaces exposed from the gate wiring 37. That is, the nanosheets of the two-input NOR cells C3 and C6 have their surfaces exposed from the gate wiring aligned in the Y direction. This allows the shape of the insulating structure, which is exposed from the gate wiring and provided between the opposing nanosheets, i.e., the size and placement area in the Y direction, to be constant, thereby facilitating the manufacture of semiconductor integrated circuit devices.

[0122] In this embodiment, two two-input NOR cells with different active area widths are arranged in a circuit block. However, three or more two-input NOR cells with different active area widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each two-input NOR cell is simply aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0123] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0124] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0125] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0126] Furthermore, in each of the above-described embodiments and variants, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M1 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0127] In the two-input NAND cells C2 and C5, the vias 66 and 67 (68) may be arranged at the bottom of the power supply wiring 11 (51) in the Y direction, as in the via 61a shown in Figure 6A. Similarly, in the two-input NOR cells C3 and C6, the vias 73 (74 and 75) may be arranged at the bottom of the power supply wiring 11 (51) in the Y direction, as in the via 61a shown in Figure 6A.

[0128] In the two-input NAND cells C2 and C5, vias whose length in the Y direction is greater than their length in the X direction, such as via 61b shown in Fig. 6(b), may be used instead of vias 66 to 68. Similarly, in the two-input NOR cells C3 and C6, vias whose length in the Y direction is greater than their length in the X direction, such as via 61b shown in Fig. 6(b), may be used instead of vias 73 to 75.

[0129] In the present disclosure, with respect to standard cells using CFETs, in the layout of a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, it is possible to reduce the area of ​​the semiconductor integrated circuit device, suppress a drop in power supply voltage, and increase the speed.

[0130] 11, 51 Power supply wiring 21-30 Nanosheet 31, 34-37 Gate wiring 52-54 Wiring 61-79, 61a, 61b Via 2P, 2P1-2P6, 2N, 2N1-2N6 Active area P1, P11, P12, P21, P22, N1, N11, N12, N21, N22 Transistor C1, C4 Inverter cell C2, C5 2-input NAND cell C3, C6 2-input NOR cell

Claims

1. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; and a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage. a first via formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring; the first and second nanosheets have a first side surface, which is one side in the second direction, exposed from the first gate wiring, and are arranged adjacent to an end of the first side of the first standard cell.

2. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the central portion of the first nanosheet in the second direction is positioned on the first side relative to the central portion of the first power supply wiring in the second direction.

3. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell further comprises: a second power supply wiring formed above the second transistor in the depth direction, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the second active region where a region serving as the source of the second transistor overlaps with the second power supply wiring, connecting the source of the second transistor in the second active region to the second power supply wiring.

4. A semiconductor integrated circuit device according to claim 1, wherein the distance from the end of the first side of the first active region to the end of the first side of the first standard cell is smaller than the distance from the end of the second side, which is the other side in the second direction of the first active region, to the end of the second side of the first standard cell.

5. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells include a second standard cell arranged adjacent to the first side of the first standard cell, and a third standard cell arranged adjacent to the second side, which is the other side in the second direction, of the first standard cell, wherein the second standard cell comprises: a third active region constituting a channel, source and drain of a third transistor of the first conductivity type, and including a third nanosheet extending in the first direction as the channel; and a third gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second direction and the depth direction; the third standard cell comprises: a fourth active region constituting a channel, source and drain of a fourth transistor of the first conductivity type, and including a fourth nanosheet extending in the first direction as the channel; and a fourth gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the depth direction; and the second side surface of the third nanosheet is exposed from the third gate wiring, a semiconductor integrated circuit device, wherein the fourth nanosheet has a second side surface exposed from the fourth gate wiring, and a distance between the first active region and the third active region in the second direction is smaller than a distance between the first active region and the fourth active region in the second direction.

6. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the first via is disposed in the center of the first active region in the second direction.

7. A semiconductor integrated circuit device according to claim 1, wherein the first via has a length in the second direction longer than a length in the first direction.

8. A semiconductor integrated circuit device according to claim 1, wherein the first active region constitutes a channel, source and drain of a fifth transistor of the first conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a sixth transistor of the second conductivity type, and includes a sixth nanosheet extending in the first direction as the channel; the first standard cell is provided with a second gate wiring extending in the second direction and surrounding the outer periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and the fifth and sixth nanosheets have surfaces on the first side exposed from the second gate wiring.

9. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; and a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage. a first via formed in a region in the first active region where a region serving as a source of the first transistor and the first power supply wiring overlap, the first and second nanosheets having a first side surface, which is one side in the second direction, exposed from the first gate wiring, the first power supply wiring being disposed in a central portion of the first standard cell in the second direction.

10. A semiconductor integrated circuit device according to claim 9, wherein, in a plan view, the central portion of the first nanosheet in the second direction is positioned on the first side relative to the central portion of the first power supply wiring in the second direction.

11. A semiconductor integrated circuit device according to claim 9, wherein the first standard cell further comprises: a second power supply wiring formed above the second transistor in the depth direction, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the second active region where a region serving as the source of the second transistor overlaps with the second power supply wiring, connecting the source of the second transistor in the second active region to the second power supply wiring.

12. A semiconductor integrated circuit device according to claim 9, wherein the first active region constitutes a channel, source and drain of a fifth transistor of the first conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a sixth transistor of the second conductivity type, and includes a sixth nanosheet extending in the first direction as the channel; the first standard cell is provided with a second gate wiring extending in the second direction and surrounding the outer periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring.

13. A semiconductor integrated circuit device comprising a plurality of standard cells including a first standard cell and a fourth standard cell arranged side by side in a first direction, wherein the first standard cell comprises: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in the first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; and a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; and the fourth standard cell comprises: a seventh active region constituting a channel, a source, and a drain of a seventh transistor of the first conductivity type, the channel being a seventh nanosheet extending in the first direction; a fifth gate wiring extending in the second direction and surrounding an outer periphery of the seventh and eighth nanosheets in the second direction and the depth direction, wherein the first and second nanosheets have a first side surface which is one side in the second direction and is exposed from the first gate wiring, and the seventh and eighth nanosheets have a first side surface which is exposed from the fifth gate wiring, wherein in a plan view, the width of the seventh nanosheet in the second direction is smaller than the width of the first nanosheet in the second direction, and wherein in a plan view, an end of the first side of the first nanosheet and an end of the first side of the seventh nanosheet are arranged at the same position in the second direction.

14. A semiconductor integrated circuit device as described in claim 13, wherein, in a planar view, the width of the eighth nanosheet in the second direction is smaller than the width of the second nanosheet in the second direction, and, in a planar view, the end of the second nanosheet on the first side and the end of the eighth nanosheet on the first side are arranged at the same position in the second direction.

15. A semiconductor integrated circuit device according to claim 13, wherein the first standard cell comprises: a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a first via formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring.

16. A semiconductor integrated circuit device according to claim 13, wherein the first, second, seventh and eighth nanosheets have their first side surfaces arranged adjacent to the first side end of the first standard cell.

17. A semiconductor integrated circuit device according to claim 13, wherein the first standard cell is formed on the back side of the first transistor, extends in the first direction, and includes a first power supply wiring that supplies a first power supply voltage, and in a planar view, a central portion of the first nanosheet in the second direction is positioned on the first side of a central portion of the first power supply wiring in the second direction.

18. A semiconductor integrated circuit device according to claim 13, wherein the first active region constitutes a channel, source and drain of a fifth transistor of the first conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a sixth transistor of the second conductivity type, and includes a sixth nanosheet extending in the first direction as the channel; the first standard cell is provided with a third gate wiring extending in the second direction and surrounding the outer periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and the fifth and sixth nanosheets have surfaces on the first side exposed from the third gate wiring.

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