Imaging device

Abstract

The present invention is for relaxing energy concentration in detection of a P-phase level of each column without referring to a D-phase level.　An imaging device comprising: a first column signal line connected to a first pixel; a first comparison circuit connected to the first column signal line; a second column signal line provided adjacent to the first column signal line and connected to a second pixel; a second comparison circuit connected to the second column signal line; a reference signal generation unit for generating a reference signal; a first lamp source follower circuit connected between the reference signal generation unit and the first comparison circuit; a second lamp source follower circuit connected between the reference signal generation unit and the second comparison circuit; and a switching unit for switching connection between an output terminal of the first lamp source follower circuit and an output terminal of the second lamp source follower circuit.

Description

Imaging device

[0001] The present technology relates to an imaging device, and more particularly to an imaging device capable of AD (Analog to Digital) conversion of a pixel signal based on a comparison result between the pixel signal and a reference signal.

[0002] In an imaging device, pixel signals are sometimes AD converted and output based on a comparison result between the pixel signals and a reference signal. For example, there is a technique for shorting column signal lines that transmit pixel signals for each column only for a certain period during a reset period of a comparator that compares the pixel signals with the reference signal (see, for example, Patent Document 1).

[0003] International Publication No. 2014 / 132822

[0004] However, in the above-described conventional technology, if the potential difference between the column signal lines is large and the potential variation of the column signal lines increases, there is a risk of errors occurring in the AD conversion results.

[0005] This technology was developed in light of these circumstances, and aims to alleviate energy concentration when detecting the P-phase level of each column without referring to the D-phase level.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including: a first column signal line connected to a first pixel; a first comparison circuit connected to the first column signal line; a second column signal line provided adjacent to the first column signal line and connected to a second pixel; a second comparison circuit connected to the second column signal line; a reference signal generation unit that generates a reference signal; a first ramp source follower circuit connected between the reference signal generation unit and the first comparison circuit; a second ramp source follower circuit connected between the reference signal generation unit and the second comparison circuit; and a switching unit that switches a connection between an output terminal of the first ramp source follower circuit and an output terminal of the second ramp source follower circuit. This results in an effect that inversion timing of the comparison circuit varies between columns based on variations in characteristics of the ramp source follower circuits.

[0007] In a first aspect, the first comparison circuit includes a first comparator that compares a first pixel signal transmitted via the first column signal line with the reference signal, a first capacitor connected to a first non-inverting input terminal of the first comparator, and a second capacitor connected to a first inverting input terminal of the first comparator. The second comparison circuit includes a second comparator that compares a second pixel signal transmitted via the second column signal line with the reference signal, and a third capacitor connected to a second non-inverting input terminal of the second comparator. and a fourth capacitor connected to the second inverting input terminal of the second comparator, wherein the first comparison circuit controls the charges stored in the first capacitor and the second capacitor so that the input potential of the first non-inverting input terminal and the input potential of the first inverting input terminal are balanced during an auto-zero period, and the second comparison circuit controls the charges stored in the third capacitor and the fourth capacitor so that the input potential of the second non-inverting input terminal and the input potential of the second inverting input terminal are balanced during the auto-zero period. This brings about an effect that the inversion timing of the comparators varies between columns based on the auto-zero operation.

[0008] In the first aspect, the charge stored in the first capacitor and the charge stored in the third capacitor when auto-zero is cancelled may be varied based on variations in characteristics of the first ramp source follower circuit and the second ramp source follower circuit, thereby resulting in variations in the inversion timing of the comparator between columns without reference to the D-phase level.

[0009] In the first aspect, the switching unit may disconnect the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit during the auto-zero period, and then connect the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit, thereby causing outputs of the ramp source follower circuits to vary between columns based on auto-zero cancellation.

[0010] In the first aspect, the switching unit may connect the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit during the auto-zero period, and then disconnect the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit, thereby causing the outputs of the ramp source follower circuits to vary between columns based on auto-zero cancellation.

[0011] In the first aspect, the reference signal generating unit may change the level of the reference signal during the auto-zero period, thereby increasing the variation between columns in the output of the ramp source follower circuit when the auto-zero mode is cancelled.

[0012] In addition, in the first aspect, the pixel array unit may further include a pixel array section in which pixels are arranged in a matrix in the row and column directions, the first pixels being arranged in a first column, and the second pixels being arranged in a second column, and a switching section control section that randomly controls the switching timing of the switching section for each row, thereby resulting in an effect that the inversion timing of the comparison circuit varies between rows.

[0013] In the first aspect, the first pixel and the second pixel may each include a lateral overflow integration capacitor (LOFIC), thereby providing an effect of expanding the dynamic range of imaging.

[0014] In the first aspect, each of the first pixel and the second pixel may further include a first photodiode and a second photodiode having a lower sensitivity than the first photodiode, and overflowing charge is accumulated in the LOFIC, thereby providing an effect of expanding the dynamic range of imaging.

[0015] In the first aspect, the signal detected by the second photodiode may be read out based on DDS (Double Data Sampling) readout, thereby providing an effect that charge overflowing from the second photodiode is read out.

[0016] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing an example of the configuration of a signal readout unit according to the first embodiment. FIG. 5 is a diagram showing an example of the configuration of a comparison circuit according to the first embodiment. FIG. 6 is a diagram showing an example of the configuration of a ramp source follower circuit according to the first embodiment. FIG. 7 is a timing chart showing an example of waveforms of each unit in a readout operation of the solid-state imaging device according to the first embodiment. FIG. 8 is a block diagram showing connection paths by a switching unit after auto-zero cancellation according to the first embodiment. FIG. 9 is a timing chart showing an example of a P-phase level distribution after dithering based on a ramp source follower of the solid-state imaging device according to the first embodiment. FIG. 10 is a timing chart showing an example of waveforms of each unit in a readout operation of the solid-state imaging device according to the second embodiment. FIG. 11 is a block diagram showing connection paths by a switching unit after auto-zero cancellation according to the second embodiment. FIG. 12 is a timing chart showing an example of waveforms of each unit in a readout operation of the solid-state imaging device according to the third embodiment. FIG. 13 is a timing chart showing an example of waveforms of each unit in a readout operation of the solid-state imaging device according to the fourth embodiment. FIG. 14 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to a fifth embodiment. 13 is a timing chart showing an example of waveforms of each part in a readout operation of a solid-state imaging device according to a fifth embodiment. FIG. 14 is a perspective view showing an example of stacking of pixel array parts according to a sixth embodiment. FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 16 is an explanatory diagram showing an example of an installation position of an imaging part.

[0017] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the P-phase level of each column is dithered by switching the output of a ramp source follower of a reference signal to be compared with a pixel signal from open to short between columns during an auto-zero period) 2. Second embodiment (an example in which the P-phase level of each column is dithered by switching the output of a ramp source follower of a reference signal to be compared with a pixel signal from short to open between columns during an auto-zero period) 3. Third embodiment (an example in which the output timing of a ramp source follower is controlled randomly for each row during an auto-zero period) 4. Fourth embodiment (an example in which the level of a reference signal to be compared with a pixel signal during an auto-zero period is changed) 5. Fifth embodiment (an example in which dithering of the D-phase level of each column is applied to DDS drive of LOFIC pixels) 6. Sixth embodiment (an example in which pixel array units are stacked) 7. Application example to a moving body

[0018] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0019] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0020] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0021] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC image sensor.

[0022] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0023] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0024] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0025] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0026] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0027] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0028] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0029] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0030] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as the horizontal direction) and a column direction (also referred to as the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits the pixel signals read out from the pixels 120 to the column signal processing unit 114 for each column.

[0031] Each pixel 120 may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixels 120 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 120 may be visible light, near-infrared light (NIR), short-wave infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0032] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel 120, the vertical scanning circuit 112 can drive each pixel 120 row by row via a horizontal drive line 131.

[0033] The column readout circuit 113 can form a source follower between itself and each pixel 120 when reading out a signal from the pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 for each column based on the charge held in each pixel 120.

[0034] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an imaging signal Gout. Here, the column signal processing unit 114 can dither the P-phase level of each column in the AD conversion processing. For this dithering, the column signal processing unit 114 can use variations in the output of a ramp source follower of a reference signal REF, which is compared with a pixel signal read from each pixel 120.

[0035] The column signal processing unit 114 includes a ramp source follower unit 114A, a switching unit 114B, a column ADC unit 114C, a reference signal generating unit 114D, and a switching control unit 114E.

[0036] The ramp source follower unit 114A inputs a reference signal REF to the column ADC unit 114C based on the source follower of the reference signal REF output from the reference signal generation unit 114D. At this time, the ramp source follower unit 114A makes the potential of the reference signal REF input to the column ADC unit 114C follow the potential of the reference signal REF output from the reference signal generation unit 114D, thereby making these potentials approximately equal. The ramp source follower unit 114A is connected between the reference signal generation unit 114D and the column ADC unit 114C. At this time, the ramp source follower unit 114A can configure a ramp source follower for each column. For example, the ramp source follower unit 114A may be provided with a buffer for each column.

[0037] The switching unit 114B switches the output of each column of the ramp source follower unit 114A between the columns. For example, during the auto-zero period, the switching unit 114B can disconnect the output of each column of the ramp source follower unit 114A and then connect the output of each column of the ramp source follower unit 114A. The switching unit 114B may be provided with a switching transistor for each column, for example.

[0038] The column ADC unit 114C can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114C can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 120 and the reference signal REF. Here, the column ADC unit 114C can be provided with a comparator for each column that compares the pixel signal read from the pixel 120 with the reference signal REF.

[0039] The reference signal generating unit 114D generates a reference signal REF. The reference signal REF may include a ramp wave. The reference signal REF may be shared by all columns. The reference signal REF is input to the column ADC unit 114C via the ramp source follower unit 114A.

[0040] The switching control unit 114E controls the switching of the switching unit 114B. For example, during the auto-zero period, the switching control unit 114E can turn on and off the switching unit 114B so that the output of each column of the ramp source follower unit 114A is connected after the output of each column of the ramp source follower unit 114A is disconnected.

[0041] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0042] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0043] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0044] 1, a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS (Metal Oxide Semiconductor) transistors.

[0045] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to a power supply VDD via a reset transistor 123. The power supply VDD is connected to a vertical signal line 132 via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0046] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG. 2 .

[0047] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and transmitted via the vertical signal line 132. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0048] 4 is a block diagram showing an example of the configuration of a signal readout unit according to the first embodiment. Although the diagram shows two columns of vertical signal lines 132-1 and 132-2, the present invention can be similarly applied to a case where there are more vertical signal lines.

[0049] In the figure, pixels 120-1 and 120-2 are connected to vertical signal lines 132-1 and 132-2, respectively. At this time, the amplification transistors 124 of the pixels 120-1 and 120-2 are connected to the vertical signal lines 132-1 and 132-2 via selection transistors 125, respectively.

[0050] The column readout circuit 113 includes current sources 130-1 and 130-2. The current sources 130-1 and 130-2 are provided for each column. The current sources 130-1 and 130-2 are connected to vertical signal lines 132-1 and 132-2, respectively. During signal readout, the current sources 130-1 and 130-2 can form source followers with the pixels 120-1 and 120-2 via the vertical signal lines 132-1 and 132-2, respectively. The current sources 130-1 and 130-2 may be MOS transistors.

[0051] The ramp source follower unit 114A includes ramp source follower circuits 141-1 and 141-2. The ramp source follower circuits 141-1 and 141-2 are provided for each column. Each ramp source follower circuit 141-1 and 141-2 is connected between the reference signal generation unit 114D and each comparator 143-1 and 143-2. ​​Each ramp source follower circuit 141-1 and 141-2 inputs a reference signal REF to each comparator 143-1 and 143-2 based on the source follower of the reference signal REF output from the reference signal generation unit 114D.

[0052] The switching unit 114B includes switching transistors 142-1 and 142-2. The switching transistors 142-1 and 142-2 are provided for each column. Each of the switching transistors 142-1 and 142-2 switches between the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2. For example, each of the switching transistors 142-1 and 142-2 can connect or disconnect the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2. The switching transistors 142-1 and 142-2 may be MOS transistors.

[0053] The switching control unit 114E inputs a switching signal CNT to the gates of the switching transistors 142-1 and 142-2. At this time, the switching control unit 114E can turn on and off each of the switching transistors 142-1 and 142-2 so that, after the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are disconnected from each other during the auto-zero period, the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are connected to each other.

[0054] The column ADC unit 114C includes comparators 143-1 and 143-2 and DC blocking capacitors 144-1, 144-2, 145-1 and 145-2.

[0055] Comparators 143-1 and 143-2 are provided for each column. The comparator 143-1 compares the pixel signal transmitted via the vertical signal line 132-1 with the reference signal REF output via the ramp source follower circuit 141-1. The comparator 143-2 compares the pixel signal transmitted via the vertical signal line 132-2 with the reference signal REF output via the ramp source follower circuit 141-2.

[0056] An auto-zero signal AZ is also input to each of the comparators 143-1 and 143-2. ​​The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, in the comparator 143-1, a DC-blocking capacitor 145-1 is connected to the non-inverting input terminal, and a DC-blocking capacitor 144-1 is connected to the inverting input terminal. In the comparator 143-2, a DC-blocking capacitor 145-2 is connected to the non-inverting input terminal, and a DC-blocking capacitor 144-2 is connected to the inverting input terminal.

[0057] In the auto-zero operation, the charges accumulated in the DC blocking capacitors 144-1 and 145-1 are controlled so that the non-inverting input and the inverting input of the comparator 143-1 are balanced. In the auto-zero operation, the charges accumulated in the DC blocking capacitors 144-2 and 145-2 are controlled so that the non-inverting input and the inverting input of the comparator 143-2 are balanced.

[0058] The auto-zero control unit 114F outputs an auto-zero signal AZ to each of the comparators 143-1 and 143-2 to control the auto-zero operation of each of the comparators 143-1 and 143-2. ​​The auto-zero signal AZ can be shared by all columns.

[0059] At this time, when auto-zero is canceled, the ramp source follower circuits 141-1 and 141-2 can vary the charge accumulated in the DC blocking capacitors 145-1 and 145-2. The variation in the charge accumulated in the DC blocking capacitors 145-1 and 145-2 can be achieved by utilizing the variation in the characteristics of the ramp source follower circuits 141-1 and 141-2. Therefore, the ramp source follower circuits 141-1 and 141-2 can vary the inversion timing of the comparators 143-1 and 143-2, thereby mitigating energy concentration when detecting the P-phase level of each column.

[0060] 5 is a diagram showing an example of the configuration of the comparison circuit according to the first embodiment. Note that, although the diagram shows an example of the configuration of the comparator 143-1, the comparator 143-2 can also be configured in the same way.

[0061] In the figure, the comparison circuit includes a comparator 143-1 and DC blocking capacitors 144-1 and 145-1. The comparator 143-1 compares the potential of a reference signal REF output via a ramp source follower circuit 141-1 with the potential VSL of a vertical signal line 132-1. The potential of the reference signal REF is input to a non-inverting input terminal of the comparator 143-1 via a DC blocking capacitor 145-1. The potential VSL of the vertical signal line 132-1 is input to an inverting input terminal of the comparator 143-1 via a DC blocking capacitor 144-1.

[0062] The comparator 143-1 balances the comparator inputs DV1 and DV2 based on the auto-zero operation, and outputs a voltage corresponding to the difference between the comparator inputs DV1 and DV2. The comparator 143-1 includes PMOS transistors 231 and 232, NMOS transistors 233 to 235, and switches 236 and 237.

[0063] The PMOS transistor 231 and the NMOS transistor 233 are connected in series. The PMOS transistor 232 and the NMOS transistor 234 are connected in series. The sources of the PMOS transistors 231 and 232 are connected to the upper potential VDD, and the gates of the PMOS transistors 231 and 232 are connected to the drain of the PMOS transistor 231. In this case, the PMOS transistors 231 and 232 can form a current mirror. The upper potential VDD may be the power supply potential.

[0064] A reference signal REF is input to the gate of the NMOS transistor 233 via a DC blocking capacitor 145-1. A potential VSL of the vertical signal line 132-1 is connected to the gate of the NMOS transistor 234 for each column via a DC blocking capacitor 144-1.

[0065] A switch 236 is connected between the gate and drain of the NMOS transistor 233, and a switch 237 is connected between the gate and drain of the NMOS transistor 234. The sources of the NMOS transistors 233 and 234 are connected to the lower potential VSS via an NMOS transistor 235. The lower potential VSS may be grounded.

[0066] The switches 236 and 237 are opened and closed based on the auto-zero signal AZ. During the auto-zero period, the switches 236 and 237 are turned on based on the auto-zero signal AZ. At this time, current flows through the PMOS transistors 231 and 232 based on the current mirror operation of the PMOS transistors 231 and 232. Charge is accumulated in the DC-blocking capacitors 144-1 and 145-1 so that the non-inverting input and the inverting input of the comparator 143-1 are balanced. By varying the charge accumulated in the DC-blocking capacitors 145-1 and 145-2 of the ramp source follower circuits 141-1 and 141-2 when the auto-zero mode is canceled, the inversion timing of the comparators 143-1 and 143-2 can be varied.

[0067] A bias voltage BIAS is applied to the gate of the NMOS transistor 235. The NMOS transistor 235 can operate as a constant current source based on the bias voltage BIAS.

[0068] 6 is a diagram showing an example of the configuration of the ramp source follower circuit according to the first embodiment, which shows an example of the configuration of ramp source follower circuits 141-1 to 141-3 for three columns.

[0069] In the figure, the ramp source follower circuit 141-1 includes PMOS transistors 311 to 313, a switch 314, and a capacitor 315. The PMOS transistors 311 to 313 are connected in series with each other. A capacitor 315 is connected between the gate and source of the PMOS transistor 311. A bias voltage BA1 is applied to the gate of the PMOS transistor 311 via the switch 314. The switch 314 can reduce noise by turning off before the slope of the P-phase ramp wave. A bias voltage BA2 is applied to the gate of the PMOS transistor 312. A reference signal REF is input to the gate of the PMOS transistor 313.

[0070] The ramp source follower circuits 141-2 and 141-3 can also be configured in the same manner as the ramp source follower circuit 141-1. In this case, source follower outputs SFO1 to SFO3 are output from the connection points of the PMOS transistors 312 and 313 of the ramp source follower circuits 141-1 to 141-3. The source follower outputs SFO1 to SFO3 can follow the potential of the reference signal REF. In this case, the source follower outputs SFO1 to SFO3 can vary based on variations in the characteristics of the PMOS transistors 313 of the ramp source follower circuits 141-1 to 141-3.

[0071] FIG. 7 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the first embodiment.

[0072] 1, each horizontal readout period is provided with an auto-zero period K11 and an AD conversion period K12. Each AD conversion period K12 is provided with a P-phase AD conversion period KP1 and a D-phase AD conversion period KD1.

[0073] During the auto-zero period K11, the auto-zero signal AZ rises, and electric charge is accumulated in each of the DC-cut capacitors 144-1, 145-1, 144-2, and 145-2 so that the non-inverting input and the inverting input of each of the comparators 143-1 and 143-2 are balanced. At this time, the switching signal CNT is set to a high level, and each of the switching transistors 142-1 and 142-2 is turned on.

[0074] After the auto-zero signal AZ rises, the switching signal CNT falls, turning off the switching transistors 142-1 and 142-2. As a result, the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are disconnected, causing variations in the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2.

[0075] Then, in the auto-zero period K11, when the switching signal CNT rises, the switching transistors 142-1 and 142-2 are turned on, so that the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are connected, and the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2 converge.

[0076] Then, during the convergence period of each ramp source follower circuit 141-1, 141-2, the auto-zero signal AZ falls, and auto-zero is canceled. At this time, the electric charges accumulated in each DC cut capacitor 145-1, 145-2 are dithered so as to reflect the variations in the source follower outputs SFO1, SFO2 during the convergence period of each ramp source follower circuit 141-1, 141-2.

[0077] Next, the reset signal RST falls and the selection signal SEL rises. At this time, the reset transistor 123 of each pixel 120-1, 120-2 turns off and the selection transistor 125 turns on. Then, the potential of each vertical signal line 132-1, 132-2 is set based on the source follower operation when the P-phase level of the floating diffusion FD of each pixel 120-1, 120-2 is applied to the gate of the amplification transistor 124, and is input to each comparator 143-1, 143-2 via each DC cut capacitor 144-1, 144-2. In addition, the source follower outputs SFO1, SFO2 dithered based on each ramp source follower circuit 141-1, 141-2 are input to each comparator 143-1, 143-2 via each DC cut capacitor 145-1, 145-2.

[0078] Then, in each comparator 143-1, 143-2, the potential of each vertical signal line 132-1, 132-2 during a P-phase AD conversion period KP1 is compared with the potential of the source follower outputs SFO1, SFO2. Then, during the P-phase AD conversion period KP1, the P-phase levels read out from each pixel 120-1, 120-2 are AD converted based on a count operation until the potential of each vertical signal line 132-1, 132-2 matches the potential of the source follower outputs SFO1, SFO2.

[0079] Next, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistors 125 of the pixels 120-1 and 120-2 turn off and the transfer transistors 122 turn on. Then, the charges accumulated in the photodiodes 121 of the pixels 120-1 and 120-2 are transferred to the floating diffusions FD.

[0080] Next, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 of each pixel 120-1, 120-2 turns on and the transfer transistor 122 turns off. Then, the potential of each vertical signal line 132-1, 132-2 is set based on the source follower operation when the D-phase level of the floating diffusion FD of each pixel 120-1, 120-2 is applied to the gate of the amplification transistor 124, and the potential is input to each comparator 143-1, 143-2 via each DC cut capacitor 144-1, 144-2.

[0081] Then, in each comparator 143-1, 143-2, the potential of each vertical signal line 132-1, 132-2 during a D-phase AD conversion period KD1 is compared with the potential of the source follower outputs SFO1, SFO2. At this time, the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are connected, so the source follower outputs SFO1, SFO2 are equal to each other. Then, during the D-phase AD conversion period KD1, the D-phase levels read out from each pixel 120-1, 120-2 are AD converted based on a count operation until the potential of each vertical signal line 132-1, 132-2 matches the potential of the source follower outputs SFO1, SFO2.

[0082] FIG. 8 is a block diagram showing connection paths by the switching unit after auto-zero cancellation according to the first embodiment.

[0083] In the diagram, during an AD conversion period K12, the switching signal CNT rises, turning on the switching transistors 142-1 and 142-2. This connects the output terminal of the ramp source follower circuit 141-1 to the output terminal of the ramp source follower circuit 141-2. As a result, the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2 are averaged between columns, making it possible to suppress random noise in the ramp source follower circuits 141-1 and 141-2.

[0084] FIG. 9 is a timing chart showing an example of a P-phase level distribution after dithering based on the ramp source follower of the solid-state imaging device according to the first embodiment.

[0085] In the figure, when the source follower outputs SFO1 and SFO2 are shorted during the auto-zero period K11, the source follower outputs SFO1 and SFO2 are not dithered, and therefore the P-phase level distribution D1 at this time becomes narrower.

[0086] On the other hand, if the source follower outputs SFO1 and SFO2 are opened before being shorted during the auto-zero period K11, the source follower outputs SFO1 and SFO2 are dithered. As a result, the P-phase level distribution D2 at this time becomes wider, and the distribution width BA can be increased.

[0087] In this way, in the first embodiment described above, the P-phase level of each column is dithered by switching the source follower outputs SFO1 and SFO2 from open to short during the auto-zero period, which makes it possible to suppress random noise in the ramp source follower circuits 141-1 and 141-2 during the AD conversion period K12 and to alleviate energy concentration when detecting the P-phase level of each column.

[0088] 2. Second Embodiment In the first embodiment described above, the P-phase level of each column is dithered by switching the source follower outputs SFO1 and SFO2 from open to short during the auto-zero period. In this second embodiment, the P-phase level of each column is dithered by switching the source follower outputs SFO1 and SFO2 from short to open during the auto-zero period.

[0089] FIG. 10 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the second embodiment.

[0090] 1, each horizontal readout period is provided with an auto-zero period K21 and an AD conversion period K22. Each AD conversion period K22 is provided with a P-phase AD conversion period KP2 and a D-phase AD conversion period KD2.

[0091] During the auto-zero period K21, the auto-zero signal AZ rises, and electric charge is accumulated in each of the DC-cut capacitors 144-1, 145-1, 144-2, and 145-2 so that the non-inverting input and the inverting input of each of the comparators 143-1 and 143-2 are balanced. At this time, the switching signal CNT is set to a low level, and each of the switching transistors 142-1 and 142-2 is turned off.

[0092] After the auto-zero signal AZ rises, the switching signal CNT rises and the switching transistors 142-1 and 142-2 are turned on. As a result, the output terminal of the ramp source follower circuit 141-1 and the output terminal of the ramp source follower circuit 141-2 are connected, and the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2 converge.

[0093] Next, in the auto-zero period K21, when the switching signal CNT falls, the switching transistors 142-1 and 142-2 are turned off, which disconnects the output terminal of the ramp source follower circuit 141-1 from the output terminal of the ramp source follower circuit 141-2, causing the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2 to vary.

[0094] Then, after the switching signal CNT falls, the auto-zero signal AZ falls, and the auto-zero is canceled. At this time, the electric charges accumulated in the DC cut capacitors 145-1 and 145-2 are dithered so as to reflect the variations in the source follower outputs SFO1 and SFO2 of the ramp source follower circuits 141-1 and 141-2.

[0095] After the charges accumulated in the DC-cut capacitors 145-1 and 145-2 are dithered, the P-phase AD conversion period KP2 and the D-phase AD conversion period KD2 are sequentially started. During the P-phase AD conversion period KP2 and the D-phase AD conversion period KD2, the same processing as during the P-phase AD conversion period KP1 and the D-phase AD conversion period KD1 is performed. However, during the P-phase AD conversion period KP1 and the D-phase AD conversion period KD1, the processing is performed with the source follower outputs SFO1 and SFO2 converged, whereas during the P-phase AD conversion period KP2 and the D-phase AD conversion period KD2, the processing is performed with the source follower outputs SFO1 and SFO2 fluctuating.

[0096] FIG. 11 is a block diagram showing connection paths by a switching unit after auto-zero cancellation according to the second embodiment.

[0097] In the figure, during the AD conversion period K22, the switching signal CNT falls, turning off the switching transistors 142-1 and 142-2. This disconnects the output terminal of the ramp source follower circuit 141-1 from the output terminal of the ramp source follower circuit 141-2. As a result, it is possible to suppress noise such as streaking caused by kickbacks KB1 and KB2 from the comparators 143-1 and 143-2 interfering with other columns.

[0098] In this way, in the second embodiment described above, the P-phase level of each column is dithered by switching the source follower outputs SFO1 and SFO2 from short to open during the auto-zero period. This makes it possible to suppress kickbacks KB1 and KB2 from the comparators 143-1 and 143-2 during the AD conversion period K12 from interfering with other columns, while mitigating energy concentration when detecting the P-phase level of each column.

[0099] 3. Third Embodiment In the first embodiment described above, the P-phase level of each column is dithered based on the variations in the source follower outputs SFO1 and SFO2. In this third embodiment, the output timing of the ramp source follower is controlled randomly for each row within the auto-zero period.

[0100] FIG. 12 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the third embodiment.

[0101] In the figure, an auto-zero period K31 is provided in each horizontal readout period instead of the auto-zero period K11 in the first embodiment. The other timing charts in the third embodiment are the same as those in the first embodiment.

[0102] During the auto-zero period K31, the auto-zero signal AZ rises, and then the switching signal CNT falls. Then, the switching signal CNT rises, and then the auto-zero signal AZ falls. Here, the switching control unit 114E can randomly control the rising timing of the switching signal CNT for each row. By randomly controlling the rising timing of the switching signal CNT for each row, the switching control unit 114E can vary the rising timing of the switching signal CNT for each row. This allows the charge accumulated in each DC-cut capacitor 145-1, 145-2 to be dithered for each row so that the row-by-row variation in the rising timing of the switching signal CNT is reflected. Therefore, not only can the charge accumulated in each DC-cut capacitor 145-1, 145-2 be dithered between different columns, but the charge accumulated in each DC-cut capacitor 145-1, 145-2 can also be dithered for each row within the same column. As a result, it is possible to alleviate energy concentration when detecting the P-phase level of each column, and also to suppress vertical streaks caused by quantization errors.

[0103] In this way, in the third embodiment described above, the output timing of the source follower outputs SFO1 and SFO2 is controlled randomly for each row within the auto-zero period, which allows dithering of the charges accumulated in the DC cut capacitors 145-1 and 145-2 for each row within the same column, thereby suppressing vertical stripes caused by quantization errors.

[0104] In the above-described third embodiment, an example has been shown in which randomization of the output timing of the ramp source follower for each row within the auto-zero period is applied to the above-described first embodiment. In addition to this, randomization of the output timing of the ramp source follower for each row within the auto-zero period may also be applied to the above-described second embodiment.

[0105] 4. Fourth Embodiment In the first embodiment described above, the P-phase level of each column is dithered by switching the source follower outputs SFO1 and SFO2 from open to short during the auto-zero period. In this fourth embodiment, the level of the reference signal REF that is compared with the pixel signal during the auto-zero period is changed.

[0106] FIG. 13 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the fourth embodiment.

[0107] 1, each horizontal readout period is provided with an auto-zero period K41 and an AD conversion period K42. Each AD conversion period K42 is provided with a P-phase AD conversion period KP4 and a D-phase AD conversion period KD4.

[0108] During the auto-zero period K41, the auto-zero signal AZ rises, and then the switching signal CNT falls. After that, the switching signal CNT rises, and then the auto-zero signal AZ falls. Here, the reference signal generation unit 114D can change the level of the reference signal REF within the auto-zero period. By changing the level of the reference signal REF within the auto-zero period, the reference signal generation unit 114D can increase the variability in the level of the reference signal REF when auto-zero is canceled, and can increase the dither of the charge accumulated in each of the DC-blocking capacitors 145-1 and 145-2.

[0109] In this way, in the fourth embodiment described above, the level of the reference signal REF is changed within the auto-zero period, which makes it possible to control the dither of the charge stored in each of the DC blocking capacitors 145-1 and 145-2 and to control the concentration of energy when detecting the P-phase level of each column.

[0110] In the fourth embodiment, the level control of the reference signal REF within the auto-zero period is applied to the first embodiment. Alternatively, the level control of the reference signal REF within the auto-zero period may be applied to the second embodiment.

[0111] 5. Fifth Embodiment In the above-described first embodiment, dithering at the P-phase level of each column is applied to CDS readout of the pixel 120 provided with a single photodiode 121. In this fifth embodiment, dithering at the D-phase level of each column is applied to DDS readout of the LOFIC pixel.

[0112] FIG. 14 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0113] In the figure, pixel 320 includes photodiodes PD1 and PD2 and floating diffusions FD1 to FD3 instead of the photodiode 121 and floating diffusion FD of the first embodiment described above. Furthermore, pixel 320 includes a capacitor 126, a pass transistor 127, a switching transistor 128, and a transfer transistor 129 in addition to pixel 120 of the first embodiment described above. Other than that, the configuration of pixel 320 of the fifth embodiment is the same as the configuration of pixel 120 of the first embodiment described above.

[0114] MOS transistors may be used for the pass transistor 127, the switching transistor 128, and the transfer transistor 129. The capacitor 126 may be a MIM (Metal Insulation Metal) capacitor.

[0115] Each of the photodiodes PD1 and PD2 performs photoelectric conversion and accumulates the photoelectrically converted charges. The sensitivity of the photodiode PD2 can be made smaller than that of the photodiode PD1. The cathode of the photodiode PD1 is connected to the floating diffusion FD1 via a transfer transistor 122. The cathode of the photodiode PD2 is connected to the connection point between the capacitor 126 and the pass transistor 127 via a transfer transistor 129.

[0116] The capacitor 126 accumulates charge that overflows from the photodiode PD2. The capacitor 126 may be light-shielded. One end of the capacitor 126 is connected to the connection point between the pass transistor 127 and the transfer transistor 129, and the other end of the capacitor 126 is grounded. The capacitor 126 may be a high-dielectric capacitor.

[0117] The pass transistor 127 sets a path for transferring the charge stored in the capacitor 126 to the floating diffusion FD2. The switching transistor 128 switches the conversion efficiency of the amplification transistor 124. The transfer transistor 129 transfers the charge stored in the photodiode PD2 to the floating diffusion FD3.

[0118] A floating diffusion FD1 is provided at the connection point between the transfer transistor 122 and the switching transistor 128. A floating diffusion FD2 is provided at the connection point between the reset transistor 123 and the switching transistor 128. A floating diffusion FD3 is provided at the connection point between the pass transistor 127 and the transfer transistor 129.

[0119] The pass transistor 127 is connected between the floating diffusions FD2 and FD3. The switching transistor 128 is connected between the floating diffusions FD1 and FD2. The transfer transistor 129 is connected between the floating diffusion FD3 and the cathode of the photodiode PD2.

[0120] A pass setting signal FCG is applied to the gate of the pass transistor 127. A switching signal FDG is applied to the gate of the switching transistor 128. A transfer signal TGS is applied to the gate of the transfer transistor 129. The transfer signal TGS, the pass setting signal FCG, and the switching signal FDG can be transmitted to each pixel 320 via the horizontal drive line 131 in FIG. 2 .

[0121] FIG. 15 is a timing chart showing an example of waveforms at various parts during the readout operation of the solid-state imaging device according to the fifth embodiment.

[0122] In the figure, during shutter period K51, the switching signal FDG, path setting signal FCG, and reset signal RST are set to high level. The selection signal SEL is set to low level. At this time, the transfer signals TGL and TGS rise, the charges in the photodiodes PD1 and PD2 and the floating diffusions FD1 to FD3 are discharged, and the conversion efficiency of the amplification transistor 124 is reduced.

[0123] Next, in an accumulation period K52, the transfer signals TGL, TGS and the path setting signal FCG fall. At this time, charges are accumulated in the photodiodes PD1, PD2 based on the incidence of light on the photodiodes PD1, PD2.

[0124] Next, in the low-efficiency first P-phase single read period K53, the selection signal SEL rises and the reset signal RST falls. At this time, the switching transistor 128 turns on, reducing the conversion efficiency of the amplification transistor 124. Furthermore, the reset transistor 123 turns off and the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gates of the amplification transistor 124. Then, the low-efficiency first P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0125] Next, in the high-efficiency first P-phase single read period K54, the switching signal FDG falls. At this time, the switching transistor 128 is turned off, and the conversion efficiency of the amplification transistor 124 increases. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency first P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0126] Thereafter, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0127] Next, in a high-efficiency first D-phase individual read period K55, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency first D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0128] Then, the selection signal SEL falls, and the transfer signal TGL and the switching signal FDG rise. At this time, the selection transistor 125 turns off, and the transfer transistor 122 and the switching transistor 128 turn on, so that the charge stored in the photodiode PD1 is transferred to the floating diffusions FD1 and FD2. At this time, the conversion efficiency of the amplification transistor 124 decreases.

[0129] Next, in a low-efficiency first D-phase individual read period K56, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gates of the amplification transistors 124. Then, the low-efficiency first D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0130] A CDS read RDA can be performed during the low-efficiency first P-phase individual read period K53, the high-efficiency first P-phase individual read period K54, the high-efficiency first D-phase individual read period K55, and the low-efficiency first D-phase individual read period K56. In this CDS read RDA, the P-phase level of each column can be dithered during the auto-zero period based on the output of a ramp source follower of a reference signal used for AD conversion. Furthermore, in this CDS read RDA, the randomization of the output timing of the ramp source follower for each row during the auto-zero period of the third embodiment described above may be applied, or the level control of the reference signal during the auto-zero period of the fourth embodiment described above may be applied.

[0131] Thereafter, the selection signal SEL falls and the reset signal RST rises, turning on the reset transistor 123 and discharging the charges in the floating diffusions FD1 and FD2.

[0132] Furthermore, after the reset signal RST falls, the path setting signal FCG rises, turning the reset transistor 123 off and the path transistor 127 on.

[0133] Next, in a second P-phase individual readout period K57, the selection signal SEL rises. At this time, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the second P-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, the second P-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0134] Thereafter, the selection signal SEL falls and the transfer signal TGS rises. At this time, the selection transistor 125 turns off and the transfer transistor 129 turns on, and the charge accumulated in the photodiode PD2 is transferred from the floating diffusion FD1 to FD3.

[0135] Next, in a second D-phase individual read period K58, the selection signal SEL rises and the transfer signal TGS falls. At this time, the potential of the vertical signal line 132 is set based on the source follower operation when the second D-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, the second D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0136] In the second P-phase individual read period K57 and the second D-phase individual read period K58, a CDS read RDA' can be performed. In this CDS read RDA', the P-phase level of each column can be dithered during the auto-zero period based on the output of the ramp source follower of the reference signal used for AD conversion. Furthermore, in this CDS read RDA', the randomization of the output timing of the ramp source follower for each row during the auto-zero period of the third embodiment described above may be applied, or the level control of the reference signal during the auto-zero period of the fourth embodiment described above may be applied.

[0137] Next, in a D-phase batch readout period K59, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, based on the potential of the vertical signal line 132 at that time, the D-phase level is AD converted.

[0138] After that, the reset signal RST rises and the selection signal SEL falls. At this time, the reset transistor 123 turns on and the selection transistor 125 turns off, and the charges in the floating diffusions FD1 to FD3 are discharged. After that, the reset signal RST falls and the reset transistor 123 turns off.

[0139] Next, in a P-phase batch readout period K60, the selection signal SEL rises. At this time, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusions FD1 to FD3 are applied to the gate of the amplification transistor 124. Then, based on the potential of the vertical signal line 132 at that time, the P-phase level is AD converted.

[0140] During the D-phase batch read period K59 and the P-phase batch read period K60, a DDS read RDB can be performed. In this DDS read RDB, the DP phase level of each column can be dithered during the auto-zero period based on the output of the ramp source follower of the reference signal used for AD conversion. Also, in this DDS read RDB, the randomization of the output timing of the ramp source follower for each row during the auto-zero period of the third embodiment described above may be applied, or the level control of the reference signal during the auto-zero period of the fourth embodiment described above may be applied.

[0141] Because the potential of the ramp wave included in the reference signal does not depend on the amount of light, the amount of variation does not change even when D-phase pre-reading of the DDS readout RDB is performed. Therefore, the inversion timing can be varied even when D-phase pre-reading is performed, which can alleviate energy concentration and suppress vertical stripes caused by quantization errors.

[0142] In this way, in the fifth embodiment, dithering at the D-phase level of each column is applied to the DDS readout of the LOFIC pixels, which makes it possible to expand the dynamic range, alleviate energy concentration, and suppress vertical stripes caused by quantization errors.

[0143] 6. Sixth Embodiment In the first embodiment described above, the P-phase level of each column is dithered based on the variations in the source follower outputs SFO1 and SFO2. In this sixth embodiment, semiconductor chips each having a pixel array unit in which pixels are arranged in a matrix are stacked.

[0144] FIG. 16 is a perspective view showing an example of a stack of pixel array units according to the sixth embodiment.

[0145] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0146] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be the pixels 120 of the first embodiment described above, or may be the pixels 320 of the first embodiment described above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0147] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and a control circuit 928 are formed in the peripheral circuit 924. Any of the column signal processing units 114 according to the first to fifth embodiments may be applied to the column ADC 926. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0148] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0149] As described above, in the sixth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0150] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0151] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0153] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0154] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0155] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0159] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0160] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0161] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0162] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0163] In FIG. 18, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0164] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0165] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0167] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0168] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0169] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0170] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to alleviate energy concentration and reduce degradation of image quality, such as vertical streaks.

[0171] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0172] The present technology may also be configured as follows: (1) An imaging device including: a first column signal line connected to a first pixel; a first comparison circuit connected to the first column signal line; a second column signal line provided adjacent to the first column signal line and connected to a second pixel; a second comparison circuit connected to the second column signal line; a reference signal generation unit that generates a reference signal; a first ramp source follower circuit connected between the reference signal generation unit and the first comparison circuit; a second ramp source follower circuit connected between the reference signal generation unit and the second comparison circuit; and a switching unit that switches a connection between an output terminal of the first ramp source follower circuit and an output terminal of the second ramp source follower circuit. (2) The first comparison circuit comprises: a first comparator that compares a first pixel signal transmitted via the first column signal line with the reference signal; a first capacitor connected to a first non-inverting input terminal of the first comparator; and a second capacitor connected to a first inverting input terminal of the first comparator; the second comparison circuit comprises: a second comparator that compares a second pixel signal transmitted via the second column signal line with the reference signal; a third capacitor connected to a second non-inverting input terminal of the second comparator; and a fourth capacitor connected to a second inverting input terminal of the second comparator; and the first comparison circuit controls charges accumulated in the first capacitor and the second capacitor so that an input potential of the first non-inverting input terminal and an input potential of the first inverting input terminal are balanced during an auto-zero period; The imaging device according to (1), wherein the second comparator circuit controls the charges accumulated in the third capacitor and the fourth capacitor so that the input potential of the second non-inverting input terminal and the input potential of the second inverting input terminal are balanced during the auto-zero period. (3) The imaging device according to (2), wherein the charge accumulated in the first capacitor and the charge accumulated in the third capacitor when auto-zero is released are varied based on a variation in the characteristics of the first ramp source follower circuit and the second ramp source follower circuit.(4) The imaging device according to (2) or (3), wherein the switching unit, during the auto-zero period, disconnects the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit, and then connects the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit. (5) The imaging device according to (2) or (3), wherein the switching unit, during the auto-zero period, connects the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit, and then disconnects the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit. (6) The imaging device according to any of (1) to (5), wherein the reference signal generation unit changes a level of the reference signal during the auto-zero period. (7) The imaging device according to any one of (1) to (6), further comprising: a pixel array unit in which pixels are arranged in a matrix in the row and column directions, the first pixel being arranged in a first column, and the second pixel being arranged in a second column; and a switching unit control unit that randomly controls switching timing of the switching unit for each row. (8) The imaging device according to any one of (1) to (7), wherein the first pixel and the second pixel each comprise a lateral overflow integration capacitor (LOFIC). (9) The imaging device according to (8), wherein the first pixel and the second pixel each further comprise: a first photodiode; and a second photodiode having a lower sensitivity than the first photodiode, with overflow charge being accumulated in the LOFIC. The imaging device according to (8). (10) The imaging device according to (9), wherein a signal detected by the second photodiode is read out based on double data sampling (DDS) readout.

[0173] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 114A Ramp source follower unit 114B Switching unit 114C Column ADC unit 114D Reference signal generation unit 114E Switching control unit 114F Auto-zero control unit 115 Horizontal scanning circuit 116 Control circuit 120 Pixel 131 Horizontal drive line 132 Vertical signal line 141-1, 141-2 Ramp source follower circuit 142-1, 142-2 Switching transistor 143-1, 143-2 Comparator 144-1, 145-1, 144-2, 145-2 DC cut capacitors

Claims

1. An imaging device comprising: a first column signal line connected to a first pixel; a first comparison circuit connected to the first column signal line; a second column signal line provided adjacent to the first column signal line and connected to a second pixel; a second comparison circuit connected to the second column signal line; a reference signal generation unit that generates a reference signal; a first ramp source follower circuit connected between the reference signal generation unit and the first comparison circuit; a second ramp source follower circuit connected between the reference signal generation unit and the second comparison circuit; and a switching unit that switches a connection between an output terminal of the first ramp source follower circuit and an output terminal of the second ramp source follower circuit.

2. The first comparison circuit comprises: a first comparator that compares a first pixel signal transmitted through the first column signal line with the reference signal; a first capacitor connected to a first non-inverting input terminal of the first comparator; and a second capacitor connected to a first inverting input terminal of the first comparator; the second comparison circuit comprises: a second comparator that compares a second pixel signal transmitted through the second column signal line with the reference signal; a third capacitor connected to a second non-inverting input terminal of the second comparator; and a fourth capacitor connected to a second inverting input terminal of the second comparator; and the first comparison circuit controls the charges stored in the first capacitor and the second capacitor so that the input potential of the first non-inverting input terminal and the input potential of the first inverting input terminal are balanced during an auto-zero period; 2. The imaging device according to claim 1, wherein the second comparison circuit controls the charges stored in the third capacitor and the fourth capacitor so that an input potential of the second non-inverting input terminal and an input potential of the second inverting input terminal are balanced during the auto-zero period.

3. The imaging device according to claim 2, wherein the charge stored in the first capacitor and the charge stored in the third capacitor when auto-zero is released are made to vary based on the variation in characteristics of the first ramp source follower circuit and the second ramp source follower circuit.

4. The imaging device according to claim 2, wherein the switching unit disconnects the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit during the auto-zero period, and then connects the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit.

5. The imaging device according to claim 2, wherein the switching unit connects the output terminal of the first ramp source follower circuit to the output terminal of the second ramp source follower circuit during the auto-zero period, and then disconnects the output terminal of the first ramp source follower circuit from the output terminal of the second ramp source follower circuit.

6. The imaging device according to claim 1, wherein the reference signal generating section changes a level of the reference signal during the auto-zero period.

7. The imaging device according to claim 1, further comprising: a pixel array section in which pixels are arranged in a matrix in row and column directions, the first pixel being arranged in a first column, and the second pixel being arranged in a second column; and a switching section control section that randomly controls the switching timing of the switching section for each row.

8. The imaging device according to claim 1, wherein the first pixel and the second pixel each include a lateral overflow integration capacitor (LOFIC).

9. The imaging device according to claim 8, wherein each of the first pixel and the second pixel further comprises: a first photodiode; and a second photodiode having a lower sensitivity than the first photodiode, the overflowing charge of which is accumulated in the LOFIC.

10. The imaging device according to claim 9, wherein the signal detected by the second photodiode is read out based on a DDS (Double Data Sampling) readout.

Images