Wiring board

Abstract

[Problem] To provide a wiring board having a novel configuration. [Solution] A wiring board 10 has a substrate 20 having a conductor layer 26, and has disposed on the substrate 20: an optical element region 30; and a plurality of optical waveguides 40 each having lower cladding 41, a core 42, and upper cladding 43. The optical element region 30 includes an electric connection material 50 for electrically connecting the conductor layer 26 and the optical element region 30. The optical waveguides 40 are arranged and have the cores 42, which are optically coupled to the optical element region 30, exposed therefrom.

Description

wiring board

[0001] The present disclosure relates to a wiring substrate.

[0002] Patent Document 1 discloses an optical module in which an optical waveguide with an inclined mirror is formed on a substrate, and also discloses an optical module having a planar optical element mounted on the upper surface of the optical waveguide, with the substrate-side pads and the planar optical element-side pads connected by solder bumps.

[0003] Japanese Patent Application Publication No. 2003-215371

[0004] The wiring board of the present disclosure is, for example, a wiring board having a substrate having a conductor layer, and an optical element region and an optical waveguide having a lower clad, a core, and an upper clad arranged on the substrate, wherein the optical element region has an electrical connecting material that electrically connects the conductor layer and the optical element region, and the core of the optical waveguide that is optically coupled to the optical element region is exposed and multiple cores are arranged.

[0005] FIG. 1A is a cross-sectional view of a wiring board 10 in which optical waveguides 40 are arranged in two directions. FIG. 1B is a plan view of a wiring board 10 in which optical waveguides 40 are arranged in two directions. FIG. 2 is a plan view of a wiring board 10A in which optical waveguides 40 are arranged in three directions. FIG. 3 is a plan view of a wiring board 10B in which optical waveguides 40 are arranged in four directions. FIG. 4A is a cross-sectional view of a wiring board 10C in which optical waveguides 40 are arranged in two directions and chips 80 are arranged. FIG. 4B is a plan view of a wiring board 10C in which optical waveguides 40 are arranged in two directions and chips 80 are arranged. FIG. 4C is a plan view of a wiring board 10D in which optical waveguides 40 are arranged in three directions and chips 80 are arranged. FIG. 4D is a plan view of a wiring board 10E in which optical waveguides 40 are arranged in four directions and chips 80 are arranged. FIG. 4E is a plan view of a wiring board 10F on which chips 80 are arranged with optical waveguides 40 arranged in two directions and two rows. FIG. 4F is a plan view of a wiring board 10G on which chips 80 are arranged with optical waveguides 40 arranged in three directions and two rows. FIG. 4G is a plan view of a wiring board 10H on which chips 80 are arranged with optical waveguides 40 arranged in four directions and two rows. FIG. 4H is a plan view of a wiring board 10I on which chips 80 are arranged with optical waveguides 40 arranged in two directions and three rows. FIG. 4I is a plan view of a wiring board 10G on which chips 80 are arranged with optical waveguides 40 arranged in three directions and three rows. FIG. 4J is a plan view of a wiring board 10K on which chips 80 are arranged with optical waveguides 40 arranged in four directions and three rows. FIG. 5A is a diagram showing a preparation process of the substrate 20. FIG. 5B is a diagram showing a formation process of the lower cladding 41. FIG. 5C is a diagram showing a formation process of the cores 42. FIG. 5D is a diagram showing a process for forming the upper clad 43. FIG. 5E is a diagram showing a process for mounting the optical element 60. FIG. 6 is a diagram showing the wiring board 10 in a first connection configuration. FIG. 7 is a diagram showing the wiring board 10 in a second connection configuration. FIG. 8 is a diagram showing the wiring board 10 in a third connection configuration. FIG. 9 is a diagram showing the wiring board 10 in a fourth connection configuration. FIG. 10 is a diagram showing adiabatic bonding. FIG. 11 is a cross-sectional view illustrating a build-up board. FIG. 12 is a cross-sectional view showing the configuration of a build-up board 20A. FIG. 13 is a plan view showing the optical waveguide 40 of a first example. FIG. 14 is a plan view showing the optical waveguide 40 of a second example. FIG. 15 is a diagram showing the role of each component of the wiring board 10, etc.

[0006] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The following embodiment is shown as a preferred example of a wiring board. However, the embodiment is not limited to this example.

[0007] The wiring board 10 is a board on which optical signals and electrical signals are input and output. A plurality of optical waveguides 40 can be arranged on the wiring board 10. In the following description, three types of directions in which the optical waveguides 40 are arranged will be described.

[0008] [Two Directions] Fig. 1A is a cross-sectional view of a wiring board 10 in which optical waveguides 40 are arranged in two directions. Fig. 1B is a plan view of the wiring board 10 in which optical waveguides 40 are arranged in two directions. The wiring board 10 shown in Figs. 1A and 1B is the first type. The wiring board 10 includes a substrate 20 having a conductor layer 26. An optical element region 30 and an optical waveguide 40 having a lower clad 41, a core 42, and an upper clad 43 are arranged on the substrate 20. Note that multiple waveguides may be arranged in one direction.

[0009] The optical element region 30 includes an electrical connection material 50 that electrically connects the conductor layer 26 and the optical element region 30. The electrical connection material 50 is a metal body such as a solder bump. The optical waveguide 40 has an exposed core 42 that optically couples with the optical element region 30. A plurality of optical waveguides 40 are arranged. The plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, two optical waveguides 40 are arranged in two directions, one on the left side and one on the right side of the optical element region 30. Furthermore, although two optical waveguides 40 are arranged in opposing positions on the same line with respect to the optical element region 30 in FIGS. 1A and 1B, two optical waveguides 40 may also be arranged in opposing positions at different angles with respect to the optical element region 30. That is, as shown in FIG. 1B , the two optical waveguides 40 are arranged so as to intersect perpendicularly with the outer edge of the optical device region 30. However, they may also be arranged so as to intersect with the outer edge of the optical device region 30 at an angle other than perpendicular (acute or obtuse). In this case, the left optical waveguide 40 and the right optical waveguide 40 may be arranged at different angles. Furthermore, instead of arranging the two optical waveguides 40 in the same straight line relative to the optical device region 30, two may be arranged in an L-shape or two may be arranged in a V-shape. Furthermore, instead of arranging the two optical waveguides 40 in the same straight line in the horizontal direction relative to the optical device region 30 in FIG. 1B , two may be arranged in the same straight line in the vertical direction relative to the optical device region 30 in FIG. 1B . In other words, the optical waveguides 40 may be arranged symmetrically left and right with respect to the optical device region 30, or symmetrically up and down.

[0010] One optical element 60 is arranged in the optical element region 30. The optical element 60 inputs and outputs optical signals and converts between electrical and optical signals. The exposed portion of the core 42 and a terminal 61 of the optical element 60 are optically coupled. In the optical element region 30, one optical element 60 can be coupled to multiple optical waveguides 40. In the optical element region 30, multiple optical elements, each coupled to one optical waveguide 40, can be arranged in one direction.

[0011] The end of the upper cladding 43 of the optical waveguide 40 is the boundary with the optical element region 30. The optical element region 30 can be disposed at one end (the inner end in FIG. 1A ) of the optical waveguide 40. An external connection member 70 (e.g., an optical fiber, an optical element, etc.) can be disposed at the other end (the outer end in FIG. 1A ) of the optical waveguide 40.

[0012] [Three Directions] FIG. 2 is a plan view of a wiring board 10A in which optical waveguides 40 are arranged in three directions. The wiring board 10A shown in FIG. 2 is a second type. The optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three optical waveguides 40 are arranged in three directions: to the left, right, and below the optical element region 30. The other configurations are the same as those in FIGS. 1A and 1B. The multiple waveguides may be arranged in one direction. The three optical waveguides 40 are arranged in a T-shape, but they may also be arranged in a Y-shape. All three optical waveguides 40 may be arranged straight along the vertical or horizontal direction. All three optical waveguides 40 may be arranged tilted from the vertical or horizontal direction. Some of the three optical waveguides 40 may be arranged straight along the vertical or horizontal direction, and the remaining optical waveguides may be arranged tilted from the vertical or horizontal direction.

[0013] [Four Directions] FIG. 3 is a plan view of a wiring board 10B in which optical waveguides 40 are arranged in four directions. The wiring board 10B shown in FIG. 3 is a third type. The optical waveguides 40 are arranged in different directions around the optical element region 30. Specifically, four optical waveguides 40 are arranged in four directions: left, right, above, and below the optical element region 30. The other configurations are the same as those in FIGS. 1A and 1B. The multiple waveguides may be arranged in one direction. The four optical waveguides 40 are arranged in a cross shape, but they may also be arranged in an X shape. All four optical waveguides 40 may be arranged straight along the vertical or horizontal direction. All four optical waveguides 40 may be arranged tilted from the vertical or horizontal direction. Some of the four optical waveguides 40 may be arranged straight along the vertical or horizontal direction, and the remaining optical waveguides may be arranged tilted from the vertical or horizontal direction.

[0014] The optical element region 30 refers to a region where an optical element 60 can be arranged. The portion where the core 42 of the optical waveguide 40 is exposed can be the boundary line between the optical element region 30 and other regions. One or more optical elements 60 may be arranged in the optical element region 30, and semiconductors and electronic components other than the optical element 60 may also be arranged. The optical element region 30 in the region where the optical waveguide 40 is not arranged can be formed to any size. For example, the optical element region 30 in the region where the optical waveguide 40 is not arranged can be determined by setting the distance between the boundary line of the portion where the core 42 of the optical waveguide 40 is exposed and the optical element 60 equal to the distance. For example, the length from the outer edge of the optical element region 30 to the optical element 60 can be the length from the inner end of the upper cladding 43 to the optical element 60.

[0015] [Chip] FIG. 4A is a cross-sectional view of a wiring substrate 10C on which optical waveguides 40 are arranged in two directions and chips 80 are arranged. FIG. 4B is a plan view of a wiring substrate 10C on which optical waveguides 40 are arranged in two directions and chips 80 are arranged. The wiring substrate 10C shown in FIGS. 4A and 4B includes a chip 80 that is electrically connected to an optical element 60. The chip 80 may be an electrical circuit, an information processing circuit, or other chip. The chip 80 can input or output an electrical signal from the optical element 60. The chip 80 can convert an analog signal to a digital signal or input or output an electrical signal (digital signal) to another component or an external terminal via the conductor layer 26 of the substrate 20.

[0016] 4B , a chip 81 separate from the chip 80 can be disposed below the chip 80. The chip 81 may have the same function as the chip 80, or may have a different function from the chip 80. The chip 81 may be electrically connected to the chip 80, or may be electrically connected to the optical element 60. Note that the arrangement of the chip 81 shown in the figure is an example, and the chip 81 may be disposed in a location not shown (for example, on a substrate separate from the substrate 20).

[0017] The size of the chips 80 and 81 is preferably larger than the size of the optical element 60. However, the size of the chips 80 and 81 may be smaller than or the same as the size of the optical element 60. As shown in FIG. 4A, the height of the chip 80 is preferably larger than the height of the optical element 60. However, the height of the chip 80 may be smaller than or the same as the height of the optical element 60. This also applies to the chip 81. As shown in FIG. 4B, the size of the chip 80 is preferably larger than the size of the chip 81. However, the size of the chip 80 may be smaller than or the same as the size of the chip 81.

[0018] The chip 80 is disposed between the two optical elements 60 so that the optical elements 60-chip 80-optical element 60 are aligned in a straight line. The chip 81 is not disposed between the two optical elements 60. The chip 80 is disposed entirely within the optical element region 30. The chip 81 is disposed partially within the optical element region 30. The chip 81 may be disposed entirely within the optical element region 30, or may be disposed outside the element region 30.

[0019] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, two optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions from the center of the optical element region 30. Specifically, two optical waveguides 40 are arranged on two sides, one on the left side and one on the right side of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30. Three optical waveguides 40 may be arranged in three directions as shown in FIG. 2, or four optical waveguides 40 may be arranged in four directions as shown in FIG. 3. Furthermore, the mounting of the optical elements 60, chip 80, and chip 81 may be performed in the following manner: the optical element 60 may be mounted first, followed by the chip 80 and chip 81; or the optical element 60 may be mounted after the chip 80 and chip 81; the order in which the optical elements 60, chip 80, and chip 81 are mounted is not particularly important. This is also true for other wiring boards.

[0020] 4C is a plan view of a wiring board 10D on which optical waveguides 40 are arranged in three directions and chips 80 are arranged. The wiring board 10D shown in FIG. 4C includes chips 80 that are electrically connected to optical elements 60. A chip 81 separate from chip 80 can be arranged below chip 80.

[0021] The chips 80 and 81 of the wiring board 10D shown in FIG. 4C may be the same as or different from the chips 80 and 81 of the wiring board 10C shown in FIG. 4B. The chips 80 and 81 are entirely disposed within the optical element region 30. The chip 81 may be partially disposed within the optical element region 30, or may be disposed outside the element region 30. The size, height, and placement position of the chips 80 and 81 may be the same as or different from those of the wiring board 10C shown in FIG. 4B. The details regarding the chips 80 and 81 of the wiring board 10D are also applicable to the wiring boards 10E, 10F, 10G, 10H, 10I, 10J, and 10K.

[0022] The chip 80 is disposed between the left optical element 60 and the right optical element 60 so that the left optical element 60-chip 80-right optical element 60 form a straight line. The chip 80 is disposed between the upper optical element 60 and chip 81 so that the upper optical element 60-chip 80-chip 81 form a straight line. The chip 81 is not disposed between the left optical element 60 and the right optical element 60.

[0023] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, three optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three optical waveguides 40 are arranged in three directions, on the left side, right side, and upper side of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0024] 4D is a plan view of a wiring board 10E on which optical waveguides 40 are arranged in four directions and chips 80 are arranged. The wiring board 10E shown in FIG. 4D includes chips 80 that are electrically connected to optical elements 60. A chip 81 separate from chip 80 can be arranged below and to the right of chip 80.

[0025] The chip 80 is disposed between the left optical element 60 and the right optical element 60 so that the left optical element 60, chip 80, and right optical element 60 are aligned in a straight line. The chip 80 is disposed between the upper optical element 60 and the lower optical element 60 so that the upper optical element 60, chip 80, and lower optical element 60 are aligned in a straight line. The chip 81 is not disposed between the left optical element 60 and the right optical element 60. The chip 81 is not disposed between the upper optical element 60 and the lower optical element 60. The chip 81 is disposed in a position where it partially overlaps with the chip 80 when viewed in the vertical direction in the figure. This allows the chips 80 and 81 to be connected in a straight line in the vertical direction in the figure. The chip 81 may also be disposed in a position where it does not overlap with the chip 80 when viewed in the vertical direction in the figure.

[0026] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, four optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, four optical waveguides 40 are arranged in four directions on the left, right, upper and lower sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0027] 4E is a plan view of a wiring board 10F on which optical waveguides 40 are arranged in two directions and in two rows, and on which chips 80 are arranged. The two rows of optical waveguides 40 may or may not be arranged parallel to each other (the same applies below). The wiring board 10F shown in FIG. 4E includes a chip 80 that is electrically connected to the optical element 60. A chip 81 separate from the chip 80 can be arranged below the chip 80.

[0028] The chip 80 is disposed between the two left-hand optical elements 60 and the two right-hand optical elements 60 such that the two left-hand optical elements 60-chip 80-two right-hand optical elements 60 are aligned in a straight line. The chip 81 is not disposed between the two left-hand optical elements 60 and the two right-hand optical elements 60.

[0029] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, four optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of four optical waveguides 40 are arranged in two rows on the left and right sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0030] 4F is a plan view of a wiring board 10G on which optical waveguides 40 are arranged in three directions and two rows, and chips 80 are arranged. The wiring board 10G shown in FIG. 4F includes chips 80 that are electrically connected to optical elements 60. A chip 81 separate from chip 80 can be arranged below chip 80.

[0031] The chip 80 is disposed between the two optical elements 60 on the left side and the two optical elements 60 on the right side so that the two optical elements 60 on the left side, the chip 80, and the two optical elements 60 on the right side are aligned in a straight line. The chip 80 is disposed between the two upper optical elements 60 and the chip 81 so that the two upper optical elements 60, the chip 80, and the chip 81 are aligned in a straight line. The chip 81 is not disposed between the two optical elements 60 on the left side and the two optical elements 60 on the right side.

[0032] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, six optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of six optical waveguides 40 are arranged in two rows in three directions on the left, right, and upper sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0033] 4G is a plan view of a wiring board 10H on which optical waveguides 40 are arranged in four directions and in two rows, and on which chips 80 are arranged. The wiring board 10H shown in FIG. 4G includes chips 80 that are electrically connected to optical elements 60. A chip 81 separate from chip 80 can be arranged below and to the right of chip 80.

[0034] The chip 80 is arranged between the two optical elements 60 on the left side and the two optical elements 60 on the right side so that the two optical elements 60 on the left side, the chip 80, and the two optical elements 60 on the right side are aligned in a straight line. The chip 80 is arranged between the two upper optical elements 60 and the two lower optical elements 60 so that the two upper optical elements 60, the chip 80, and the two lower optical elements 60 are aligned in a straight line. The chip 81 is not arranged between the two optical elements 60 on the left side and the two right side. The chip 81 is not arranged between the two upper optical elements 60 and the two lower optical elements 60. The chip 81 is arranged in a position where it partially overlaps with the chip 80 when viewed in the vertical direction in the figure. This allows the chips 80 and 81 to be connected in a straight line in the vertical direction in the figure. The chip 81 may also be arranged in a position where it does not overlap with the chip 80 when viewed in the vertical direction in the figure.

[0035] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, eight optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of eight optical waveguides 40 are arranged in two rows in four directions on the left, right, upper, and lower sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0036] 4H is a plan view of a wiring board 10I on which optical waveguides 40 are arranged in two directions and in three rows, and on which chips 80 are arranged. The three rows of optical waveguides 40 may or may not be arranged in parallel (the same applies below). The wiring board 10I shown in FIG. 4H includes a chip 80 that is electrically connected to the optical element 60. A chip 81 separate from the chip 80 can be arranged below the chip 80.

[0037] The chip 80 is disposed between the three optical elements 60 on the left side and the three optical elements 60 on the right side so that the three optical elements 60 on the left side, the chip 80, and the three optical elements 60 on the right side are aligned in a straight line. The chip 81 is not disposed between the three optical elements 60 on the left side and the three optical elements 60 on the right side.

[0038] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, six optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of six optical waveguides 40 are arranged in three rows on two directions, on the left and right sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0039] 4I is a plan view of a wiring board 10G on which optical waveguides 40 are arranged in three directions and three rows, and chips 80 are arranged. The wiring board 10J shown in FIG. 4I includes chips 80 that are electrically connected to the optical elements 60. A chip 81 separate from the chip 80 can be arranged below and to the right of the chip 80.

[0040] The chip 80 is arranged between the three optical elements 60 on the left side and the three optical elements 60 on the right side so that the three optical elements 60 on the left side, the chip 80, and the three optical elements 60 on the right side are aligned in a straight line. The chip 80 is arranged between the three optical elements 60 on the upper side and the chip 81 so that the three optical elements 60 on the upper side, the chip 80, and the chip 81 are aligned in a straight line. The chip 81 is not arranged between the three optical elements 60 on the left side and the three optical elements 60 on the right side.

[0041] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, nine optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of nine optical waveguides 40 are arranged in three rows on the left, right, and upper sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0042] 4J is a plan view of a wiring board 10K on which optical waveguides 40 are arranged in four directions and three rows, and chips 80 are arranged. The wiring board 10K shown in FIG. 4J includes chips 80 that are electrically connected to optical elements 60. A chip 81 separate from chip 80 can be arranged below chip 80.

[0043] The chip 80 is arranged between the three optical elements 60 on the left side and the three optical elements 60 on the right side so that the three optical elements 60 on the left side, the chip 80, and the three optical elements 60 on the right side are aligned in a straight line. The chip 80 is arranged between the three optical elements 60 on the upper side and the three optical elements 60 on the lower side so that the three optical elements 60 on the upper side, the chip 80, and the three optical elements 60 on the lower side are aligned in a straight line. The chip 81 is not arranged between the three optical elements 60 on the left side and the three optical elements 60 on the right side. The chip 81 is not arranged between the three optical elements 60 on the upper side and the three optical elements 60 on the lower side. The chip 81 is arranged in a position where it partially overlaps with the chip 80 when viewed in the vertical direction in the figure. This allows the chips 80 and 81 to be connected in a straight line in the vertical direction in the figure. The chip 81 may also be arranged in a position where it does not overlap with the chip 80 when viewed in the vertical direction in the figure.

[0044] A plurality of optical elements 60 are arranged in the optical element region 30. Specifically, twelve optical elements 60 are arranged in the optical element region 30. A plurality of optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, a total of twelve optical waveguides 40 are arranged in three rows in four directions on the left, right, upper, and lower sides of the optical element region 30. A plurality of optical waveguides 40 and a plurality of optical elements 60 are arranged in the optical element region 30.

[0045] Although the number of rows of the optical waveguides 40 has been described as one to three, it may be four or more. The number of rows of the optical waveguides 40 can be changed depending on the direction. For example, the optical waveguides 40 may have one row on the upper and left sides and two rows on the lower and right sides. Alternatively, the optical waveguides 40 may have one row on the upper and lower sides and two rows on the left and right sides. Furthermore, the optical waveguides 40 may have one row on the upper side, two rows on the left side, three rows on the lower side, and four rows on the right side.

[0046] The wiring boards 10 and the like described so far (wiring board 10, wiring board 10A, wiring board 10B, wiring board 10C, wiring board 10D, wiring board 10E, wiring board 10F, wiring board 10G, wiring board 10H, wiring board 10I, wiring board 10J, and wiring board 10K) can be manufactured by the following processes.

[0047] [Substrate 20 Preparation Process] FIG. 5A is a diagram showing the substrate 20 preparation process. The upper view in the figure is a plan view. The lower left view in the figure is a side view. The lower right view in the figure is a cross-sectional view. This also applies to FIGS. 5B to 5E and FIGS. 6 to 9. The substrate 20 preparation process is a process of preparing the substrate 20 to be used in the wiring board 10. Any substrate can be used as the substrate 20. It is preferable to use a substrate 20 on which a solder resist layer is formed. It is preferable that the substrate 20 is a build-up substrate or a subtractive substrate. An opening is formed in the substrate 20 to expose the conductor layer 26 in order to form the electrical connection material 50.

[0048] [Step of Forming the Lower Clad 41] Fig. 5B is a diagram showing the step of forming the lower clad 41. The step of forming the lower clad 41 is a step of forming the lower clad 41 on the substrate 20. The lower clad 41 is formed by applying a spin coat onto the substrate 20. A resin film can be used as the lower clad 41. The thickness of the lower clad 41 can be any desired thickness. The thickness of the lower clad 41 is preferably 5 to 100 µm, and more preferably 10 to 50 µm.

[0049] [Core 42 Forming Process] FIG. 5C is a diagram showing the core 42 forming process. The core 42 forming process is a process of forming the core 42 on the lower clad 41. The core 42 is formed on the lower clad 41 by spin coating, and is then exposed and developed to a predetermined shape. A resin film can be used for the core 42. The exposed portion of the core 42 is rectangular. The core 42 may have a tapered shape (a tapered shape that narrows toward the left side in the figure) (see dotted line). The thickness of the core 42 can be any thickness. The thickness of the core 42 is preferably 1 to 20 μm, and more preferably 3 to 10 μm.

[0050] The core 42 may be compatible with either a single mode or a multimode. The width of the core 42 (the horizontal length of the core 42 as viewed from the side) can be any width. The width of the core 42 is preferably 1 to 40 μm, and more preferably 3 to 20 μm. The height of the core is preferably 1 to 40 μm, and more preferably 3 to 20 μm. The shape of the core 42 (the shape of the core 42 as viewed from the side) may be square, rectangular, circular, elliptical, or any other shape.

[0051] The number of cores 42 can be any value. The number of cores 42 is preferably 2 to 64. The number of cores 42 is preferably an even number. In the illustrated example, the number of cores 42 is four, but it may be three or less, or five or more. A clad may be disposed on the side of the core 42. In this case, the resin used for the core 42 can be irradiated with radiation to change the refractive index of the resin, thereby forming the clad. The core 42 can be formed by photolithography, photobleaching, or core cutting.

[0052] [Step of Forming Upper Clad 43] FIG. 5D is a diagram showing the step of forming the upper clad 43. The step of forming the upper clad 43 is a step of forming the upper clad 43 on the core 42. The upper clad 43 is formed by spin coating on the substrate 20. A resin film can be used for the upper clad 43. The thickness of the upper clad 43 can be any thickness. The thickness of the upper clad 43 is preferably 5 to 100 μm, and more preferably 10 to 50 μm. The lower clad 41, the core 42, and the upper clad 43 constitute the optical waveguide 40. In this case, the optical waveguide 40 may be formed with the core 42 exposed at one end, the core 42 exposed at the other end, or both the cores 42 of the optical waveguide 40.

[0053] [Mounting Process of Optical Element 60] Figure 5E is a diagram showing the mounting process of the optical element 60. The mounting process of the optical element 60 is a process of mounting the optical element 60 on the substrate 20. In the mounting process of the optical element 60, the exposed portion of the core 42 and the terminal 61 of the optical element 60 are optically coupled. One end of the optical element 60 (the lower surface on the right side in Figure 5E) is optically coupled to the core 42. The other end of the optical element 60 (the lower surface on the left side in Figure 5E) is electrically connected to the electrical connection material 50.

[0054] The optical element 60 can be mounted after forming the electrical connection material 50 on the substrate 20 on which the optical waveguide 40 is disposed. The electrical connection material 50 may be formed on the substrate 20 on which the optical waveguide 40 is disposed. The optical waveguide 40 may be disposed on the substrate 20 on which the electrical connection material 50 is formed. The electrical connection material 50 is a metal body and may be a solder bump or a conductive post. The solder bump may be formed using, for example, tin-based solder or gold-based solder. The conductive post may be formed using a metal such as nickel or copper. The electrical connection material 50 may have two or more layers as necessary. For example, two layers may be formed on a conductor post using tin-based solder or gold-based solder.

[0055] A transparent resin may be disposed between the optical element 60 and the optical waveguide 40. An underfill may be disposed between the optical element 60 and the electrical connecting material 50. An external connection member 70 (see FIG. 1A) may be disposed at the other end of the optical waveguide 40 (the end on the right side in FIG. 5E). A chip 80 may also be disposed as needed. The wiring substrate 10 and the like can be manufactured by such a process.

[0056] The wiring board 10 can employ, for example, the four connection configurations shown below. However, the connection configurations are not limited to these. These connection configurations can be applied not only to the wiring board 10 but also to the wiring board 10A, wiring board 10B, wiring board 10C, wiring board 10D, wiring board 10E, wiring board 10F, wiring board 10G, wiring board 10H, wiring board 10I, wiring board 10J, wiring board 10K, etc.

[0057] [First Connection Configuration] Fig. 6 is a diagram showing the wiring board 10 in the first connection configuration. The wiring board 10 in the first connection configuration has an optical element 60 connected to one end of an optical waveguide 40 and an external connection member 70 connected to the other end of the optical waveguide 40. The optical waveguide 40 has an optical element region 30 disposed at one end and an external connection member 70 disposed at the other end. The core 42 of the optical waveguide 40 is exposed at one end and not exposed at the other end. Note that an optical waveguide may be disposed instead of the external connection member 70. The right end (other end) of the optical waveguide 40 and the right end of the substrate 20 are flush with each other.

[0058] [Second Connection Configuration] FIG. 7 is a diagram showing a wiring board 10 in a second connection configuration. In the wiring board 10 in the second connection configuration, an optical element 60 is connected to one end of an optical waveguide 40, and an optical waveguide 140 is connected to the other end of the optical waveguide 40. The optical waveguide 40 has an optical element region 30 disposed at one end and an optical waveguide 140 with an exposed core 142 disposed at the other end. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide 40 at one end. The core 42 of the optical waveguide 40 at the other end is optically coupled to the core 142 of the optical waveguide 140. In the wiring board 10 in the second connection configuration, the left optical waveguide 40 has the core 42 exposed at one end and the core 42 exposed at the other end. This is the same in the third and fourth connection configurations.

[0059] [Third Connection Configuration] FIG. 8 is a diagram showing a wiring board 10 in a third connection configuration. In the wiring board 10 in the third connection configuration, an optical element 60 is connected to one end of an optical waveguide 40, and an optical element 160 is connected to the other end of the optical waveguide 40. The optical waveguide 40 has an optical element region 30 disposed at one end and an optical element region 130 separate from the optical element region 30 disposed at the other end. One or more optical elements 160 can be disposed in the separate optical element region 130. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide at one end. Furthermore, the terminal 161 of the separate optical element 160 is optically coupled to the core 42 of the optical waveguide at the other end. The conductor layer of the substrate 20 and the optical element 60 are electrically connected by an electrical connection material 50. The conductor layer of the substrate 20 and the optical element 160 are electrically connected by an electrical connection material 150.

[0060] [Fourth Connection Configuration] FIG. 9 is a diagram showing a wiring board 10 in a fourth connection configuration. The diagram at the bottom right of FIG. 9 is a cross-sectional view of a connection portion between an optical waveguide 40 and an external connection member 70. In the wiring board 10 in the fourth connection configuration, an optical element 60 is connected to one end of an optical waveguide 40, and an external connection member 70 is connected to the other end of the optical waveguide 40. The optical waveguide 40 has an optical element region 30 disposed at one end and an external connection member 70 (e.g., an optical fiber) with an exposed core 71 disposed at the other end. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide 40. The core 42 of the optical waveguide 40 is optically coupled to the core 71 of the external connection member 70. The external connection member 70 may be connected to the wiring board 10 in the same or different connection configurations. For example, the multiple connection portions of the external connection member 70 may have the same connection form, or different connection forms. Furthermore, when multiple optical waveguides are arranged on one side of the wiring board 10, the external connection member 70 may have the same connection form for the multiple optical waveguides, or different connection forms for the multiple waveguides. In other words, the connection form of the external connection member 70 can be freely changed. Furthermore, the connection form of the multiple connection portions included in the external connection member 70 can be freely changed.

[0061] FIG. 10 is a diagram showing an adiabatic junction. The upper diagram in the figure is a cross-sectional view of the wiring board 10. The lower diagram in the figure is a plan view of the wiring board 10. The adiabatic junction optically couples the exposed core 42 of the optical waveguide 40 with the terminal 61 of the optical element 60. An optical signal 90 passes through the core 42 of the optical waveguide 40 and is output to the terminal 61 of the optical element 60. The optical element 60 converts the optical signal 90 into an electrical signal 91. The electrical signal 91 passes through the electrical connection material 50 and is output to the conductor layer 26 for transmission. The terminal 61 is made of a semiconductor material or an inorganic material. The terminal 61 forms an optical waveguide of, for example, silicon. The core 42 is made of an organic material or an inorganic material. The core 42 forms an optical waveguide of, for example, a thermosetting resin or an ultraviolet-curing resin.

[0062] Fig. 11 is a cross-sectional view illustrating a buildup substrate. The substrate 20 shown in Fig. 1A can be a buildup substrate 20A shown in Fig. 11. The buildup substrate 20A includes a core substrate 21, a first insulating layer 22, a second insulating layer 23, a third insulating layer 24, a solder resist layer 25, a conductor layer 26, and through holes 27. The first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 are buildup layers formed on both surfaces of the core substrate 21. The number of insulating layers may be two or less, or four or more.

[0063] The size of the buildup substrate 20A can be any size, but the size of the buildup substrate 20A is preferably 200 mm or less in length and 200 mm or less in width, and more preferably 120 mm or less in length and 120 mm or less in width.

[0064] A plurality of optical waveguides 40 and optical elements 60 are arranged on the buildup substrate 20A. The optical elements 60 and the buildup substrate 20A are connected by an electrical connecting material 50. An optical element region 30 can be arranged at one end (the inner end in FIG. 11 ) of the optical waveguide 40. An external connection member 70 (e.g., an optical fiber, an optical element, etc.) or an optical waveguide can be arranged at the other end (the outer end in FIG. 11 ) of the optical waveguide 40.

[0065] The manufacturing process of the wiring substrate 10 (build-up substrate 20A) is as follows. The following description shows an example of the manufacturing process of the wiring substrate 10. The manufacturing process of the wiring substrate 10 is not limited to this.

[0066] [Process for Forming Core Substrate 21] The process for forming core substrate 21 is a process for forming core substrate 21 used in build-up substrate 20A. In the process for forming core substrate 21, through-holes 27 are formed penetrating from the front to the back of core substrate 21, such as a double-sided copper-clad laminate, by drilling or irradiating with laser light. Conductors are formed on the inner walls of through-holes 27 by plating, and conductor layers 26 are formed by a semi-additive method or a tenting method. The cavities of through-holes 27 can be filled with resin. The cavities of through-holes 27 may also be filled with a conductor. Conductor layers 26 are formed on both sides of core substrate 21. Any irregularities between conductor layer 26 and core substrate 21 can be filled with resin to make them flat.

[0067] [Insulating Layer Forming Process] The insulating layer forming process is a process of forming insulating layers (first insulating layer 22, second insulating layer 23, third insulating layer) using insulating resin. In the insulating layer forming process, a concave-convex layer is formed on the conductor layer 26 of the core substrate 21 by solution or plating. The concave-convex layer adheres the conductor layer 26 to the insulating resin. A thermosetting resin or an ultraviolet curing resin can be used as the insulating resin. The insulating layer is formed by curing the insulating resin. The insulating resin can be arranged by thermocompression bonding of a film or by applying a resin composition. As an example, the insulating layer is formed by laminating and thermocompression bonding an insulating resin such as a film of epoxy resin. Through holes penetrating the insulating layer are formed in the insulating layer by irradiating it with a laser beam such as carbon dioxide gas.

[0068] After the through holes are formed, a conductor layer 26 is formed on the insulating layer using a semi-additive method or the like. This results in via conductors being formed within the through holes in the insulating layer. The insulating layer is roughened using a strong oxidizing agent (e.g., chromic acid, permanganic acid, etc.). The roughening treatment roughens the resin surface to facilitate adhesion of chemical copper. After the roughening treatment, a catalyst is applied to the entire substrate, and an electroless plating film is formed on the insulating layer. The electroless plating film contains copper, nickel, etc. The thickness of the electroless plating film is not particularly limited, but is preferably 0.1 to 5 μm. A dry film is formed on the insulating layer on which the electroless plating film has been formed. A conductor circuit pattern is formed on the dry film by exposure. The exposed dry film is developed using a chemical such as alkali, and the film is partially removed. This results in dry film-formed and non-formed areas on the substrate. An electroplated film is formed on the non-formed areas. The electroplated film contains copper, nickel, etc. The thickness of the electroplated film is not particularly limited, but is preferably 3 to 20 μm. The dry film is then peeled off, and a substrate with a conductor layer 26 formed thereon is obtained by chemical etching. Furthermore, by forming an insulating layer on the substrate with the conductor layer 26 formed thereon, a substrate with multilayered conductor layers can be obtained. The number of insulating layers is not limited, but one example is a three-layer structure consisting of a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24. This results in a substrate with multilayered conductor layers. Two such substrates are then joined together vertically to form a build-up substrate consisting of three insulating layers, two core substrates, and three insulating layers.

[0069] [Step of forming solder resist layer 25] The step of forming the solder resist layer 25 is a step of forming the solder resist layer 25 on the third insulating layer 24. In the step of forming the solder resist layer 25, the solder resist layer 25 is formed by applying or spraying a photosensitive epoxy resin. An opening that exposes a part of the conductor layer 26 is formed in the solder resist layer 25 by exposure and development.

[0070] [Step of forming the electrical connection material 50] The step of forming the electrical connection material 50 is a step of forming the electrical connection material 50 on the solder resist layer 25. In the step of forming the electrical connection material 50, the electrical connection material 50 is formed by mounting conductive balls using solder or the like and performing a reflow process, etc. The build-up substrate 20A is completed through the above steps.

[0071] [Process for forming optical waveguide 40] The process for forming the optical waveguide 40 is a process for forming the optical waveguide 40 on the build-up substrate 20A. In the process for forming the optical waveguide 40, a plurality of optical waveguides 40 are formed on the solder resist layer 25. Note that the optical element 60 is disposed between the plurality of optical waveguides 40. The wiring board 10 is completed through the above processes.

[0072] FIG. 12 is a cross-sectional view showing the configuration of the build-up board 20A. The build-up board 20A can be a board with a fan-out structure. A fan-out structure is a structure in which wiring spreads outward relative to the optical element 60 (chip). A large number of circular external terminals 93 are formed on the back surface 92 of the optical element. A large number of circular external terminals 95 are formed on the back surface 94 of the lower solder resist layer 25. The size of the external terminals 95 is larger than the size of the external terminals 93. The number of external terminals 95 is smaller than the number of external terminals 93.

[0073] 13 is a plan view showing a first example of an optical waveguide 40. In the first example of the optical waveguide 40, the end E1 of the core 42 is located more inward than the end E2 of the lower cladding 41. The exposed length L1 of the core 42 can be any length. The exposed length L1 of the core 42 is preferably 10 mm or less, more preferably 5 mm or less, and even more preferably 3 mm or less. The exposed length L1 of the core 42 is the distance from the end (left end) of the upper cladding 43 of the optical waveguide 40, passing through the exposed core 42, to the end (left end) of the core 42.

[0074] 14 is a plan view showing a second example of an optical waveguide 40. In the second example of the optical waveguide 40, the end E1 of the core 42 is positioned so as to align with the end E2 of the lower cladding 41. The exposed length L2 of the core 42 can be any length. The exposed length L2 of the core 42 may be the same as the exposed length L1 of the core 42 in FIG. 13 or may be longer than the exposed length L1 of the core 42.

[0075] FIG. 15 is a diagram showing the role of each component of the wiring board 10, etc. Preferably, the wiring board 10, etc. includes at least one of the following components. The wiring board 10, etc. includes an information processing circuit 100, an electric circuit 101 (EIC: Electrical IC), an optical element 60, and an optical waveguide 40. The information processing circuit 100 performs information processing (calculation). The information processing circuit 100 outputs the calculation result as a digital signal to other components of the information processing circuit, etc. The electric circuit 101 converts a digital waveform signal into an analog signal. The electric circuit 101 converts an analog signal output from an optical element into a digital signal. The optical element 60 converts an optical signal into an analog electrical signal. The optical element 60 converts an analog electrical signal into an optical signal. Note that the optical element 60 may include the function of the electric circuit 101. The optical element 60, which includes the function of the electrical circuit 101, converts an optical signal into an analog electrical signal, and can also convert the analog electrical signal into a digital signal. Chips 80 and 81 in Figures 4A and 4B correspond to the electrical circuit 101 or the information processing circuit 100. The optical waveguide 40 transmits the optical signal to another optical element, etc. The optical waveguide 40 plays a role similar to that of copper wiring for electrical signals. The optical signal is in analog format.

[0076] The flow on the input side is as follows: An analog optical signal is input to the optical waveguide 40. The optical waveguide 40 outputs an analog optical signal. An analog optical signal is input to the optical element 60. The optical element 60 outputs an analog electrical signal. An analog electrical signal is input to the electrical circuit 101. The electrical circuit 101 outputs a digital electrical signal. A digital electrical signal is input to the information processing circuit 100. The information processing circuit 100 outputs a digital electrical signal.

[0077] The flow on the output side is as follows: A digital electrical signal is input to the information processing circuit 100. The information processing circuit 100 outputs a digital electrical signal. A digital electrical signal is input to the electrical circuit 101. The electrical circuit 101 outputs an analog electrical signal. An analog electrical signal is input to the optical element 60. The optical element 60 outputs an analog optical signal. An analog optical signal is input to the optical waveguide 40. The optical waveguide 40 outputs the analog optical signal.

[0078] As described above, this embodiment has the following advantages. (1) According to this embodiment, because the cores 42 of the optical waveguide 40 are exposed, the height of the exposed cores 42 can be reduced. This allows the height of the electrical connection material 50 to be reduced, making it possible to provide a wiring board 10 or the like that has excellent electrical connectivity and optical coupling. The closer the distance between the optical waveguide 40 and the optical element 60, the more likely it is that poor connection will occur. Furthermore, because there are multiple optical waveguides 40, the optical waveguides 40 can be used for a variety of purposes, making it possible to provide a highly scalable wiring board 10 or the like. Furthermore, because there are multiple optical waveguides 40 and the cores 42 are exposed, it is possible to provide a wiring board 10 with a novel configuration.

[0079] (2) According to this embodiment, one or more optical elements 60 are arranged in the optical element region 30, so the number of arranged optical elements 60 can be flexibly changed.

[0080] (3) According to this embodiment, the multiple optical waveguides 40 are arranged in different directions (see Figures 1B, 2, and 3), which increases the number of uses of the optical waveguides 40 compared to a method in which the optical waveguides 40 are arranged in one direction.

[0081] (4) According to this embodiment, the core 42 at the other end is not exposed (see FIG. 6), so that loss of optical signals can be suppressed.

[0082] (5) According to this embodiment, the core 42 at the other end is exposed (see FIGS. 7, 8, and 9). Therefore, the height of the exposed portion of the core 42 at the other end can also be reduced.

[0083] (6) According to this embodiment, an external connection member 70 (e.g., an optical fiber) is disposed at the other end of the optical waveguide 40 (see FIG. 6 ). Therefore, the external connection member 70 can be utilized to increase the number of uses of the wiring substrate 10, etc.

[0084] (7) According to this embodiment, since the optical waveguide 40 is disposed at the other end of the optical waveguide 40 (see FIG. 7), the optical waveguide 40 can be used to increase the number of uses of the wiring board 10 and the like.

[0085] (8) According to this embodiment, another optical element region 30 is disposed at the other end of the optical waveguide 40 (see FIG. 8), and therefore, the other optical element region 30 can be utilized to increase the uses of the wiring substrate 10, etc.

[0086] (9) According to this embodiment, an external connection member 70 (e.g., an optical fiber) having an exposed core 71 is disposed at the other end of the optical waveguide 40 (see FIG. 9 ). Therefore, the external connection member 70 having an exposed core 71 can be utilized to increase the applications of the wiring substrate 10, etc.

[0087] (10) According to this embodiment, since the chip 80 that connects the multiple optical elements 60 is provided (see FIGS. 4A and 4B), the multiple optical elements 60 can be linked together.

[0088] (11) According to this embodiment, the end E1 of the core 42 is positioned more inward than the end E2 of the lower cladding 41 (see FIG. 13 ), so that damage to the core 42 at the end E1 of the core 42 can be avoided.

[0089] (12) According to this embodiment, the end E1 of the core 42 is aligned with the end E2 of the lower clad 41 (see FIG. 14), so that the exposed portion of the core 42 can be made longer.

[0090] (13) According to this embodiment, the substrate 20 can be a build-up substrate 20A (see FIG. 11), which can improve the performance of the wiring substrate 10 and the like.

[0091] (14) While the above-mentioned techniques have been proposed as conventional techniques, it is desirable to provide a wiring board that can efficiently transmit optical signals or electrical signals, for example, when bonding optical elements to optical waveguides and connecting optical elements to a substrate. In this regard, according to the present embodiment, a plurality of optical waveguides 40 with exposed cores 42 are arranged on a substrate 20. Therefore, when bonding optical elements 60 to optical waveguides 40 and connecting optical elements 60 to the substrate 20, the distance between the optical elements 60 and the cores 42 and between the optical elements 60 and the conductor layer 26 of the substrate 20 is reduced, resulting in a wiring board 10 or the like that efficiently performs optical bonding of optical signals or electrical connection of electrical signals. Furthermore, even if the optical signals or electrical signals become large, these signals can be efficiently communicated. Furthermore, by lowering the height of the electrical connection material 50 in the wiring board 10 or the like, the electrical connection material 50 is less likely to break, thereby improving connection reliability.

[0092] [Modifications] The present disclosure is not limited to the above-described embodiment and can be implemented in various modifications. (1) When the optical waveguide 40 is arranged in two directions, it may be arranged in an L-shape, such as on the left and upper sides, the left and lower sides, the right and upper sides, or the right and lower sides. (2) Although the optical waveguide 40 has been described as being arranged in two to four directions, it may also be arranged in five or more directions. (3) The wiring substrate does not need to include the chip 80 or the chip 81.

[0093] [Example Problems to be Solved by the Present Disclosure] Although the technology of Patent Document 1 has been proposed as a conventional technology, a wiring board having a novel configuration is desired.

[0094] Therefore, an exemplary object of the present disclosure is to provide a wiring board having a novel configuration.

[0095] It should be noted that the present disclosure is merely an example and is not limited thereto. Furthermore, the present disclosure may be a disclosure including at least one of the specific matters set forth in the present disclosure. Furthermore, each specific matter set forth in the present disclosure may be sub-conceptualized by adding an element that limits the specific matter, or may be sub-conceptualized by deleting an element that limits the specific matter.

[0096] [Example Effects of the Present Disclosure] According to the present disclosure, it is possible to provide a wiring board having a novel configuration.

[0097] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K Wiring board 20 Substrate 20A Build-up board 21 Core substrate 22 First insulating layer 23 Second insulating layer 24 Third insulating layer 25 Solder resist layer 26 Conductor layer 27 Through hole 30, 130 Optical element region 40, 140 Optical waveguide 41, 141 Lower clad 42, 142 Core 43, 143 Upper clad 50, 150 Electrical connecting material 60, 160 Optical element 61, 161 Terminal 70 External connecting member 71 Core 80, 81 Chip 90 Optical signal 91 Electrical signal 92 Back surface of optical element 93 External terminal 94 Back surface of solder resist layer 95 External terminal 100 Information processing circuit 101 Electric circuit

Claims

1. A wiring board comprising: a substrate having a conductor layer; and an optical element region and an optical waveguide having a lower cladding, a core, and an upper cladding disposed on the substrate, wherein the optical element region has an electrical connecting material that electrically connects the conductor layer and the optical element region; and the optical waveguide has an exposed core that is optically coupled to the optical element region and is disposed in plurality.

2. In the wiring board according to claim 1, one or more optical elements are arranged in the optical element region.

3. A wiring board according to claim 1, wherein the plurality of optical waveguides are arranged in different directions with the optical element region as a center.

4. A wiring board according to claim 1, wherein the optical waveguide has an exposed core at one end and an unexposed core at the other end.

5. A wiring board according to claim 1, wherein the optical waveguide has an exposed core at one end and an exposed core at the other end.

6. In the wiring board according to claim 1, the optical waveguide has the optical element region disposed at one end and an external connection member disposed at the other end.

7. A wiring board according to claim 1, wherein the optical waveguide has the optical element region disposed at one end and an optical waveguide with an exposed core disposed at the other end.

8. A wiring board according to claim 1, wherein the optical waveguide has the optical element region disposed at one end and an optical element region different from the optical element region disposed at the other end.

9. A wiring board according to claim 1, wherein the optical waveguide has the optical element region disposed at one end and an external connection member with an exposed core disposed at the other end.

10. A wiring board according to claim 1, wherein the optical element region has a plurality of optical elements arranged therein, and further comprises a chip electrically connected to the optical elements.

11. A wiring board as claimed in claim 1, wherein an end of the core is disposed inside an end of the lower clad.

12. A wiring board as claimed in claim 1, wherein an end of the core is arranged in a position aligned with an end of the lower clad.

13. The wiring board according to claim 1, wherein the board is a build-up board comprising a core board and build-up layers formed on both sides of the core board.

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