Memory chip, logic chip, chip stacking structure, and memory

Abstract

Provided in the embodiments of the present disclosure are a memory chip, a logic chip, a chip stacking structure, and a memory. A global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, and each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, wherein the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; and the first redundant conductive through hole group is configured to transmit the same first global signal, and the second redundant conductive through hole group is configured to transmit the same second global signal.

Description

A memory chip, a logic chip, a chip stacking structure and a memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on December 18, 2023, with application number 202311748315X and application name “A memory chip, logic chip, chip stacking structure and memory”, the entire contents of which are incorporated by reference in this disclosure. Technical Field

[0003] The present disclosure relates to, but is not limited to, a memory chip, a logic chip, a chip stacking structure, and a memory. Background Art

[0004] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing development technology, and limits of storage electron density. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit memory unit, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a memory chip, wherein a center point of an active surface of the memory chip and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface;

[0008] The global signal area is penetrated by a plurality of conductive via groups, each of the conductive via groups including a first redundant conductive via group and a second redundant conductive via group, the first redundant conductive via group including a first conductive via and a fourth conductive via, the second redundant conductive via group including a second conductive via and a third conductive via; the first redundant conductive via group is used to transmit a same first global signal, and the second redundant conductive via group is used to transmit a same second global signal;

[0009] For each of the conductive through-hole groups, the first conductive through-hole and the second conductive through-hole are symmetrical about the first axis, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the first axis, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

[0010] In a second aspect, an embodiment of the present disclosure provides a logic chip, wherein a center point of an active surface of the logic chip and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface;

[0011] The global signal area is penetrated by a plurality of conductive via groups, each of the conductive via groups including a first redundant conductive via group and a second redundant conductive via group, the first redundant conductive via group including a first conductive via and a fourth conductive via, the second redundant conductive via group including a second conductive via and a third conductive via; the first redundant conductive via group is used to transmit a same first global signal, and the second redundant conductive via group is used to transmit a same second global signal;

[0012] For each of the conductive via groups, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

[0013] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising a logic chip as described in any one of the second aspects and at least one stacking unit, wherein the logic chip and the at least one stacking unit are stacked sequentially along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to a top surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in any one of the first aspects;

[0014] The first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face;

[0015] The first memory chip and the logic chip in the first stacking unit are stacked back to face, or the first memory chip and the logic chip in the first stacking unit are stacked back to back; the n conductive through-hole groups in the logic chip correspond one-to-one with the n conductive through-hole groups in each of the first memory chips, the n conductive through-hole groups in each of the second memory chips, the n conductive through-hole groups in each of the third memory chips, and the n conductive through-hole groups in each of the fourth memory chips, and are aligned along the third direction, where n is a positive integer.

[0016] In a fourth aspect, an embodiment of the present disclosure provides a memory comprising a chip stacking structure as described in any one of the third aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic diagram of the structure of a chip;

[0018] FIG2A is a first schematic diagram of signal transmission in a chip stacking structure;

[0019] FIG2B is a second schematic diagram of signal transmission of a chip stacking structure;

[0020] FIG3 is a schematic diagram of an active surface in a memory chip provided by an embodiment of the present disclosure;

[0021] FIG4 is a first schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure;

[0022] FIG5 is a second schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure;

[0023] FIG6 is a schematic diagram of the structure of a decoding circuit provided in an embodiment of the present disclosure;

[0024] FIG7 is a third schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure;

[0025] FIG8 is a fourth schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure;

[0026] FIG9 is a fifth structural diagram of a memory chip provided by an embodiment of the present disclosure;

[0027] FIG10 is a schematic diagram of an active surface in a logic chip provided by an embodiment of the present disclosure;

[0028] FIG11 is a schematic diagram of the first structure of a logic chip provided in an embodiment of the present disclosure;

[0029] FIG12 is a second schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure;

[0030] FIG13 is a third schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure;

[0031] FIG14 is a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0032] FIG15A / FIG15B is a specific schematic diagram 1 of a chip stacking structure provided by an embodiment of the present disclosure;

[0033] FIG16A / FIG16B is a second specific schematic diagram of a chip stacking structure provided by an embodiment of the present disclosure;

[0034] FIG17A / FIG17B is a third specific schematic diagram of a chip stacking structure provided by an embodiment of the present disclosure;

[0035] FIG18A / FIG18B is a fourth specific schematic diagram of a chip stacking structure provided by an embodiment of the present disclosure;

[0036] FIG19 is a schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure;

[0037] FIG20 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0042] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0043] Referring to Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, a direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. Two mutually perpendicular directions, namely a first direction and a second direction, are defined on the top surface of the semiconductor chip. The first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0044] Please refer to Figure 1. The semiconductor chip includes a substrate. The side of the substrate used to make devices (such as transistors, capacitors, etc.) forms an active surface (the side of the substrate opposite to the active surface is the inactive surface, i.e., the bottom surface in Figure 1). There are multiple metal layers distributed between the substrate and the top surface, such as M1, M2, M3... Figure 1 also shows two types of conductive through-holes (such as silicon through-holes), both of which are used to realize signal connection between different stacked chips.

[0045] As shown in FIG. 1 , a type 1 conductive via penetrates the bottom surface and the top surface along a third direction, and is connected to an internal circuit of the chip through a metal layer.

[0046] As shown in FIG1 , for the conductive via of type 2, it only penetrates the substrate along the third direction (through the active surface and the bottom surface), and needs to cooperate with the contact structure that penetrates the top surface along the third direction to realize signal transmission; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: the contact structure in FIG1 is connected to M4, M4 is connected to M1 via M3 and M2 in turn, and M1 is connected to the conductive via; or, the conductive via in FIG1 is connected to the input end of the chip internal circuit (the device in the substrate of FIG1 ) via M1-M4, and the output signal processed by the chip internal circuit is then output to the corresponding contact structure via the metal layer M1-M4. Similarly, the contact structure in FIG1 can also be connected to the input end of the chip internal circuit (the device in the substrate of FIG1 ) via M1-M4, and the output signal processed by the chip internal circuit is then output to the corresponding conductive via via M1-M4. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0047] Meanwhile, the types of conductive vias are not limited to the two above-mentioned types, which are merely examples. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the drawings are not necessarily drawn to scale.

[0048] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0049] In one embodiment, a memory chip and a logic chip are provided. Each memory chip and the logic chip include multiple conductive vias extending through the chip along a third direction. The conductive vias are used to transmit signals between different chips. All conductive vias can be located at any position. In particular, every four conductive vias can be functionally considered a conductive via group, but the positions of the four conductive vias are not limited.

[0050] In a specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. The conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Please refer to FIG2A , which shows a signal transmission schematic diagram of a chip stacking structure. As shown in FIG2A , the chip stacking structure includes memory chips 0 to 7 and a logic chip. FIG2A shows only four conductive vias D0 to D3 for each memory chip, and these four conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive vias D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... The remaining conductive vias are similar.

[0051] At the same time, each memory chip and logic chip is also equipped with multiple drive circuits (only one of these drive circuits is shown in a dotted box in Figure 2A; the remaining drive circuits are not framed), and each conductive via is connected to a drive circuit. Each memory chip is also equipped with multiple data selectors (for example, mux0-7 in Figure 2A), with each conductive via group corresponding to one data selector. That is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can select which conductive via transmits the signal to output to the memory chip or which conductive via to input the signal output by the memory chip.

[0052] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "the conductive through hole D0 in the logic chip, the conductive through hole D0 in memory chip 0 - the conductive through hole D0 in memory chip 1 - the conductive through hole D0 in memory chip 2 - the conductive through hole D0 in memory chip 3 - the conductive through hole D0 in memory chip 4 - the conductive through hole D0 in memory chip 5 - the conductive through hole D0 in memory chip 6 - the conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0053] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive through-hole D0, and memory chip 1 only needs to obtain signals from conductive through-hole D1... That is, each memory chip only needs to obtain signals from one of the conductive through-holes in a conductive through-hole group. It is worth noting that different memory chips may need to obtain signals from different conductive through-holes. However, since all memory chips need to be designed into exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive through-holes in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Further, when the chip stacking structure shown in FIG2A is adopted, each conductive through-hole corresponds to a drive circuit; during the operation of the chip stacking structure, it is necessary to drive all drive circuits in all memory chips in the same channel, the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts transmission efficiency and increases power consumption, and also restricts the number of chips stacked in the three-dimensional device.

[0054] In another embodiment, please refer to FIG2B , which shows a second schematic diagram of signal transmission of a chip stacking structure. In particular, FIG2B only labels some of the conductive through-holes (D0 to D3), and omits the others. However, for FIG2B , the labels of the conductive through-holes aligned along the third direction are the same. As shown in FIG2B , the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through-holes in each memory chip are rotationally connected to another conductive through-hole at a different position in another memory chip, realizing a spiral upward connection as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive through-hole D0 in logic chip - conductive through-hole D1 in memory chip 0 - conductive through-hole D2 in memory chip 1 - conductive through-hole D3 in memory chip 2 - conductive through-hole D0 in memory chip 3 - conductive through-hole D1 in memory chip 4 - conductive through-hole D2 in memory chip 5 - conductive through-hole D3 in memory chip 6 - conductive through-hole D0 in memory chip 7”, and the remaining signals are similar.

[0055] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of the conductive through hole D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of the conductive through hole D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of the conductive through hole D0 in memory chip 1, and memory chip 3 can obtain signal Signal_CH5 through the input end of the conductive through hole D0 in memory chip 2... For each memory chip, only one conductive through hole in each conductive through hole group is required to connect to the driving circuit, and there is no need to set a data selector, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to the conductive via direct connection configuration of FIG2A , the process for the conductive via rotational connection in FIG2B is more complicated. Specifically, a horizontal interconnection structure needs to be set between adjacent conductive vias in each memory chip in FIG2B (only one of them is marked with a five-pointed star in FIG2B ). The signal interconnection structure can be a metal interconnection line, a conductive via, etc. In order to achieve the conductive via rotational connection, the input signal signal_CH0 must first be transmitted upward from the conductive via D0 of the logic chip to the interconnection structure below the conductive via D0 of the memory chip 0 (not connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is, the structure shown in FIG2B also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar. This will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0056] In particular, in the chip stacking structure of Figures 2A and 2B, all chips are active-side up, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0057] In summary, on the one hand, the chip stacking structure of Figure 2A requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in larger loads and parasitic capacitances. The chip stacking structure of Figure 2B has a larger parasitic resistance due to the rotational configuration. On the other hand, both the stacking structures of Figures 2A and 2B have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if you want to further realize a face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as chips with the active surface facing up and the active surface facing down. This method has a high process complexity and uncontrollable costs. Another way is to make an extra set of conductive vias and connect both sets of conductive vias to the same drive circuit in the memory chip. However, this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity but also increase power consumption.

[0058] Therefore, the embodiments of the present disclosure propose a memory chip, a logic chip, a chip stacking structure and a memory. The chip stacking structure not only has smaller parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method. In particular, the embodiments of the present disclosure also provide relevant mechanisms for global signal switching and redundancy repair under this structure.

[0059] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0060] In one embodiment of the present disclosure, referring to FIG3 , a schematic diagram of an active surface of a memory chip provided by an embodiment of the present disclosure is shown, which can be specifically understood as a cross-sectional schematic diagram of the active surface. As shown in FIG3 , the memory chip 10 includes m channels (m is a positive integer, and FIG3 illustrates m=4 as an example), the m channels are sequentially arranged along a first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along a second direction, and the center of each channel signal region coincides with the center of the corresponding channel.

[0061] It should be noted that during the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made in the reference channel (for example, the first channel) of the storage chip 10, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and other channels can be identified in combination with the active surface orientation of the chip.

[0062] FIG3 illustrates m=4 as an example, and the following description also takes m=4 as an example, but m can be any positive integer.

[0063] As shown in FIG3 , the center point of the active surface of the memory chip 10 and its adjacent area are defined as a global signal area 111 , and the center point of the global signal area 111 coincides with the center point of the active surface; the m channels are symmetrical about the global signal area 111 .

[0064] It should be noted that both the global signal area 111 and the channel signal area are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface. Here, the conductive via can be a through silicon via (TSV), which is specifically a vertical interconnection structure that penetrates the silicon wafer / chip, or, in other embodiments, it can also be other conductive vias with conductive functions, which are not specifically limited. In addition, the conductive via can be in the form of the aforementioned type 1 or in the form of the aforementioned type 2.

[0065] For the global signal area 111, each conductive through-hole is used to transmit a global signal, and the global signal is shared by all areas of the corresponding memory chip 10. Global signals include but are not limited to: reset signal, power-on signal, stack identification signal SID / CID, power-related signal Voltage Monitor, timing-related signal Timing Aligner. In some cases, the global signal area 111 may also refer to a pad area. The global signal can be a test signal of the Design For Test (DFT), and the working status of the internal circuit of the chip and the transmission status of related signals can be known through the global signal. In addition, because the pin pad (PAD) of the DFT in the memory chip 10 is generally located in the middle of the chip, the conductive through-holes of global signals such as the DFT are preferably located in the narrower area in the middle of the chip, that is, the position of the global signal area 111 as shown in Figure 3.

[0066] In the channel signal region, each conductive via is used to transmit a channel signal. The signal transmitted by each channel signal region is used only by the corresponding channel. The conductive vias in each channel signal region are specific to their respective channel signal regions and are only used by the local memory chip 10 (corresponding channel). The conductive vias in the global signal region 111 located in the center of the memory chip 10 are used to test the entire memory chip 10. The signals transmitted by the global signal region 111 are shared by all m channels of the memory chip 10.

[0067] Referring to FIG. 3 , the active surface of memory chip 10 includes a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center of the active surface. The first axis AA' is parallel to a first side of memory chip 10, and the second axis BB' is parallel to a second side of memory chip 10. In FIG. 3 , the first axis AA' may extend along a first direction, and the second axis BB' may extend along a second direction. In other embodiments, the first axis AA' may extend along the second direction, and the second axis BB' may extend along the first direction. This is not particularly limited.

[0068] Further, referring to FIG4 , which shows a schematic diagram of the composition structure of a memory chip provided by an embodiment of the present disclosure. As shown in FIG4 , in the memory chip 10, the global signal region is penetrated by multiple conductive via groups 20 (only one conductive via group 20 is shown in FIG4 , the others are omitted). Each conductive via group 20 includes a first redundant conductive via group 21 and a second redundant conductive via group 22. The first redundant conductive via group 21 includes a first conductive via D0 and a fourth conductive via D3, and the second redundant conductive via group 22 includes a second conductive via D1 and a third conductive via D2. The first redundant conductive via group 21 is used to transmit the same first global signal, and the second redundant conductive via group 22 is used to transmit the same second global signal.

[0069] In particular, Figure 4 can be viewed as a schematic cross-section of the memory chip 10 along the active surface. Referring to Figure 4 , for the same conductive via group 20, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0070] In this embodiment, for the first conductive via D0 and the fourth conductive via D3 in the same first redundant conductive via group 21, or for the second conductive via D1 and the third conductive via D2 in the same second redundant conductive via group 22, each conductive via transmits exactly the same signal, i.e., a signal of the same transmission type and signal value, and further transmits it to the internal circuit of the memory chip 10. Furthermore, the first global signal transmitted by the first conductive via D0 and the fourth conductive via D3 is different from the second global signal transmitted by the second conductive via D1 and the third conductive via D2. Here, the first global signal can be represented by A, and the second global signal can be represented by B. The first global signal and the second global signal need to appear in pairs. Furthermore, the first global signal and the second global signal include, but are not limited to, a reset signal, a power-on signal, a stack identification signal SID / CID, a power-related signal Voltage Monitor, and a timing-related signal Timing Aligner, without specific limitation.

[0071] It should be noted that the positions of the conductive via groups 20 in the global signal region vary. Specifically, the number and position of the conductive via groups 20 can be adjusted based on actual conditions and are not limited thereto. However, the number of conductive vias in each conductive via group 20 must be the same and must adhere to the aforementioned symmetrical distribution rules. The following description uses the example of a global signal region being penetrated by one conductive via group 20, with the conductive via group 20 including a first redundant conductive via group 21 and a second redundant conductive via group 22, and with four conductive vias in the conductive via group 20.

[0072] It should also be noted that the conductive vias mentioned above can at least be embodied as through-silicon vias, specifically a vertical interconnect structure that penetrates the silicon wafer / memory chip, such as type 1 in FIG1 . Of course, the conductive vias can also be type 2 in FIG1 , which together with the contact structure realize signal transmission. In other embodiments, other electrical connection structures can also be selected as the conductive vias.

[0073] It is understood that the numbering order of the conductive vias in each conductive via group 20 does not constitute any limitation. In addition, for ease of illustration, the conductive via group, the first redundant conductive via group, and the second redundant conductive via group are no longer labeled in subsequent figures. Please refer to Figure 4 for understanding.

[0074] Based on the memory chip 10 shown in FIG4 , FIG5 is a second schematic diagram illustrating the structure of a memory chip according to an embodiment of the present disclosure. As shown in FIG5 , in one embodiment, the memory chip 10 may further include multiple input selection circuits 30 (only one input selection circuit 30 is shown in FIG5 , with the others omitted). One side of each input selection circuit 30 is coupled to a conductive via group 20 , and the other side of each input selection circuit 30 is coupled to a first signal input node and a second signal input node within the memory chip 10 .

[0075] The input selection circuit 30 is configured to electrically connect the coupled first redundant conductive via group 21 to the coupled first signal input node, and to electrically connect the coupled second redundant conductive via group 22 to the coupled second signal input node; or, to electrically connect the coupled first redundant conductive via group 21 to the coupled second signal input node, and to electrically connect the coupled second redundant conductive via group 22 to the coupled first signal input node.

[0076] The first signal input node can be represented by G, and the second signal input node can be represented by H.

[0077] It should be noted that the number of the plurality of conductive via groups 20 and the number of the plurality of input selection circuits 30 may be the same or different, and there is no specific limitation on this.

[0078] As shown in FIG5 , in some embodiments, the input selection circuit 30 may include a first OR gate 31 , a second OR gate 32 , a first signal selection circuit 33 , and a second signal selection circuit 34 ;

[0079] A first OR gate 31 is coupled to the first conductive via D0 and the fourth conductive via D3 and configured to perform an OR operation on the signal of the first conductive via D0 and the signal of the fourth conductive via D3 to output a first intermediate signal;

[0080] A second OR gate 32 is coupled to the second conductive via D1 and the third conductive via D2 and configured to perform an OR operation on the signal of the second conductive via D1 and the signal of the third conductive via D2 to output a second intermediate signal;

[0081] A first signal selection circuit 33 receives the first intermediate signal at a first terminal and receives the second intermediate signal at a second terminal. The first signal selection circuit 33 is configured to receive a position identification signal and transmit one of the first intermediate signal and the second intermediate signal to the first signal input node based on the position identification signal.

[0082] The second signal selection circuit 34 receives the second intermediate signal at its first end and the first intermediate signal at its second end; the second signal selection circuit 34 is configured to receive a position identification signal and transmit the other of the first intermediate signal and the second intermediate signal to the second signal input node based on the position identification signal.

[0083] Specifically, the first OR gate 31 can be coupled to the active surface portion of the first conductive via D0 and the fourth conductive via D3 in the same first redundant conductive via group 21, and the second OR gate 32 can be coupled to the active surface portion of the second conductive via D1 and the third conductive via D2 in the same second redundant conductive via group 22. That is, for each memory chip 10, all conductive vias in part of the first redundant conductive via group 21 are coupled to their corresponding first OR gate 31, and the first OR gate 31 is respectively coupled to the first signal selection circuit 33 and the second signal selection circuit 34 corresponding to them. All conductive vias in part of the second redundant conductive via group 22 are coupled to their corresponding second OR gate 32, and the second OR gate 32 is respectively coupled to the first signal selection circuit 33 and the second signal selection circuit 34 corresponding to them. When the position identification signal indicates that the first signal input node G is connected to the first redundant conductive via group 21, the global signal transmitted by the first redundant conductive via group 21 will pass through the first OR gate 31 coupled to it. and the first signal selection circuit 33 are transmitted to the first signal input node G, and the global signal transmitted by the second redundant conductive via group 22 will be transmitted to the second signal input node H via the second OR gate 32 and the second signal selection circuit 34 coupled accordingly; and when the position identification signal indicates that the first signal input node G is connected to the second redundant conductive via group 22, the global signal transmitted by the first redundant conductive via group 21 will be transmitted to the second signal input node H via the first OR gate 31 and the second signal selection circuit 34 coupled accordingly, and the global signal transmitted by the second redundant conductive via group 22 will be transmitted to the first signal input node G via the second OR gate 32 and the first signal selection circuit 33 coupled accordingly.

[0084] It should be noted that the first and second ends of the first signal selection circuit 33 and the second signal selection circuit 34 are input ends, and they may also have a third end (i.e., an output end), wherein the output end of the first signal selection circuit 33 is coupled to the first signal input node G, and the output end of the second signal selection circuit 34 is coupled to the second signal input node H.

[0085] It can be understood that as long as one of the signals transmitted by the first conductive via D0 and the fourth conductive via D3 is connected normally and transmits signals, the first global signal can be output, and the signal of the first conductive via D0 and the signal of the fourth conductive via D3 are redundant with each other; similarly, as long as one of the signals transmitted by the second conductive via D1 and the third conductive via D2 is connected normally and transmits signals, the second global signal can be output, and the signal of the second conductive via D1 and the signal of the third conductive via D2 are redundant with each other.

[0086] In some embodiments, the first signal selection circuit 33 is configured to transmit the first intermediate signal to the first signal input node G when the position identification signal is in the first state; or transmit the second intermediate signal to the first signal input node G when the position identification signal is in the second state;

[0087] The second signal selection circuit 34 is configured to transmit the second intermediate signal to the second signal input node H when the position identification signal is in the first state; or to transmit the first intermediate signal to the second signal input node H when the position identification signal is in the second state.

[0088] It should be noted that the control ends of the first signal selection circuit 33 and the second signal selection circuit 34 are both used to receive position identification signals. The first state of the position identification signal can be a low level state (logic "0"), and the second state can be a high level state (logic "1").

[0089] As shown in FIG5 , in some embodiments, each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0090] Among them, if the conductive through hole does not transmit a signal or the connection is abnormal, the weak ground terminal controls the level state of the conductive through hole to be a low level; if the conductive through hole is connected normally and transmits a signal, the level state of the conductive through hole depends on the transmitted signal.

[0091] It should be noted that the resistance of the resistor in the weak ground terminal is relatively large to reduce the current and power loss caused by the weak ground terminal connection, but the specific value of the resistor is not specifically limited. In addition, the weak ground terminal can be represented by weak pull "0".

[0092] In some embodiments, every four memory chips 10 are stacked into a stacking unit along a third direction, and in each stacking unit, the low-order transmission areas of the memory chips 10 in the first type of position and the high-order transmission areas of the memory chips 10 in the second type of position are aligned along the third direction; wherein each memory chip 10 is divided into a low-order transmission area and a high-order transmission area by the first axis AA', or each memory chip 10 is divided into a low-order transmission area and a high-order transmission area by the second axis BB'.

[0093] Referring to FIG. 2A or FIG. 2B , a logic chip and multiple memory chips are stacked along a third direction to form a chip stack structure. In the disclosed embodiment, in the chip stack structure, four memory chips 10 form a stacking unit. Each memory chip 10 also has a chip position identification code (CID) and a stacking position identification code (SID). The chip position identification code (CID) indicates the position number of the memory chip 10 within the stacking unit to which it belongs, while the stacking position identification code (SID) indicates the position number of the stacking unit to which the memory chip 10 belongs within the chip stack structure to which it belongs.

[0094] Taking a chip stacking structure formed by stacking 1 logic chip and 8 memory chips 10 (every 4 memory chips 10 form a stacking unit, with a total of 2 stacking units) as an example, the chip position identification code CID includes 2-bit sub-signals CID[1] and CID[0], expressed as CID[1:0] (that is, the combined writing of CID[1] and CID[0]), and the chip position identification code CID[1:0] is decoded from the chip position identification signal group CID0[3:0]; the stacking position identification code SID includes 2-bit sub-signals SID[1] and SID[0], expressed as SID[1:0] (that is, the combined writing of SID[1] and SID[0]). In particular, during the normal operation phase of the memory chip 10, the chips are numbered from the side of the logic chip (i.e., from bottom to top). At this time, the chip position identification code CID[1:0] and the stacking position identification code SID[1:0] of each chip are as shown in Table 1. During the initialization phase of the memory chip 10, the chips are numbered from the side away from the logic chip (i.e., from top to bottom). This situation is not shown yet, but can be understood accordingly.

[0095] In particular, in the embodiment of the present disclosure, different memory chips 10 are placed in different positions in the chip stacking structure. For the convenience of explanation, the active surface of each memory chip 10 (the plane where the first direction and the second direction are located) is divided into a low-level transmission area and a high-level transmission area (the present disclosure takes the division of the low-level transmission area and the high-level transmission area in the first direction as an example for demonstration). The placement positions of the memory chips 10 in the chip stacking structure of the present disclosure may be different as follows: the high-level transmission area is located on the side pointed by the second direction arrow or the low-level transmission area is located on the side pointed by the second direction arrow. For further reference, please refer to the description and drawings in the chip stacking structure.

[0096] Table 1

[0097] Furthermore, the memory chip 10 also includes: a decoding circuit, coupled to the first signal selection circuit 33 and the second signal selection circuit 34, configured to receive a chip position identification code, the chip position identification code including a high-order position parameter and a low-order position parameter; if the chip position identification code indicates that the memory chip 10 is in a first type of position, a position identification signal of a first state is output; if the chip position identification code indicates that the memory chip 10 is in a second type of position, a position identification signal of a second state is output.

[0098] It can be understood that because the chip location identification code CID[1:0] is decoded from the chip location identification signal group CID0[3:0], when the chip location identification signal group CID0[3:0] indicates that the memory chip 10 is in the first type of position, the chip location identification code CID[1:0] also indicates that the memory chip 10 is in the first type of position; similarly, when the chip location identification signal group CID0[3:0] indicates that the memory chip 10 is in the second type of position, the chip location identification code CID[1:0] also indicates that the memory chip 10 is in the second type of position. Among them, the chip location identification signal group CID0[3:0] indicates the position of the memory chip 10 in the corresponding stacking unit.

[0099] In one possibility, for each stacking unit, the first and fourth memory chips 10 are in the first type of position, and the second and third memory chips 10 are in the second type of position;

[0100] As shown in FIG6 , the decoding circuit is a two-input XOR gate; wherein, the first input end of the two-input XOR gate is used to receive the low-order position parameter, the second input end of the two-input XOR gate is used to receive the high-order position parameter, and the output end of the two-input XOR gate is used to output the position identification signal.

[0101] It should be noted that the chip location identification code CID has two sub-signals CID[1] and CID[0]. Here, the lower position parameter is CID[0] and the upper position parameter is CID[1]. For example, in Table 1, for the first memory chip 100, that is, when CID[1:0]=00, the XOR result is 0, and the location identification signal is in the first state; for the second memory chip 101, that is, when CID[1:0]=01, the XOR result is 1, and the location identification signal is in the second state; for the third memory chip 102, that is, when CID[1:0]=10, the XOR result is 1, and the location identification signal is in the second state; for the fourth memory chip 103, that is, when CID[1:0]=11, the XOR result is 0, and the location identification signal is in the first state.

[0102] In another possibility, for each stacking unit, the first and second memory chips 10 are in the first position, and the third and fourth memory chips 10 are in the second position;

[0103] The decoding circuit determines the high-order position parameter as a position identification signal.

[0104] For example, in Table 1, for the first memory chip 100, that is, when CID[1:0]=00, the high-order position parameter CID[1]=0, and the position identification signal is in the first state; for the second memory chip 101, that is, when CID[1:0]=01, the high-order position parameter CID[1]=0, and the position identification signal is in the first state; for the third memory chip 102, that is, when CID[1:0]=10, the high-order position parameter CID[1]=1, and the position identification signal is in the second state; for the fourth memory chip 103, that is, when CID[1:0]=11, the high-order position parameter CID[1]=1, and the position identification signal is in the second state.

[0105] In this case, the decoding circuit may be a buffer or a driver, which is not particularly limited.

[0106] Regarding the first signal selection circuit 33 and the second signal selection circuit 34, see FIG7 , which shows a third schematic diagram of the structure of a memory chip provided by an embodiment of the present disclosure. As shown in FIG7 , in some embodiments, the first signal selection circuit 33 may include a first driver a1 and a first data selector a2, and the second signal selection circuit 34 may include a second driver a3 and a second data selector a4;

[0107] A first terminal of the first data selector a2 receives the first intermediate signal, a second terminal of the first data selector a2 receives the second intermediate signal, a third terminal of the first data selector a2 is coupled to the first terminal of the first driver a1, and a second terminal of the first driver a1 is coupled to the first signal input node;

[0108] A first end of the second data selector a4 receives the second intermediate signal, a second end of the second data selector a4 receives the first intermediate signal, a third end of the second data selector a4 is coupled to a first end of the second driver a3, and a second end of the second driver a3 is coupled to the second signal input node.

[0109] It should be noted that the first and second ends of the first data selector a2 and the second data selector a4 are input ends, and the third end is an output end; wherein the first end is a logic "0" end, and the second end is a logic "1" end.

[0110] It should also be noted that, as shown in FIG7 , the first driver a1 and the second driver a3 are specifically input drivers, which may also be referred to as input drive branches (Receive, RX).

[0111] It can be understood that for the conductive through-hole group 20, the first driver a1 is coupled to its corresponding first data selector a2, so that one of the first intermediate signal or the second intermediate signal selected and output by the first data selector a2 is input into the memory chip 10 via the first driver a1 coupled to its corresponding one; the second driver a3 is coupled to its corresponding second data selector a4, so that the other of the first intermediate signal or the second intermediate signal selected and output by the second data selector a4 is input into the memory chip 10 via the second driver a3 coupled to its corresponding one.

[0112] Based on FIG7 , FIG8 is shown, which illustrates a fourth schematic diagram of the composition structure of a memory chip provided by an embodiment of the present disclosure. As shown in FIG8 , in another possibility, the memory chip 10 may further include multiple output selection circuits 40 (only one output selection circuit 40 is shown in FIG8 , and the others are omitted). One side of each output selection circuit 40 is coupled to a first signal output node and a second signal output node within the memory chip 10, and the other side of each output selection circuit 40 is coupled to a conductive via group 20.

[0113] The output selection circuit 40 is configured to electrically connect the coupled first signal output node with the coupled first redundant conductive via group 21, and to electrically connect the coupled second signal output node with the coupled second redundant conductive via group 22; or, to electrically connect the coupled first signal output node with the coupled second redundant conductive via group 22, and to electrically connect the coupled second signal output node with the coupled first redundant conductive via group 21.

[0114] The first signal output node can be represented by P, and the second signal output node can be represented by Q.

[0115] It should be noted that the number of the plurality of conductive via groups 20 and the number of the plurality of output selection circuits 40 may be the same or different, and there is no specific limitation on this.

[0116] It should also be noted that the memory chip 10 may include only the output selection circuit 40, or may include both the input selection circuit 30 and the output selection circuit 40, without specific limitation. For example, FIG8 includes both the input selection circuit 30 and the output selection circuit 40 (the reference numeral for the input selection circuit 30 is omitted; please refer to FIG5 for further understanding).

[0117] In some embodiments, as shown in FIG8 , the output selection circuit 40 may include a third signal selection circuit 41 and a fourth signal selection circuit 42 ;

[0118] A third signal selection circuit 41 has a first terminal coupled to the first signal output node, a second terminal coupled to the second signal output node, and a third terminal coupled to the first redundant conductive via group 21. The third signal selection circuit 41 is configured to receive a position identification signal and, based on the position identification signal, electrically connect one of the first signal output node and the second signal output node to the first redundant conductive via group 21.

[0119] The fourth signal selection circuit 42 has a first end coupled to the second signal output node, a second end coupled to the first signal output node, and a third end coupled to the second redundant conductive through-hole group 22; the fourth signal selection circuit 42 is configured to receive a position identification signal, and based on the position identification signal, electrically connect the other of the first signal output node and the second signal output node to the second redundant conductive through-hole group 22.

[0120] The control terminals of the third signal selection circuit 41 and the fourth signal selection circuit 42 are both used to receive the position identification signal. In some embodiments, the third signal selection circuit 41 is configured to electrically connect the first signal output node P to the first redundant conductive via group 21 when the position identification signal is in the first state (logical "0"); or, when the position identification signal is in the second state (logical "1"), to electrically connect the second signal output node Q to the first redundant conductive via group 21; and the fourth signal selection circuit 42 is configured to electrically connect the second signal output node Q to the second redundant conductive via group 22 when the position identification signal is in the first state; or, when the position identification signal is in the second state, to electrically connect the first signal output node P to the second redundant conductive via group 22.

[0121] Further, as shown in FIG8 , in some embodiments, the third signal selection circuit 41 includes a third driver u1 and a third data selector u2 , and the fourth signal selection circuit 42 includes a fourth driver u3 and a fourth data selector u4 ;

[0122] A first terminal of the third data selector u2 is coupled to the first signal output node, a second terminal of the third data selector u2 is coupled to the second signal output node, a third terminal of the third data selector u2 is coupled to a first terminal of the third driver u1, and a second terminal of the third driver u1 is coupled to the first redundant conductive via group 21;

[0123] The first end of the fourth data selector u4 is coupled to the second signal output node, the second end of the fourth data selector u4 is coupled to the first signal output node, the third end of the fourth data selector u4 is coupled to the first end of the fourth driver u3, and the second end of the fourth driver u3 is coupled to the second redundant conductive through-hole group 22.

[0124] It should be noted that the first and second ends of the third data selector u2 and the fourth data selector u4 are input ends, and the third end is an output end; wherein the first end is a logic "0" end, and the second end is a logic "1" end.

[0125] It should also be noted that, as shown in Figure 8, the third driver u1 and the fourth driver u3 are specifically output drivers, which can also be called output drive branches (Transmit, TX), which output the global signal generated by the internal circuit of the memory chip 10 to the corresponding coupled first redundant conductive through-hole group 21 or the second redundant conductive through-hole group 22.

[0126] It can be understood that for part of the first redundant conductive via group 21, the third driver u1 is coupled to its corresponding third data selector u2, so that one of the first signal output node P or the second signal output node Q selected by the third data selector u2 is coupled to the corresponding first redundant conductive via group 21 via the third driver u1 coupled to it; for part of the second redundant conductive via group 22, the fourth driver u3 is coupled to its corresponding fourth data selector u4, so that the other of the first signal output node P or the second signal output node Q selected by the fourth data selector u4 is coupled to the corresponding second redundant conductive via group 22 via the fourth driver u3 coupled to it.

[0127] Referring to FIG9 , which shows a fifth structural diagram of a memory chip according to an embodiment of the present disclosure, as shown in FIG9 , in some embodiments, the memory chip 10 may further include a plurality of bidirectional selection circuits 43 , one side of each bidirectional selection circuit 43 being coupled to a conductive via group 20 , and the other side of each bidirectional selection circuit 43 being coupled to a first bidirectional signal node and a second bidirectional signal node within the memory chip 10 ;

[0128] The bidirectional selection circuit 43 is configured to electrically connect the coupled first redundant conductive via group 21 to the coupled first bidirectional signal node, and to electrically connect the coupled second redundant conductive via group 22 to the coupled second bidirectional signal node; or to electrically connect the coupled first redundant conductive via group 21 to the coupled second bidirectional signal node, and to electrically connect the coupled second redundant conductive via group 22 to the coupled first bidirectional signal node;

[0129] The bidirectional selection circuit 43 is also configured to receive an input enable signal and an output enable signal; when the input enable signal is in an enabled state, the signal received from the first redundant conductive via group 21 is driven to be transmitted to the bidirectional signal node coupled thereto, and the signal received from the second redundant conductive via group 22 is driven to be transmitted to the bidirectional signal node coupled thereto; or, when the output enable signal is in an enabled state, the signal received from the first bidirectional signal node is driven to be transmitted to the redundant conductive via group coupled thereto, and the signal received from the second bidirectional signal node is driven to be transmitted to the redundant conductive via group coupled thereto.

[0130] The first bidirectional signal node can be represented by R, and the second bidirectional signal node can be represented by T.

[0131] Here, the number of the plurality of conductive via groups 20 and the number of the plurality of bidirectional selection circuits 43 may be the same or different, and there is no specific limitation on this.

[0132] It should be noted that, at the same time, only one of the input enable signal and the output enable signal is in the enabled state.

[0133] It should also be noted that, when the input enable signal is in the enabled state, the signal received from the first redundant conductive via group 21 can be driven and transmitted to the first bidirectional signal node R or the second bidirectional signal node T coupled thereto, and the signal received from the second redundant conductive via group 22 can be driven and transmitted to the second bidirectional signal node T or the first bidirectional signal node R coupled thereto. When the output enable signal is in the enabled state, the signal received from the first bidirectional signal node R can be driven and transmitted to the first redundant conductive via group 21 or the second redundant conductive via group 22 coupled thereto, and the signal received from the second bidirectional signal node T can be driven and transmitted to the second redundant conductive via group 22 or the first redundant conductive via group 21 coupled thereto.

[0134] Furthermore, as shown in FIG9 , in some embodiments, the bidirectional selection circuit 43 may further include a first OR gate 31 , a second OR gate 32 , a first bidirectional selection circuit 44 , and a second bidirectional selection circuit 45 ;

[0135] A first OR gate 31 is coupled to the first conductive via D0 and the fourth conductive via D3 and configured to perform an OR operation on the signal of the first conductive via D0 and the signal of the fourth conductive via D3 to output a first intermediate signal;

[0136] A second OR gate 32 is coupled to the second conductive via D1 and the third conductive via D2 and configured to perform an OR operation on the signal of the second conductive via D1 and the signal of the third conductive via D2 to output a second intermediate signal;

[0137] a first bidirectional selection circuit 44 configured to receive and transmit one of the first intermediate signal and the second intermediate signal to the first bidirectional signal node based on the position identification signal when the input enable signal is in an enabled state;

[0138] a second bidirectional selection circuit 45 configured to receive and transmit the other of the first intermediate signal and the second intermediate signal to the second bidirectional signal node based on the position identification signal when the input enable signal is in an enabled state;

[0139] The first bidirectional selection circuit 44 is further configured to receive and transmit the signal output by the first bidirectional signal node to one of the first redundant conductive via group 21 and the second redundant conductive via group 22 based on the position identification signal when the output enable signal is in the enabled state;

[0140] The second bidirectional selection circuit 45 is further configured to receive and transmit the signal output by the second bidirectional signal node to the other of the first redundant conductive via group 21 and the second redundant conductive via group 22 based on the position identification signal when the output enable signal is in the enabled state.

[0141] The enable terminals of the first bidirectional selection circuit 44 and the second bidirectional selection circuit 45 are used to receive an input enable control signal and an output enable control signal (the enable terminals are not shown in FIG. 9 ).

[0142] In some embodiments, each conductive via in the memory chip 10 can be prepared by any one or more of the processes of via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip 10 are electrically isolated from each other.

[0143] Among them, the via-first process refers to a via-hole process method that first creates a via structure before manufacturing the device structure of a device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET or MOS transistor). The intermediate via process is a via structure formed during the manufacturing process flow, often after the device is formed and before the stack is fabricated. The via-last process is a manufacturing process that forms a via from the front side of the wafer after the back-end of line (BEOL) processing is completed. The back-end via process is a manufacturing process that creates a via structure from the back side of the wafer after the BEOL processing is completed. In other words, the via-first process can refer to first forming the via, then forming the circuit, such as the conductive via of type 1 in Figure 1; the intermediate via process can refer to first forming the circuit and part of the metal layer, then forming the via, and finally forming the remaining via, such as the conductive via of type 2 in Figure 1; the via-last process and the back-end via process can refer to first forming the circuit and metal layer, then forming the via, such as the conductive via of type 2 in Figure 1.

[0144] The embodiment of the present disclosure provides a memory chip in which the conductive through-holes have a special symmetry and can be directly applied to a stacking structure constructed in any manner such as face-to-face / back-to-back / face-to-back, without the need for two sets of masks or two sets of conductive through-holes. Compared with the memory chip of Figure 1, the parasitic capacitance can be reduced, the circuit area can be saved, and the chip manufacturing cost can be reduced; the subsequent memory chip 10 can also reduce the parasitic resistance compared with the memory chips of Figures 2A and 2B when forming a stacking structure (for specific reasons, see the subsequent description).

[0145] In another embodiment of the present disclosure, see Figure 10, which illustrates a schematic diagram of an active surface of a logic chip according to an embodiment of the present disclosure. As shown in Figure 10, the center point of the active surface of logic chip 50 and its adjacent signal area are defined as a global signal region 111. The center point of global signal region 111 coincides with the center point of the active surface, and channel signal regions are located on both sides of global signal region 111.

[0146] Both the global signal region 111 and the channel signal region are penetrated by numerous conductive vias along a third direction perpendicular to the active surface. Furthermore, because the PADs in the logic chip 50 are typically located in the center of the chip, conductive vias for global signals such as the DFT are preferably located in the narrower region in the center of the chip, as shown in the global signal region 111 in FIG. 10 .

[0147] In addition, the areas of the logic chip 50 and the memory chip 10 may be the same or different, which is not specifically limited. However, the global signal regions in both are located in the middle of their respective chips, and the areas of the two global signal regions are the same.

[0148] Referring to FIG. 10 , the active surface of logic chip 50 includes a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center of the active surface. The first axis AA' is parallel to a first side of logic chip 50, and the second axis BB' is parallel to a second side of logic chip 50. In FIG. 10 , the first axis AA' extends along a first direction, and the second axis BB' extends along a second direction. This is merely an example and does not constitute a specific limitation.

[0149] Further, referring to FIG11 , which shows a schematic diagram of the structure of a logic chip provided by an embodiment of the present disclosure. As shown in FIG11 , in a logic chip 50, the global signal region is penetrated by multiple conductive via groups 60 (only one conductive via group 60 is shown in FIG11 , the others are omitted). Each conductive via group 60 includes a first redundant conductive via group 61 and a second redundant conductive via group 62. The first redundant conductive via group 61 includes a first conductive via D0 and a fourth conductive via D3, and the second redundant conductive via group 62 includes a second conductive via D1 and a third conductive via D2. The first redundant conductive via group 61 is used to transmit the same first global signal, and the second redundant conductive via group 62 is used to transmit the same second global signal.

[0150] In particular, Figure 11 can be viewed as a schematic cross-section of the active surface of the logic chip 50. Referring to Figure 11 , for the same conductive via group 60, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0151] In this embodiment, for the first conductive via D0 and the fourth conductive via D3 in the same first redundant conductive via group 61, or for the second conductive via D1 and the third conductive via D2 in the same second redundant conductive via group 62, each conductive via transmits exactly the same signal, that is, a signal with the same transmission type and signal value, and will further transmit it to different memory chips.

[0152] It should be noted that the positions of the conductive via groups 60 in the global signal region vary. Specifically, the number and position of the conductive via groups 60 can be adjusted based on actual conditions and are not limited thereto. However, the number of conductive vias in each conductive via group 60 must be the same and must adhere to the aforementioned symmetrical distribution rules. The following example illustrates a situation where the global signal region is penetrated by one conductive via group 60, and the conductive via group 60 includes a first redundant conductive via group 61 and a second redundant conductive via group 62, with four conductive vias in the conductive via group 60.

[0153] It can be understood that the numbering sequence of the conductive vias in each conductive via group 60 does not constitute any limitation.

[0154] Referring to FIG12 , which shows a second schematic diagram of the structure of a logic chip provided by an embodiment of the present disclosure, as shown in FIG12 , in one embodiment, the logic chip 50 may further include multiple first output drive circuits 71 and multiple second output drive circuits 72 ( FIG12 only shows one first output drive circuit 71 and one second output drive circuit 72; the others are omitted).

[0155] A first output driver circuit 71 is coupled to all conductive vias in a first redundant conductive via group 61 , and a second output driver circuit 72 is coupled to all conductive vias in a second redundant conductive via group 62 ;

[0156] A first output driving circuit 71 is configured to send a first global signal generated inside the logic chip 50 to all correspondingly coupled conductive vias;

[0157] The second output driving circuit 72 is configured to send the second global signal generated inside the logic chip 50 to all correspondingly coupled conductive vias.

[0158] The first output driver circuit 71 can be coupled to the active surface portions of the first conductive via D0 and the fourth conductive via D3 in the corresponding first redundant conductive via group 61, and the second output driver circuit 72 can be coupled to the active surface portions of the second conductive via D1 and the third conductive via D2 in the corresponding second redundant conductive via group 62. That is, for the first redundant conductive via group 61, the first conductive via D0 and the fourth conductive via D3 are connected to the same first output driver circuit 71, and the first global signal transmitted by each conductive via is output from within the logic chip 50 and sent to all conductive vias coupled thereto. The second conductive via D1 and the third conductive via D2 are connected to the same second output driver circuit 72, and the second global signal transmitted by each conductive via is output from within the logic chip 50 and sent to all conductive vias coupled thereto.

[0159] Based on FIG12 , FIG13 shows a third schematic diagram of the structure of a logic chip according to an embodiment of the present disclosure. As shown in FIG13 , in another embodiment, the logic chip 50 may further include multiple input drive circuits 73 ( FIG13 shows only one input drive circuit 73 , with the others omitted). Each input drive circuit 73 is coupled to a conductive via group 60 .

[0160] The logic chip 50 is configured to send an enable control signal to the target memory chip and receive the first global signal and the second global signal sent by the target memory chip via the input drive circuit 73;

[0161] Among them, each input drive circuit 73 may include a third OR gate b1, a first input driver b2, a fourth OR gate b3 and a second input driver b4; the first input end of the third OR gate b1 is connected to the first conductive through hole D0, the second input end of the third OR gate b1 is connected to the fourth conductive through hole D3, and the output end of the third OR gate b1 is coupled to the first input driver b2; the first input end of the fourth OR gate b3 is connected to the second conductive through hole D1, the second input end of the fourth OR gate b3 is connected to the third conductive through hole D2, and the output end of the fourth OR gate b3 is coupled to the second input driver b4.

[0162] Specifically, the third OR gate b1 can be coupled to the active surface portions of all conductive vias in the same first redundant conductive via group 61, and the fourth OR gate b3 can be coupled to the active surface portions of all conductive vias in the same second redundant conductive via group 62. Furthermore, within the global signal region, the signal transmission channels formed by the conductive vias are mostly unidirectional transmission channels, that is, they transmit global signals from the logic chip 50 to the memory chip 10. A small number of the signal transmission channels formed by the conductive vias also have a reverse transmission function, that is, they are bidirectional transmission channels, and can also transmit global signals from the memory chip 10 to the logic chip 50. For logic chip 50, all conductive vias in a portion of first redundant conductive via group 61 are coupled to their corresponding third OR gates b1, and the third OR gates b1 are coupled to their corresponding first input drivers b2. Global signals transmitted by the first redundant conductive via group 61 enter the logic chip 50 via the third OR gates b1 and first input drivers b2. Similarly, all conductive vias in a portion of second redundant conductive via group 62 are coupled to their corresponding fourth OR gates b3, and the fourth OR gates b3 are coupled to their corresponding second input drivers b4. Global signals transmitted by the second redundant conductive via group 62 enter the logic chip 50 via the fourth OR gates b3 and second input drivers b4. Furthermore, a driving circuit may be provided between the third OR gates b1 and all conductive vias in the first redundant conductive via group 61 to drive the global signal, and between the fourth OR gates b3 and all conductive vias in the second redundant conductive via group 62 to drive the global signal. This is not specifically limited.

[0163] It should be noted that when multiple memory chips transmit global signals to the logic chip 50, it is possible that memory chip 0 (i.e., the first memory chip 11 in the chip stacking structure 80 described below) and memory chip 3 (i.e., the fourth memory chip 14 in the chip stacking structure 80 described below) may transmit signals through the same conductive via. In this case, the logic chip 50 can distinguish which conductive via the global signal is transmitted from by using the following mechanism: If the logic chip 50 needs to receive a global signal from a target memory chip, the logic chip 50 first transmits an enable control signal. For example, the enable control signal is sent to the first memory chip 11. Subsequently, the global signal received from the first conductive via D0 or the fourth conductive via D3 indicates that the signal is transmitted from the first memory chip 11. The enable control signal is sent to the fourth memory chip 14. Subsequently, the global signal received from the first conductive via D0 or the fourth conductive via D3 indicates that the signal is transmitted from the fourth memory chip 14. However, this is not specifically limited to this. In addition, when multiple memory chips transmit global signals to the logic chip 50, only one memory chip transmits the global signal to the logic chip 50 at a time.

[0164] In some embodiments, as shown in FIG13 , each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0165] Among them, if the conductive through hole does not transmit a signal or the connection is abnormal, the weak ground terminal controls the level state of the conductive through hole to be a low level; if the conductive through hole is connected normally and transmits a signal, the level state of the conductive through hole depends on the transmitted signal.

[0166] It should be noted that in some embodiments, some global signals can be transmitted bidirectionally, that is, they can be transmitted from the logic chip 50 to the memory chip 10, or from the memory chip 10 to the logic chip 50, but this is not specifically limited. When the global signal is transmitted from the logic chip 50 to the memory chip 10, because each conductive via in the memory chip 10 is connected to the weak ground terminal, that is, the default level value of each conductive via is 0, in the first redundant conductive via group 21 or the second redundant conductive via group 22, as long as one of the two conductive vias in the signal transmission channel can normally transmit signal data, even if some of the conductive vias are disconnected (open), it will not affect the final signal reception, thus forming a 2-dummy signal transmission architecture.

[0167] Similarly, when a global signal is transmitted from the memory chip 10 to the logic chip 50, because each conductive via in the logic chip 50 is connected to the weak ground terminal, that is, the default level value of each conductive via is 0, as long as one of the two signal transmission channels formed by the conductive vias in the first redundant conductive via group 61 or the second redundant conductive via group 62 can normally transmit signal data, even if some of the conductive vias are open, it will not affect the final signal reception, thus forming a 2-dummy signal transmission architecture.

[0168] In some embodiments, each conductive via in the logic chip 50 can be prepared by any one or more of the processes of via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same logic chip 50 are electrically isolated from each other.

[0169] The embodiment of the present disclosure provides a logic chip, wherein the conductive vias in the logic chip and the aforementioned memory chip are arranged in the same position. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0170] In another embodiment of the present disclosure, refer to FIG14 , which shows a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure. As shown in FIG14 , the chip stacking structure 80 includes a logic chip 50 and at least one stacking unit (only two stacking units are shown in FIG14 , and the rest are omitted), and the logic chip 50 and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13, and a fourth memory chip 14 stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each memory chip; the structures of the first memory chip 11, the second memory chip 12, the third memory chip 13, and the fourth memory chip 14 are all the aforementioned memory chips 10, and the structure of the logic chip 50 is the aforementioned logic chip 50. In particular, in FIG14 , the portion shown is only the global signal area of ​​each chip, not the entire active surface.

[0171] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to back, or the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to back.

[0172] In the disclosed embodiments, face-to-face stacking means that the top surfaces of the two chips are approximately aligned along a third direction, and the center points, first axis AA', and second axis BB' of the top surfaces of the two chips are all aligned along the third direction. Back-to-back stacking means that the bottom surfaces of the two chips are approximately aligned along the third direction. Back-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of the other chip along the third direction. When logic chip or memory chip is not specified, "chip" can refer to both logic chip and memory chip.

[0173] The n conductive through-hole groups in the logic chip 50 (only one conductive through-hole group is shown in FIG14 , and the rest are omitted) correspond one-to-one with the n conductive through-hole groups in each first memory chip 11, the n conductive through-hole groups in each second memory chip 12, the n conductive through-hole groups in each third memory chip 13, and the n conductive through-hole groups in each fourth memory chip 14, and are aligned along the third direction, where n is a positive integer.

[0174] It should also be noted that due to process errors, the "alignment" in this article is not absolute alignment, and any deviation within a reasonable range can be considered alignment.

[0175] In the embodiment of the present disclosure, the chip stacking structure 80 may be a high bandwidth memory (HBM) stacked product, particularly involving a repair pattern design for multiple (multidrop) conductive vias in the global signal area of ​​each chip under the condition of four-quadrant symmetry in each chip (i.e., the conductive via group is symmetrical about the first axis and also about the second axis), utilizing the face-to-face and back-to-back symmetry between the multiple conductive vias and the chips, and applying it to signal transmission through the multiple conductive vias, such as reset signals, power-on signals, stack identification signals SID / CID, power-related signals Voltage Monitor, timing-related signals Timing Aligner, etc., without specific limitation. Here, the memory chip can be represented by Core die, and the logic chip can be represented by Base die.

[0176] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a hybrid bonding (Hyperbonding, also known as bonding column) process; for two chips connected back to back or back to face, the bonding surfaces of the two (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a conductive bump (UBump, also known as micro-bump) bonding process.

[0177] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding process.

[0178] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the bonding surfaces of both chips (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a conductive bump bonding process.

[0179] Here, the above chip may refer to a logic chip 50 or a memory chip 10 .

[0180] It should be noted that compared to the conductive bump bonding process, the face-to-face connection using the hybrid bonding process can make the adjacent memory chips fit more closely, with essentially no gaps, thereby significantly reducing the height of the chip stacking structure. This is also one of the advantages of face-to-face stacking. Of course, two memory chips connected back to back can also be electrically connected using the hybrid bonding process, but its connection performance is weaker than when the electrical connection is achieved using the conductive bump process. In this way, in the embodiment of the present disclosure, the chip stacking structure supports face-to-face stacking and has better performance.

[0181] It should be understood that the logic chip 50 or each memory chip can be divided into a high-order transmission area and a low-order transmission area, and the arrows in the subsequent Figures 15A to 18B are uniformly located in the high-order transmission area of ​​the chip. In particular, the high-order transmission area and the low-order transmission area in the embodiment of the present disclosure are merely two areas that distinguish the logic chip 50 or each memory chip, and do not have any additional restrictions. They may not be directly related to the high-order data and low-order data commonly referred to in data transmission. In addition, Figures 14 to 19 only illustrate one conductive through-hole group in the global signal area as an example, but in fact there are multiple conductive through-hole groups in the global signal area, and different conductive through-hole groups have similar alignment characteristics. The alignment of the remaining conductive through-holes is no longer shown. Please combine the following text description and Figures 14 to 19 for adaptive understanding.

[0182] It should be noted that the top surface of the logic chip 50 or each memory chip is divided into 2×2 signal areas, namely the first signal area, the second signal area, the third signal area, and the fourth signal area, denoted by C, D, E, and F. The first signal area (C) and the second signal area (D) are symmetrical along their respective first axis AA', the first signal area (C) and the fourth signal area (F) are symmetrical along their respective second axis BB', and the third signal area (E) and the fourth signal area (F) are symmetrical along their respective first axis AA'. The first axis AA' of the logic chip 50 and each memory chip is aligned along a third direction, and the second axis BB' of the logic chip 50 and each memory chip is aligned along the third direction.

[0183] It should be noted that the first conductive through hole D0 in each conductive through hole group is located in the first signal area (C), the second conductive through hole D1 in each conductive through hole group is located in the second signal area (D), the third conductive through hole D2 in each conductive through hole group is located in the third signal area (E), and the fourth conductive through hole D3 in each conductive through hole group is located in the fourth signal area (F).

[0184] When the logic chip 50 and the first memory chip 11 are stacked back-to-back and the logic chip 50 and the fourth memory chip 14 are placed in the same manner, a first specific implementation method and a second specific embodiment method are provided; when the logic chip 50 and the first memory chip 11 are stacked back-to-back and the logic chip 50 and the second memory chip 12 are placed in the same manner, a third specific implementation method and a fourth specific embodiment method are provided, as described in detail below.

[0185] In the first specific embodiment, as shown in Figure 15A, assuming that the first axis AA' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (that is, the first axis AA' extends along the first direction, the first signal area (C) and the fourth signal area (F) are located in the high-order transmission area, and the second signal area (D) and the third signal area (E) are located in the low-order transmission area), the high-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0186] In a second specific embodiment, as shown in FIG16A , assuming that the second axis BB' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the second axis BB' extends along the first direction, the first signal area (C) and the second signal area (D) are located in the high-order transmission area, and the third signal area (E) and the fourth signal area (F) are located in the low-order transmission area), the high-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0187] Referring to FIG. 15A or FIG. 16A , for the first and second specific embodiments, each signal region has the following alignment relationship:

[0188] (1) The fourth signal area (F) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0189] (2) the third signal area (E) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction;

[0190] (3) The second signal area (D) of the logic chip 50, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction;

[0191] (4) The first signal area (C) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0192] It should also be noted that each conductive via group of the logic chip 50 and each memory chip includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 distributed in a 2×2 array.

[0193] Referring to FIG. 15B or FIG. 16B , for the first and second specific embodiments, only for the multiple signal regions aligned along the third direction, each conductive via has the following alignment relationship:

[0194] (1) The fourth conductive via D3 in the i-th first redundant conductive via group in the logic chip 50, the first conductive via D0 in the i-th first redundant conductive via group in each first memory chip 11, the second conductive via D1 in the i-th second redundant conductive via group in each second memory chip 12, the third conductive via D2 in the i-th second redundant conductive via group in each third memory chip 13, and the fourth conductive via D3 in the i-th first redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0195] (2) the third conductive via D2 in the i-th second redundant conductive via group in the logic chip 50, the second conductive via D1 in the i-th second redundant conductive via group in each first memory chip 11, the first conductive via D0 in the i-th first redundant conductive via group in each second memory chip 12, the fourth conductive via D3 in the i-th first redundant conductive via group in each third memory chip 13, and the third conductive via D2 in the i-th second redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0196] (3) The second conductive via D1 in the i-th second redundant conductive via group in the logic chip 50, the third conductive via D2 in the i-th second redundant conductive via group in each first memory chip 11, the fourth conductive via D3 in the i-th first redundant conductive via group in each second memory chip 12, the first conductive via D0 in the i-th first redundant conductive via group in each third memory chip 13, and the second conductive via D1 in the i-th second redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0197] (4) The first conductive via D0 in the i-th first redundant conductive via group in the logic chip 50, the fourth conductive via D3 in the i-th first redundant conductive via group in each first memory chip 11, the third conductive via D2 in the i-th second redundant conductive via group in each second memory chip 12, the second conductive via D1 in the i-th second redundant conductive via group in each third memory chip 13, and the first conductive via D0 in the i-th first redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel.

[0198] It should be noted that i is a positive integer less than or equal to n.

[0199] Please refer to Figures 15A and 15B . The arrow direction of each chip indicates the high-order transmission area. The memory chips in the first position are those whose high-order transmission area (i.e., the area where the first signal area (C) and the fourth signal area (F) are located) is located on the side indicated by the second direction arrow, namely, memory chips 11 and 14. The memory chips in the second position are those whose low-order transmission area (i.e., the area where the second signal area (D) and the third signal area (E) are located) is located on the side indicated by the second direction arrow, namely, memory chips 12 and 13. Please refer to Figures 16A and 16B . The memory chips in the first position are those whose high-order transmission area (i.e., the area where the first signal area (C) and the second signal area (D) are located) is located on the side indicated by the second direction arrow, namely, memory chips 11 and 12. The memory chips in the second position are those whose low-order transmission area (i.e., the area where the third signal area (E) and the fourth signal area (F) are located) is located on the side indicated by the second direction arrow, namely, memory chips 13 and 14.

[0200] For the first and second specific embodiments, in some embodiments, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned; or,

[0201] The high-order transmission area of ​​the first memory chip 11 , the high-order transmission area of ​​the second memory chip 12 , the low-order transmission area of ​​the third memory chip 13 , and the low-order transmission area of ​​the fourth memory chip 14 are aligned.

[0202] Specifically, referring to Figures 15A and 15B, the first specific embodiment is that the high-order transmission area of ​​the first storage chip 11, the low-order transmission area of ​​the second storage chip 12, the low-order transmission area of ​​the third storage chip 13, and the high-order transmission area of ​​the fourth storage chip 14 are aligned; referring to Figures 16A and 16B, the second specific embodiment is that the high-order transmission area of ​​the first storage chip 11, the high-order transmission area of ​​the second storage chip 12, the low-order transmission area of ​​the third storage chip 13, and the low-order transmission area of ​​the fourth storage chip 14 are aligned.

[0203] In a third specific embodiment, as shown in FIG17A , assuming that the first axis AA' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the first axis AA' extends along the first direction, the first signal area (C) and the fourth signal area (F) are located in the high-order transmission area, and the second signal area (D) and the third signal area (E) are located in the low-order transmission area), the low-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the high-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0204] In a fourth specific embodiment, as shown in FIG18A , assuming that the second axis BB' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the second axis BB' extends along the first direction, the first signal area (C) and the second signal area (D) are located in the high-order transmission area, and the third signal area (E) and the fourth signal area (F) are located in the low-order transmission area), the low-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the high-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0205] Referring to FIG. 17A or FIG. 18A , for the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0206] (1) The second signal area (D) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0207] (2) the first signal area (C) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction;

[0208] (3) the fourth signal region (F) of the logic chip 50, the third signal region (E) of the first memory chip 11, the fourth signal region (F) of the second memory chip 12, the first signal region (C) of the third memory chip 13, and the second signal region (D) of the fourth memory chip 14 are aligned along the third direction;

[0209] (4) The third signal area (E) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0210] Referring to FIG. 17B or FIG. 18B , for the third and fourth specific embodiments, only for the multiple signal regions aligned along the third direction, each conductive via has the following alignment relationship:

[0211] (1) The second conductive via D1 in the i-th second redundant conductive via group in the logic chip 50, the first conductive via D0 in the i-th first redundant conductive via group in each first memory chip 11, the second conductive via D1 in the i-th second redundant conductive via group in each second memory chip 12, the third conductive via D2 in the i-th second redundant conductive via group in each third memory chip 13, and the fourth conductive via D3 in the i-th first redundant conductive via group in each fourth memory chip 14 are aligned along a third direction and constitute a signal transmission channel;

[0212] (2) the first conductive via D0 of the i-th first redundant conductive via group in the logic chip 50, the second conductive via D1 of the i-th second redundant conductive via group in each first memory chip 11, the first conductive via D0 of the i-th first redundant conductive via group in each second memory chip 12, the fourth conductive via D3 of the i-th first redundant conductive via group in each third memory chip 13, and the third conductive via D2 of the i-th second redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0213] (3) The fourth conductive via D3 in the i-th first redundant conductive via group in the logic chip 50, the third conductive via D2 in the i-th second redundant conductive via group in each first memory chip 11, the fourth conductive via D3 in the i-th first redundant conductive via group in each second memory chip 12, the first conductive via D0 in the i-th first redundant conductive via group in each third memory chip 13, and the second conductive via D1 in the i-th second redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0214] (4) The third conductive via D2 in the i-th second redundant conductive via group in the logic chip 50, the fourth conductive via D3 in the i-th first redundant conductive via group in each first memory chip 11, the third conductive via D2 in the i-th second redundant conductive via group in each second memory chip 12, the second conductive via D1 in the i-th second redundant conductive via group in each third memory chip 13, and the first conductive via D0 in the i-th first redundant conductive via group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel.

[0215] Please refer to Figures 17A and 17B. The memory chips in the first position refer to the memory chips whose high-order transmission area (i.e., the area where the first signal area (C) and the fourth signal area (F) are located) are located on the side pointed by the second direction arrow, namely, memory chip 11 and memory chip 14; the memory chips in the second position refer to the memory chips whose low-order transmission area (i.e., the area where the second signal area (D) and the third signal area (E) are located) are located on the side pointed by the second direction arrow, namely, memory chip 12 and memory chip 13. Please refer to Figures 18A and 18B. The memory chips in the first position refer to the memory chips whose high-order transmission area (i.e., the area where the first signal area (C) and the second signal area (D) are located) are located on the side pointed by the second direction arrow, namely, memory chip 11 and memory chip 12; the memory chips in the second position refer to the memory chips whose low-order transmission area (i.e., the area where the third signal area (E) and the fourth signal area (F) are located) are located on the side pointed by the second direction arrow, namely, memory chip 13 and memory chip 14.

[0216] For the third and fourth specific embodiments, in some embodiments, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned; or,

[0217] The high-order transmission area of ​​the first memory chip 11 , the high-order transmission area of ​​the second memory chip 12 , the low-order transmission area of ​​the third memory chip 13 , and the low-order transmission area of ​​the fourth memory chip 14 are aligned.

[0218] Specifically, referring to Figures 17A and 17B, the third specific embodiment is that the high-order transmission area of ​​the first storage chip 11, the low-order transmission area of ​​the second storage chip 12, the low-order transmission area of ​​the third storage chip 13, and the high-order transmission area of ​​the fourth storage chip 14 are aligned; referring to Figures 18A and 18B, the fourth specific embodiment is that the high-order transmission area of ​​the first storage chip 11, the high-order transmission area of ​​the second storage chip 12, the low-order transmission area of ​​the third storage chip 13, and the low-order transmission area of ​​the fourth storage chip 14 are aligned.

[0219] In some embodiments, please refer to Figure 19, which shows a signal transmission schematic diagram of a chip stacking structure provided by an embodiment of the present disclosure. In particular, Figure 19 is illustrated for the chip stacking structure shown in Figures 15A to 16B. In addition, Figure 19 is only an abstract circuit schematic diagram, "OR" represents the first OR gate and the second OR gate, and the first signal selection circuit and the second signal selection circuit are combined and shown. The input selection circuit 30 in Figure 19 is simply placed next to the conductive through-hole, and the connection relationship is not specifically drawn. Please also combine the text description for adaptive understanding. In Figure 19, Signal 1 represents the first global signal, and Signal 2 represents the second global signal.

[0220] Thus, referring to FIG. 19 , for the chip stacking structure 80, the bottom-up signal transmission path will be similar to the following form: the fourth conductive via D3 in the logic chip 50 - the first conductive via D0 in the first memory chip 11 - the second conductive via D1 in the second memory chip 12 - the third conductive via D2 in the third memory chip 13 - the fourth conductive via D3 in the fourth memory chip 14... " for transmission, and the rest of the signals are similar. That is to say, for the chip stacking structure 80, from a physical point of view, the conductive vias therein are still directly connected, but from the absolute position of the conductive vias on the active surface, the conductive vias are directly connected. Specifically, the conductive vias can be viewed as a functionally rotated configuration, that is, a signal transmission effect similar to that shown in FIG2B (i.e., a rotational transmission effect such as conductive via D0 - conductive via D1 - conductive via D2 - conductive via D3 ...) is achieved through a physically direct connection configuration. Furthermore, in FIG2A and FIG2B , the signal transmission channels in the chip stack structure consisting of eight memory chips can only be transmitted to two memory chips (e.g., signal Signal_CH0 is transmitted to memory chip 0 and memory chip 4), while the signal transmission channels in the chip stack structure 80 in the embodiment of the present disclosure can be transmitted to all memory chips.

[0221] From the above, it can be seen that in the embodiments of the present disclosure, although one connection point on the logic chip corresponds to four different connection points of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip, every two conductive through-holes in the same redundant conductive through-hole group transmit the same global signal, so that the memory chips flipped to different positions can receive the same global signal output by the logic chip through two signal transmission channels. In other words, every two conductive through-holes in the same redundant conductive through-hole group transmit the same global signal, that is, the two signal transmission channels formed are redundant with each other. When some of the conductive through-holes have defects and cause one signal transmission channel to be unable to transmit the global signal normally, the other redundant signal transmission channel can still ensure that all memory chips can receive the correct global signal, thereby achieving a repair effect. In addition, when the four quadrants of each chip are symmetrical, in the global signal area, at least two conductive through-holes are required to transmit the same global signal to achieve a redundant repair effect. Under normal circumstances, in order to ensure that the memory chips in four different stacking positions (i.e., the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip) can all receive the global signal, the logic chip requires at least eight conductive through-holes (i.e., four groups of two conductive through-holes corresponding to the memory chips in the four stacking positions, respectively) to transmit the global signal. However, in the embodiment of the present disclosure, the same global signal of the logic chip is transmitted using only two conductive through-holes, with each two global signals forming a group. After the global signal is transmitted from the logic chip to the memory chips in different stacking positions, the different memory chips are distinguished by the position identification signal, so that different conductive through-holes in the memory chip respectively switch to output the first global signal or the second global signal. The conductive through-hole setting of this scheme can achieve the redundant repair effect of the global signal with the minimum number of conductive through-holes, reduce the occupied area of ​​the global signal area, and further reduce the area of ​​the memory chip.

[0222] In another embodiment of the present disclosure, referring to Figure 20, a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure is shown. As shown in Figure 20, the memory 90 includes the chip stacking structure 80 described in the above embodiment.

[0223] In some embodiments, the chip stacking structure 80 can be applied to a memory 90. The memory 90 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0224] In the embodiment of the present disclosure, for the memory 90, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0225] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0226] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0227] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0228] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0229] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0230] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0231] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0232] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0233] The embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure and a memory, which utilize conductive through-holes with special symmetry to not only reduce the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip and the logic chip realizes a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and also reduces parasitic resistance; further, in the same conductive through-hole group, two conductive through-holes are utilized to form a redundant conductive through-hole group for transmitting the same global signal, thereby achieving a redundant repair effect; and the conductive through-hole setting can achieve a redundant repair effect of the global signal with a minimum number of conductive through-holes, thereby reducing the occupied area of ​​the global signal area and further reducing the area of ​​the memory chip.

Claims

1. A memory chip (10), wherein the center point of the active surface of the memory chip (10) and its adjacent area are defined as a global signal region (111), and the center point of the global signal region (111) coincides with the center point of the active surface; The global signal region (111) is penetrated by a plurality of conductive via groups (20), each conductive via group (20) includes a first redundant conductive via group (21) and a second redundant conductive via group (22), the first redundant conductive via group (21) includes a first conductive via (D0) and a fourth conductive via (D3), and the second redundant conductive via group (22) includes a second conductive via (D1) and a third conductive via (D2); the first redundant conductive via group (21) is used to transmit the same first global signal, and the second redundant conductive via group (22) is used to transmit the same second global signal; For each conductive via group (20), the first conductive via (D0) and the second conductive via (D1) are symmetric about a first axis, the third conductive via (D2) and the fourth conductive via (D3) are symmetric about the first axis, and the first conductive via (D0) and the fourth conductive via (D3) are symmetric about a second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip (10), and the second axis is parallel to the second side of the memory chip (10).

2. The memory chip (10) according to claim 1, wherein, The memory chip (10) further includes a plurality of input selection circuits (30), one side of each input selection circuit (30) is coupled to one of the conductive via groups (20), and the other side of each input selection circuit (30) is coupled to a first signal input node and a second signal input node inside the memory chip (10); The input selection circuit (30) is configured to electrically connect the coupled first redundant conductive via group (21) to the coupled first signal input node, and electrically connect the coupled second redundant conductive via group (22) to the coupled second signal input node; Or, electrically connect the coupled first redundant conductive via group (21) to the coupled second signal input node, and electrically connect the coupled second redundant conductive via group (22) to the coupled first signal input node.

3. The memory chip (10) according to claim 2, wherein, The input selection circuit (30) includes a first OR gate (31), a second OR gate (32), a first signal selection circuit (33), and a second signal selection circuit (34); The first OR gate (31) is coupled to the first conductive via (D0) and the fourth conductive via (D3), and is configured to perform an OR operation on the signals of the first conductive via (D0) and the fourth conductive via (D3), and output a first intermediate signal; The second OR gate (32) is coupled to the second conductive via (D1) and the third conductive via (D2), and is configured to perform an OR operation on the signals of the second conductive via (D1) and the third conductive via (D2), and output a second intermediate signal; The first signal selection circuit (33), its first end receives the first intermediate signal, and its second end receives the second intermediate signal; the first signal selection circuit (33) is configured to receive a position identification signal, and based on the position identification signal, transmit one of the first intermediate signal and the second intermediate signal to the first signal input node; The second signal selection circuit (34), its first end receives the second intermediate signal, and its second end receives the first intermediate signal; the second signal selection circuit (34) is configured to receive the position identification signal, and based on the position identification signal, transmit the other of the first intermediate signal and the second intermediate signal to the second signal input node.

4. The memory chip (10) according to any one of claims 1-3, wherein Each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal; Wherein, if the conductive via does not transmit a signal or is abnormally connected, the weak ground terminal controls the level state of the conductive via to be low level; if the conductive via is normally connected and transmits a signal, the level state of the conductive via depends on the transmitted signal.

5. The memory chip (10) according to claim 3, wherein, Every 4 memory chips (10) are stacked in the third direction to form 1 stacking unit. In each stacking unit, the low-order transmission regions of the memory chips (10) in the first type of position and the high-order transmission regions of the memory chips (10) in the second type of position are aligned in the third direction; wherein, each memory chip (10) is divided into a low-order transmission region and a high-order transmission region by the first axis, or each memory chip (10) is divided into a low-order transmission region and a high-order transmission region by the second axis; The memory chip (10) further includes: A decoding circuit, coupled to the first signal selection circuit (33) and the second signal selection circuit (34), is configured to receive a chip position identification code, and the chip position identification code includes a high-order position parameter and a low-order position parameter; if the chip position identification code indicates that the memory chip (10) is in the first type of position, output the position identification signal in the first state; if the chip position identification code indicates that the memory chip (10) is in the second type of position, output the position identification signal in the second state.

6. The memory chip (10) according to claim 5, wherein For each stacking unit, the first and fourth memory chips (10) are in the first type of position, and the second and third memory chips (10) are in the second type of position; The decoding circuit is a two-input exclusive OR gate; wherein, the first input terminal of the two-input exclusive OR gate is used to receive the low-order position parameter, the second input terminal of the two-input exclusive OR gate is used to receive the high-order position parameter, and the output terminal of the two-input exclusive OR gate is used to output the position identification signal.

7. The memory chip (10) according to claim 5, wherein, For each of the stacking units, the first and second memory chips (10) are in the first type of position, and the third and fourth memory chips (10) are in the second type of position; The decoding circuit determines the high-order position parameter as the position identification signal.

8. The memory chip (10) according to any one of claims 3, 5 - 7, wherein, The first signal selection circuit (33) includes a first driver (a1) and a first data selector (a2), and the second signal selection circuit (34) includes a second driver (a3) and a second data selector (a4); The first end of the first data selector (a2) receives the first intermediate signal, the second end of the first data selector (a2) receives the second intermediate signal, the third end of the first data selector (a2) is coupled to the first end of the first driver (a1), and the second end of the first driver (a1) is coupled to the first signal input node; The first end of the second data selector (a4) receives the second intermediate signal, the second end of the second data selector (a4) receives the first intermediate signal, the third end of the second data selector (a4) is coupled to the first end of the second driver (a3), and the second end of the second driver (a3) is coupled to the second signal input node.

9. The memory chip (10) according to any one of claims 1-8, wherein, The memory chip (10) further includes a plurality of output selection circuits (40), one side of each output selection circuit (40) is coupled to a first signal output node and a second signal output node inside the memory chip (10), and the other side of each output selection circuit (40) is coupled to one of the conductive via groups (20); The output selection circuit (40) is configured to electrically connect the coupled first signal output node to the coupled first redundant conductive via group (21), and electrically connect the coupled second signal output node to the coupled second redundant conductive via group (22); Or, electrically connect the coupled first signal output node to the coupled second redundant conductive via group (22), and electrically connect the coupled second signal output node to the coupled first redundant conductive via group (21).

10. The memory chip (10) according to claim 9, wherein, The output selection circuit (40) includes a third signal selection circuit (41) and a fourth signal selection circuit (42); The third signal selection circuit (41) has its first end coupled to the first signal output node, its second end coupled to the second signal output node, and its third end coupled to the first redundant conductive via group (21); the third signal selection circuit (41) is configured to receive a position identification signal and, based on the position identification signal, electrically connect one of the first signal output node and the second signal output node to the first redundant conductive via group (21). The fourth signal selection circuit (42) has its first end coupled to the second signal output node, its second end coupled to the first signal output node, and its third end coupled to the second redundant conductive via group (22); the fourth signal selection circuit (42) is configured to receive the position identification signal and, based on the position identification signal, electrically connect the other of the first signal output node and the second signal output node to the second redundant conductive via group (22).

11. The memory chip (10) according to claim 10, wherein the third signal selection circuit (41) includes a third driver (u1) and a third data selector (u2), and the fourth signal selection circuit (42) includes a fourth driver (u3) and a fourth data selector (u4); a first end of the third data selector (u2) is coupled to the first signal output node, a second end of the third data selector (u2) is coupled to the second signal output node, a third end of the third data selector (u2) is coupled to a first end of the third driver (u1), and a second end of the third driver (u1) is coupled to the first redundant conductive via group (21); a first end of the fourth data selector (u4) is coupled to the second signal output node, a second end of the fourth data selector (u4) is coupled to the first signal output node, a third end of the fourth data selector (u4) is coupled to a first end of the fourth driver (u3), and a second end of the fourth driver (u3) is coupled to the second redundant conductive via group (22).

12. The memory chip (10) according to any one of claims 1-11, wherein, The memory chip (10) further includes a plurality of bidirectional selection circuits (43), one side of each bidirectional selection circuit (43) is coupled to one of the conductive via groups (20), and the other side of each bidirectional selection circuit (43) is coupled to a first bidirectional signal node and a second bidirectional signal node inside the memory chip (10); the bidirectional selection circuit (43) is configured to electrically connect the coupled first redundant conductive via group (21) to the coupled first bidirectional signal node and electrically connect the coupled second redundant conductive via group (22) to the coupled second bidirectional signal node; or, electrically connect the coupled first redundant conductive via group (21) to the coupled second bidirectional signal node and electrically connect the coupled second redundant conductive via group (22) to the coupled first bidirectional signal node; The two-way selection circuit (43) is further configured to receive an input enable signal and an output enable signal; when the input enable signal is in an enabled state, drive and transmit the signal received from the first redundant conductive via group (21) to the two-way signal node to which it is coupled. And drive and transmit the signal received from the second redundant conductive via group (22) to the two-way signal node to which it is coupled; alternatively, when the output enable signal is in an enabled state, drive and transmit the signal received from the first two-way signal node to the redundant conductive via group to which it is coupled, and drive and transmit the signal received from the second two-way signal node to the redundant conductive via group to which it is coupled.

13. The memory chip (10) according to claim 12, wherein, The two-way selection circuit (43) further includes a first OR gate (31), a second OR gate (32), a first two-way selection circuit (44), and a second two-way selection circuit (45); The first OR gate (31) is coupled to the first conductive via (D0) and the fourth conductive via (D3), and is configured to perform an OR operation on the signal of the first conductive via (D0) and the signal of the fourth conductive via (D3), and output a first intermediate signal; The second OR gate (32) is coupled to the second conductive via (D1) and the third conductive via (D2), and is configured to perform an OR operation on the signal of the second conductive via (D1) and the signal of the third conductive via (D2), and output a second intermediate signal; The first two-way selection circuit (44) is configured to, when the input enable signal is in an enabled state, receive and based on the position identification signal, transmit one of the first intermediate signal and the second intermediate signal to the first two-way signal node; The second two-way selection circuit (45) is configured to, when the input enable signal is in an enabled state, receive and based on the position identification signal, transmit the other of the first intermediate signal and the second intermediate signal to the second two-way signal node; The first two-way selection circuit (44) is further configured to, when the output enable signal is in an enabled state, receive and based on the position identification signal, transmit the signal output from the first two-way signal node to one of the first redundant conductive via group (21) and the second redundant conductive via group (22); The second two-way selection circuit (45) is further configured to, when the output enable signal is in an enabled state, receive and based on the position identification signal, transmit the signal output from the second two-way signal node to the other of the first redundant conductive via group (21) and the second redundant conductive via group (22).

14. The memory chip (10) according to any one of claims 1-13, wherein The conductive vias are fabricated by any one or more of the via - first process, via - middle process, via - last process, and back side via - last process, and different conductive vias in the same memory chip (10) are electrically isolated from each other.

15. A logic chip (50), the center point and its adjacent area of the active surface of the logic chip (50) are defined as a global signal region (111), and the center point of the global signal region (111) coincides with the center point of the active surface; The global signal region (111) is penetrated by a plurality of conductive via groups (60). Each conductive via group (60) includes a first redundant conductive via group (61) and a second redundant conductive via group (62). The first redundant conductive via group (61) includes a first conductive via (D0) and a fourth conductive via (D3), and the second redundant conductive via group (62) includes a second conductive via (D1) and a third conductive via (D2). The first redundant conductive via group (61) is used to transmit the same first global signal, and the second redundant conductive via group (62) is used to transmit the same second global signal; For each conductive via group (60), the first conductive via (D0) and the second conductive via (D1) are symmetric about a first axis, the third conductive via (D2) and the fourth conductive via (D3) are symmetric about the first axis, and the first conductive via (D0) and the fourth conductive via (D3) are symmetric about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the logic chip (50), and the second axis is parallel to the second side of the logic chip (50).

16. The logic chip (50) according to claim 15, wherein, The logic chip (50) further includes a plurality of first output driving circuits (71) and a plurality of second output driving circuits (72); One first output driving circuit (71) is coupled to all the conductive vias in one first redundant conductive via group (61), and one second output driving circuit (72) is coupled to all the conductive vias in one second redundant conductive via group (62); The first output driving circuit (71) is configured to send the first global signal generated inside the logic chip (50) to all the conductive vias to which it is correspondingly coupled; The second output driving circuit (72) is configured to send the second global signal generated inside the logic chip (50) to all the conductive vias to which it is correspondingly coupled.

17. The logic chip (50) according to claim 15 or 16, wherein, The logic chip (50) further includes a plurality of input driving circuits (73), and each input driving circuit (73) is coupled to one conductive via group (60); The logic chip (50) is configured to send an enable control signal to a target memory chip and receive the first global signal and the second global signal sent by the target memory chip via the input driving circuit (73); Each of the input driving circuits (73) includes a first input driver (b2), a second input driver (b4), a third OR gate (b1), and a fourth OR gate (b3); a first input terminal of the third OR gate (b1) is connected to the first conductive via (D0), a second input terminal of the third OR gate (b1) is connected to the fourth conductive via (D3), and an output terminal of the third OR gate (b1) is coupled to the first input driver (b2); a first input terminal of the fourth OR gate (b3) is connected to the second conductive via (D1), a second input terminal of the fourth OR gate (b3) is connected to the third conductive via (D2), and an output terminal of the fourth OR gate (b3) is coupled to the second input driver (b4).

18. The logic chip (50) according to any one of claims 15-17, wherein Each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal; Wherein, if the conductive via does not transmit a signal or is abnormally connected, the weak ground terminal controls the level state of the conductive via to be low level; if the conductive via is normally connected and transmits a signal, the level state of the conductive via depends on the transmitted signal.

19. The logic chip (50) according to any one of claims 15-18, wherein The conductive via is fabricated by any one or more of the via-first process, via-middle process, via-last process, and back side via-last process, and different conductive vias in the same logic chip (50) are electrically isolated from each other.

20. A chip stack structure (80), the chip stack structure (80) includes the logic chip (50) according to any one of claims 15-19 and at least one stack unit, and the logic chip (50) and at least one stack unit are stacked in sequence along a third direction; each of the stack units includes a first memory chip (11), a second memory chip (12), a third memory chip (13), and a fourth memory chip (14) stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each memory chip; the first memory chip (11), the second memory chip (12), the third memory chip (13), and the fourth memory chip (14) are all memory chips (10) according to any one of claims 1-14; The first memory chip (11) and the second memory chip (12) are stacked face to face, the second memory chip (12) and the third memory chip (13) are stacked back to back, and the third memory chip (13) and the fourth memory chip (14) are stacked face to face; The first memory chip (11) in the first stacking unit and the logic chip (50) are stacked back to back, or the first memory chip (11) in the first stacking unit and the logic chip (50) are stacked back to back; n conductive via groups in the logic chip (50) correspond one by one to n conductive via groups in each of the first memory chips (11), n conductive via groups in each of the second memory chips (12), n conductive via groups in each of the third memory chips (13), and n conductive via groups in each of the fourth memory chips (14) and are aligned along the third direction, where n is a positive integer.

21. The chip stacking structure (80) according to claim 20, wherein, In the case where the logic chip (50) and the first memory chip (11) are stacked back to back, The fourth conductive via (D3) in the i-th first redundant conductive via group in the logic chip (50), the first conductive via (D0) in the i-th first redundant conductive via group in each of the first memory chips (11), the second conductive via (D1) in the i-th second redundant conductive via group in each of the second memory chips (12), the third conductive via (D2) in the i-th second redundant conductive via group in each of the third memory chips (13), and the fourth conductive via (D3) in the i-th first redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The third conductive via (D2) in the i-th second redundant conductive via group in the logic chip (50), the second conductive via (D1) in the i-th second redundant conductive via group in each of the first memory chips (11), the first conductive via (D0) in the i-th first redundant conductive via group in each of the second memory chips (12), the fourth conductive via (D3) in the i-th first redundant conductive via group in each of the third memory chips (13), and the third conductive via (D2) in the i-th second redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The second conductive vias (D1) in the i-th second redundant conductive via group in the logic chip (50), the third conductive vias (D2) in the i-th second redundant conductive via group in each of the first memory chips (11), the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the second memory chips (12), the first conductive vias (D0) in the i-th first redundant conductive via group in each of the third memory chips (13), and the second conductive vias (D1) in the i-th second redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The first conductive vias (D0) in the i-th first redundant conductive via group in the logic chip (50), the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the first memory chips (11), the third conductive vias (D2) in the i-th second redundant conductive via group in each of the second memory chips (12), the second conductive vias (D1) in the i-th second redundant conductive via group in each of the third memory chips (13), and the first conductive vias (D0) in the i-th first redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; wherein, i is a positive integer less than or equal to n.

22. The chip stack structure (80) according to claim 21, wherein, The high-order transmission regions of the first memory chip (11), the low-order transmission regions of the second memory chip (12), the low-order transmission regions of the third memory chip (13), and the high-order transmission regions of the fourth memory chip (14) are aligned; Or, The high-order transmission regions of the first memory chip (11), the high-order transmission regions of the second memory chip (12), the low-order transmission regions of the third memory chip (13), and the low-order transmission regions of the fourth memory chip (14) are aligned.

23. The chip stack structure (80) according to claim 20, wherein, When the logic chip (50) and the first memory chip (11) are stacked back-to-back, The second conductive vias (D1) in the i-th second redundant conductive via group in the logic chip (50), the first conductive vias (D0) in the i-th first redundant conductive via group in each of the first memory chips (11), the second conductive vias (D1) in the i-th second redundant conductive via group in each of the second memory chips (12), the third conductive vias (D2) in the i-th second redundant conductive via group in each of the third memory chips (13), and the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The first conductive vias (D0) in the i-th first redundant conductive via group in the logic chip (50), the second conductive vias (D1) in the i-th second redundant conductive via group in each of the first memory chips (11), the first conductive vias (D0) in the i-th first redundant conductive via group in each of the second memory chips (12), the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the third memory chips (13), and the third conductive vias (D2) in the i-th second redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The fourth conductive vias (D3) in the i-th first redundant conductive via group in the logic chip (50), the third conductive vias (D2) in the i-th second redundant conductive via group in each of the first memory chips (11), the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the second memory chips (12), the first conductive vias (D0) in the i-th first redundant conductive via group in each of the third memory chips (13), and the second conductive vias (D1) in the i-th second redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel; The third conductive vias (D2) in the i-th second redundant conductive via group in the logic chip (50), the fourth conductive vias (D3) in the i-th first redundant conductive via group in each of the first memory chips (11), the third conductive vias (D2) in the i-th second redundant conductive via group in each of the second memory chips (12), the second conductive vias (D1) in the i-th second redundant conductive via group in each of the third memory chips (13), and the first conductive vias (D0) in the i-th first redundant conductive via group in each of the fourth memory chips (14) are aligned along the third direction and form a signal transmission channel.

24. The chip stack structure (80) according to claim 23, wherein, The high-order transmission regions of the first memory chip (11), the low-order transmission regions of the second memory chip (12), the low-order transmission regions of the third memory chip (13), and the high-order transmission regions of the fourth memory chip (14) are aligned; Or, The high-order transmission regions of the first memory chip (11), the high-order transmission regions of the second memory chip (12), the low-order transmission regions of the third memory chip (13), and the low-order transmission regions of the fourth memory chip (14) are aligned.

25. The chip stack structure (80) according to any one of claims 20-24, wherein, For two face-to-face connected chips, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected through a hybrid bonding process; for two back-to-back connected chips or for two back-to-face connected chips, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected through a conductive bump bonding process; or, For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the positions where the conductive vias are aligned in the third direction in both are electrically connected through the hybrid bonding process; or, For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the positions where the conductive vias are aligned in the third direction in both are electrically connected through the conductive bump bonding process.

26. A memory (90), the memory (90) comprising a chip stack structure (80) as described in any one of claims 20-25.

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