Non-overlapping clock generator based on exclusive-or gate

Abstract

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

Description

TECHNICAL FIELD

[0001] The present invention relates to a non-overlapping clock generator, and more particularly to a non-overlapping clock generator based on an exclusive-NOR gate. BACKGROUND

[0002] Please refer to Figure 1A and Figure 1B , Figure 1A A prior art non-overlapping clock generator is shown. Figure 1B An operation waveform diagram corresponding to Figure 1A is shown. The non-overlapping clock generator 1001 comprises a cross-coupled NAND gate pair, which generates two non-overlapping clock signals, a non-inverted clock signal PH1 and an inverted clock signal PH2, from an input clock signal CLK.

[0003] Figure 1A , Figure 1B The prior art non-overlapping clock generator 1001 has the disadvantage that it requires a large circuit area and current consumption for low frequency clock applications, or when a long non-overlapping period is required between the non-inverted clock signal PH1 and the inverted clock signal PH2.

[0004] Compared to Figure 1A , Figure 1B The non-overlapping clock generator 1001 of the present invention can greatly reduce the required circuit area and current consumption, and is particularly suitable for low frequency or long non-overlapping period applications. SUMMARY

[0005] In one aspect, the present application provides a non-overlapping clock generator for generating a non-overlapping in-phase output clock signal and an in-phase output clock signal from an input clock signal, the non-overlapping clock generator comprising: a first exclusive-NOR gate and a second exclusive-NOR gate cross-coupled to each other, wherein a first input of the first exclusive-NOR gate is configured to receive an in-phase sub-signal of the input clock signal, a second input of the first exclusive-NOR gate is configured to receive a first control voltage, wherein a first input of the second exclusive-NOR gate is configured to receive an in-phase sub-signal of the input clock signal, a second input of the second exclusive-NOR gate is configured to receive the first control voltage; wherein the first exclusive-NOR gate is configured to generate the in-phase output clock signal at an in-phase output of the non-overlapping clock generator, the second exclusive-NOR gate is configured to generate the in-phase output clock signal at an in-phase output of the non-overlapping clock generator; a first load transistor having a first terminal coupled to the in-phase output of the non-overlapping clock generator, a control terminal of the first load transistor controlled by the in-phase output clock signal; and a second load transistor having a first terminal coupled to the in-phase output of the non-overlapping clock generator, a control terminal of the second load transistor controlled by the in-phase output clock signal; wherein each of the first exclusive-NOR gate and the second exclusive-NOR gate comprises at least one wired logic to implement exclusive-NOR logic, wherein the at least one wired logic is coupled to the first control voltage; wherein a non-overlapping period between the in-phase output clock signal and the in-phase output clock signal is determined according to the first control voltage.

[0006] In one embodiment, each of the first exclusive-NOR gate and the second exclusive-NOR gate comprises: a first transistor having a control terminal coupled to the first input, a first terminal coupled to an output of the exclusive-NOR gate; a second transistor having a control terminal coupled to the first input, a first terminal coupled to the output of the exclusive-NOR gate, a second terminal coupled to the second input; and a third transistor having a control terminal coupled to the second input, a first terminal coupled to the output of the exclusive-NOR gate, a second terminal coupled to the first input.

[0007] In one embodiment, the first control voltage is greater than a first predetermined value to avoid the first transistor and the second transistor in the exclusive-NOR gate being simultaneously non-conductive, wherein the first predetermined value is related to a threshold voltage of at least one transistor in the exclusive-NOR gate.

[0008] In one embodiment, the first control voltage is less than a difference between a power voltage of the non-overlapping clock generator and a threshold voltage of at least one transistor in the exclusive-NOR gate.

[0009] In one embodiment, the first control voltage is set as a power voltage of the non-overlapping clock generator.

[0010] In one embodiment, each of the first and second exclusive-NOR gates further comprises: a fourth transistor connected in series with the first transistor, a control terminal of the fourth transistor coupled to a third input terminal; wherein the third input terminal of the first exclusive-NOR gate and the third input terminal of the second exclusive-NOR gate are coupled to a second control voltage, wherein the non-overlapping period is further determined according to the second control voltage.

[0011] In one embodiment, the second control voltage is greater than a turn-on threshold voltage of at least one transistor in the exclusive-NOR gate, and less than or equal to a power voltage of the non-overlapping clock generator.

[0012] In one embodiment, the non-overlapping clock generator further comprises: a first delay circuit coupled between the inverting output terminal of the non-overlapping clock generator and the control terminal of the first load transistor, for delaying the inverting output clock signal by a first delay period to generate an inverting delay signal for controlling the first load transistor; and a second delay circuit coupled between the non-inverting output terminal of the non-overlapping clock generator and the control terminal of the second load transistor, for delaying the non-inverting output clock signal by a second delay period to generate a non-inverting delay signal for controlling the second load transistor; wherein the non-overlapping period is further determined according to the first delay period and / or the second delay period.

[0013] In one embodiment, each of the first and second delay circuits comprises: a plurality of delay units connected in series to generate a corresponding delay period; and a selection circuit for selecting a number of series connections of the plurality of delay units to adjust the corresponding delay period.

[0014] The objects, technical contents, characteristics and effects of the present application will be more clearly understood through the following detailed description of specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1A A prior art non-overlapping clock generator is shown.

[0016] Figure 1B Operation waveform diagrams corresponding to Figure 1A are shown.

[0017] Figure 2 A circuit schematic diagram of one embodiment of a non-overlapping clock generator according to the present application is shown.

[0018] Figure 3A circuit diagram showing one embodiment of the non-overlapping clock generator according to the present application.

[0019] Figure 4A A circuit diagram showing another embodiment of the non-overlapping clock generator according to the present application.

[0020] Figure 4B A circuit diagram showing one embodiment of the non-overlapping clock generator according to the present application.

[0021] Figure 5 A circuit diagram showing one embodiment of the non-overlapping clock generator according to the present application.

[0022] Figure 6 A circuit diagram showing one embodiment of the non-overlapping clock generator according to the present application.

[0023] Figure 7 A waveform diagram showing the operation of the non-overlapping clock generator according to the present application. DETAILED DESCRIPTION

[0024] The drawings in the present application are schematic and mainly intended to show the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, the signal waveforms and the frequencies are not drawn according to the scale.

[0025] Figure 2 A circuit diagram showing one embodiment of the non-overlapping clock generator 1002 according to the present application. As shown in the figure, the non-overlapping clock generator 1002 is used to generate in-phase output clock signal PH1 and anti-phase output clock signal PH2 which are non-overlapping with each other according to the input clock signal, in other words, the in-phase output clock signal PH1 and the anti-phase output clock signal PH2 have a non-overlapping period Tnov between them (please refer to Figure 7 ), in one embodiment, during the non-overlapping period Tnov, the in-phase output clock signal PH1 and the anti-phase output clock signal PH2 are both in the forbidden state (for example, in the low level state). The aforementioned input clock signal includes in-phase sub-signal CLK and anti-phase sub-signal CLK_B, the in-phase sub-signal CLK of the input clock signal is generated by an inverter to generate the anti-phase sub-signal CLK_B, and the in-phase sub-signal CLK and the anti-phase sub-signal CLK_B can be two clock signals which have some overlap on the rising edge and the falling edge.

[0026] The non-overlapping clock generator 1002 includes a first exclusive OR gate 100, a second exclusive OR gate 200, a first load transistor M1 and a second load transistor M2.

[0027] The first OR gate 100 and the second OR gate 200 are cross-coupled. Specifically, the first input terminal (A) of the first OR gate 100 receives the in-phase sub-signal CLK of the input clock signal, and the second input terminal (B) of the first OR gate 100 receives the first control voltage VCTRL1. On the other hand, the first input terminal (A) of the second OR gate 200 receives the inverted sub-signal CLK_B of the input clock signal, and the second input terminal (B) of the second OR gate 200 receives the first control voltage VCTRL1. Through the above coupling relationship, the first OR gate 100 generates an inverted output clock signal PH2 at the inverted output terminal ND2 of the non-overlapping clock generator 1002, while the second OR gate 200 generates a non-overlapping output clock signal PH1 at the non-overlapping output terminal ND1 of the non-overlapping clock generator 1002.

[0028] The first terminal (e.g., the drain) of the first load transistor M1 is coupled to the non-inverting output terminal ND1 of the non-overlapping clock generator 1002 (corresponding to the output terminal Y of the first mutex OR gate 100), and the control terminal (e.g., the gate) of the first load transistor M1 is controlled by the inverting output clock signal PH2. On the other hand, the first terminal of the second load transistor M2 is coupled to the inverting output terminal ND2 of the non-overlapping clock generator 1002 (corresponding to the output terminal Y of the second mutex OR gate 200), and the control terminal of the second load transistor M2 is controlled by the non-inverting output clock signal PH1.

[0029] In one embodiment, each of the first OR gate 100 and the second OR gate 200 includes at least one pass transistor logic to implement the OR logic, wherein the at least one pass transistor logic is coupled to a first control voltage VCTRL1, and detailed embodiments of the pass transistor logic will be described later.

[0030] In one embodiment, the non-overlapping time period Tnov between the in-phase output clock signal PH1 and the inverted output clock signal PH2 (e.g., Figure 7 (As shown) is determined based on the first control voltage VCTRL1.

[0031] In one embodiment, such as Figure 2 As shown, the non-overlapping clock generator 1002 also includes buffers 500 and 600, which buffer and adjust the waveforms of the in-phase output clock signal PH1 and the out-of-phase output clock signal PH2, respectively, to generate in-phase output clock signal PH1' and out-of-phase output clock signal PH2', with a non-overlapping time period Tnov' between the in-phase output clock signal PH1' and the out-of-phase output clock signal PH2'.

[0032] Figure 3Figure 6 shows a circuit diagram of a specific embodiment of an exclusive-NOR gate (exclusive-NOR gate 103) in a non-overlapping clock generator according to the present application. The exclusive-NOR gate 103 comprises a first transistor M10, a second transistor M20, and a third transistor M30.

[0033] The control terminal of the first transistor M10 is coupled to the first input (A) of the exclusive-NOR gate 103, the first terminal of the first transistor M10 is coupled to the output (Y) of the exclusive-NOR gate 103, and the second terminal of the first transistor M10 is coupled to a reference potential (e.g. ground potential). In particular, the first transistor M10 is responsible for pull-down of the exclusive-NOR gate 103.

[0034] The control terminal of the second transistor M20 is coupled to the first input (A) of the exclusive-NOR gate 103, the first terminal of the second transistor M20 is coupled to the output (Y) of the exclusive-NOR gate 103, and the second terminal of the second transistor M20 is coupled to the second input (B) of the exclusive-NOR gate 103. The control terminal of the third transistor M30 is coupled to the second input (B) of the exclusive-NOR gate 103, the first terminal of the third transistor M30 is coupled to the output (Y) of the exclusive-NOR gate 103, and the second terminal of the third transistor M30 is coupled to the first input (A) of the exclusive-NOR gate 103. In particular, the second transistor M20 and the third transistor M30 are coupled to the inputs from the source terminals, in other words, the exclusive-NOR gate 103 comprises pass-transistor logic configured by the second transistor M20 and the third transistor M30. It is worth noting that the exclusive-NOR gate can be implemented by only three transistors (M10, M20, M30) using the pass-transistor logic, and the non-overlapping clock generator 1002 can be configured based on the exclusive-NOR gate. Furthermore, since the exclusive-NOR gate uses the pass-transistor logic, the non-overlapping period Tnov can be adjusted by adjusting the voltage of at least one input (e.g. the first control voltage VCTRL1) of the exclusive-NOR gate.

[0035] In an embodiment, the first control voltage VCTRL1 is greater than a first preset value to avoid the first transistor M10 and the second transistor M20 in the exclusive-NOR gate 103 being simultaneously non-conductive. In an embodiment, the first preset value is related to the threshold voltage of the first transistor M10 and the second transistor M20.

[0036] Figure 4A Figure 7 shows a circuit diagram of another specific embodiment of an exclusive-NOR gate (exclusive-NOR gate 104) in a non-overlapping clock generator according to the present application. The exclusive-NOR gate 104 in this embodiment is similar to the exclusive-NOR gate 103 in Figure 6, and the differences between the exclusive-NOR gate 104 and the exclusive-NOR gate 103 will be described below. Figure 3The exclusive OR gate 104 is similar to the exclusive OR gate 103, except that the exclusive OR gate 104 further includes a fourth transistor M40 coupled in series with the first transistor M10. In the present embodiment, the fourth transistor M40 is coupled between the first transistor M10 and the ground potential. The control terminal of the fourth transistor M40 is coupled to the third input terminal C.

[0037] In one embodiment, as shown in FIG. 10A, the first transistor M10 and the fourth transistor M40 can be configured as, for example but not limited to, NMOS transistors, the bulk of which can be coupled to the substrate bias VSUB, while the second transistor M20 and the third transistor M30 can be configured as, for example but not limited to, PMOS transistors, the bulk of which can be coupled to the power supply voltage AVDD. Figure 4A

[0038] Figure 4B FIG. 10B shows a circuit schematic diagram of one embodiment of a non-overlapping clock generator (non-overlapping clock generator 1004) according to the present application. The non-overlapping clock generator 1004 in the present embodiment is similar to the non-overlapping clock generator 1002 of FIG. 10A, except that the non-overlapping clock generator 1004 includes a first exclusive OR gate 140 and a second exclusive OR gate 240 (corresponding to the exclusive OR gate 104 described above), the third input terminal C of the first exclusive OR gate 140 and the third input terminal C of the second exclusive OR gate 240 are coupled to each other at a second control voltage VCTRL2, wherein the non-overlapping period Tnov is further determined according to the second control voltage VCTRL2. In one embodiment, the second control voltage VCTRL2 is greater than the threshold voltage of the fourth transistor M40. Figure 2

[0039] Please refer to FIG. 10C and FIG. 10D for further understanding of the non-overlapping clock generators (1002 and 1004). Figure 2 Figure 4B The non-overlapping clock generators (1002 and 1004) further include a first delay circuit 300 and a second delay circuit 400. The first delay circuit 300 is coupled between the inverting output terminal ND2 of the non-overlapping clock generator 1002 and the control terminal of the first load transistor M1, to delay the inverting output clock signal PH2 by a first delay period, to generate an inverting delayed signal PH2D to control the first load transistor M1. The second delay circuit 400 is coupled between the non-inverting output terminal ND1 of the non-overlapping clock generator 1002 and the control terminal of the second load transistor M2, to delay the non-inverting output clock signal PH1 by a second delay period, to generate a non-inverting delayed signal PH1D to control the second load transistor M2. In the present embodiment, the non-overlapping periods Tnov, Tnov' are further determined according to the first delay period and / or the second delay period.

[0040] Figure 5 ​​​A circuit diagram showing a specific embodiment of a delay circuit in a non-overlapping clock generator according to the present application (the delay circuit 305, corresponding to the aforementioned first delay circuit 300 or the second delay circuit 400) In an embodiment, the delay circuit 305 comprises a plurality of delay units and a selection circuit 550, the plurality of delay units comprising, for example Figure 5 the delay units 511-512, 521-524, 531-536, 541-548 shown, wherein the delay units 511-512 are connected in series to form a delay branch 510 to generate a corresponding delay period, the delay units 521-524 are connected in series to form a delay branch 520 to generate a corresponding delay period, the delay units 531-536 are connected in series to form a delay branch 530 to generate a corresponding delay period, and the delay units 541-548 are connected in series to form a delay branch 540 to generate a corresponding delay period, wherein the corresponding delay period of each delay branch is substantially positively correlated to the number of delay units connected in series in each delay branch.

[0041] The selection circuit 550 is configured to select the number of delay units connected in series to adjust the corresponding delay period. In this embodiment, the selection circuit 550 generates adjustment control signals (e.g. Figure 5 EN1-EN4 shown) according to a delay control signal Sdly to enable or disable the corresponding delay branch and the delay units therein, in other words, to thereby select the corresponding delay branch to generate the corresponding delay period.

[0042] Figure 6 A circuit diagram showing an embodiment of a non-overlapping clock generator according to the present application (the non-overlapping clock generator 1006). The non-overlapping clock generator 1006 in this embodiment is similar to the non-overlapping clock generator 1002 of Figure 2 the difference being that in the non-overlapping clock generator 1006, the first control voltage VCTRL1 and the second control voltage VCTRL2 are set to the power supply voltage AVDD of the non-overlapping clock generator 1006. In an embodiment, the first control voltage VCTRL1 and the second control voltage VCTRL2 can also be set to the power supply voltage AVDD of the non-overlapping clock generator 1006 only one of them. It should be noted that in an embodiment, in the case where the first control voltage VCTRL1 or the second control voltage VCTRL2 is not set to the power supply voltage AVDD, the first control voltage VCTRL1 or the second control voltage VCTRL2 is respectively less than or equal to the power supply voltage AVDD.

[0043] As mentioned above, the non-overlapping period Tnov can be adjusted according to the aforementioned several manners, i.e. by the delay period of the delay circuit, the first control voltage VCTRL1 or the second control voltage VCTRL2. In one embodiment, the first control voltage VCTRL1 or the second control voltage VCTRL2 can be used for the coarse adjustment of the non-overlapping period Tnov, while the delay period of the delay circuit can be used for the fine adjustment of the non-overlapping period Tnov.

[0044] In a preferred embodiment, the first control voltage VCTRL1 and the second control voltage VCTRL2 can be adjusted according to the following ranges and combinations to achieve better adjustment effects.

[0045] In a preferred embodiment, the first control voltage VCTRL1 is between 0 and AVDD-Vth, where Vth is the aforementioned turn-on threshold voltage, and the second control voltage VCTRL2 can be between the turn-on threshold voltage Vth and the power supply voltage AVDD, or set to the power supply voltage AVDD. In another preferred embodiment, the first control voltage VCTRL1 is between the aforementioned first preset value and AVDD-Vth, and the second control voltage VCTRL2 can be between the turn-on threshold voltage Vth and the power supply voltage AVDD, or set to the power supply voltage AVDD.

[0046] In yet another preferred embodiment, the first control voltage VCTRL1 can be set to the power supply voltage AVDD, and the second control voltage VCTRL2 can be between the turn-on threshold voltage Vth and the power supply voltage AVDD.

[0047] Figure 7 The operation waveform diagrams corresponding to the non-overlapping clock generator of the present application are shown. As shown, the non-overlapping clock generator (such as 1002, 1004, 1006) generates in-phase output clock signals PH1, PH1' and anti-phase output clock signals PH2, PH2' with a non-overlapping period Tnov between each other according to the input clock signal (corresponding to CLK), and the non-overlapping period Tnov can be adjusted according to the aforementioned first control voltage VCTRL1, the second control voltage VCTRL2, the setting of the delay circuit, and the combination of the aforementioned adjustment manners.

[0048] The above has been described for the preferred embodiments of the present application, but the above description is only for the purpose of making those skilled in the art easily understand the content of the present application, and is not intended to limit the broadest scope of the present application. The various embodiments described are not limited to separate applications, but can also be combined, for example, two or more embodiments can be combined, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, various equivalent changes and various combinations can be conceived by those skilled in the art in the same spirit of the present application, for example, the present application refers to "processing or operating or generating an output result according to a certain signal", which is not limited to processing or operating or generating an output result according to the signal itself, but also includes, if necessary, voltage-current conversion, current-voltage conversion, and / or scaling conversion, etc., and then processing or operating or generating an output result according to the converted signal. Therefore, it can be seen that various equivalent changes and various combinations can be conceived by those skilled in the art in the same spirit of the present application, and the combination methods are various, which are not listed one by one here. Therefore, the scope of the present application should cover all the above and other equivalent changes.

Claims

1. A non-overlap clock generator for generating a non-overlapping in-phase output clock signal and a non-overlapping inverted output clock signal from an input clock signal, the non-overlap clock generator comprising: a first exclusive-NOR gate and a second exclusive-NOR gate, wherein a first input of the first exclusive-NOR gate is configured to receive an in-phase sub-signal of the input clock signal, a second input of the first exclusive-NOR gate is configured to receive a first control voltage, wherein a first input of the second exclusive-NOR gate is configured to receive an inverted sub-signal of the input clock signal, a second input of the second exclusive-NOR gate is configured to receive the first control voltage; wherein the first exclusive-NOR gate is configured to generate the inverted output clock signal at an inverted output of the non-overlap clock generator, and the second exclusive-NOR gate is configured to generate the in-phase output clock signal at an in-phase output of the non-overlap clock generator; a first load transistor having a first terminal coupled to the in-phase output of the non-overlap clock generator, and a control terminal controlled by the inverted output clock signal; and a second load transistor having a first terminal coupled to the inverted output of the non-overlap clock generator, and a control terminal controlled by the in-phase output clock signal; wherein each of the first and second exclusive-NOR gates comprises at least one pass transistor logic to implement exclusive-NOR logic, and the at least one pass transistor logic is coupled to the first control voltage; wherein a non-overlap period between the in-phase output clock signal and the inverted output clock signal is determined based on the first control voltage. Each of the first and second exclusive-NOR gates comprises: a first transistor having a control terminal coupled to the first input, and a first terminal coupled to an output of the exclusive-NOR gate; a second transistor having a control terminal coupled to the first input, a first terminal coupled to the output of the exclusive-NOR gate, and a second terminal coupled to the second input; and a third transistor having a control terminal coupled to the second input, a first terminal coupled to the output of the exclusive-NOR gate, and a second terminal coupled to the first input. The first control voltage is greater than a first predetermined value related to a turn-on threshold voltage of at least one transistor in the exclusive-NOR gate, to prevent the first and second transistors in the exclusive-NOR gate from being simultaneously non-conductive. The first control voltage is less than a difference between a supply voltage of the non-overlap clock generator and the turn-on threshold voltage of at least one transistor in the exclusive-NOR gate. The first control voltage is set to be the supply voltage of the non-overlap clock generator. Each of the first and second exclusive-NOR gates further comprises: a fourth transistor in series with the first transistor, the fourth transistor having a control terminal coupled to a third input; wherein the third input of the first exclusive-NOR gate and the third input of the second exclusive-NOR gate are coupled to each other to a second control voltage, and the non-overlap period is further determined based on the second control voltage. The second control voltage is greater than the turn-on threshold voltage of at least one transistor in the exclusive-NOR gate, and is less than or equal to a supply voltage of the non-overlap clock generator.

2. The non-overlapping clock generator of claim 1, wherein, The non-overlap clock generator further comprises: ​ ​ ​ 3. The non-overlapping clock generator of claim 2, wherein, ​ 4. The non-overlapping clock generator of claim 3, wherein, ​ 5. The non-overlapping clock generator of claim 2, wherein, ​ 6. The non-overlapping clock generator of claim 2, wherein, ​ ​ ​ 7. The non-overlapping clock generator of claim 6, wherein, ​ 8. The non-overlapping clock generator of claim 1, wherein, ​ a first delay circuit coupled between the inverting output terminal of the non-overlapping clock generator and the control terminal of the first load transistor for delaying the inverting output clock signal by a first delay period to generate an inverting delay signal for controlling the first load transistor; and a second delay circuit coupled between the non-inverting output terminal of the non-overlapping clock generator and the control terminal of the second load transistor for delaying the non-inverting output clock signal by a second delay period to generate a non-inverting delay signal for controlling the second load transistor; wherein the non-overlapping period is further determined according to the first delay period and / or the second delay period.

9. The non-overlapping clock generator of claim 8, wherein, Each delay circuit of the first delay circuit and the second delay circuit comprises: a plurality of delay units connected in series to generate a corresponding delay period; and a selection circuit for selecting a number of the series connection of the plurality of delay units to adjust the corresponding delay period.

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