Repeatable trigger type monostable circuit based on multipath signal control

By designing a repeatable triggerable monostable circuit based on multi-signal control, the problem of intermittent pulses in existing monostable circuits during continuous triggering applications is solved, achieving simplification of circuit structure and improvement of signal stability, making it suitable for various applications in digital systems.

CN122268328APending Publication Date: 2026-06-23SHANGHAI UNIV
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Patent Information

Application Number
CN202610176251.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-02-06
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

Existing monostable circuits cannot respond to new trigger signals before the output pulse has ended, resulting in intermittent output pulses that cannot meet the requirements of continuous triggering applications.

Method used

Design a repeatable triggerable monostable circuit based on multi-signal control, including a data selector, a tri-state gate buffer, NAND and OR NOT logic gates, and realize pulse delay and stable output through delay unit and input coupling bias unit, supporting the selection, isolation and logic processing of multiple signals.

Benefits of technology

It achieves a high degree of integration and modularity in circuit structure, flexible path control, simplifies pulse output, improves signal integrity and anti-interference ability, and is suitable for a variety of application scenarios.

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Abstract

The invention relates to a repeatable trigger type monostable circuit based on multipath signal control. The circuit comprises a data selector; the enabling end of each three-state gate buffer is connected with the output end of the data selector, and the input end of each three-state gate buffer is used for being connected with an external sensor; one input end of the NAND logic gate is connected with the output end of each three-state gate buffer through an input coupling bias unit; one input end of the NOR logic gate is connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate is grounded, and the output end of the NOR logic gate is connected with the other input end of the NAND logic gate; and the control unit is used for controlling the enabling state of each three-state gate buffer and continuously responding to the input trigger signal of the enabled three-state gate buffer within the delay time limited by the delay unit. Compared with the prior art, the method has the advantages of simplicity, capability of selectively acting based on different trigger sources and the like.
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