A multi-channel signal control based repeatable trigger monostable circuit

Abstract

The application relates to a repeatable trigger type monostable circuit based on multi-channel signal control, comprising a data selector, a plurality of tri-state gate buffers, the enable ends of the tri-state gate buffers being connected with the output ends of the data selector respectively, the input ends of the tri-state gate buffers being used for connecting external sensors, a NAND logic gate, one input end of the NAND logic gate being connected with the output ends of the tri-state gate buffers through an input coupling bias unit, an NOR logic gate, one input end of the NOR logic gate being connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate being grounded, and the output end of the NOR logic gate being connected with the other input end of the NAND logic gate, and the enable state of each tri-state gate buffer is controlled, and the input trigger signal of the tri-state gate buffer being enabled is continuously responded within the delay time defined by the delay unit. Compared with the prior art, the application has the advantages of simplicity, selectivity based on different trigger sources, and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and to a trigger circuit, and more particularly to a repeatable triggerable monostable circuit based on multi-signal control. Background Technology

[0002] In electronic systems, there is often a need for a functional circuit that outputs a fixed-time pulse after being triggered by an input signal. This circuit can be used for: delay and timing control; signal shaping (filtering out glitches and de-jitter); and providing a stable single pulse response, etc.

[0003] The initial monostable circuit that implemented this function could only trigger its function once after the input signal arrived, and then output a pulse of fixed width. It could only wait for the next trigger after the output pulse ended. Therefore, the drawback was that it required a continuous trigger signal, causing the output delayed pulse signal to be intermittent. For example, the existing patent CN106374886B discloses a non-repeatable CMOS integrated monostable circuit, which includes an input control circuit U1, a resistor-capacitor series network, a latch, a timing control network, a reference current source IREF, a Zener diode D1, and an output inverter U6. The resistor-capacitor series network includes a resistor R1 and a capacitor C1. The output terminal of the latch is connected to the input terminal of the output inverter U6. The latch includes a NOR gate U4, a capacitor C2, an inverter U5, and a level-shift circuit U3.

[0004] However, in some applications with continuous triggering (e.g., continuous detection signal, periodic triggering to maintain state), the function of the trigger circuit is required to be that if a new trigger signal arrives before the output pulse has ended, the duration of the output pulse will be "re-timing" and extended.

[0005] Existing monostable circuits cannot meet the above requirements. Therefore, it is necessary to design a repeatably triggered monostable circuit based on multi-signal control to solve the above technical problems. Summary of the Invention

[0006] The purpose of this invention is to overcome the defects of the prior art by providing a simple, selectively triggerable monostable circuit based on multiple signal control that can be triggered by different trigger sources, thus solving the problem of intermittent output pulses in non-repeatable triggerable circuits.

[0007] The objective of this invention can be achieved through the following technical solutions: A retrievable triggerable monostable circuit based on multi-signal control, comprising: Data selector; Multiple tri-state gate buffers are provided, with the enable terminal of each tri-state gate buffer connected to the output terminal of a data selector, the input terminal of each tri-state gate buffer used to connect to an external sensor, and the output terminal of each tri-state gate buffer connected to; A NAND logic gate, one input of which is connected to the output of each of the tri-state gate buffers via an input coupling bias unit; A NOR gate, one input of which is connected to the output of the NAND gate via a delay unit, and the other input is grounded; the output of the NOR gate is connected to the other input of the NAND gate. The enable state of each of the three-state gate buffers is controlled based on the input state of the data selector, and the input trigger signal of the enabled three-state gate buffer is continuously responded to within the delay time defined by the delay unit.

[0008] Furthermore, the data selector is a 2-4 line data selector.

[0009] Furthermore, the tri-state gate buffer is a CMOS tri-state gate buffer.

[0010] Furthermore, the sensor is one or more of the following: an infrared sensor, a sound sensor, a gyroscope, and a temperature sensor.

[0011] Furthermore, the input coupling bias unit includes a capacitor C1, a resistor R2, a resistor R3, and a power supply VDD. One end of the capacitor C1, resistor R2, and resistor R3 are connected to each other and connected to one input terminal of the NAND logic gate. The other end of the capacitor C1 is connected to the output terminal of each of the tri-state gate buffers. The other end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R3 is grounded.

[0012] Furthermore, the resistance value of resistor R2 is greater than the resistance value of resistor R3.

[0013] Furthermore, the delay unit includes a capacitor C2 and a resistor R1. The capacitor C2 is connected between the output terminal of the NAND gate and the input terminal of the OR NOT gate. One end of the resistor R1 is connected to the connection point between the capacitor C2 and the input terminal of the OR NOT gate, and the other end is grounded.

[0014] Furthermore, the delay time is adjusted based on the parameter configuration of the capacitor C2 and the resistor R1.

[0015] Furthermore, the operating states of this monostable circuit include a static state without external triggering and a metastable state with external triggering.

[0016] Furthermore, the output pulse of this monostable circuit is a negative pulse.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. High integration and modularity: This invention organically combines data selectors, tri-state gate buffers and logic gate circuits to realize the functions of gating, isolating, driving and logic processing of multiple signals in one, which significantly simplifies the circuit structure.

[0018] 2. Flexible path control: By changing the input to the data selector, different signal paths can be dynamically selected, realizing flexible configuration of signal paths.

[0019] 3. Simple pulse output circuit: Pulse output can be achieved through two logic gate circuits and two RC differentiating circuits, and the delay time of the pulse can be changed.

[0020] 4. Easy to reuse: The clever addition of a three-state gate buffer, combined with different sensors, allows for selective implementation of different trigger sources for the same circuit, enabling the same circuit to be used in multiple scenarios and making the circuit easier to reuse.

[0021] 5. Excellent signal integrity: The tri-state gate buffer provides good signal isolation and driving capability. Combined with the RC auxiliary network for signal conditioning, it effectively improves the anti-interference and stability of the system.

[0022] 6. Wide range of applications: By cleverly adding a tri-state gate circuit and cooperating with different sensors, this circuit can selectively realize different trigger sources for the same circuit. It can be widely used in scenarios such as bus driving, signal isolation, multi-channel signal distribution and custom logic function implementation in digital systems, and has high practical value.

[0023] The monostable circuit of this invention is suitable for applications requiring high-precision signal path management and multi-channel output. It has the advantages of compact structure, fast response speed and strong anti-interference, and can be widely used in digital system interfaces, bus drivers and signal conditioning. Attached Figure Description

[0024] Figure 1 This is a circuit schematic provided in an embodiment of the present invention; Figure 2 for Figure 1 An enlarged view of the right side of the middle section; Figure 3 This is a schematic diagram of a fixed-width pulse according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a continuous pulse signal according to an embodiment of the present invention; Description of main components in the diagram: U7A: 2-4 line data selector; U2, U4, U5, U6: Tri-state gate buffers; U1A: NAND gate; U3A: NOR gate; R1, R2, R3: Resistors; C1, C2: Capacitors. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0026] Figure 1 This is a structural diagram of a repeatable triggerable monostable circuit based on multi-signal control, as shown in some embodiments of this specification. It includes a data selector, multiple tri-state gate buffers, NAND gates, and OR gates. The enable terminal of each tri-state gate buffer is connected to the output terminal of the data selector. The input terminals of each tri-state gate buffer are used to connect to external sensors. The output terminals of each tri-state gate buffer are connected to...; one input terminal of the NAND gate is connected to the output terminal of each tri-state gate buffer through an input coupling bias unit; one input terminal of the OR gate is connected to the output terminal of the NAND gate through a delay unit, and the other input terminal is grounded; the output terminal of the OR gate is connected to the other input terminal of the NAND gate. In this monostable circuit, the components are connected through a specific topology to achieve the selection, isolation, logic processing, and output control of multiple signals. Specifically, the enable state of each tri-state gate buffer is controlled based on the input state of the data selector. Within the delay time defined by the delay unit, the input trigger signal of the enabled tri-state gate buffer is continuously responded to. Different trigger sources can be selectively implemented for the same circuit, and the same circuit can be used in multiple scenarios, solving the problem of intermittent output pulses in non-repeatable triggering circuits.

[0027] The data selector in this embodiment is a 2-4 line data selector U7A. It controls which sensor in the subsequent tri-state gate circuit is in the working state by using two input level signals, while turning off other sensors. This allows the circuit to be conveniently, quickly, and easily reused for different working scenarios.

[0028] In this embodiment, the tri-state gate buffers U2, U4, U5, and U6 are all CMOS tri-state gate buffers. In the static state (i.e., when the output state is stable at high or low and no state switching occurs), one of the P-channel and N-channel MOSFETs in the CMOS circuit is always completely cut off. There is no direct DC path from the power supply to ground, so the static current is extremely small (typically in the nanoamp level).

[0029] The types of sensors in this embodiment include infrared sensors, sound sensors, gyroscopes, and temperature sensors, which can be used in different working scenarios. For example, if a three-state door signal with an external infrared sensor is selected, this circuit can be used for security and sensing: opening and closing of automatic doors, sensing of faucets, and automatic control of light switches. If the delay time of the monostable circuit is set to 3 minutes, if someone triggers the infrared sensor within these 3 minutes, this circuit will continuously re-trigger the monostable circuit, so that the automatic door is always open, the faucet is always running water, or the automatically controlled light is always on.

[0030] In one specific embodiment, port 1 of the 2-4 line data selector U7A is set to a low level, at which point U7A is enabled. Ports 2 and 3 of U7A are also set to a low level; at this time, only 1Y0 of U7A's four output ports is low, while 1Y1, 1Y2, and 1Y3 are high. The tri-state gate U6 connected to 1Y0 is then enabled. The optional sensor 1 connected to the tri-state gate U6 is then available.

[0031] Specifically, such as Figure 2 As shown, the input coupling bias unit of this embodiment includes a capacitor C1, a resistor R2, a resistor R3, and a power supply VDD. One end of the capacitor C1, resistor R2, and resistor R3 are connected to each other to form an intermediate node A. This intermediate node A is connected to one input terminal of the NAND logic gate U1A. The other end of the capacitor C1 is connected to the output terminal of each tri-state gate buffer. The other end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R3 is grounded.

[0032] Furthermore, the resistance of resistor R2 is greater than that of resistor R3, so as to facilitate the change of the input level of the NOT logic gate U1A.

[0033] The main function of the input coupling bias unit is to transmit changes in external signals (AC signals or pulses) into the circuit and provide a stable bias to the input node. In one specific implementation, to achieve the circuit function, the power supply VDD can be set to 5V, C1 to 1μF, R2 to 10k ohms, and R3 to 1k ohms.

[0034] Specifically, the main function of the NAND gate U1A is to detect the high or low voltage of the input node and output a digital level (used as a "comparator"). In this embodiment, U1A can be set to 4011BD_5V, where a voltage greater than 3.5V is considered a high-level signal and a voltage lower than 1.5V is considered a low-level signal.

[0035] Specifically, the delay unit in this embodiment includes a capacitor C2 and a resistor R1. Capacitor C2 is connected between the output of the NAND gate U1A and the input of the OR gate U3A. One end of resistor R1 is connected to the junction of capacitor C2 and the input of the NAND gate, and the other end is grounded. Resistor R1 and capacitor C2 are crucial components determining the delay time of this retriggerable monostable circuit. Adjusting the values ​​of R1 and C2 changes the product of R1 and C2, thus altering the delay time of the pulse signal output by the circuit in a single trigger.

[0036] The delay unit and the OR / NOT logic gate U3A are combined to form a timing output module. Its main function is to generate a pulse delay or monostable output, and to provide feedback to maintain the logic state. In a specific implementation, C2 can be set to 10μF, R1 to 1k ohms, and U3A to 4001BD_5V. In U3A, an input voltage greater than 3.5V is considered a high-level signal, and a voltage less than 1.5V is considered a low-level signal.

[0037] The input of the above-mentioned overall circuit is a 2-4 line data selector, and the output of the overall circuit is the output of the NOR gate U3A. The sensor can be selected for different working scenarios through two input signals, and the output signal with different delay times can be changed, making it extremely versatile.

[0038] against Figure 2 The circuit structure shown operates in two main states: a static state without external triggering and a quasi-stable state with external triggering. These two states will be analyzed and explained below according to the settings described above.

[0039] Static state: First, analyze the input signal of U3A. Intermediate node B is one input terminal of U3A. In the static state, it is grounded through R1, which is a low-level input. The other input terminal of U3A is also grounded. Therefore, the output of this NOR gate of U3A is a high-level output. That is, in the static state, the Vo output of the entire circuit is also high.

[0040] When Vo is high, this high-level signal will be fed back to one input of U1A; while the power supply voltage VDD is 5V, the voltage of intermediate node A is 0.45V, which is low. For the two inputs of device U1A, one is a high-level input and the other is a low-level input. Therefore, for the NAND gate U1A, its output signal is a high-level output.

[0041] It should be noted that in the static state, one end of capacitor C2 is at a high level and the other end is at a low level. Therefore, in the static state, capacitor C2 carries positive and negative charges respectively, meaning that capacitor C2 is fully charged in the static state.

[0042] Quasi-stable state: When a rising edge (positive pulse) of an external signal arrives, it is coupled to the input node Vi through capacitor C1. The quasi-stable state process is as follows: (1) Transient response of capacitor C1: A positive change in the external signal causes the voltage at the left end of C1 to rise; the voltage across C1 cannot change instantaneously, therefore the voltage at the right end (input point of U1A) also rises instantaneously; this rise causes the input voltage to jump suddenly from 0.45V to several volts (depending on the amplitude of the external pulse). If the external signal is from 0V to 5V, the voltage at the right end of C1 may rise by about 3~4V due to the voltage divider effect.

[0043] (2) Determine changes in voltage level: When the voltage at input node Vi is greater than 3.5V, the input logic state of U1A becomes high.

[0044] If both inputs to U1A are high, then the output of U1A is low. Therefore, the output of U1A changes from high to low instantaneously. This is a negative transition.

[0045] (3) The negative transition is coupled to the U3A input via C2: The U1A output jumps from 5V to 0V, causing a momentary pull-down (generating a negative pulse) at the U3A input node through the 10µF capacitor C2. Because R1 is very small at 1kΩ, the capacitor discharges quickly, but the instantaneous current is sufficient to rapidly lower the U3A input voltage below 1.5V. The result is: a negative pulse appears at the U3A input, corresponding to a logic "low→high→low" change.

[0046] (4) U3A output response: Since U3A is a NOR gate, one of its inputs is fixed to ground (low level), and the other input is connected to intermediate node B. When the other input is also low, the output is high. When intermediate node B changes from low to high, the output goes low; when intermediate node B returns to low, the output goes high again. In other words, U3A outputs a brief pulse (the width of which is determined by R1 and C2). This pulse is the output signal of the monostable circuit.

[0047] (5) Feedback function: When the output of U3A goes low, the feedback line also temporarily changes the input condition of U1A; this prevents false triggering again during the return current phase of capacitor C1 (i.e., reverse coupling after the signal disappears); once C2 has discharged (the voltage returns to static), the output of U3A returns to high, and the circuit returns to its initial stable state.

[0048] (6) Calculation of time constant / pulse width Calculation of the critical time constant τ: τ = R1·C2 = 1k ohms × 10μF = 10ms; therefore, this circuit can generate a fixed-width pulse of 10ms. Figure 3 As shown.

[0049] If a new input trigger signal is received within the 10ms output pulse, then that 10ms period will be extended by the new trigger signal, generating a new 10ms pulse signal. (See...) Figure 4 As shown.

[0050] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A retrievable triggerable monostable circuit based on multi-signal control, characterized in that, include: Data selector; Multiple tri-state gate buffers are provided, with the enable terminal of each tri-state gate buffer connected to the output terminal of a data selector, the input terminal of each tri-state gate buffer used to connect to an external sensor, and the output terminal of each tri-state gate buffer connected to; A NAND logic gate, one input of which is connected to the output of each of the tri-state gate buffers via an input coupling bias unit; A NOR gate, one input of which is connected to the output of the NAND gate via a delay unit, and the other input is grounded; the output of the NOR gate is connected to the other input of the NAND gate. The enable state of each of the three-state gate buffers is controlled based on the input state of the data selector, and the input trigger signal of the enabled three-state gate buffer is continuously responded to within the delay time defined by the delay unit.

2. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The data selector is a 2-4 line data selector.

3. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The tri-state gate buffer is a CMOS tri-state gate buffer.

4. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The sensor is one or more of the following: infrared sensor, sound sensor, gyroscope, and temperature sensor.

5. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The input coupling bias unit includes a capacitor C1, a resistor R2, a resistor R3, and a power supply VDD. One end of the capacitor C1, resistor R2, and resistor R3 are connected to each other and connected to one input terminal of the NAND logic gate. The other end of the capacitor C1 is connected to the output terminal of each of the tri-state gate buffers. The other end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R3 is grounded.

6. The repeatably triggered monostable circuit based on multi-signal control according to claim 5, characterized in that, The resistance of resistor R2 is greater than that of resistor R3.

7. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The delay unit includes a capacitor C2 and a resistor R1. The capacitor C2 is connected between the output terminal of the NAND gate and the input terminal of the OR NOT gate. One end of the resistor R1 is connected to the connection point of the capacitor C2 and the input terminal of the OR NOT gate, and the other end is grounded.

8. The repeatable triggerable monostable circuit based on multi-signal control according to claim 7, characterized in that, The delay time is adjusted based on the parameter configuration of the capacitor C2 and the resistor R1.

9. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The monostable circuit operates in two states: a static state without external triggering and a metastable state with external triggering.

10. The repeatable triggerable monostable circuit based on multi-signal control according to claim 1, characterized in that, The output pulse of this monostable circuit is a negative pulse.

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