A circuit automatic pruning method based on global optimization algorithm

Abstract

The application provides an approximate circuit automatic pruning method based on a global optimization algorithm, which obtains an automatic pruning result of the circuit by decomposing an original circuit structure and with the help of a global optimization algorithm. The application changes the deleted minimum unit into a basic NAND logic, improving the precision of deletion. At the same time, the decomposed NAND logic is converted into a C language model, so that the whole iteration is separated from the synthesis tool and the simulation tool, and the simulation is replaced by the C language, saving a large amount of time. Finally, the global optimization algorithm is added, and the optimal solution of each iteration is no longer searched for in the selection of the deleted node, but the whole is considered, and a suitable node set is searched for deletion, so that the effect of the deleted node is optimal. In the approximate processing of 16 8-bit additions, the highest area reduction of 18.47% and the power consumption reduction of 38.91% are obtained under the mse limit of 100.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and relates to an automatic circuit pruning method based on a global optimization algorithm. Background Technology

[0002] As process linewidths shrink, chip integration density increases, and the performance per unit area of ​​integrated circuits continuously improves. Consequently, power consumption becomes an increasingly serious issue, drawing significant attention. Researchers are focusing on achieving superior design performance, making power consumption a crucial metric in chip design. In addressing power consumption, researchers are moving beyond simply reducing voltage (VOS) to explore other power reduction methods. Approximate computation has thus become a popular research topic. As the name suggests, approximate computation uses imprecise calculations to replace precise ones, thereby reducing circuit complexity, circuit area, and power consumption. In practical applications of integrated circuits, many fault-tolerant scenarios do not require perfectly accurate or high-precision calculations. For example, in many image processing applications, the inherent quantization error allows for a degree of fault tolerance, accepting errors in the output data. This makes approximate computation a highly efficient power optimization solution.

[0003] Most current approximate design methods rely on manual design based on the designer's experience. They estimate circuit errors using their expertise and then modify the circuit accordingly. Therefore, for different circuit designs, new approximation schemes need to be designed based on the circuit's characteristics. Because this method is highly dependent on experience, it typically requires a significant amount of time for trial and error to obtain an approximation scheme that achieves a good balance between performance and error. Furthermore, when using this method for approximate design of large-scale circuits, modifications to the circuit may introduce substantial errors, leading to situations where a suitable starting point cannot be found.

[0004] Therefore, automatic pruning has emerged as a new option, as it is not application-specific and can be applied to all combinational logic circuits. It primarily prunes based on the common characteristics of combinational logic, achieving an approximate design for the desired application through error metric constraints. Different designs only require iterative deletion, eliminating the need for additional design time. Automatic pruning evaluates the common characteristics of combinational logic, obtains sufficient information from the circuit, calculates the error function values ​​of nodes in the circuit based on this information, sorts them, finds the current optimal deletion node, and iterates through the nodes sequentially. However, this automatic pruning method searches for the current optimal deletion node in each iteration, eventually getting stuck in local optima and failing to find the global optimum. Furthermore, the smallest unit deleted is a composite gate in the synthesized circuit, resulting in insufficient deletion precision. Additionally, each iteration requires the use of synthesis and simulation tools, consuming significant time. Summary of the Invention

[0005] To address the aforementioned issues with automatic pruning, this invention modifies the smallest unit of deletion to basic AND, OR, and NOT logic, improving deletion accuracy. Simultaneously, the decomposed AND, OR, and NOT logic is converted into a C language model, allowing the overall iteration to operate independently of synthesis and simulation tools, using C language instead of simulation, saving significant time. Finally, a global optimization algorithm is incorporated, which, instead of searching for the optimal solution in each iteration, considers the overall process to find a suitable set of nodes for deletion, achieving the best overall deletion effect.

[0006] The technical solution adopted in this invention is as follows:

[0007] The present invention proposes an automatic pruning method for approximate circuits based on a global optimization algorithm, comprising the following steps:

[0008] Step 1: Based on the Verilog code of the target circuit, synthesize the circuit Verilog file to obtain the synthesized netlist file.

[0009] Step 2: Using the Verilog library, decompose the netlist file obtained in Step 1 using Python, converting all composite gates into simple 2-input logic gates, and recording the decomposition of composite gates.

[0010] Step 3: Convert the logic gates from Step 2 into graph connections, making the input and output connections of the logic gates into graph nodes, thus converting the circuit into a directed acyclic graph (DAG). Set the line weights for all connections. The weight of a graph node is the weight of all its next-level nodes multiplied by the weight of the corresponding connection. Therefore, by traversing backwards based on the output weights, the weights of the entire graph can be obtained.

[0011] Step 4: Based on the directed acyclic graph obtained in Step 3, traverse each node in reverse order, converting the unique associated logic gate of each node into its corresponding C language logic expression. Record the expressions in order and then reverse the order to obtain a new list. Execute the logic expressions according to the order of the new list, and you can simulate the original parallel execution logic combinational logic circuit using the sequential execution logic in C language. This achieves random stimulus simulation and records node information and error information.

[0012] Step 5: Using the global optimization algorithm, set the initial values ​​for the global optimization algorithm, including the number of individuals and the number of nodes to be deleted. Set the set of locally optimal nodes, the set of globally deleted nodes, and the set of previously deleted nodes to empty sets. Set the overall optimal direction and the overall incorrect direction to empty sets.

[0013] Step 6: Save the overall set of deleted nodes using the old set of deleted nodes.

[0014] Step 7: Based on the node information obtained from the C language simulation in Step 4, and combined with the node weight information obtained in Step 3, calculate two deletion function values ​​for each node. Then, based on the overall error direction of the nodes, reduce the priority of nodes in the error direction. Obtain the deletion node set according to the sorting order of the deletion function values. Then, map the deletion set to the C language simulation structure, and obtain the error information of this deletion node set through C language simulation. If the error is too large, iterate again to obtain the deletion node set. Repeat the iteration until the deletion node set for all individuals is obtained.

[0015] Step 8: Based on the set of deleted nodes obtained in Step 7, find the optimal set for the population using a global optimization algorithm. Update the set of deleted nodes for all individuals through random crossover.

[0016] Step 9: Map the updated set of deleted nodes to the C language simulation model, and obtain error and node information through simulation. If the error increases abnormally, discard the current iteration result of the current individual and use the old set of deleted nodes to cover the overall set of deleted nodes.

[0017] Step 10: Determine if the error of each individual exceeds the limit. If all exceed the limit, proceed to Step 11; otherwise, repeat Step 6 to start a new round of iteration.

[0018] Step 11: Reduce the number of nodes to be deleted according to the set determined in Step 9 to obtain the reduced circuit structure.

[0019] Step 12: Based on the composite gate combination information obtained in Step 2, extract the circuit logic to be removed in Step 11 from the instantiation names of the logic gates. If it can be found, add it to the synthesis input. After synthesis, an approximate circuit of the original composite gate can be obtained. Finally, combine all the approximate composite gates to complete the approximation of the overall circuit.

[0020] Specifically, the node weight in step three represents the degree of impact of deleting the node on the output result. The larger the weight, the greater the output error that may result after deletion.

[0021] Specifically, regarding step four, since the graph nodes are connections between logic gates, these connections simultaneously function as both outputs of the preceding logic gate and inputs of the following logic gate. Furthermore, according to Verilog syntax, to avoid multiple drivers, a connection used as an output can only be driven by one logic gate; therefore, a unique and relevant logical expression can be found.

[0022] Specifically, the global optimization algorithm in step five uses the idea of ​​particle swarm optimization. By setting the number of individuals and the number of nodes to be deleted in a single iteration, the optimization algorithm is iterated. Each iteration requires obtaining the deleted nodes multiple times based on the number of individuals, and the calculation of the deleted nodes for each individual is independent.

[0023] Specifically, each node in step seven has two possible deletions: it can be set to 0 or 1. Therefore, for each of the two deletion methods, each node has two corresponding deletion function values.

[0024] Specifically, the mapping principle in step seven is that if this node needs to be set to 0, then the original logical expression of this node is not retrieved, but instead it is directly set to 0. The mapping method for setting to 1 is the same.

[0025] Specifically, in step seven, due to errors in the overall deletion node selection model, such as weight estimation and error function value estimation, there is a possibility that the error may be too large after deleting a node. Therefore, step seven incorporates a method of iterative backtracking to obtain new deletion nodes.

[0026] Specifically, regarding step eight, based on the idea of ​​particle swarm optimization, each individual will gradually approach the optimal state of the group. This is reflected here by updating some globally optimal nodes and some locally optimal nodes for each deletion set.

[0027] Specifically, regarding step nine, when the iterative optimization algorithm randomly approaches the optimal direction for the population, it may approach the wrong direction, thus potentially causing an abnormally large increase in error. Step nine avoids this problem by discarding the results of this iteration of elimination.

[0028] The beneficial effects of this invention are as follows: This invention addresses three major problems in current automatic pruning approximate circuit deletion methods: insufficient deletion accuracy, long overall iteration time, and susceptibility to local optima in deletion node selection. It proposes improvements to address these issues. This invention decomposes the circuit into basic AND, OR, and NOT logic units, making the smallest deletion unit a basic AND, OR, and NOT logic unit, thus improving deletion accuracy. Simultaneously, this invention uses a C language model to simulate the original circuit logic, freeing the overall iteration process from synthesis and simulation tools. Using C language instead of simulation saves significant simulation time. Finally, this invention incorporates a global optimization algorithm in the node selection process. Instead of searching for the optimal solution in each iteration, it considers the overall picture and finds a suitable set of nodes for deletion, making the deleted nodes more globally optimal. Attached Figure Description

[0029] Figure 1 This is a flowchart of automatic pruning of approximate circuits based on a global optimization algorithm.

[0030] Figure 2 This is a diagram illustrating the transfer of weights.

[0031] Figure 3 This is a schematic diagram illustrating the decomposition principle of composite gates. Detailed Implementation

[0032] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0033] This invention provides an automatic pruning method for approximate circuits based on a global optimization algorithm. By decomposing the original circuit structure, the automatic pruning result of the circuit is obtained with the help of a global optimization algorithm.

[0034] like Figure 1 As shown, the flowchart of this invention is divided into three stages: information collection stage, optimization iteration stage, and combined pruning stage.

[0035] The information collection phase primarily involves decomposing the circuit and converting it into a Directed Acyclic Graph (DAG) to provide a foundation for subsequent phases. Simultaneously, it obtains node weight information, node activity information, and overall circuit error information. The specific implementation method in this embodiment is as follows: By synthesizing the component circuits, a synthesized netlist file is obtained. Then, using the Verilog library, the circuit in the netlist file is decomposed, converting all composite gates into simple 2-input logic gates and recording the decomposition of the composite gates. After decomposition, the logic gates are converted into graph connections, and the input / output connections of the logic gates are converted into graph nodes, thus converting it into a DAG. The line weights of all connections are set to 0.5, and the weight of a graph node is the weight of all next-level nodes multiplied by the weight of the corresponding connection. Figure 2This allows for reverse traversal based on the output weights to obtain the weights of the entire graph. Finally, the logic gates used as output nodes are converted into C language logic expressions. By executing these expressions sequentially, a combinational logic circuit capable of parallel execution can be simulated. Random stimuli are used during simulation, and the number of times each node is 0 or 1 is recorded to provide node information for subsequent reduction processes and obtain error information such as MSE (Mean Sequence Result) information.

[0036] The optimization iteration phase primarily performs iterative deletion. Utilizing a global optimization algorithm, it finds the globally optimal set of deleted nodes within the overall error constraint. The specific implementation method in this embodiment is as follows: The initial value of the global optimization algorithm is set, and the previous overall set of deleted nodes is saved. Combining node information and node weight information, two deletion function values ​​are calculated for each node. Then, based on the nodes in the overall error direction, the priority of nodes in that direction is reduced. The deleted node set is obtained according to the sorting order of the deletion function values. This deleted node set is then mapped to a C language simulation structure, and error information for this deleted node set is obtained through C language simulation. If the error is too large, the deleted node set is iterated again. This iteration is repeated until the deleted node sets for all individuals are obtained. Then, the group-optimal set is found using the global optimization algorithm. The deleted node sets for all individuals are updated through random crossover. The updated deleted node set is mapped to a C language simulation model, and the simulation obtains the error and node information. If the error increases abnormally, the iteration result for the current individual is discarded, and the old deleted node set is used to overwrite the overall deleted node set. If the error of all individuals exceeds the limit, proceed to the next stage; otherwise, start a new round of iterations.

[0037] The pruning phase primarily implements the node deletion set obtained in the iterative optimization phase. Based on this set, the decomposed circuit is pruned. Then, based on the composite gate information, the pruned circuit is recombined using synthesis tools. In this embodiment, the specific implementation method is as follows: Obtain the node deletion set obtained in the iterative optimization phase; set the corresponding nodes to 0 or 1 according to their function values; then search the entire circuit, deleting logic with constant outputs and simplifying logic with constant inputs, until all logic gates have no constant inputs or outputs. Next, based on the decomposition information of each composite gate, extract the instantiation name of the logic gate. If it can be found, add it to the synthesis input. After synthesis, an approximate circuit of the original composite gate is obtained. Finally, combine all the approximate composite gates to complete the approximation of the overall circuit.

[0038] The working principle of this embodiment is as follows:

[0039] By removing some logic from composite gates, an approximation of the composite gates is achieved. Then, by combining these approximated composite gates, an approximation of the overall circuit is obtained. Because the logic of the composite gates is reduced, their area and power consumption decrease to some extent, but some error is also introduced. Therefore, I use a global optimization algorithm to guide the planning of logic removal methods for all composite gates, removing as much of the original logic as possible within certain error constraints, thereby obtaining the globally optimal circuit result.

[0040] Since the entire circuit structure is decomposed into two-input logic gates, the benefit of deleting each node is approximately the same. Therefore, this invention uses error and the number of deleted points as metrics and employs the following steps for automatic pruning:

[0041] Step 1: Perform synthesis processing on the Verilog code that needs to be automatically deleted to obtain the synthesized netlist file.

[0042] Step 2: Using the Verilog file from the library, decompose the compound gates in the netlist file obtained in Step 1, converting all compound gates into simple 2-input logic gates (AND, OR, Buf, NOT), obtaining circuit logic A composed only of simple 2-input logic gates. Simultaneously, record the decomposition of the compound gates, such as... Figure 3 .

[0043] Step 3: Convert the logic gates in A into graph connections and set the line weights of the connections to 0.5. This converts the input and output connections of the logic gates into graph nodes, transforming the circuit in A into a DAG. The weight W of a graph node is the weight of all the next-level nodes multiplied by the weight of the corresponding connection. Therefore, by traversing backwards based on the output weights, the weights of the entire graph can be obtained.

[0044] Step 4: Based on the directed acyclic graph obtained in Step 3, traverse each node in reverse order. Use C language to convert the logic gates of the nodes as outputs into C language logic expressions. Record the logic expressions sequentially to obtain a list of expressions. Then, reverse this list to obtain a new list, Logic_list. The C language is executed according to the order of Logic_list, allowing the sequential execution of logic to simulate combinational logic circuits that execute logic in parallel. Random stimuli are used during simulation, and the number of times each node is 0 and 1 is recorded as T0 and T1 respectively. This provides node information for the subsequent reduction process and obtains error information such as MSE.

[0045] Step 5: Using a global optimization algorithm, set the number of individuals N and the number of nodes removed in a single operation M. Set three initial sets for the N individuals: RAW_DELi (locally optimal node set), DELi (overall removed nodes), and OLD_DELi (old node set) (i = 1 to N), all initially empty. Simultaneously, set MSEi, initially 0, to describe the error level of DELi. Finally, set GLOBAL_DEL as the optimal direction for the population and WRONG_DEL as the error direction.

[0046] Step 6: Make OLD_DELi = DELi and save the old set of deleted nodes.

[0047] Step 7: Then, based on the node information T0 and T1 obtained from the C language simulation in Step 4, and combined with the node weight information W obtained in Step 3, calculate the pruning function value for each node using the following formula.

[0048] TR0=W×T0 (1)

[0049] TR1=W×T1 (2)

[0050] func0 = TR0 × TR1 + TR0 2 +TR0×mse (3)

[0051] func1 = TR0 × TR1 + TR1 2 +TR1×mse (4)

[0052] Where TR0 represents the error that may be caused by setting a node to 1, TR1 represents the error that may be caused by setting a node to 0, mse represents the mse error value of the previous iteration, and func0 and func1 are the corresponding pruning function values.

[0053] Then, based on the nodes in WRONG_DEL, the corresponding deletion function value is doubled to reduce the priority of nodes in the wrong direction. The deletion function values ​​are sorted, and the top M nodes are taken as the deletion node set RAW_DELi. Following the sorting order of the deletion function values, from highest to lowest priority, each deletion set DELi+RAW_DELi is mapped to a C language simulation structure. Through C language simulation, the ΔMSEi of this deletion node set is obtained. If ΔMSEi is too large, DELi is returned to OLD_DELi, and individual i does not accept the result of this iteration. WRONG_DEL updates the nodes in RAW_DELi, and individual i repeats step seven to obtain a new deletion node set. The maximum number of repetitions is L (this variable can be set). If ΔMSEi is still too large after L repetitions, the result with the smallest ΔMSEi from the previous L repetitions is selected as RAW_DELi.

[0054] Step 8: Based on the ΔMSEi obtained in Step 7, assuming the lowest result is ΔMSEj, set RAW_DELj for individual j to GLOBAL_DEL, and use this set as the population optimum. For individual j, directly add M nodes from GLOBAL_DEL to DELj. For the remaining individuals, randomly select M / 2 nodes from GLOBAL_DEL and then randomly select M / 2 nodes from RAW_DELi for DELi.

[0055] Step 9: Map all updated DELi to the C language simulation model, and obtain MSEi and node information through simulation. If MSEi increases abnormally, individual i will discard this iteration and return DELi to OLD_DELi.

[0056] Step 10: Check if MSEi exceeds the error limit for all individuals. If all exceed the limit, proceed to Step 11; otherwise, repeat Step 6 to start a new round of iteration.

[0057] Step 11: Based on the DELi determined in Step 9, reduce the A obtained in Step 2 to obtain the reduced circuit structure RAW_DEL_Ai.

[0058] Step 12: Extract the logic of RAW_DEL_Ai obtained in Step 11 based on the composite gate combination structure obtained in Step 2. After extraction, synthesize using synthesis software to complete the transformation of logic into composite gates, record the generated composite gates, iteratively combine all composite gates, and after the combination is completed, obtain DEL_Ai, thus completing the automatic pruning of the circuit.

[0059] This embodiment is used for approximate processing of 16 8-bit additions, achieving a maximum area reduction of 18.47% and a power reduction of 38.91% under an MSE limit of 100.

[0060] Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the essence of this invention, and these modifications and combinations are still within the protection scope of this invention.

Claims

1. A method for automatic circuit pruning based on global optimization, characterized in that, Includes the following steps: Step 1: Obtain the Verilog code of the target circuit, and then synthesize it to obtain the synthesized netlist file; Step 2: By decomposing the composite gates in the netlist file, convert all composite gates into 2-input logic gates, thereby obtaining the circuit logic composed only of 2-input logic gates, and recording the decomposition data of the composite gates at the same time. Step 3: Convert the logic gates in the circuit logic into graph connections, and set the line weight of the connections to 0.5, so that the input and output connections of the logic gates become nodes in the graph, thus converting the circuit logic into a directed acyclic graph. The weight W of the graph node is the weight of all the next-level nodes multiplied by the line weight of the corresponding connection. By traversing backwards according to the output weight, the weight of the entire graph is obtained. The weight W is used to represent the degree of influence of deleting the node on the output result. The larger the weight, the greater the output error after deletion. Step 4: Based on the directed acyclic graph obtained in Step 3, traverse each node in reverse order. Use C language to convert the logic gates of the nodes as outputs into C language logic expressions. Record the logic expressions in order to obtain a list of expressions. Then, reverse this list to obtain a new list defined as Logic_list. According to the order of Logic_list, execute the logic expressions in the order of C language to simulate the combinational logic circuit that executes logic in parallel, thereby realizing random excitation simulation. Record the number of times all nodes are 0 and 1 during the simulation, which are defined as T0 and T1 respectively. Step 5: Using a global optimization algorithm, set the number of individuals N and the number of nodes removed in a single operation M. Set an initial set of N individuals, including the local optimum node set RAW_DELi, the overall deleted node set DELi, and the old node set OLD_DELi, i = 1 to N. All three sets are initially empty. At the same time, set MSEi to describe the error level of DELi, with an initial value of 0. Define GLOBAL_DEL as the population optimal direction and WRONG_DEL as the error direction. Step 6: Set OLD_DELi = DELi to save the old set of deleted nodes; Step 7: Based on the node information T0 and T1 obtained from the C language simulation in Step 4, and combined with the node weight information W obtained in Step 3, calculate the pruning function value for each node using the following formula: TR0 = W × T0 TR1 = W × T1 func0=TR0×TR1+TR0 2 +TR0×mse func1=TR0×TR1+TR1 2 +TR1×mse Where TR0 represents the error caused by setting the node to 1, TR1 represents the error caused by setting the node to 0, mse represents the mse error value of the previous iteration, and func0 and func1 are the corresponding pruning function values. Then, based on the nodes in WRONG_DEL, the deletion function value of the corresponding node is increased by 2 times, and the priority of the node in the wrong direction is reduced; Sort the deletion function values ​​and take the top M nodes as the deletion node set RAW_DELi; according to the sorting order of the deletion function values, from high to low priority, map each deletion set DELi+RAW_DELi to the C language simulation structure, and obtain the ΔMSEi of this deletion node set through C language simulation. If ΔMSEi is greater than the set threshold, DELi is returned to OLD_DELi, individual i does not accept the result of this iteration, WRONG_DEL updates the nodes in RAW_DELi, and individual i repeats step seven to obtain the set of deleted nodes again; Set the maximum number of repetitions to L. If ΔMSEi is still greater than the set threshold after L repetitions, select the result with the smallest ΔMSEi from the previous L repetitions as RAW_DELi. Step 8: Based on the ΔMSEi obtained in Step 7, define the lowest result as ΔMSEj, set the RAW_DELj of individual j to GLOBAL_DEL, and use this set as the population optimum; directly add M nodes from GLOBAL_DEL to the DELj of individual j, and randomly select M / 2 nodes from GLOBAL_DEL and then randomly select M / 2 nodes from RAW_DELi for the DELi of the other individuals; Step 9: Map all updated DELi to the C language simulation model, and obtain MSEi and node information through simulation. If MSEi increases abnormally, individual i will discard this iteration and return DELi to OLD_DELi. Step 10: Check if MSEi exceeds the error limit for all individuals. If all exceed the limit, proceed to Step 11; otherwise, repeat Step 6 to start a new round of iteration. Step 11: Based on the DELi determined in Step 9, reduce the circuit logic obtained in Step 2 to obtain the reduced circuit structure RAW_DEL_Ai; Step 12: Extract the logic of RAW_DEL_Ai obtained in Step 11 based on the composite gate combination structure obtained in Step 2. After extraction, synthesize the logic using synthesis software to complete the transformation into composite gates. Record the generated composite gates. Combine all composite gates in a loop. After the combination is completed, obtain DEL_Ai and complete the automatic pruning of the circuit.

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