NOR gate, NOR gate and maximum gate circuit realized based on three-valued memristor

Abstract

The invention discloses an OR gate, a NOR gate and a maximum gate circuit realized based on a three-valued memristor, and belongs to the technical field of digital logic circuit design, the three-valued memristor is used in a three-valued digital logic circuit, and the OR gate, the NOR gate and the maximum gate circuit are realized. The multi-valued digital logic circuit carries more information, the complexity degree between circuit connecting lines is lower, the area and power consumption of the logic circuit are effectively reduced, the operational capability of the circuit is higher, the structure is clear and simple, implementation is easy, and the multi-valued digital logic circuit can be used for application research in many fields such as multi-valued digital logic operation.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital logic circuit design, and particularly relates to an OR gate, a NOR gate, and a maximum gate circuit implemented based on a ternary memristor. Background Art

[0002] In the design of traditional digital logic circuits, most adopt binary logic. The corresponding circuits have advantages such as simple structure, easy signal generation, and strong anti-interference ability. However, in binary logic circuits, since only two signals, "0" and "1", are transmitted, the information carried by a single line is less, resulting in a significant increase in the wiring area in integrated circuits. Ternary logic, as a multi-valued logic, has advantages such as more information carried, lower complexity between circuit connections, and stronger computing ability of the circuit compared with traditional binary logic.

[0003] Basic logic gate circuits are the basic operation units of digital logic circuits. In logical operations, any complex logical operation can be achieved through the cascading method of basic logic gates. Most current integrated chips are of CMOS process. With the continuous improvement of the integration degree of digital systems, the size of CMOS devices is gradually approaching its physical limit. In 2008, Hewlett-Packard Laboratories successfully synthesized a physical device of a memristor, which attracted the attention of researchers. Memristors have characteristics such as nano-size, simple structure, low power consumption, and easy integration. In digital logic circuits, using memristors instead of CMOS can effectively reduce the area and power consumption of logic circuits. At the same time, introducing memristors into digital logic design is of great significance. With the characteristics of memristors, data storage and processing can be carried out in one device, reducing the time and power consumption of data transmission.

[0004] The three configurations R H 、R M and R L of the ternary memristor respectively correspond to the ternary logic "0", "1", and "2", providing conditions for constructing ternary logic circuits. However, due to strict technical conditions and high costs, it is still difficult for researchers to obtain practical memristors for actual research. At the same time, in existing research, the research on digital logic circuits based on ternary memristors is also very limited, facing a series of problems of integrated storage and computing. Therefore, by establishing a mathematical model, an LTSpice simulation model, and an effective circuit model of the ternary memristor and applying them to ternary digital logic circuits, it is of great significance for the research on the application of multi-valued memristors in digital logic circuits. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention proposes an OR gate, a NOR gate, and a maximum gate circuit implemented based on a ternary memristor.

[0006] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0007] An OR gate circuit implemented based on a ternary memristor, including three memristors, namely two input memristors M in1 、M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; two voltage-controlled switches S1 and S2.

[0008] In the OR gate circuit described above, the positive pole of the voltage source V is connected to the positive poles of the input memristors M in1 、M in2 and the positive pole of the voltage-controlled switch S1; the negative poles of the input memristors M in1 、M in2 , the negative pole of the voltage-controlled switch S1, and the positive pole of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative pole of the output memristor M out , the negative pole of the voltage-controlled switch S2, and the ground wire; the positive pole of V set0 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S1; the positive pole of V set2 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S2, and the negative poles of the voltage sources V, V set0 and V set2 are grounded.

[0009] A NOR gate circuit implemented based on a ternary memristor, including three memristors, namely two input memristors M in1 、M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; two voltage-controlled switches S1 and S2.

[0010] In the NOR gate circuit described above, the positive pole of the voltage source V is connected to the positive poles of the input memristors M in1 、M in2 and the positive pole of the voltage-controlled switch S1; the negative poles of the input memristors M in1 、M in2 , the negative pole of the voltage-controlled switch S1, and the positive pole of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative pole of the output memristor M out , the negative pole of the voltage-controlled switch S2, and the ground wire; the positive pole of V set2 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S1; Vset0 The positive electrode of out is connected to the output memristor M through the voltage-controlled switch S2 set0 ; the negative electrodes of the voltage sources V, V set2 and V

[0011] A maximum gate circuit implemented based on a ternary memristor includes four memristors, namely three input memristors M in1 , M in2 , M in3 and an output memristor M out ; the three voltage sources are V, V set0 and V set2 ; two voltage-controlled switches S1 and S2.

[0012] In the maximum gate circuit, the positive electrode of the voltage source V is connected to the positive electrodes of the input memristors M in1 , M in2 , M in3 and the positive electrode of the voltage-controlled switch S1; the negative electrodes of the input memristors M in1 , M in2 , M in3 , the negative electrode of the voltage-controlled switch S1, and the positive electrode of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrode of the output memristor M out , the negative electrode of the voltage-controlled switch S2, and the ground wire; the positive electrode of V set0 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S1; the positive electrode of V set2 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S2.

[0013] The input memristors of the OR gate circuit adopt a parallel structure, and the initial resistance state of the output memristor is R M . The working process of the OR gate circuit is carried out in two stages, driven by the excitation voltage source V. The first stage is the initial stage (0 - 10 ms), and V outputs a smaller initial voltage V Init to obtain the initial resistance state of the memristor; the second stage is the operation stage (10 - 20 ms), and V outputs a larger operation voltage V Run to complete the OR logic operation. V set0 and V set2 are set voltage sources used to perform the "0" and "2" setting operations on M out . The switches S1 and S2 are voltage-controlled switches, and the switches conduct only when the applied control voltage exceeds their threshold voltages. The working principle of the OR gate circuit is to utilize the parallel voltage division of the input memristors M in1 and M in2 ​ab Control the conduction of the voltage-controlled switch S1, and the divided voltage V of the auxiliary resistor R bc Control the conduction of the voltage-controlled switch S2, and further according to V ab and V bc Determine the threshold voltages V of S1 and S2 based on the divided voltages S1 and V S2 , thereby realizing the OR logic operation.

[0014] Based on the OR gate circuit, the NOR gate circuit changes the positions of the setting voltage sources V set0 and V set2 . Its excitation voltage source output, switch threshold voltage are the same as those of the OR gate circuit, so that the circuit realizes the NOR logic operation.

[0015] The maximum gate circuit is also based on the OR gate circuit. On the basis of the OR gate circuit, the two-input memristors of the OR gate circuit are changed to three-input memristors, and the OR operation is performed on the three values to finally obtain A + B + C. The working principle of the maximum gate circuit is to use the parallel voltage division V of the three input memristors in the circuit ab Control the conduction of the voltage-controlled switch S1, and the divided voltage V of R bc Control the conduction of the voltage-controlled switch S2, so as to determine the threshold voltages V of the voltage-controlled switches S1 and S2 according to V ab and V bc based on the divided voltages S1 and V S2 .

[0016] The present invention realizes ternary logic. Compared with the traditional binary logic, it has more information-carrying capacity, lower complexity between circuit connections, effectively reduces the area and power consumption of the logic circuit, has stronger computing power of the circuit, and has a clear and simple structure, is easy to implement and reduces costs. This circuit model can be used for application research in many fields such as multi-valued digital logic operations, which has important significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the present invention, the drawings required in the description of the prior art will be briefly introduced below.

[0018] Figure 1 is the OR gate circuit based on ternary memristors of the present invention;

[0019] Figure 2 is the NOR gate circuit based on ternary memristors of the present invention;

[0020] Figure 3 is the maximum gate circuit based on ternary memristors of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] To enable those skilled in the art to better understand the solution of the present invention, the model proposed by the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0022] As Figure 1 shown, an OR gate circuit implemented based on a ternary memristor includes three memristors, namely two input memristors M in1 , M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; two voltage-controlled switches S1 and S2.

[0023] In the ternary OR gate circuit, the positive pole of the voltage source V is connected to the positive poles of the input memristors M in1 , M in2 and the positive pole of the voltage-controlled switch S1; the negative poles of the input memristors M in1 , M in2 , the negative pole of the voltage-controlled switch S1, and the positive pole of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative pole of the output memristor M out , the negative pole of the voltage-controlled switch S2, and the ground wire; the positive pole of V set0 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S1; the positive pole of V set2 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S2, and the negative poles of the voltage sources V, V set0 and V set2 are grounded.

[0024] As Figure 2 shown, a NOR gate circuit implemented based on a ternary memristor includes three memristors, namely two input memristors M in1 , M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; two voltage-controlled switches S1 and S2.

[0025] In the ternary NOR gate circuit, the positive pole of the voltage source V is connected to the positive poles of the input memristors M in1 , M in2 and the positive pole of the voltage-controlled switch S1; the negative poles of the input memristors M in1 , M in2 , the negative pole of the voltage-controlled switch S1, and the positive pole of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the output memristor M outThe negative electrode of, the negative electrode of the voltage-controlled switch S2, and the ground wire are connected; V set2 The positive electrode of is connected to the output memristor M through the voltage-controlled switch S1 out Positive electrode; V set0 The positive electrode of is connected to the output memristor M through the voltage-controlled switch S2 out Positive electrode; voltage sources V, V set0 And V set2 The negative electrode of is grounded.

[0026] As Figure 3 Shown, a maximum gate circuit implemented based on a ternary memristor includes four memristors, namely three input memristors M in1 、M in2 、M in3 And an output memristor M out ; The three voltage sources are V, V set0 And V set2 ; Two voltage-controlled switches S1 and S2.

[0027] In the ternary maximum gate circuit, the positive electrode of the voltage source V is connected to the positive electrodes of the input memristors M in1 、M in2 、M in3 、the positive electrode of the voltage-controlled switch S1; the negative electrodes of the input memristors M in1 、M in2 、M in3 、the negative electrode of the voltage-controlled switch S1, the positive electrode of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrode of the output memristor M out 、the negative electrode of the voltage-controlled switch S2, and the ground wire; V set0 The positive electrode of is connected to the positive electrode of the output memristor M through the voltage-controlled switch S1 out Positive electrode; V set2 The positive electrode of is connected to the positive electrode of the output memristor M through the voltage-controlled switch S2 out Positive electrode.

[0028] The ternary memristor circuit adopted in the design of the present invention is a voltage-controlled threshold type ternary memristor, and its two threshold voltages are v th1 = 1V, v th2 = 1.2V, where R L 、R M And R H The three resistance states are 100Ω, 500Ω, 1500Ω. The resistance state of the memristor is analyzed below.

[0029] (1) When the initial state of the memristor is R H Or R MWhen the voltage \(v > 1.2V\) at this time, the state of the memristor switches to \(R\). L If the initial state of the memristor is \(R\). L When \(v\geq - 1V\), the memristor remains \(R\). L Therefore, when \(v > 1.2V\), the memristor can switch to the state of \(R\). L or remain in the state of \(R\). L

[0030] (2) When the initial state of the memristor is \(R\). H If the voltage \(1V < v < 1.2V\) at this time, the state of the memristor switches to \(R\). M When the initial state of the memristor is \(R\). L If the voltage \(-1.2V < v < 1V\) at this time, the state of the memristor switches to \(R\). M When the initial state of the memristor is \(R\). M When the voltage range is \(-1.2V\leq v\leq1.2V\), the memristor remains in the state of \(R\). M Therefore, when the voltage range is \([-1.2V, 1.2V]\), the memristor can switch to the state of \(R\). M or remain in the state of \(R\). M

[0031] (3) When the initial state of the memristor is \(R\). H or \(R\). M If the voltage \(v < - 1.2V\) at this time, the state of the memristor switches to \(R\). H When the initial state of the memristor is \(R\). H As long as \(v\leq1V\) is ensured, its resistance value remains \(R\). H unchanged. Therefore, when \(v < - 1.2V\), the memristor can switch to the state of \(R\). H or remain in the state of \(R\). H

[0032] The OR gate, NOR gate and maximum gate circuit models based on the ternary memristor designed by the present invention. The ternary logic described is a multi - valued logic with three different logic states, namely: "0", "1" and "2". The ternary combinational logic gate circuits designed by the present invention all use the resistance value of the memristor as the logic state variable. The states of the memristor corresponding to the three values are \(R\). H , \(R\). M and \(R\). L , where \(R\). H represents the logic "0"; \(R\). M represents the logic "1"; \(R\). L represents the logic "2". The circuit block diagram of its OR gate is as shown in Figure 1 , where \(M\). in1 and \(M\). in2 are two input memristors, \(M\). out ​​​For the output memristor, the initial state of the output memristor is set to R M . Among the three voltage sources, V is the excitation voltage source, V Set0 and V Set2 are the setting voltage sources. V Set0 and V Set2 are used to complete the "0" and "2" setting operations on M out . The voltage values output by V Set0 and V Set2 are determined according to the threshold voltages of the ternary memristor. From the above analysis of the memristor resistance state, the threshold voltages for the memristor to switch to logic "0" and "2" are -1.2V and 1.2V respectively. Therefore, V Set0 is set to -1.3V, and V Set2 is set to 1.4V. S1 and S2 are voltage-controlled switches in the circuit, and the on and off of the switches can be controlled by voltage division. When the voltage across the switch exceeds the set threshold, the switch will conduct; otherwise, the switch is in the off state. The auxiliary resistor R is added to the circuit to increase the voltage division situation of the circuit to assist the circuit in realizing the OR logic operation. The value of R should be taken between the high-resistance state and the low-resistance state of the ternary memristor, and the value of R is 600Ω.

[0033] The truth table of the ternary OR gate designed in the present invention is shown in Table 1 below, where X1 and X2 represent the input signals of the OR gate, and Y OR represents the output of the OR gate.

[0034] Table 1

[0035]

[0036] The working principle of the OR gate circuit is to use the parallel voltage division V in1 of the input memristors M in2 to control the conduction of S1, and the voltage division V ab of R to control the conduction of S2. Under different input voltage divisions, by setting the threshold voltages of the voltage-controlled switches S1 and S2, it is ensured that only one voltage-controlled switch conducts or neither conducts under each input, so as to realize the setting operation of a single voltage source on M bc . In the present invention, the threshold voltages V out of the switches S1 and S2 are set to 0.4V, and V S1 is set to 0.8V. S2

[0037] Both of the two circuits involved in the present invention are driven by an excitation voltage source V, and the operation can be divided into two stages. The first stage is the initial stage (0 - 10ms), and V outputs a relatively small initial voltage V Init ​, to obtain the initial resistance state of the memristor; the second stage is the operation stage (10 - 20 ms), and V outputs a relatively large operation voltage V Run to complete an OR logic operation. The OR gate circuit designed in this section takes V Init set to 0.5V, and V Run set to 1V.

[0038] The ternary OR gate circuit can be classified into the following 6 cases according to different combinations of the input memristors M in1 and M in2 :

[0039] (1) When the input logic is "00", the memristor M in1 = M in2 = 1500Ω, corresponding to the divided voltages V ab = 0.566V, V bc = 0.444V. V ab exceeds the threshold V S1 of S1, and V bc is lower than the threshold V S2 of S2. At this time, the switch S1 conducts, S2 disconnects, and the voltage source V Set0 will set the output memristor M out to 1500Ω, and the logic gate outputs the logic "0".

[0040] (2) When the input logic is "01", M in1 = 1500Ω, M in2 = 500Ω or M in1 = 500Ω, M in2 = 1500Ω. The divided voltages V ab and V bc are 0.385V and 0.615V respectively. The divided voltages V ab and V bc of the control switches S1 and S2 are lower than their threshold voltages V S1 and V S2 . Therefore, both switches S1 and S2 disconnect, and the output memristor M out maintains the initial state R M unchanged, and the logic gate outputs the logic "1".

[0041] (3) When the input logic is "02", M in1 = 1500Ω, M in2 = 100Ω or M in1 = 100Ω, M in2 = 1500Ω. The divided voltages V ab and V bc are 0.135V and 0.865V respectively. At this time, V ab is lower than the threshold V S1 of S1, Vbc A threshold value V higher than S2 S2 , corresponding to switch S1 being off and S2 being on, the voltage source V Set2 sets the output memristor M out to 100 Ω, and the logic gate outputs "2".

[0042] (4) When the input logic is "11", M in1 = M in2 = 500 Ω, the voltage divisions V ab and V bc are 0.294 V and 0.706 V respectively, and both voltage divisions are lower than V S1 and V S2 , so switches S1 and S2 are both off, and the output memristor maintains the initial state R M unchanged, and the logic gate outputs logic "1".

[0043] (5) When the input logic is "12", M in1 = 500 Ω, M in2 = 100 Ω or M in1 = 100 Ω, M in2 = 500 Ω. The voltage divisions V ab and V bc are 0.122 V and 0.878 V respectively, V ab is lower than the threshold value V of S1 S1 , V bc is higher than the threshold value V of S2 S2 , corresponding to switch S1 being off and S2 being on, V Set2 sets the output memristor M out to 100 Ω, and the logic gate outputs "2".

[0044] (6) When the input logic is "22", M in1 = M in2 = 100 Ω. The voltage divisions V ab and V bc are 0.077 V and 0.923 V respectively. V ab is lower than the threshold value V of S1 S1 , V bc is higher than the threshold value V of S2 S2 , corresponding to switch S1 being off and S2 being on, V Set2 sets the output memristor M out to 100 Ω, and the logic gate outputs "2".

[0045] The three - valued NOR gate circuit designed by the present invention, based on the three - valued OR gate circuit, can obtain a three - valued NOR gate without changing the overall circuit structure and wiring, but only by changing the position of the voltage source. The truth tables of the three - valued OR gate and the NOR gate are shown in Table 2 below, where X1, X2 represent the input signals of the circuit, YOR Represents the output of an OR gate, Y NOR Represents the output of a NOR gate.

[0046] Table 2

[0047]

[0048] It can be observed from the truth table that when the OR gate outputs "0", the NOR gate outputs "2"; when the OR gate outputs "1", the NOR gate outputs "1"; when the OR gate outputs "2", the NOR gate outputs "0". Therefore, only by swapping the positions of the voltage source V Set0 with the set logic "0" and the voltage source V Set2 with the set logic "2" in the OR gate circuit can the NOR gate circuit be obtained. The circuit structure of the three-valued NOR gate is as Figure 2 shown, and its excitation voltage source output, switch threshold voltage are the same as those of the OR gate. The V Init = 0.5V, V Run = 1V, V S1 = 0.4V, V S2 = 0.8V.

[0049] The truth table of the three-valued maximum gate circuit designed by the present invention is shown in Table 3 below, where X1, X2, and X3 represent the input signals of the maximum gate circuit, and Y MAX represents the output of the maximum gate circuit.

[0050] Table 3

[0051]

[0052] The initial voltage V Init and the operating voltage V Run of the three-valued maximum gate circuit are set to 0.5V and 1V respectively. The threshold voltages V S1 and V S2 of switches S1 and S2 are set to 0.4V and 0.8V respectively. According to different input combinations, the working conditions of the circuit are summarized as follows:

[0053] (1) When the input logic is "000", M in1 = 1500Ω, M in2 = 1500Ω, M in3 = 1500Ω, and the voltage divisions V ab and V bc are 0.455V and 0.545V respectively. V ab exceeds the threshold V S1 of S1, and V bc is lower than the threshold V S2 of S2. At this time, switch S1 is turned on and S2 is turned off. V Set0 will output the memristor Mout Set to 1500Ω, the logic gate outputs logic "0".

[0054] (2) When the input logic is "001", M in1 = 1500Ω, M in2 = 1500Ω, M in3 = 500Ω, the voltage division V ab and V bc are 0.333V and 0.667V respectively. V ab and V bc are lower than their threshold voltages V S1 and V S2 , at this time both switches S1 and S2 are off. The output memristor M out maintains the initial state R M unchanged, and the logic gate outputs logic "1".

[0055] (3) When the input logic is "002", M in1 = 1500Ω, M in2 = 1500Ω, M in3 = 100Ω, the voltage division V ab and V bc are 0.128V and 0.872V respectively. V ab is lower than the threshold V S1 of S1, V bc is higher than the threshold V S2 of S2, at this time switch S1 is off and S2 is on. V Set2 will set the output memristor M out to 100Ω, and the logic gate outputs logic "2".

[0056] (4) When the input logic is "011", M in1 = 1500Ω, M in2 = 500Ω, M in3 = 500Ω, the voltage division V ab and V bc are 0.263V and 0.737V respectively. V ab and V bc are lower than their threshold voltages V S1 and V S2 , at this time both switches S1 and S2 are off. The output memristor M out maintains the initial state R M unchanged, and the logic gate outputs logic "1".

[0057] (5) When the input logic is "012", M in1 = 1500Ω, M in2 = 500Ω, M in3 = 100Ω, the voltage division V aband V bc are 0.116 V and 0.884 V respectively. V ab is lower than the threshold voltage V of S1 S1 , V bc is higher than the threshold voltage V of S2 S2 , at this time, switch S1 is turned off and S2 is turned on. V Set2 Set the output memristor M out to 100 Ω, and the logic gate outputs logic "2".

[0058] (6) When the input logic is "022", M in1 = 1500 Ω, M in2 = 100 Ω, M in3 = 100 Ω, the voltage division V ab and V bc are 0.075 V and 0.925 V respectively. V ab is lower than the threshold voltage V of S1 S1 , V bc is higher than the threshold voltage V of S2 S2 , at this time, switch S1 is turned off and S2 is turned on. V Set2 Set the output memristor M out to 100 Ω, and the logic gate outputs logic "2".

[0059] (7) When the input logic is "111", M in1 = 500 Ω, M in2 = 500 Ω, M in3 = 500 Ω, the voltage division V ab and V bc are 0.127 V and 0.783 V respectively. V ab and V bc are lower than their threshold voltages V S1 and V S2 , at this time, both switches S1 and S2 are turned off. The output memristor M out maintains the initial state R M unchanged, and the logic gate outputs logic "1".

[0060] (8) When the input logic is "112", M in1 = 500 Ω, M in2 = 500 Ω, M in3 = 100 Ω, the voltage division V ab and V bc are 0.106 V and 0.894 V respectively. V ab is lower than the threshold voltage V of S1 S1 , V bc is higher than the threshold voltage V of S2 S2 , at this time, switch S1 is turned off and S2 is turned on. V Set2 Set the output memristor Mout Set to 100Ω, the logic gate outputs logic "2".

[0061] (9) When the input logic is "122", M in1 = 1500Ω, M in2 = 100Ω, M in3 = 100Ω, the voltage division V ab and V bc are 0.07V and 0.93V respectively. V ab is lower than the threshold V S1 of S1, V bc is higher than the threshold V S2 of S2. At this time, the switch S1 is off and S2 is on. V Set2 The output memristor M out will be set to 100Ω, and the logic gate outputs logic "2".

[0062] (10) When the input logic is "222", M in1 = 100Ω, M in2 = 100Ω, M in3 = 100Ω, the voltage division V ab and V bc are 0.053V and 0.947V respectively. V ab is lower than the threshold V S1 of S1, V bc is higher than the threshold V S2 of S2. At this time, the switch S1 is off and S2 is on. V Set2 The output memristor M out will be set to 100Ω, and the logic gate outputs logic "2".

[0063] Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. As long as it is within the scope of the present invention, changes and modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. An OR gate circuit implemented based on a ternary memristor, characterized in that It includes three memristors, three voltage sources, two voltage-controlled switches, and an auxiliary resistor R; The three memristors are two input memristors M in1 , M in2 and one output memristor M out ; the three voltage sources are V, V set0 and V set2 ; the two voltage-controlled switches are S1 and S2; The positive pole of the voltage source V is connected to the positive poles of the input memristors M in1 , M in2 ; the negative poles of the input memristors M in1 , M in2 , the negative pole of the voltage-controlled switch S1, and the positive pole of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative pole of the output memristor M out , the negative pole of the voltage-controlled switch S2, and the ground wire; the positive pole of V set0 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S1; the positive pole of V set2 is connected to the positive pole of the output memristor M out through the voltage-controlled switch S2; the negative poles of the voltage sources V, V set0 and V set2 are grounded.

2. The OR gate circuit implemented based on a ternary memristor according to claim 1, characterized in that, In the initial stage of the OR gate circuit, the voltage source V outputs an initial voltage V Init , and the initial resistance state of the memristor is obtained; in the operation stage, the voltage source V outputs an operating voltage V Run to complete the OR logic operation; V set0 and V set2 are set voltage sources to complete the "0" and "2" setting operations on the output memristor M out . For the voltage-controlled switches S1 and S2, they conduct only when the applied control voltage exceeds their threshold voltages.

3. The OR gate circuit implemented based on a ternary memristor according to claim 2, wherein Input memristor M in1 and M in2 parallel voltage division V ab control the conduction of voltage-controlled switch S1, and the voltage division V of auxiliary resistor R bc control the conduction of voltage-controlled switch S2. According to V ab and V bc determine the threshold voltages V of S1 and S2 based on the voltage division S1 and V S2 , and implement the OR logic operation.

4. A NOR gate circuit implemented based on a ternary memristor, characterized in that, It includes three memristors, three voltage sources, two voltage-controlled switches, and an auxiliary resistor R; The three memristors are respectively two input memristors M in1 and M in2 and one output memristor M out ; the three voltage sources are respectively V, V set0 and V set2 ; the two voltage-controlled switches are respectively S1 and S2; The positive electrode of the voltage source V is connected to the positive electrodes of the input memristors M in1 , M in2 ; the negative electrodes of the input memristors M in1 , M in2 , the negative electrode of the voltage-controlled switch S1, and the positive electrode of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrode of the output memristor M out , the negative electrode of the voltage-controlled switch S2, and the ground wire; the positive electrode of V set2 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S1; the positive electrode of V set0 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S2; the negative electrodes of the voltage sources V, V set0 and V set2 are grounded.

5. A maximum gate circuit implemented based on a ternary memristor, characterized in that, It includes four memristors, three voltage sources, two voltage-controlled switches, and an auxiliary resistor R; The four memristors are respectively three input memristors M in1 、M in2 、M in3 and an output memristor M out ; The three voltage sources are respectively V, V set0 and V set2 ; The two voltage-controlled switches are respectively S1 and S2; The positive electrode of the voltage source V is connected to the positive electrodes of the input memristors M in1 , M in2 , M in3 and the positive electrode of the voltage-controlled switch S1; the negative electrodes of the input memristors M in1 , M in2 , M in3 , the negative electrode of the voltage-controlled switch S1, and the positive electrode of the voltage-controlled switch S2 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrode of the output memristor M out , the negative electrode of the voltage-controlled switch S2, and the ground wire; the positive electrode of V set0 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S1; the positive electrode of V set2 is connected to the positive electrode of the output memristor M out through the voltage-controlled switch S2; the negative electrodes of the voltage sources V, V set0 and V set2 are grounded.

6. The maximum gate circuit implemented based on a ternary memristor according to claim 5, characterized in that The parallel voltage division V of the three input memristors ab controls the conduction of the voltage-controlled switch S1, and the voltage division V of the auxiliary resistor R bc controls the conduction of the voltage-controlled switch S2. According to V ab and V bc the threshold voltages V S1 and V S2 of the voltage-controlled switches S1 and S2 are determined

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