Circuit for adapting a logic control signal

Abstract

The invention relates to a circuit for adapting a logic control signal to the input of a GaN-technology power integrated circuit, comprising: - an input diode (D1) connected between the input (IN) receiving a logic control signal and a first internal node (11), and being blocked when the logic signal is at the high level, and conducting when the logic signal is at the low level; - a first branch (21) between a supply node (10) and a second internal node (12), formed by a first transistor (M1) the gate of which is connected to its drain, and the source of which is connected to the second internal node (12), and a resistor (R1) connected between the reference node (10) and the drain of the first transistor (M1); - a second branch (22) between the supply node (10) and the first internal node (11), formed by a second transistor (M2) the gate of which is connected to the drain of the first transistor (M1), the source of which is connected to the first internal node (11), and another resistor (R2) connected between the supply node (10) and the drain of the second transistor (M2); - a third branch (23) between the supply node (10) and ground (GND), formed by a third transistor (M3) the gate of which is connected to the drain of the second transistor (M2), the drain of which is connected to the output (OUT), and the source of which is connected to ground (GND). - the potential of the second internal node (12) setting the drain voltage of the first transistor (M1) to a value close to the threshold conduction voltage of the second transistor (M2); - the potential of the first internal node (11) making the second transistor (M2) conduct when the input diode (D1) is conducting; all of the transistors being GaN-based N-channel transistors.

Description

[0001] CONTROL LOGIC SIGNAL ADAPTATION CIRCUIT

[0002] Technical field

[0003] The invention relates to the field of transistor switching control circuits. The invention relates more particularly to a circuit for adapting a control signal intended to be integrated as an input stage of a power circuit based on transistors, for example GaN transistors.

[0004] State of the art

[0005] GaN-based transistors have the advantage of supporting high current densities and very high switching frequencies. They find applications in the field of power circuits such as electrical energy converters, inverters, etc.

[0006] The voltage to be applied to the gate of an N-channel GaN transistor must however be less than 7V, the recommended value being 6V, otherwise the component may be permanently damaged.

[0007] However, in the current market, the control circuits based on mature technology to drive GaN transistor converters are those designed for silicon (Si) or silicon carbide (SiC) based power components. These control circuits produce control voltages (P WM) which are either higher, generally 10V to 15V (analog control circuits), or lower, generally 3.3V or 5V (digital control circuits), than the control voltage of a GaN transistor. Therefore, if we want to have total compatibility, it is necessary to provide an input stage to adapt the different levels of the existing PWM control signal, to the level accepted by the GaN transistors of an integrated circuit.

[0008] A solution illustrated in Figure 1 can consist of using a resistor R and a limiter, for example in the form of several diodes D1-D2 in series, to adjust the level of a control input signal IN delivered by a commercial control circuit, to the gate voltage of a GaN transistor TR. The input signal IN is generally in the form of an on-off signal, of the pulse width modulation (PWM) type and of amplitude fixed by the control device. In this configuration, if the range of values ​​of the input voltage IN is large, it is necessary to choose a large resistor. A large value of the resistor combined with the parasitic capacitances of the limiter can induce delays in the rise times of the restored signal. This solution is therefore not suitable for the use of PWM signals with narrow pulse widths or for very high frequency applications.

[0009] For control circuits delivering voltages of the order of 3.3V, it is necessary to provide an intermediate input stage to raise this voltage to make it compatible for controlling GaN transistors.

[0010] In other words, using commercial driver circuits to drive GaN transistors requires knowing in advance the type of driver circuit to be used or that will be used, in order to plan and size the input stage accordingly.

[0011] Statement of the invention

[0012] The invention thus aims to propose an alternative solution which does not require prior knowledge of the type of control circuit or the characteristic of the signal delivered by the control circuit.

[0013] More specifically, the invention aims to propose an input stage for a transistor-based power integrated circuit, particularly suitable for the switching control of GaN transistors. The invention aims in particular to make the power integrated circuit integrating GaN-based transistors to be controlled compatible with logic control signals of any kind, and in particular with PWM type signals with amplitude and duty cycle included in a very wide range of values.

[0014] Thus, the invention proposes an input stage with an extended operating range, accepting for example voltages ranging from 3.3V to 15V. The subject of the invention is therefore a circuit for adapting a logic control signal to the input of an integrated circuit in GaN technology comprising at least one power transistor.

[0015] The adaptation circuit includes:

[0016] - a supply node to which a supply voltage is applied relative to a ground of the adaptation circuit;

[0017] - an input configured to receive said logic control signal;

[0018] - an output configured to deliver a logic output signal whose high and low levels are directly compatible with said integrated circuit;

[0019] - an input diode connected between the input and a first internal node;

[0020] - a first branch mounted between the power supply node and a second internal node, and comprising at least a first transistor whose gate is connected to its drain, and whose source is connected to the second internal node, and a resistor connected between the reference node and the drain of the first transistor;

[0021] - a second branch mounted between the power supply node and the first internal node, and comprising at least one second transistor whose gate is connected to the drain of the first transistor, whose source is connected to the first internal node via a dipole, and another resistor connected between the power supply node and the drain of the second transistor, said dipole being able to be a resistor or a short circuit;

[0022] - a third branch mounted between the power supply node and ground, and comprising at least a third transistor whose gate is connected to the drain of the second transistor, whose drain is connected to the output, and whose source is connected to ground.

[0023] According to the invention:

[0024] - the second internal node is at a constant potential fixing the drain voltage of the first transistor to a value close to the conduction threshold voltage of the second transistor;

[0025] - the first internal node is at a potential substantially equal to that of the second internal node when the input diode is blocked, and is at a potential inducing conduction of the second transistor when the input diode is on;

[0026] - the diode is blocked when the control logic signal is at a high level, and conductive when the control logic signal is at a low level.

[0027] The configuration of the invention makes it possible to generate at the output of the adaptation circuit, a high voltage or a voltage representative of a high logic level when the control logic signal applied at the input is at the low level, the output of the adaptation circuit generating by default a low voltage or a voltage representative of a low logic level. In other words, the circuit of the invention detects the low levels of the control logic signal, and more particularly the voltage values ​​included in the low range of values ​​representative of the low level of the control logic signal.

[0028] Thus, unlike the solutions of the prior art which simply adapt the voltages of the logic levels by lowering or increasing the voltage level, the invention proposes to detect the low logic levels of the logic signal applied at the input and to generate at the output a signal representative of the input logic signal on the basis of this detection of the low logic levels.

[0029] The solution of the invention takes advantage of the fact that the voltage representing a low logic level is always close to zero, while the high logic level can take different values ​​depending on the technology implemented.

[0030] By detecting only the low logic levels of the signal applied to the input of the adaptation circuit, the invention does away with the voltages representative of the high logic level, and therefore accepts logic control signals having any maximum amplitude within a very wide range of values. In practice, the upper limit of this range of maximum amplitude values ​​is fixed by the characteristics of the input diode. For example, the maximum amplitude of the logic signal at input IN can be between 3 V and 20 V, or even between 3 V and 200 V.

[0031] Furthermore, the high voltage at the output of the matching circuit is preferably of a value adapted to be directly compatible with a power integrated circuit in GaN technology, this power integrated circuit integrating for example a gate driver followed by a GaN-based power transistor. Thus, the signal generated at the output of the matching circuit of the invention is of the opposite form to the control logic signal, and of maximum amplitude adapted for the control of transistors, such as GaN-based transistors. For example, at the output of the matching circuit, the high voltage can be 6V or 12V, and the low voltage can be between 0 and 0.05V. According to the invention, all the transistors are GaN-based N-channel transistors. In practice, the transistors of the matching circuit are all of the enhancement type.

[0032] In practice, each of the first, second and third branches further comprises a resistor connected between the supply node and the respective drains of the first, second and third transistors.

[0033] The power node may be connected to a fixed voltage source and configured to generate said supply voltage.

[0034] The matching circuit may further include a first resistor mounted between the first internal node and ground, and configured to set the potential of the first internal node substantially equal to that of the second internal node when the input diode is off.

[0035] The second internal node may be connected to an internal voltage reference, said internal voltage reference comprising at least one diode connected between ground and the second internal node, this diode being able to be in the form of a transistor whose source is connected to its gate and to the second internal node.

[0036] For example, the internal voltage reference can be formed:

[0037] - a diode connected between ground and the second internal node;

[0038] - two diodes connected in series between ground and the second internal node, the diode connected to ground fixing the potential of the second internal node and the diode connected to the second internal node being configured to compensate for variations in the input diode;

[0039] - a diode and a resistor connected in series between the ground and the second internal node;

[0040] - a transistor and a resistor connected in series between ground and the second internal node.

[0041] The matching circuit may further comprise a fourth transistor whose gate is connected to its drain and to the drain of the second transistor and whose source is connected to the gate of the third transistor. In practice, since the drain voltage of the second transistor may not be exactly zero when the second transistor is conducting, this fourth transistor makes it possible to ensure the application of a zero voltage to the gate of the third transistor.

[0042] The matching circuit may further comprise a hysteresis circuit comprising at least a fifth transistor whose gate is connected to the gate of the third transistor, whose source is connected to ground and whose drain is connected to a terminal of the internal voltage source.

[0043] The hysteresis circuit may further include a resistor connected between the drain and source of the fifth transistor.

[0044] The input diode can be in the form of a transistor whose gate is connected to its source and the first internal node, and whose drain is connected to the input.

[0045] The invention also relates to a power integrated circuit based on GaN transistors comprising as input stage the adaptation circuit of the invention. The power circuit is thus compatible with different values ​​of high logic level voltages at the output of a commercial control circuit.

[0046] The matching circuit may also be coupled to an intermediate stage to adapt the signal generated at the output of the matching circuit of the invention, depending on the applications. For example, it may sometimes be necessary to switch or translate the high levels of the signal at the output of the matching circuit into low levels, and vice versa. This intermediate stage may be in the form of a resistor coupled to an N-channel transistor whose gate is connected to the output of the matching circuit.

[0047] Description of figures

[0048] The manner of carrying out the invention, as well as the advantages which result therefrom, will emerge clearly from the description of the embodiments which follow, supported by the appended figures in which:

[0049] [Eig 1] Figure 1 is a basic electrical diagram of a prior art matching circuit. [Fig 2] Figure 2 is a basic electrical diagram of a matching circuit according to one embodiment.

[0050] [Fig 3] Figure 3 is a graph of the evolution of the voltages at different nodes of the adaptation circuit of Figure 2 for an input logic signal varying between 0 and 5V, and an output signal varying between 0 and 6V.

[0051] [Fig 4] Figure 4 is a basic electrical diagram of an adaptation circuit according to another embodiment.

[0052] [Fig 5] Figure 5 is a graph of the evolution of voltages at different nodes of the adaptation circuit of Figure 4 for an input logic signal varying between 0 and 20V.

[0053] [Fig 6] Figure 6 is a basic electrical diagram of an adaptation circuit according to another embodiment integrating a hysteresis circuit.

[0054] [Fig 7] Figure 7 is a graph of the evolution of voltages at different nodes of the adaptation circuit of Figure 6 for an input logic signal varying between 0 and 20V.

[0055] [Fig 8] Figure 8 is a basic electrical diagram of an adaptation circuit according to another embodiment.

[0056] [Fig 9] Figure 9 is a graph of the evolution of voltages at different nodes of the adaptation circuit of Figure 8 for an input logic signal varying between 0 and 20V.

[0057] Detailed description of the embodiments

[0058] As explained above, the adaptation circuit of the invention detects a low logic level of a control logic signal. The logic signal alternates between a high logic level for which the voltage is in a high range of values ​​and a low logic level for which the voltage is in a low range of values.

[0059] A first embodiment is illustrated in Figure 2. The adaptation circuit comprises:

[0060] - an IN input configured to receive the control logic signal;

[0061] - an OUT output delivering a signal whose shape is representative of the transition from the high level to the low level of the control logic signal;

[0062] - a power supply node 10 to which a direct voltage Vdc is applied, this direct voltage Vdc can correspond to a desired high logic level at output OUT;

[0063] - an input diode DI mounted between the input IN and a first internal node 11;

[0064] - a resistor R6 connected between a ground GND of the adaptation circuit and the first internal node 11; and - an internal voltage source 3 formed by two diodes D3, D5 connected in series between the ground GND and a second internal node 12.

[0065] The adaptation circuit further comprises a first branch 21 mounted between the power supply node 10 and the second internal node 12. This first branch 21 comprises:

[0066] - a first transistor Ml whose gate is connected to its drain, and whose source is connected to a second internal node 12;

[0067] - a first resistor RI connected between the reference node 10 and the drain of the first transistor Ml; and

[0068] - a second resistor R3 connected between the second internal node 12 and the source of the first transistor Ml.

[0069] The adaptation circuit further comprises a second branch 22 mounted between the power supply node 10 and the first internal node 11. This second branch 22 comprises:

[0070] - a second transistor M2 whose gate is connected to the drain of the first transistor M1;

[0071] - a third resistor R2 connected between the power supply node 10 and the drain of the second transistor M2; and

[0072] - a fourth resistor R4 connected between the first internal node 11 and the source of the second transistor M2.

[0073] The adaptation circuit further comprises a third branch 23 mounted between the power supply node 10 and the ground GND. This third branch 23 comprises:

[0074] - a third transistor M3 whose gate is connected to the drain of the second transistor M2, whose drain is connected to the output OUT, and whose source is connected to ground GND; and

[0075] - a fifth resistor R5 connected between the drain of the third transistor M3 and the power supply node 10.

[0076] In practice, the DI input diode is configured to be on when the logic signal applied to the IN input is at the low logic level, and off when the logic signal applied to the IN input is at the high logic level.

[0077] Furthermore, the voltage Vref at the second reference node 12 is configured so that the drain-source voltage of the first transistor M1 is close to or substantially equal to the conduction switching threshold voltage of the second transistor M2. The resistor R6 is dimensioned to bring the potential Vint of the first internal node 11 to a voltage substantially equal to the voltage Vref of the second internal node 12, so that when the input diode DI is blocked, the voltage applied to the gate of the second transistor M2 makes it possible to pre-bias this second transistor M2. When the input diode DI is conducting, the potential Vint at the first internal node 11 decreases so that the gate-source voltage of the second transistor M2 triggers the switching of the second transistor M2 also inducing the switching of the third transistor M3.

[0078] The different voltage curves at different nodes of the matching circuit are shown schematically in Figure 3:

[0079] - the V(in) curve corresponds to the voltage applied to the IN input of the adaptation circuit;

[0080] - the curve V(vint) corresponds to the potential of the first internal node 11;

[0081] - the curve V(vref) corresponds to the potential of the second internal node 12;

[0082] - the curve V(vg3) corresponds to the gate voltage of the third transistor M3; and

[0083] - the V(out) curve corresponds to the output voltage OUT of the adaptation circuit.

[0084] Thus, in this configuration, when the logic signal applied to the input IN is at the low logic level, the output voltage OUT generates a high logic level of amplitude defined by the power supply node 10. In other words, the detection of a low logic level at the input IN results in the signal at the output OUT going to a high logic level.

[0085] Another embodiment of the matching circuit is illustrated in Figure 4. This matching circuit differs from the matching circuit of Figure 2 in that a pull-down circuit 4 configured to ensure that the gate voltage of the third transistor M3 is zero when the drain voltage of the second transistor M2 when this second transistor M2 conducts. This pull-down circuit 4 can be formed by a fourth transistor M4 whose gate is connected to its drain and to the drain of the second transistor M2 and whose source is connected to the gate of the third transistor M3.

[0086] Furthermore, in this embodiment, the internal voltage source 3 is formed by a diode D3 in series with the second resistor R3, the diode D3 being connected between the second internal node 12 and one terminal of the resistor R3, the other terminal of the resistor R3 being connected to the ground GND. Of course, this configuration is given as a non-limiting example since other variant embodiments of the internal voltage source 3 can be envisaged.

[0087] The operating principle remains similar to that of Figure 2. The different voltage curves at different nodes of the matching circuit are shown schematically in Figure 5:

[0088] - the V(in) curve corresponds to the voltage applied to the IN input of the adaptation circuit;

[0089] - the V(out) curve corresponds to the output voltage OUT of the adaptation circuit;

[0090] - the curve V(vg3) corresponds to the gate voltage of the third transistor M3;

[0091] - the curve V(vd2) corresponds to the drain voltage of the second transistor M2; and

[0092] - the curve V(vint) corresponds to the potential of the first internal node 11.

[0093] Another embodiment of the matching circuit is illustrated in Figure 6. This matching circuit differs from the matching circuit of Figure 4 in that it incorporates a hysteresis circuit 5 connected between ground GND and a terminal of the internal voltage source 3, and controlled by the source of the fourth transistor. The hysteresis circuit 5 comprises a fifth transistor M5 whose gate is connected to the gate of the third transistor M3, whose source is connected to ground GND and whose drain is connected to a terminal of the internal voltage source 3, and a resistor R8 connected between the drain and the gate of the fifth transistor M5.

[0094] The different voltage curves at different nodes of the matching circuit are shown schematically in Figure 7:

[0095] - the V(in) curve corresponds to the voltage applied to the IN input of the adaptation circuit;

[0096] - the V(out) curve corresponds to the output voltage OUT of the adaptation circuit;

[0097] - the curve V(vg3) corresponds to the gate voltage of the third transistor M3;

[0098] - the curve V(vd2) corresponds to the drain voltage of the second transistor M2; and

[0099] - the curve V(vint) corresponds to the potential of the first internal node 11.

[0100] Another embodiment of the matching circuit is illustrated in Figure 8. This matching circuit differs from the matching circuit of Figure 6 in that the input diode DI is formed by a transistor M8 configured to operate as a diode, and in that the diode D3 of the internal voltage source 3 is formed by a transistor M7 configured to operate as a diode. The different curves of the voltages at different nodes of the matching circuit are shown schematically in Figure 9:

[0101] - the V(in) curve corresponds to the voltage applied to the IN input of the adaptation circuit;

[0102] - the V(out) curve corresponds to the output voltage OUT of the adaptation circuit; - the V(vg3) curve corresponds to the gate voltage of the third transistor M3;

[0103] - the curve V(vd2) corresponds to the drain voltage of the second transistor M2; and

[0104] - the curve V(vint) corresponds to the potential of the first internal node 11.

[0105] The configurations described above make it possible to generate at the output OUT of the adaptation circuit a high voltage representative of a high logic level when the control logic signal applied at the input is at the low level, the output OUT of the adaptation circuit generating by default a low voltage or a voltage representative of a low logic level. In practice, the addition of a stage at output OUT in the form of a resistor coupled to an N-channel transistor whose gate is connected to the output OUT of the adaptation circuit makes it possible to find an output signal similar to the input signal but with an amplitude adapted to the power circuit to be controlled.

Claims

CLAIMS 1. Circuit for adapting a logic control signal to the input of a power integrated circuit in GaN technology comprising at least one power transistor, the adaptation circuit comprising: - a power supply node (10) to which a power supply voltage (Vdc) is applied relative to a ground of the adaptation circuit; - an input (IN) configured to receive said logic control signal; - an output (OUT) configured to deliver a logic output signal whose high and low levels are directly compatible with said integrated circuit; - an input diode (Dl) mounted between the input (IN) and a first internal node (11); - a first branch (21) mounted between the supply node (10) and a second internal node (12), and comprising at least a first transistor (Ml) whose gate is connected to its drain, and whose source is connected to the second internal node (12), and a resistor (RI) connected between the reference node (10) and the drain of the first transistor (Ml); - a second branch (22) mounted between the power supply node (10) and the first internal node (11), and comprising at least one second transistor (M2) whose gate is connected to the drain of the first transistor (M1), whose source is connected to the first internal node (11) via a dipole, and another resistor (R2) connected between the power supply node (10) and the drain of the second transistor (M2); - a third branch (23) mounted between the power supply node (10) and ground (GND), and comprising at least one third transistor (M3) whose gate is connected to the drain of the second transistor (M2), whose drain is connected to the output (OUT), and whose source is connected to ground (GND); - the second internal node (12) is at a constant potential (Vref) fixing the drain voltage of the first transistor (Ml) to a value close to the conduction threshold voltage of the second transistor (M2); - the first internal node (11) is at a potential (Vint) substantially equal to that of the second internal node (12) when the input diode (Dl) is blocked, and is at a potential inducing the conduction of the second transistor (M2) when the input diode (Dl) is conducting; - the diode (Dl) is blocked when the control logic signal is at the high level, and conducting when the control logic signal is at the low level; all the transistors being GaN-based N-channel transistors.

2. Adaptation circuit according to claim 1, characterized in that it further comprises a first resistor (R6) mounted between the first internal node (11) and the ground (GND), and configured to set the potential (Vint) of the first internal node (11) substantially equal to that of the second internal node (12) when the input diode (Dl) is blocked.

3. Matching circuit according to claim 1 or 2, characterized in that the second internal node (12) can be connected to an internal voltage source (3), said internal voltage source (3) comprising at least one diode (D3) mounted between ground (GND) and the second internal node (12), this diode being able to be in the form of a transistor (M7) whose source is connected to its gate and to the second internal node (12).

4. Adaptation circuit according to one of claims 1 to 3, characterized in that it further comprises a fourth transistor (M4) whose gate is connected to its drain and to the drain of the second transistor (M2), and whose source is connected to the gate of the third transistor (M3).

5. Adaptation circuit according to one of claims 1 to 4, characterized in that it further comprises a hysteresis circuit (5) comprising at least a fifth transistor (M5) whose gate is connected to the gate of the third transistor (M3), whose source is connected to ground (GND) and whose drain is connected to a terminal of the internal voltage source (3).

6. Matching circuit according to claim 5, characterized in that the hysteresis circuit (5) can further comprise a resistor (R8) connected between the drain and the gate of the fifth transistor (M5).

7. Matching circuit according to one of claims 1 to 6, characterized in that the input diode (Dl) can be in the form of a transistor (M8) whose gate is connected to its source and to the first internal node (Vint), and whose drain is connected to the input (IN).

8. Power integrated circuit based on GaN transistors comprising as input stage the adaptation circuit according to one of claims 1 to 7.

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