Gate drive device

Abstract

A gate drive device for driving semiconductor elements of upper and lower arms comprises an impedance adjustment unit for individually controlling the impedances of the gate discharge paths of the upper and lower arms. The impedance adjustment unit sets, during ON-switching period of one arm of the upper and lower arms, a first impedance of the gate discharge path of the other arm higher than a second impedance of the gate discharge path of the other arm during OFF-switching period of the one arm.

Description

Gate Driver

[0001] The present invention relates to a gate driver.

[0002] The three-phase switching arms of a power conversion device have upper and lower arm switching elements for each phase. However, when one of the upper and lower arm switching elements switches, crosstalk can cause the switching element of the other arm to self-turn on. In this case, the upper and lower arms are simultaneously conducting, causing a short-circuit current to flow between the semiconductor elements of the upper and lower arms. This short-circuit current can increase losses in the switching elements.

[0003] For this reason, Patent Document 1 proposes a method for suppressing self-turn-on. The technology described in Patent Document 1 provides an impedance adjustment circuit in the gate driver, which reduces the impedance between the gate and source during turn-on and turn-off. This suppresses self-turn-on of the switching element of one arm and negative surges in the gate voltage when the switching element of the other arm is turned on and off.

[0004] Japanese Patent Application Publication No. 2021-151039

[0005] However, as mentioned above, reducing the impedance of the arm itself when the arm is turned on increases the linking surge voltage (recovery surge) that occurs when the freewheeling diode of the switching element of the arm transitions from a conducting state to a blocking state. To suppress this recovery surge, it is necessary to slow down the switching speed, which increases switching loss.

[0006] A gate drive device according to one aspect of the present invention is a gate drive device that drives semiconductor elements of upper and lower arms, and includes an impedance adjustment unit that individually controls the impedances of the gate discharge paths of the upper and lower arms, and the impedance adjustment unit sets a first impedance of the gate discharge path of one of the upper and lower arms during an ON-switching period of the other arm to be higher than a second impedance of the gate discharge path of the one arm during an OFF-switching period of the other arm.

[0007] According to the present invention, when the paired arm is turned on, the turn-on speed can be improved while suppressing the recovery surge in the arm itself, and the total switching loss on the paired arm and the arm itself can be reduced.

[0008] 1 is a diagram illustrating an example of a power conversion device; 2 is a diagram illustrating a conventional configuration of a single-phase circuit; 3 is a diagram illustrating a comparative example; 4 is a diagram illustrating a first embodiment of a gate drive device; 5 is a diagram illustrating an impedance control operation, showing waveforms (A) to (D); 6 is a diagram illustrating a first modified example of the first embodiment; 7 is a diagram illustrating a second modified example of the first embodiment; 8 is a diagram illustrating a first modified example of an impedance adjustment circuit; 9 is a diagram illustrating a second modified example of an impedance adjustment circuit; 10 is a diagram illustrating a third modified example of an impedance adjustment circuit; 11 is a diagram illustrating a fourth modified example of an impedance adjustment circuit; 12 is a diagram illustrating a fifth modified example of an impedance adjustment circuit; 13 is a diagram illustrating a second embodiment of a gate drive device; 14 is a diagram illustrating a third embodiment of a gate drive device; 15 is a diagram illustrating a fourth embodiment of a gate drive device; and 16 is a diagram illustrating a fifth embodiment of a gate drive device.

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows an example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0010] First Embodiment Fig. 1 is a diagram illustrating an example of a power conversion device. In the first embodiment, a power conversion device 20 mounted on a vehicle 1000 will be described as an example. The power conversion device 20 drives an electric motor 30 mounted on the vehicle 1000. The vehicle 1000 is provided with a power storage device 10, and the power conversion device 20 converts DC power supplied from the power storage device 10 into AC power to drive the electric motor 30.

[0011] The electric motor 30 is, for example, a traction motor for rotating wheels. The electric motor 30 has three-phase coils that are connected in a predetermined pattern. The connection pattern is not limited to the Y-pattern shown in FIG. 1 , and other connection patterns such as a delta pattern may also be used. The electric motor 30 is driven to rotate by applying a predetermined current pattern from the power conversion device 20 to the three-phase coils.

[0012] The power storage device 10 has a positive electrode terminal 10a and a negative electrode terminal 10b. The power conversion device 20 has a positive electrode bus line 21p, a negative electrode bus line 21n, a smoothing capacitor 11, and three-phase switching arms 50 (U, V, W). The positive electrode bus line 21p is connected to the positive electrode terminal 10a of the power storage device 10. The negative electrode bus line 21n is connected to the negative electrode terminal 10b of the power storage device 10. Both ends of the smoothing capacitor 11 and the three-phase switching arms 50 (U, V, W) are connected to the positive electrode bus line 21p and the negative electrode bus line 21n.

[0013] Each of the three-phase switching arms 50 (U, V, W) is provided with an upper arm switching element 70A and a lower arm switching element 70B. The switching elements 70A, 70B are, for example, power switching elements, such as IGBTs or MOSFETs. Each of the switching elements 70A, 70B has a freewheeling diode (or body diode) connected in parallel. In the embodiment, the switching elements 70A, 70B are MOSFETs.

[0014] The upper arm switching element 70A and the lower arm switching element 70B are connected in series. A connection point between the upper arm switching element 70A and the lower arm switching element 70B is connected to one end of the coil of the corresponding phase of the electric motor 30. In the example shown in Fig. 1, one switching element is provided for each of the upper and lower arms, but a configuration in which multiple switching elements are used in parallel may also be used.

[0015] The power conversion device 20 includes a control circuit 40 that controls the gate drive devices 60A and 60B. The control circuit 40 outputs PWM control commands P1 and P2 to the gate drive devices 60A and 60B to individually control each switching element 70A and 70B. The control circuit 40 includes, for example, a CPU, RAM, ROM, and a communication circuit. The PWM control commands P1 and P2 are pulse signals having a predetermined pulse width, and the control circuit 40 PWM-controls the switching elements 70A and 70B. The PWM control commands P1 and P2 alternately turn on and off the switching elements 70A and 70B of the upper and lower arms of the same phase, so long as they are not turned on simultaneously. As a result, DC power from the power storage device 10 is converted into AC power, which drives and rotates the electric motor 30.

[0016] In this embodiment, the power conversion device 20 constituting an inverter as shown in FIG. 1 will be described as an example, but the present invention is not limited to this and can also be applied to a DC / DC converter, an AC / AC converter, an AC / DC inverter, etc.

[0017] <Explanation of Crosstalk Phenomenon> Figure 2 is a diagram showing a conventional configuration of a single-phase circuit in a one-phase switching arm 50. Gate drivers 61A and 61B are shown with a conventional, general configuration. Gate driver 61A and gate driver 61B have the same configuration and include a gate driver IC 610, a gate resistor Ron that controls the turn-on speed, and a gate resistor Roff that controls the turn-off speed. In Figure 2, the gate driver IC 610 of gate driver 61A is denoted by reference numeral 610a, and the gate driver IC 610 of gate driver 61B is denoted by reference numeral 610b.

[0018] Each of the switching elements 70A, 70B has a drain electrode D, a source electrode S, and a gate electrode G. The gate electrode G and source electrode S of each of the switching elements 70A, 70B are connected to the gate drive devices 61A, 61B, respectively. Hereinafter, the lower arm switching element 70B may be referred to as the own arm switching element 70B, and the upper arm switching element 70A may be referred to as the opposite arm switching element 70A.

[0019] The source electrode S of the paired arm switching element 70A and the drain electrode D of the corresponding arm switching element 70B are connected to an AC terminal. Each switching element 70A, 70B is switched between conduction (turned on) and cut-off (turned off) by the voltage (gate voltage) Vgs between the gate electrode G and the source electrode S. For example, when the gate voltage Vgs is higher than a predetermined turn-on threshold voltage, the switching element is in a conduction state, and when the gate voltage Vgs is lower than the turn-on threshold voltage, the switching element is in a cut-off state.

[0020] In the single-phase circuit of Figure 2, a phenomenon called crosstalk occurs when one of the arms switches. Here, we will explain the crosstalk that occurs when the paired arm switching element 70A is turned on. Each of the switching elements 70A and 70B has parasitic capacitances Cgd and Cgs between the gate and drain and between the gate and source.

[0021] As shown in the figure, when the paired arm switching element 70A is turned on, the potential of the source electrode S of the paired arm switching element 70A and the drain electrode D of the arm switching element 70B rises rapidly. In this case, as the potential of the drain electrode D of the arm switching element 70B rises, a current of magnitude (dV / dt) × Cgd proportional to the rate of potential change (dV / dt) flows, charging the parasitic capacitance Cgd of the arm switching element 70B. In addition, part of the current of magnitude (dV / dt) × Cgd flows to the source electrode S via the gate resistance Roff, charging the parasitic capacitance Cgs.

[0022] The magnitude of the rate of change |Vgs / dt| of the gate voltage Vgs of the switching element 70B in its own arm can be expressed by the following equation (1). In equation (1), Zgs is the impedance between the gate and source. In this case, the impedance Zgs is mainly the gate resistance Roff. |Vgs / dt|=1 / Cgs[Cgd×|dV / dt|−(Vgs / Zgs)] ... (1)

[0023] In this way, charging of the parasitic capacitances Cgd and Cgs causes the gate voltage Vgs of the arm switching element 70B to exceed the turn-on threshold voltage, causing the arm switching element 70B, which was previously in the off state, to become conductive. This phenomenon is called parasitic turn-on or self-turn-on. As shown in equation (1), the larger the (dV / dt) or the gate resistance Roff, the more likely the gate voltage Vgs will rise and the more likely self-turn-on will occur. When self-turn-on occurs, the paired arm switching element 70A and the arm switching element 70B become conductive at the same time, and a short-circuit current flows between the two switching elements 70A and 70B. This short-circuit current may increase losses in the paired arm switching element 70A and the arm switching element 70B.

[0024] Furthermore, although not shown, when the counter arm switching element 70A is turned off, the potential of the drain electrode D of the arm switching element 70B suddenly decreases ((dV / dt) becomes a negative value). In this case, current flows from the source electrode S of the arm switching element 70B, discharging the parasitic capacitances Cgd and Cgs. This reduces the gate voltage Vgs of the arm switching element 70B, causing a negative surge. In this case, as shown in equation (1), the larger the (dV / dt) or the gate resistance Roff, the more likely the gate voltage Vgs is to decrease and the more likely a negative surge is to occur. This negative surge in the gate voltage Vgs stresses the gate oxide film and shortens the life of the switching element. Therefore, measures must be taken to suppress the negative surge.

[0025] Measures to suppress the self-turn-on and negative surge caused by the above-mentioned (dV / dt) include, for example, slowing down the switching speed of the paired arm switching element 70A, providing a negative bias to the gate electrode G of the arm switching element 70B, reducing the gate-source impedance, etc. The invention described in Patent Document 1 proposes a circuit that reduces the gate-source impedance of the arm switching element 70B.

[0026] FIG. 3 is a diagram showing an example in which a conventional circuit for reducing gate-source impedance is provided in a gate driver. Hereinafter, the configuration shown in FIG. 3 will be referred to as a comparative example to this embodiment. Gate drivers 62A and 62B have the same configuration, and the configuration of the upper-arm gate driver 62A will be described as a representative. The gate driver 62A of the comparative example includes a gate driver IC 620a, gate resistors Ron and Roff, and an impedance adjustment circuit Z. A PWM control command P1 is input from the control circuit 40 to the gate driver IC 620a of the gate driver 62A. A PWM control command P2 is input from the control circuit 40 to the gate driver IC 620b of the lower-arm gate driver 62B.

[0027] The impedance adjustment circuit Z is a circuit that adjusts the gate-source impedance of the switching element 70A. The impedance adjustment circuit Z is connected to the gate electrode G of the switching element 70A. In the example shown in FIG. 3, the impedance adjustment circuit Z is composed of a switch element. The gate driver IC 620a is a circuit that controls the on / off of the switching element 70A based on a PWM control command P1 input from the control circuit 40. The gate driver IC 620a includes a turn-off detection unit 621 and a logic circuit 622 as components related to impedance adjustment.

[0028] A turn-off detection unit 621 that detects the turn-off operation of the switching element 70A monitors the gate voltage on the gate-on side. In the example shown in Figure 3, the turn-off detection unit 621 is configured with a comparator that compares the monitored gate voltage Vgs with a threshold voltage Vamc, and outputs a HIGH signal (detection signal) to a logic circuit 622 if Vgs < Vamc. The logic circuit 622 generates a control signal for the impedance adjustment circuit Z based on the PWM control command P1 and the signal from the turn-off detection unit 621.

[0029] The impedance adjustment circuit Z changes the impedance between the gate and source in response to a control signal from the logic circuit 622. In the example shown in FIG. 3, an ON / OFF signal that turns on and off the switching element of the impedance adjustment circuit Z is input as the control signal. When an ON signal is input to the impedance adjustment circuit Z, the gate and source are shorted and the impedance decreases. On the other hand, when an OFF signal is input to the impedance adjustment circuit Z, the short between the gate and source is released and the impedance increases.

[0030] FIG. 4 is a diagram showing gate driving devices 60A and 60B according to the first embodiment. Both gate driving devices 60A and 60B have the same configuration, and the configuration of gate driving device 60A will be described here as a representative example. Gate driving device 60A includes a gate driver IC 600a, gate resistors Ron and Roff, and an impedance adjustment circuit Z. The gate resistors Ron and Roff and the impedance adjustment circuit Z have the same configurations as those in the comparative example ( FIG. 3 ). The gate driver IC 600a differs from gate driver IC 620a in the configuration related to impedance adjustment. The gate driver IC of gate driving device 60B is designated by the reference symbol 620b, but has the same configuration as gate driver IC 620a.

[0031] The gate driver IC 600a includes, as components related to impedance adjustment, a turn-on detection unit 601, a turn-off detection unit 621, and a logic circuit 602. The turn-off detection unit 621 is the same as the turn-off detection unit 621 provided in the gate driver IC 620a described above. Furthermore, the logic circuit 602 differs from the logic circuit 622 only in the control content, and therefore the logic circuit 622 of the comparative example can be used as is.

[0032] 4, the turn-on detection unit 601 is configured with a comparator, compares the monitored gate voltage Vgs with a threshold voltage Vpto, and outputs a HIGH signal (detection signal) to a logic circuit 602 when Vgs>Vpto.

[0033] The logic circuit 602 of the upper-arm driver IC 600a receives as inputs the PWM control command P1, a signal from the turn-off detection unit 621, the lower-arm PWM control command P2, and a signal from the turn-on detection unit 601 of the lower-arm driver IC 600b (the gate turn-on signal of the switching element 70B). On the other hand, the logic circuit 602 of the lower-arm driver IC 600b receives as inputs the PWM control command P2, the signal from the turn-off detection unit 621, the upper-arm PWM control command P1, and a signal from the turn-on detection unit 601 of the upper-arm driver IC 600a (the gate turn-on signal of the switching element 70A). The logic circuits 602 of each of the driver ICs 600a, 600b generate control signals for the impedance adjustment circuits Z based on the input signals.

[0034] (1. Description of Impedance Control Operation) A control example of the logic circuit 602 in the first embodiment will be described in comparison with the control of the logic circuit 622 of the comparative example. Fig. 5 is a diagram for explaining the control operation of the logic circuits 602, 622, and is a diagram showing example waveforms of each signal when PWM controlling the switching elements 70A, 70B. In Fig. 5, waveform (A) shows PWM control commands P1, P2 of the upper and lower arms. The waveform shown by the thick solid line is the waveform of the PWM control command P1, and the waveform shown by the thin solid line is the waveform of the PWM control command P2.

[0035] Waveform (B) shows the gate voltage Vgs of switching elements 70A and 70B. The waveform shown by the thick solid line is the gate voltage Vgs1 of switching element 70A, and the waveforms shown by the thin solid line and dashed line are the gate voltage Vgs2 of switching element 70B. Note that the waveform of the gate voltage Vgs2 differs between the first embodiment and the comparative example; the dashed line shows the gate voltage Vgs2 in the first embodiment, and the solid line shows the gate voltage Vgs2 in the comparative example.

[0036] Waveform (C) shows the main voltage (drain-source voltage) Vds of switching elements 70A and 70B. The thick solid line shows the main voltage Vds1 of switching element 70A, and the thin solid and dashed lines show the main voltage Vds2 of switching element 70B. Of the waveform showing the main voltage Vds2, the dashed line shows the main voltage Vds2 in the first embodiment, and the solid line shows the main voltage Vds2 in the comparative example.

[0037] Waveform (D) shows the impedance Zgs2 between the gate and source of the lower arm switching element 70B. The dashed line shows the impedance Zgs2 in the first embodiment, and the solid line shows the impedance Zgs2 in the comparative example. The impedance Zgs2 becomes low when the gate and source are shorted by the impedance adjustment circuit Z, and becomes high when the short between the gate and source is released.

[0038] Waveform (E) shows the main current (drain current) Ids of switching elements 70A and 70B. The thick solid line shows the main current Ids1 of switching element 70A, and the thin solid and dashed lines show the main current Ids2 of switching element 70B. Of the waveform showing the main current Ids2, the dashed line shows the main current Ids2 in the first embodiment, and the solid line shows the main current Ids2 in the comparative example.

[0039] The PWM control command waveform shown in waveform (A) represents the waveform pattern of PWM control commands P1 and P2 when current is passed by turning on and off the upper-arm switching element 70A. In this case, the period from time t3 to time t5, when the PWM control command P1 is turned on, is the current-passing period, and the period when the PWM control command P1 is turned off is the freewheeling period. During the freewheeling period, when the lower-arm switching element 70B is off, a freewheeling current flows through the freewheeling diode, and when the switching element 70B is on (synchronous rectification), a freewheeling current flows through the switching element 70B.

[0040] In the following description of the operation, the switching element through which the energizing current flows is the aforementioned paired switching element, and the switching element through which the reflux current flows is the aforementioned own-arm switching element. That is, in the energization pattern shown in Fig. 5, the upper-arm switching element 70A corresponds to the paired switching element, and the lower-arm switching element 70B corresponds to the own-arm switching element. On the other hand, in the energization pattern in Fig. 2 in which the energizing current flows through the AC terminal from the right side to the left side in the figure, the energizing current flows through switching element 70B, so that switching element 70B corresponds to the paired switching element, and switching element 70A corresponds to the own-arm switching element.

[0041] In the on / off operation of the paired arm switching element (switching element 70A in FIG. 2 ) through which a current flows, the period from time t3 when the PWM control command P1 of waveform (A) rises to ON to time t4 when the gate voltage Vgs1 of waveform (B) reaches a predetermined threshold voltage Vpto is the "on switching period" when the paired arm switching element 70A is turned on. Also, the period from time t5 when the PWM control command P1 switches from ON to OFF to time t51 when the main current Ids1 of waveform (E) reaches zero is the "off switching period" when the paired arm switching element 70A is turned off.

[0042] (1-1. Control in Comparative Example) First, the impedance control operation in the comparative example shown in FIG. 3 will be described. In the comparative example, the impedance adjustment circuit Z reduces the gate-source impedance, thereby suppressing self-turn-on and negative surges caused by (dV / dt) of the paired arm switching element (upper arm switching element) 70A. The logic circuit 622 provided in the gate driver IC 620b shown in FIG. 3 controls the gate-source impedance Zgs2 of the switching element 70B, as indicated by the solid line in waveform (D). That is, the impedance Zgs2 is switched from HIGH to LOW at time t2, and then switched back from LOW to HIGH at time t6.

[0043] As shown in waveform (A), the paired arm switching element 70A and the own arm switching element 70B alternately repeat the ON state. In Fig. 5, the own arm switching element 70B is controlled to the OFF state from time t1 to time t6, and the paired arm switching element 70A is controlled to the ON state from time t3 to time t5. At time t1, an OFF PWM control command P2 is input to the lower arm gate driver IC 620b. After a while, the gate voltage Vgs2 of the own arm switching element 70B begins to decrease.

[0044] The turn-off detection unit 621 of the gate driver IC 620b compares the gate voltage Vgs2 of its own arm switching element 70B that it is monitoring with the threshold voltage Vamc, and outputs a HIGH signal to the logic circuit 622 at time t2 when Vgs2<Vamc. When the PWM control command P1 is OFF and the output of the turn-off detection unit 621 is HIGH, the logic circuit 622 outputs a signal (i.e., an ON signal) that reduces the impedance Zgs2 in the HIGH state to LOW. When the ON signal is input to the impedance adjustment circuit Z, the gate and source of the own arm switching element 70B are short-circuited, and the impedance Zgs2 is switched from HIGH to LOW.

[0045] When the PWM control command P1 switches from OFF to ON at time t3, the paired arm switching element 70A begins to turn on. After a while, the gate voltage Vgs1 of the paired arm switching element 70A begins to rise, and the main voltage Vds1 begins to decrease. In the comparative example, the impedance Zgs2 of the arm switching element 70B is low, so the increase in the gate voltage Vgs2 due to crosstalk (the spike at the location indicated by the arrow S1) is suppressed. On the other hand, by setting the impedance Zgs2 to low, as shown by the thin solid line in waveform (C), the linking surge voltage (recovery surge of the main voltage Vds2) generated when the freewheeling diode of the arm switching element 70B transitions from a conductive state to a cutoff state increases. This hinders an increase in switching speed and leads to increased switching loss.

[0046] When the PWM control command P1 switches from ON to OFF at time t5, the paired arm switching element 70A starts to turn off. After a while, the gate voltage Vgs of the paired arm switching element 70A starts to decrease, and the main voltage Vds1 starts to increase. In the comparative example, because the impedance Zgs2 of the own arm switching element 70B is LOW, negative spikes (spikes indicated by arrow S2) in the gate voltage Vgs2 of the own arm switching element 70B due to crosstalk are suppressed.

[0047] At time t6, when the PWM control command P1 switches from OFF to ON, the logic circuit 622 of the gate driver IC 620b outputs an OFF signal that raises the impedance Zgs2 from a LOW state to a HIGH state. When the OFF signal is input to the impedance adjustment circuit Z, the short circuit between the gate and source is released and the impedance Zgs2 switches from LOW to HIGH.

[0048] (1-2. Control in First Embodiment) Next, the impedance control operation in the first embodiment shown in Fig. 4 will be described. The logic circuit 602 provided in the gate driver ID 600b shown in Fig. 4 controls the impedance Zgs2 of its own arm switching element 70B as shown by the dashed line in waveform (D) in Fig. 5. That is, the impedance Zgs2 is switched from HIGH to LOW at time t2, returned from LOW to HIGH at time t3, switched from HIGH to LOW again at time t4, and returned from LOW to HIGH again at time t6.

[0049] Here, the HIGH value of the impedance Zgs2 is set to an impedance such that the gate voltage Vgs2 on the own arm side raised by turning on the paired arm switching element 70A exceeds the threshold voltage Vth (see waveform (B) in FIG. 5), i.e., such that the own arm switching element 70B turns on itself. On the other hand, the LOW value is set to an impedance such that the own arm switching element 70B does not turn on itself when the paired arm switching element 70A turns on.

[0050] The gate voltage Vgs2 of the arm switching element 70B when the counter arm switching element 70A is turned on is expressed by integrating the left side of the above-mentioned equation (1). The integration period is the turn-on time (on-switching period), and an impedance Zgs2 during which the gate voltage Vgs2 exceeds the threshold voltage Vth at any time during this period corresponds to an impedance HIGH at which self-turn-on occurs. On the other hand, an impedance Zgs2 during which the gate voltage Vgs2 does not exceed the threshold voltage Vth at any time during this period corresponds to an impedance LOW at which self-turn-on does not occur.

[0051] First, shortly after an OFF PWM control command P2 is input to the gate driver IC 600b at time t1 in Figure 5, the gate voltage Vgs2 of the arm switching element 70B begins to decrease. The turn-off detection unit 621 of the gate driver IC 600b compares the gate voltage Vgs2 of the arm switching element 70B it is monitoring with the threshold voltage Vamc, and outputs a HIGH signal to the logic circuit 602 at time t2 when Vgs2 < Vamc. When the PWM control command P1 is OFF and the output of the turn-off detection unit 621 is HIGH, the logic circuit 602 outputs an ON signal that reduces the impedance Zgs2 in the HIGH state to LOW. When the ON signal is input to the impedance adjustment circuit Z, the gate and source of the arm switching element 70B are shorted, and the impedance Zgs2 is switched from HIGH to LOW.

[0052] When the PWM control command P1 switches from OFF to ON at time t3, the logic circuit 602 of the gate driver IC 600b outputs an OFF signal that increases the impedance Zgs2 from a LOW state to a HIGH state. When the OFF signal is input to the impedance adjustment circuit Z, the impedance Zgs2 switches from LOW to HIGH.

[0053] At time t3, the paired arm switching element 70A starts to turn on, and after a while the gate voltage Vgs1 of the paired arm switching element 70A starts to rise and the main voltage Vds1 starts to decrease. In the first embodiment, because the impedance Zgs2 is HIGH, during the turn-on period of the paired arm switching element 70A, a spike in the gate voltage Vgs2 generated in the arm switching element 70B due to crosstalk exceeds the threshold voltage Vth. As a result, the arm switching element 70B is in a conductive state for a while, clamping the linking of the freewheeling diode and greatly reducing the recovery surge of the main voltage Vds2 compared to the comparative example.

[0054] In the operation after time t4, the impedance Zgs2 is controlled in the same manner as in the comparative example, as shown by the waveform (D). Therefore, the negative spike of the switching element 70B of the arm that occurs during the turn-off period after time t5 (the spike indicated by the arrow S2) is suppressed in the same manner as in the comparative example.

[0055] As described above, in the comparative example, the impedance Zgs2 is switched to the LOW state from time t2 to time t6, which prevents self-turn-on of the arm when the paired arm is turned on and suppresses negative surges when the paired arm is turned off. However, the recovery surge of the arm when the paired arm is turned on increases, which becomes an obstacle to increasing the switching speed.

[0056] On the other hand, in the first embodiment, as shown by the dashed line in waveform (D), control is performed to return impedance Zgs2 from LOW to HIGH during the paired arm turn-on period. By doing so, the gate impedance of the own arm is raised to HIGH during paired arm turn-on, slowing the rate at which carriers are extracted from the gate of the own arm and inducing self-turn-on. As a result, crosstalk-induced spikes in the gate voltage Vgs2 exceed the threshold voltage Vth, clamping the linking of the freewheeling diode and significantly reducing the recovery surge of the main voltage Vds2. This enables the turn-on speed to be increased while suppressing the own arm recovery surge during paired arm turn-on, thereby reducing the combined switching loss of the paired arm and the own arm. Furthermore, as in the comparative example, the gate negative surge of the own arm during paired arm turn-off can also be suppressed.

[0057] (Variation 1) FIG. 6 is a diagram showing Variation 1 of the first embodiment, in which impedance control is performed as indicated by the dashed line in waveform (D) of FIG. 5 . In gate driver ICs 600a and 600b in Variation 1, the turn-on detection unit 601 is omitted, and the signals input to the logic circuit 602A differ from those in the logic circuit 602 described above. The logic circuit 602A of the gate driver IC 600a receives a PWM control command P1, a signal from a turn-off detection unit 621, and a PWM control command P2 for the lower arm. Meanwhile, the logic circuit 602A of the gate driver IC 600b receives a PWM control command P2, a signal from the turn-off detection unit 621, and a PWM control command P1 for the upper arm. The remaining configuration of the gate drivers 60A and 60B is the same as that of the first embodiment shown in FIG. 4 .

[0058] The control operation of the impedance Zgs2 by the logic circuit 602A will be described. In the first modification, the control pattern of the impedance Zgs2 is the same as in the first embodiment described above, and is controlled as shown by the dashed line in the waveform (D) in Fig. 5. At time t2, as in the first embodiment, the turn-off detection unit 621 detects that Vgs2<Vamc, thereby switching the impedance Zgs2 from HIGH to LOW.

[0059] At time t3, as in the first embodiment, when the PWM control command P1 on the opposing arm switches from OFF to ON, the logic circuit 602A outputs an OFF signal to raise the impedance Zgs2 from LOW to HIGH. Furthermore, when a predetermined delay time Δt1 has elapsed since the logic circuit 602A detected the PWM control command P1 switching from OFF to ON, the logic circuit 602A switches the impedance Zgs2 from HIGH to LOW. Here, the delay time Δt1 is set to be equal to or longer than the ON switching period of the opposing arm switching element 70A being turned on and within the period until the start of turn-off (time t5). At time t6, as in the first embodiment, when the PWM control command P2 on the own arm switches from OFF to ON, the impedance Zgs2 is returned from LOW to HIGH.

[0060] (Variation 2) FIG. 7 is a diagram showing Variation 2 of the first embodiment, in which impedance control is performed as indicated by the dashed line in waveform (D) in FIG. 5 . In the gate driver ICs 600a and 600b in Variation 2, the signals input to the logic circuit 602B are different from those of the logic circuit 602 in the first embodiment. The logic circuit 602B of the upper-arm gate driver IC 600a receives a PWM control command P1, a signal from a turn-off detection unit 621, and a signal from a turn-on detection unit 601 of the lower-arm gate driver IC 600b. Meanwhile, the logic circuit 602B of the lower-arm gate driver IC 600b receives a PWM control command P2, a signal from the turn-off detection unit 621, and a signal from a turn-on detection unit 601 of the upper-arm gate driver IC 600a. The remaining configuration of the gate drivers 60A and 60B is the same as that of the first embodiment shown in FIG. 4 .

[0061] The control operation of the impedance Zgs2 by the logic circuit 602B will be described. At time t2, as in the first embodiment, the turn-off detection unit 621 detects that Vgs2<Vamc, thereby switching the impedance Zgs2 from HIGH to LOW. The logic circuit 602B monitors the upper-arm gate voltage Vgs1 via the upper-arm turn-on detection unit 601, and when the gate voltage Vgs1 begins to increase, returns the impedance Zgs2 from LOW to HIGH. This timing corresponds to time t3 in FIG. 5.

[0062] Thereafter, when a HIGH signal is input from the upper arm turn-on detection unit 601 (time t4), the impedance Zgs2 is switched again from HIGH to LOW. Then, when the lower arm PWM control command P2 is switched from OFF to ON (time t6), the impedance Zgs2 is returned again from LOW to HIGH.

[0063] (2. Impedance Adjustment Circuit Z) In the above-described embodiment and modified examples, the impedance adjustment circuit Z is configured with one switch element provided on the wiring. When the switch element is turned on, the impedance becomes LOW, and when the switch element is turned off, the impedance becomes HIGH. Other configurations of the impedance adjustment circuit Z will be described below.

[0064] 8A is a diagram showing a first modification of the impedance adjustment circuit Z. In the first modification, the impedance adjustment circuit Z is a series circuit of a switch element 80 and a capacitor 81. When the switch element 80 is turned on, the impedance becomes HIGH, and when the switch element 80 is turned off, the impedance becomes LOW. Since the impedance of the capacitor 81 is 1 / C with respect to the capacitance C, the smaller the capacitance C, the larger the impedance. This makes it possible to suppress the recovery surge.

[0065] 8B is a diagram showing a second modification of the impedance adjustment circuit Z. In the second modification, the impedance adjustment circuit Z is a series circuit of a switch element 80 and a resistor 82. When the switch element 80 is turned on, the impedance is LOW, and when the switch element 80 is turned off, the impedance is HIGH. The magnitude of the impedance of the impedance adjustment circuit Z depends on the impedance of the resistor 82, and is the same value whether the circuit is on or off.

[0066] 8C is a diagram showing a third modification of the impedance adjustment circuit Z. In the third modification, the impedance adjustment circuit Z is a series circuit of a switch element 80 and a diode 83. The diode 83 is preferably connected so that the cathode is on the gate side. When the switch element 80 is turned on, the impedance becomes LOW, and when the switch element 80 is turned off, the impedance becomes HIGH.

[0067] When the switch element 80 is turned on while the paired arm is turned off, a spike current flows from the source to the gate when a negative gate spike occurs. The magnitude of the negative gate spike is proportional to the product of this current and the impedance toward the gate, and the negative gate spike can be reduced by reducing the impedance toward the gate using the diode 83.

[0068] FIG. 8D shows a fourth modification of the impedance adjustment circuit Z. In the fourth modification, a parallel circuit of a resistor 82 and a diode 83 is connected in series to the switch element 80. In the parallel circuit, the impedance of the resistor 82 is the impedance for the flow from the top to the bottom of the figure, reducing the recovery surge when the arm is turned on. On the other hand, the diode 83 is dominant for the flow from the bottom to the top, resulting in zero impedance, reducing the negative surge when the arm is turned off. In the third modification of FIG. 8C, the impedance is infinite for the flow from the top to the bottom of the figure, so the configuration of the fourth modification is preferable. Alternatively, a parallel circuit of three elements, a diode, a resistor, and a capacitor, may be used.

[0069] 8E is a diagram showing a fifth modification of the impedance adjustment circuit Z. In the fifth modification, a series circuit of a switch element 80A and a resistor 82A and a series circuit of a switch element 80B and a resistor 82B are connected in parallel. By operating the switch elements 80A and 80B as follows, the impedance can be changed in multiple stages.

[0070] When switch elements 80A and 80B are turned off simultaneously, the impedance becomes the largest, Z1. Conversely, when switch elements 80A and 80B are turned on simultaneously, the impedance becomes the smallest, Z4. The impedance when switch element 80A is turned on and switch element 80B is turned off is Z2, and the impedance when switch element 80A is turned off and switch element 80B is turned on is Z3. Here, the values ​​of resistors 82A and 82B are set so that Z2 > Z3. That is, by controlling the on / off of switch elements 80A and 80B, the impedance can be controlled to four levels: Z1, Z2, Z3, and Z4 (Z1 > Z2 > Z3 > Z4).

[0071] The impedance of the impedance adjustment circuit Z during the period from time t3 to time t4 in the waveform (D) of FIG. 5 is set to Z1 (corresponding to HIGH) in the first half and to Z2 or Z3 in the second half. Then, from times t2 to t3 and t4 to t6, the impedance is set to Z4 (corresponding to LOW). In this way, by controlling the impedance during times t3 to t4 according to the state of the switching elements 70A and 70B, recovery surges can be appropriately suppressed, optimizing losses. This prevents an increase in losses due to excessive surge suppression. While two parallel connections are shown in FIG. 8E, three or more parallel connections are also acceptable, allowing for more precise impedance adjustment.

[0072] Furthermore, the impedance value from time t3 to t4 may be adjusted based on the state (main voltage, main current, junction temperature) of the switching elements 70A, 70B. For example, with respect to junction temperatures T1, T2 (>T1), a control method may be used in which the impedance value from time t3 to t4 at junction temperature T1 is set to Z1, and the impedance value from time t3 to t4 at junction temperature T2 is set to Z2 or Z3.

[0073] As an example based on the main current Ids, consider a first main current and a second main current higher than the first main current. In this case, a control method may be used in which the impedance value for the first main current from time t3 to t4 is set to Z1, and the impedance value for the second main current from time t3 to t4 is set to Z2 or Z3.

[0074] Second Embodiment Fig. 9 is a diagram showing a second embodiment of a gate driver. As shown in Fig. 9, gate driver ICs 600a and 600b include a turn-on detection unit 601 and a logic circuit 602C. In the second embodiment, a control signal for an impedance adjustment circuit Z is generated based on a PWM control command on the own arm side and a signal from the turn-on detection unit 601 on the opposite arm side.

[0075] The logic circuit 602C of the upper-arm gate driver IC 600a generates a control signal for the impedance adjustment circuit Z based on the PWM control command P1 and the output signal of the turn-on detection unit 601 of the lower-arm gate driver IC 600b. On the other hand, the logic circuit 602C of the lower-arm gate driver IC 600a generates a control signal for the impedance adjustment circuit Z based on the PWM control command P2 and the output signal of the turn-on detection unit 601 of the upper-arm gate driver IC 600b.

[0076] In the second embodiment, a control pattern such as that shown by the dashed line in waveform (D) in Fig. 5 is generated by the following control signal generation method. The logic circuit 602C on the own arm (lower arm) switches the impedance Zgs2 from high to low at a timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed since the timing (time t1) when the PWM control command P2 on the own arm is turned off. Thereafter, the logic circuit 602C monitors the gate voltage Vgs1 on the opposite arm via the turn-on detection unit 601 on the opposite arm, and when the gate voltage Vgs1 begins to increase, returns the impedance Zgs2 from low to high (corresponding to time t3).

[0077] When a HIGH signal is input from the turn-on detection unit 601 on the opposing arm side (time t4), the logic circuit 602C switches the impedance Zgs2 from HIGH to LOW. Thereafter, when the PWM control command P2 on the own arm side switches from LOW to HIGH (time t6), the logic circuit 602C returns the impedance Zgs2 from LOW to HIGH again. As a result, the second embodiment can also achieve the same effects as the first embodiment.

[0078] 10 is a diagram showing a gate driver according to a third embodiment. PWM control commands P1 and P2 for the respective arms are input to a logic circuit 602D of each gate driver IC 600a, 600b. The logic circuit 602D generates a control signal for an impedance adjustment circuit Z based on the PWM control commands P1 and P2.

[0079] In the third embodiment, a control pattern such as that shown by the dashed line in waveform (D) in Fig. 5 is generated by the following control signal generation method. The logic circuit 602D on the own arm side (lower arm side) switches the impedance Zgs2 from high to low at a timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed since the timing (time t1) when the PWM control command P2 on the own arm side turns off. Thereafter, when the PWM control command P1 on the opposite arm side switches from off to on (time t3), the logic circuit 602D returns the impedance Zgs2 from low to high.

[0080] The logic circuit 602D switches the impedance Zgs2 from High to Low at a timing (corresponding to time t4) when a predetermined delay time Δt1 has elapsed since the timing (time t3) when the PWM control command P1 on the opposing arm is switched ON. Thereafter, when the PWM control command P2 on the own arm is switched from Low to High (time t6), the logic circuit 602D returns the impedance Zgs2 from Low to High again. As a result, the third embodiment can also achieve the same effects as the first embodiment.

[0081] 11 is a diagram showing a fourth embodiment of the gate driver. The gate driver ICs 600a and 600b each include a main voltage detector 603, a main current detector 604, and a logic circuit 602E. The main voltage detector 603 and the main current detector 604 are configured, for example, with comparators. The main voltage detector 603 of each gate driver IC 600a and 600b compares the main voltages (drain-source voltages) Vds1 and Vds2 of the corresponding switching elements 70A and 70B with a reference voltage, and outputs a Vds detection signal to the logic circuit 602E if the main voltages Vds1 and Vds2 are equal to or greater than the reference voltage. The main current detection unit 604 of each gate driver IC 600a, 600b compares the main currents (drain currents) Ids1, Ids2 of the corresponding switching elements 70A, 70B with a reference current, and outputs an Ids detection signal to the logic circuit 602E when the main currents Ids1, Ids2 are equal to or less than the reference current. The logic circuit 602E controls the impedance Zgs2 based on the PWM control command and at least one of the Vds detection signal and the Ids detection signal.

[0082] In the fourth embodiment, a control pattern such as that shown by the dashed line in waveform (D) in FIG. 5 is generated by the following control signal generation method. The logic circuit 602E on the own arm side (lower arm side) switches the impedance Zgs2 from high to low at a timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed since the timing (time t1) when the PWM control command P2 on the own arm side is turned off. When at least one of the Ids detection signal and the Vds detection signal of the own arm is input (time t31), the logic circuit 602E returns the impedance Zgs2 from low to high again. Here, time t31 corresponds to time t3 in the first embodiment.

[0083] Next, the logic circuit 602E switches the impedance Zgs2 from High to Low again at the timing when a predetermined delay time Δt3 has elapsed since time t31 (corresponding to time t4). Thereafter, when the PWM control command P2 for the own arm switches from Low to High (time t6), the logic circuit 602E switches the impedance Zgs2 back from Low to High again. As a result, the fourth embodiment can also achieve the same effects as the first embodiment.

[0084] Although the ground potential differs between the paired arm (upper arm) and the own arm (lower arm), in the configuration shown in Fig. 11, the paired arm performs impedance control based on a signal from the paired arm side, while the own arm performs impedance control based on a signal from the own arm side, so the upper and lower arms are independent. For example, in the configuration shown in Fig. 4, the upper and lower arms are not independent, so an insulating element is required to exchange signals between the upper and lower arms. On the other hand, in the configuration shown in Fig. 11, the upper and lower arms are independent, so no such insulating element is required, and costs can be reduced.

[0085] Fifth Embodiment Fig. 12 is a diagram showing the configuration of a single-phase circuit according to a fifth embodiment. In the fifth embodiment, the upper and lower arm switching elements of the first embodiment are configured with a plurality of switching elements connected in parallel. In the example shown in Fig. 12, the upper arm side is provided with switching elements 70A1 and 70A2 connected in parallel, and the lower arm side is provided with switching elements 70B1 and 70B2 connected in parallel.

[0086] An electronic component (e.g., a resistor or inductor) 91a having an impedance Z1a is connected to the gate terminal of the switching element 70A1. An electronic component 91b having an impedance Z1b is connected to the gate terminal of the switching element 70A2. The other ends of the electronic components 91a and 91b are connected to the gate driver IC 600a. The impedances Z1a and Z1b are set so that the recovery surges of the switching elements 70A1 and 70A2 during the recovery period have similar values ​​(e.g., a difference of no more than 50 V).

[0087] Similarly, an electronic component 92a having an impedance Z2a is connected to the gate terminal of switching element 70B1. An electronic component 92b having an impedance Z2b is connected to the gate terminal of switching element 70B2. The other ends of electronic components 92a and 92b are connected to gate driver IC 600b. Impedances Z2a and Z2b are set so that the recovery surges of switching elements 70B1 and 70B2 during their recovery periods have similar values ​​(e.g., a difference of no more than 50 V).

[0088] In this way, even in a configuration in which a plurality of switching elements are connected in parallel, the same effects as in the first embodiment can be achieved by providing gate drive devices 60A, 60B similar to those in the first embodiment and performing impedance control as shown in waveform (D) in Fig. 5. Note that a configuration in which a plurality of switching elements are connected in parallel, as in the case of Fig. 12, may be applied to the configurations of the second to fourth embodiments.

[0089] 12 shows the case of two switching elements connected in parallel, but the present invention can also be applied to a configuration in which three or more switching elements are connected in parallel. In this case, too, an electronic component whose impedance is set so that the recovery surges in each switching element have approximately the same value is connected to the gate terminal of each switching element.

[0090] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0091] (C1) As shown in FIGS. 4 and 5 , etc., gate driving devices 60A, 60B drive upper and lower arm switching elements (semiconductor elements) 70A, and include a turn-on detection unit 601, a turn-off detection unit 621, a logic circuit 602, and an impedance adjustment circuit Z as impedance adjustment units that individually control the impedance of the gate discharge paths of the upper and lower arms, and the logic circuit 602 sets a first impedance (HIGH) of the gate discharge path of one of the upper and lower arms (one arm) during an ON switching period of the paired arm (one arm) to be higher than a second impedance (LOW) of the gate discharge path of the other arm during an OFF switching period of the other arm.

[0092] By setting the first impedance in this manner, the gate impedance of the arm itself is increased to HIGH when the arm itself is turned on, thereby slowing down the speed at which carriers are extracted from the gate of the arm itself, thereby inducing self-turn-on. As a result, the arm itself can be turned on faster while suppressing the recovery surge of the arm itself, and the total switching loss on both the arm itself and the arm itself can be reduced.

[0093] (C2) In (C1) above, as shown in Fig. 5, the logic circuit 602 of the impedance adjustment unit changes the impedance of the gate discharge path of the arm (the other arm) from HIGH (first impedance) to LOW (second impedance) during the period from when the paired arm (one arm) has completed turning on (time t4) to when the paired arm starts turning off (time t5). Since the impedance of the gate discharge path of the arm is set to LOW during the turn-off period (off switching period), damage to the oxide film of the gate can be prevented, and a decrease in gate reliability can be prevented.

[0094] (C3) In (C1) above, as shown in FIG. 4 and other figures, the impedance adjustment unit includes a Miller clamp circuit that maintains the impedance between the gate and source of the switching elements 70A and 70B at LOW (second impedance). In the comparative example configuration of FIG. 3, the turn-off detection unit 621, logic circuit 622, and impedance adjustment circuit Z constitute a Miller clamp circuit. The impedance adjustment unit in the first embodiment shown in FIG. 5 is configured using this Miller clamp circuit, which allows for circuit simplification. Of course, a circuit having the function of the impedance adjustment unit may be configured without using a Miller clamp circuit.

[0095] (C4) In the above (C1), as shown in Fig. 5 etc., the first impedance (HIGH) is set to a value HIGH at which the switching element 70B of the own arm (the other arm) is self-turned on when the paired arm (one arm) is turned on. In this way, the self-turning on of the switching element 70B of the own arm can reduce the recovery surge of the own arm.

[0096] (C5) In (C1) above, as shown in Figures 4, 5, 10, etc., the logic circuit 602 of the impedance adjustment unit controls the impedance of the gate discharge path of its own arm (the other arm) to HIGH and LOW based on gate information of the paired arm (one arm). Examples of gate information include a PWM control command P1 of the paired arm and a signal from the turn-on detection unit 601 in the configuration shown in Figure 4, and a PWM control command P1 of the paired arm in the configuration shown in Figure 10. In this way, determining the timing of adjusting the gate impedance of its own arm from the gate information of the paired arm can simplify the circuit.

[0097] (C6) In (C1) above, as shown in FIGS. 5, 11, etc., the impedance adjustment unit includes at least one of a main voltage detection unit 603 that detects a main voltage Vds2 (main voltage information) of the own arm (the other arm) and a main current detection unit 604 that detects a main current Ids2 (main current information) of the own arm, and a logic circuit 602E of the impedance adjustment unit controls the impedance of the gate discharge path of the own arm to HIGH (first impedance) and LOW (second impedance) based on at least one of the main voltage Vds2 and the main current Ids2.

[0098] 11, the ground potential is different between the paired arm (upper arm) and the own arm (lower arm). As described above, impedance control is performed in the paired arm based on the signal from the paired arm, and in the own arm based on the signal from the own arm. This makes it possible to omit the insulating elements required for exchanging signals between the upper and lower arms, thereby reducing costs.

[0099] (C7) In (C1) above, as shown in FIG. 8A etc., the impedance adjustment unit includes a capacitor 81 (capacitive element) as an impedance adjustment element. When adjusting the gate impedance, it is generally configured with a resistor (including a 0 Ω shunt resistor and a jumper), but as mentioned above, it is also possible to adjust it with a capacitive element (capacitance C). Since the impedance is proportional to 1 / C, the larger the capacitance C, the lower the impedance. This makes it possible to suppress recovery surges.

[0100] (C8) In (C1) above, as shown in Figures 8C, 8D, etc., the impedance adjustment unit includes a diode 83 as an impedance adjustment element. By providing the diode 83, the impedance toward the gate is reduced, and the gate negative spike can be reduced.

[0101] (C9) In (C1) above, as shown in Figure 12 etc., the upper arm is made up of a plurality of switching elements 70A1, 70A2 connected in parallel, and the lower arm is made up of a plurality of switching elements 70B1, 70B2 connected in parallel. The impedance (gate impedance) of each of electronic components 92a, 92b provided on the gate wiring of the plurality of switching elements 70B1, 70B2 of the own arm (the other arm) is set so that the recovery surges of the switching elements 70B1, 70B2 when the paired arm (one arm) is turned on are equalized.

[0102] If the gate impedances of the parallel-connected switching elements 70B1 and 70B2 are adjusted to the same value as in Figure 12, different recovery surges may occur. In this case, the switching element with the larger recovery surge may fail early. Therefore, impedance-adjusting electronic components 92a and 92b are provided on the gate wiring of the switching elements 70B1 and 70B2, and the impedances of the electronic components 92a and 92b are set so that the recovery surges that occur are equal. This makes it possible to prevent the inconvenience of early failure of one of the switching elements 70B1 and 70B2.

[0103] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0104] 10... Power storage device, 20... Power conversion device, 30... Electric motor, 40... Control circuit, 60A, 60B, 61A, 61B, 62A, 62B... Gate drive device, 70A, 70B... Switching element, 600a, 600b, 610 (610a, 610b), 620a, 620b... Gate driver IC, 601... Turn-on detection unit, 602, 602A, 602B, 602C, 602D, 622... Logic circuit, 603... Main voltage detection unit, 604... Main current detection unit, 621... Turn-off detection unit, P1, P2... PWM control command, Z... Impedance adjustment circuit

Claims

1. A gate drive device for driving semiconductor elements of upper and lower arms, comprising an impedance adjustment unit that individually controls the impedance of the gate discharge paths of the upper and lower arms, the impedance adjustment unit setting a first impedance of the gate discharge path of one of the upper and lower arms during an ON switching period of the other arm to be higher than a second impedance of the gate discharge path of the one arm during an OFF switching period of the one arm.

2. A gate drive device as claimed in claim 1, wherein the impedance adjustment section changes the impedance of the gate discharge path of the one arm from the first impedance to the second impedance during the period from when the one arm has completed turning on to when the other arm starts turning off.

3. A gate driver according to claim 1, wherein the impedance adjustment section includes a Miller clamp circuit that holds the impedance between the gate and source of the semiconductor element at the second impedance.

4. A gate driver as claimed in claim 1, wherein the first impedance is set to a value at which turning on the one arm causes the semiconductor element of the other arm to self-turn on.

5. A gate drive device according to claim 1, wherein the impedance adjustment section controls the impedance of the gate discharge path of the one arm to the first and second impedances based on gate information of the other arm.

6. A gate drive device according to claim 1, wherein the impedance adjustment section includes at least one of a main voltage detection section which detects main voltage information of the other arm and a main current detection section which detects main current information of the other arm, and the impedance adjustment section controls the impedance of the gate discharge path of the other arm to the first and second impedances based on at least one of the main voltage information and the main current information.

7. A gate driver according to claim 1, wherein the impedance adjustment section includes a capacitive element as an impedance adjustment element.

8. A gate driver according to claim 1, wherein the impedance adjustment section includes a diode as an impedance adjustment element.

9. A gate drive device as claimed in claim 1, wherein each of the upper and lower arms is composed of a plurality of semiconductor elements connected in parallel, and the gate impedances of the plurality of semiconductor elements in the other arm are set so that the recovery surges of the plurality of semiconductor elements when the one arm is turned on are uniform.

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