Semiconductor light-emitting device

Abstract

A semiconductor light-emitting device (100) is provided with a substrate (10), a semiconductor layer (20), an insulating film (30), and a metal layer (40). The semiconductor layer is disposed on the substrate. In the semiconductor layer, a first groove (20a) and a second groove (20b) which penetrate the semiconductor layer and expose the substrate are formed. In a plan view, the first groove and the second groove extend along a first direction (DR1) and are arranged with a spacing therebetween along a second direction (DR2) perpendicular to the first direction. The semiconductor layer between the first groove and the second groove forms a mesa structure (24) serving as a light-emitting part. The insulating film is disposed on the substrate exposed from the first groove and the second groove, on a side wall of the first groove, on a side wall of the second groove, and on the semiconductor layer. An opening part (31) is formed in the insulating film on the mesa structure. The metal layer is disposed on the insulating film and is electrically connected to the mesa structure via the opening part. The metal layer has a first layer (41) and a second layer (42).

Description

Semiconductor light-emitting device

[0001] The present disclosure relates to semiconductor light emitting devices.

[0002] For example, Japanese Patent Laid-Open No. 2023-100967 (Patent Document 1) describes a semiconductor light emitting device, which includes a substrate, a semiconductor layer, an insulating film, and a metal layer.

[0003] The semiconductor layer is disposed on a substrate. A first groove and a second groove are formed in the semiconductor layer. In a plan view, the first groove and the second groove extend along a first direction and are spaced apart along a second direction perpendicular to the first direction. The first groove and the second groove penetrate the semiconductor layer. That is, the substrate is exposed from each of the first groove and the second groove. A portion of the semiconductor layer between the first groove and the second groove forms a mesa structure that serves as a light emitting portion.

[0004] The semiconductor layer (mesa structure) has a light-emitting layer and a contact layer. The light-emitting layer has an n-type cladding layer, a p-type cladding layer, and an active layer. The active layer is disposed on the n-type cladding layer. The p-type cladding layer is disposed on the active layer. That is, the active layer is sandwiched between the n-type cladding layer and the p-type cladding layer in the thickness direction of the semiconductor layer. The contact layer is disposed on the light-emitting layer (p-type cladding layer).

[0005] The insulating film is disposed on the substrate exposed from each of the first and second grooves, on the sidewalls of the first and second grooves, and on the mesa structure. An opening is formed in the insulating film on the mesa structure. The opening penetrates the insulating film, and the mesa structure (contact layer) is exposed from the opening. The metal layer is disposed on the insulating film so as to be electrically connected to the mesa structure through the opening.

[0006] JP 2023-100967 A

[0007] In the semiconductor light-emitting device described in Patent Document 1, dielectric breakdown may occur in a portion of the insulating film disposed on the substrate that is exposed from the end of the first groove (second groove) in the first direction. In other words, the semiconductor light-emitting device described in Patent Document 1 has room for improvement in reverse voltage resistance.

[0008] The semiconductor light emitting device of the present disclosure includes a substrate, a semiconductor layer, an insulating film, and a metal layer. The semiconductor layer is disposed on the substrate. A first groove and a second groove are formed in the semiconductor layer, penetrating the semiconductor layer to expose the substrate. In a plan view, the first groove and the second groove extend along a first direction and are spaced apart along a second direction perpendicular to the first direction. The semiconductor layer between the first groove and the second groove forms a mesa structure that serves as a light emitting portion. An insulating film is disposed on the substrate exposed from the first groove and the second groove, on the sidewalls of the first groove, on the sidewalls of the second groove, and on the semiconductor layer. An opening is formed in the insulating film on the mesa structure. The metal layer is disposed on the insulating film and is electrically connected to the mesa structure via the opening. The metal layer has a first layer and a second layer. The first layer is disposed on the insulating film. The second layer is disposed on the first layer. An end of the first layer in the first direction is located inside an end of the second layer in the first direction.

[0009] 14. A plan view of the semiconductor light emitting device 100. A cross-sectional view taken along line II-II in FIG. 1. A cross-sectional view taken along line III-III in FIG. 1. An enlarged cross-sectional view of the light emitting layer 21. An enlarged cross-sectional view of the active layer 21c. An enlarged cross-sectional view of the tunnel layer 23. A schematic graph showing the relationship between the forward current flowing through the mesa structure 24 in the semiconductor light emitting device 100 and the optical output. A manufacturing process diagram of the semiconductor light emitting device 100. A cross-sectional view illustrating the semiconductor layer forming step S2. A cross-sectional view illustrating the groove forming step S3. A cross-sectional view illustrating the insulating film forming step S4. A cross-sectional view illustrating the first metal layer forming step S5. A cross-sectional view illustrating the second metal layer forming step S6. A plan view of the semiconductor light emitting device 100A. A cross-sectional view taken along line XV-XV in FIG. 14. A cross-sectional view taken along line XVI-XVI in FIG. 14. A schematic graph showing the relationship between the forward current flowing through the mesa structure 24 in the semiconductor light emitting device 100 and the semiconductor light emitting device 100A and the optical output. A plan view of the semiconductor light emitting device 200. 10 is a cross-sectional view illustrating an insulating film forming step S4 in the manufacturing method of the semiconductor light emitting device 200. FIG.

[0010] [DETAILED DESCRIPTION] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0011] First Embodiment A semiconductor light emitting device (semiconductor light emitting device 100) according to a first embodiment will be described.

[0012] <Configuration of Semiconductor Light-Emitting Device 100> The configuration of the semiconductor light-emitting device 100 will be described below.

[0013] Fig. 1 is a plan view of a semiconductor light-emitting device 100. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. As shown in Figs. 1, 2, and 3, the semiconductor light-emitting device 100 includes a substrate 10, a semiconductor layer 20, an insulating film 30, a metal layer 40, and a metal layer 50.

[0014] The substrate 10 is made of a semiconductor material, such as gallium arsenide (GaAs). The conductivity type of the substrate 10 is, for example, n-type. The substrate 10 has a main surface 10a and a main surface 10b. The main surface 10b is the surface opposite to the main surface 10a. The main surface 10a and the main surface 10b are end surfaces of the substrate 10 in the thickness direction.

[0015] The semiconductor layer 20 is disposed on the substrate 10. More specifically, the semiconductor layer 20 is disposed on the major surface 10a. The semiconductor layer 20 is epitaxially grown on the substrate 10 (major surface 10a). The semiconductor layer 20 includes at least one light-emitting layer 21 and a contact layer 22. In the example shown in FIGS. 1 to 3, the number of light-emitting layers 21 is three. When the number of light-emitting layers 21 is multiple, the multiple light-emitting layers 21 are stacked along the thickness direction of the semiconductor layer 20. In this case, the semiconductor layer 20 further includes a tunnel layer 23. The tunnel layer 23 is disposed between two adjacent light-emitting layers 21.

[0016] The contact layer 22 is disposed on the uppermost light-emitting layer 21. The material of the contact layer 22 is, for example, gallium arsenide, which is doped with p-type impurities.

[0017] 4 is an enlarged cross-sectional view of the light-emitting layer 21. As shown in FIG. 4, the light-emitting layer 21 includes, for example, a first n-type cladding layer 21a, a second n-type cladding layer 21b, an active layer 21c, a first p-type cladding layer 21d, and a second p-type cladding layer 21e. The first n-type cladding layer 21a is disposed on the second n-type cladding layer 21b. The active layer 21c is disposed on the first n-type cladding layer 21a. The first p-type cladding layer 21d is disposed on the active layer 21c. The second p-type cladding layer 21e is disposed on the first p-type cladding layer 21d. From another perspective, the active layer 21c is sandwiched between the first n-type cladding layer 21a and the first p-type cladding layer 21d, and this three-layer structure is sandwiched between the second n-type cladding layer 21b and the second p-type cladding layer 21e.

[0018] The first n-type cladding layer 21a, the second n-type cladding layer 21b, the first p-type cladding layer 21d, and the second p-type cladding layer 21e are made of, for example, aluminum gallium arsenide (AlGaAs). Ｘ Ga （１－Ｘ） The value of X in the first n-type cladding layer 21a is smaller than the value of X in the second n-type cladding layer 21b. The value of X in the first p-type cladding layer 21d is smaller than the value of X in the second p-type cladding layer 21e.

[0019] The value of X in the first n-type cladding layer 21a is, for example, 0.3 or more and 0.4 or less. The value of X in the second n-type cladding layer 21b is, for example, 0.5 or more and 0.6 or less. The value of X in the first p-type cladding layer 21d is, for example, 0.3 or more and 0.4 or less. The value of X in the second p-type cladding layer 21e is, for example, 0.5 or more and 0.6 or less.

[0020] 5 is an enlarged cross-sectional view of the active layer 21c. As shown in FIG. 5, the active layer 21c includes, for example, a first guide layer 21ca, a first well layer 21cb, a barrier layer 21cc, a second well layer 21cd, and a second guide layer 21ce. The first guide layer 21ca is disposed on the first n-type cladding layer 21a. The first well layer 21cb is disposed on the first guide layer 21ca. The barrier layer 21cc is disposed on the first well layer 21cb. The second well layer 21cd is disposed on the barrier layer 21cc. The second guide layer 21ce is disposed on the second well layer 21cd. A first p-type cladding layer 21d is disposed on the second guide layer 21ce.

[0021] From another perspective, the barrier layer 21cc is sandwiched between the first well layer 21cb and the second well layer 21cd, and this three-layer structure is sandwiched between the first guide layer 21ca and the second guide layer 21ce.

[0022] The first guide layer 21ca and the second guide layer 21ce are made of, for example, aluminum gallium arsenide. For example, the value of X in the first guide layer 21ca is smaller than the value of X in the first n-type cladding layer 21a, and the value of X in the second guide layer 21ce is smaller than the value of X in the first p-type cladding layer 21d. The values ​​of X in the first guide layer 21ca and the second guide layer 21cd are, for example, 0.05 or more and 0.15 or less.

[0023] The barrier layer 21cc is made of, for example, aluminum gallium arsenide. The value of X in the barrier layer 21cc is smaller than the value of X in the first n-type cladding layer 21a (the value of X in the second guide layer 21ce). The value of X in the barrier layer 21cc is, for example, 0.05 or more and 0.15 or less. The first well layer 21cb and the second well layer 21cd are made of, for example, indium gallium arsenide (InGaAs). The composition of indium gallium arsenide is In Ｙ Ga （１－Ｙ） The value of Y in the first well layer 21cb and the value of Y in the second well layer 21cd are, for example, greater than 0 and equal to or less than 0.15.

[0024] 6 is an enlarged cross-sectional view of the tunnel layer 23. As shown in FIG. 6, the tunnel layer 23 includes a p-type tunnel layer 23a and an n-type tunnel layer 23b. The p-type tunnel layer 23a is disposed on the second p-type cladding layer 21e. The n-type tunnel layer 23b is disposed on the p-type tunnel layer 23a. The second n-type cladding layer 21b is disposed on the n-type tunnel layer 23b. The constituent materials of the p-type tunnel layer 23a and the n-type tunnel layer 23b are, for example, aluminum gallium arsenide. The constituent materials of the p-type tunnel layer 23a and the n-type tunnel layer 23b are doped with p-type impurities and n-type impurities, respectively.

[0025] 1, 2, and 3, a first groove 20a and a second groove 20b are formed in the semiconductor layer 20. In a plan view, each of the first groove 20a and the second groove 20b extends along a first direction DR1. An end of the first groove 20a in the first direction DR1 and an end of the second groove 20b in the first direction DR1 reach an end of the substrate 10 in the first direction DR1.

[0026] Here, the plan view refers to the case where the semiconductor light emitting device 100 is viewed along the normal direction to the main surface 10a. Even if the extension direction of the first grooves 20a (extension direction of the second grooves 20b) and the first direction DR1 are not completely parallel, as long as the angle between the two directions is within 5°, the first grooves 20a (second grooves 20b) are considered to extend along the first direction DR1.

[0027] In a plan view, the first grooves 20 a and the second grooves 20 b are aligned along the second direction DR2. The second direction DR2 is perpendicular to the first direction DR1. Even if the direction in which the first grooves 20 a and the second grooves 20 b are aligned is not completely parallel to the second direction DR2, the first grooves 20 a and the second grooves 20 b are considered to be aligned along the second direction DR2 as long as the angle between the two directions is within 5°.

[0028] The first groove 20a and the second groove 20b penetrate the semiconductor layer 20. That is, the substrate 10 (major surface 10a) is exposed from the first groove 20a and the second groove 20b. In a cross-sectional view perpendicular to the first direction DR1, the distance between a pair of sidewalls of the first groove 20a and the distance between a pair of sidewalls of the second groove 20b become smaller as they approach the substrate 10.

[0029] The portion of the semiconductor layer 20 between the first groove 20a and the second groove 20b forms a mesa structure 24. The mesa structure 24 serves as a light-emitting portion of the semiconductor light-emitting device 100.

[0030] The insulating film 30 is made of an insulating material, such as silicon nitride (SiN) or silicon oxide (SiO). The insulating film 30 is disposed on the sidewalls of the first groove 20a, the sidewalls of the second groove 20b, the portion of the substrate 10 exposed from the first groove 20a, the portion of the substrate 10 exposed from the second groove 20b, and the semiconductor layer 20.

[0031] An opening 31 is formed in a portion of the insulating film 30 above the mesa structure 24. The opening 31 extends along the first direction DR1 in a plan view. However, it is preferable that the end of the opening 31 in the first direction DR1 does not reach the end of the mesa structure 24 in the first direction DR1, and is located inside the end of the mesa structure 24 in the first direction DR1. The opening 31 penetrates the insulating film 30 in the thickness direction. In other words, the mesa structure 24 (contact layer 22) is exposed from the opening 31.

[0032] The metal layer 40 is disposed on the insulating film 30 so as to be electrically connected to the mesa structure 24 (contact layer 22) through the opening 31. The metal layer 40 has a first layer 41 and a second layer 42. The first layer 41 is disposed on the insulating film 30. The first layer 41 is also disposed on the mesa structure 24 exposed from the opening 31. The second layer 42 is disposed on the first layer 41. However, an end of the second layer 42 in the first direction DR1 is disposed on the insulating film 30.

[0033] The thickness of the second layer 42 is greater than the thickness of the first layer 41, for example. The first layer 41 is, for example, a vapor deposition layer. The second layer 42 is, for example, a plating layer. The constituent materials of the first layer 41 and the second layer 42 are conductive materials. The constituent materials of the first layer 41 and the second layer 42 are, for example, gold (Au). The end of the first layer 41 in the first direction DR1 is located more inward than the end of the second layer 42 in the first direction DR1. The end of the second layer 42 in the first direction DR1 is, for example, located more inward than the end of the mesa structure 24 in the first direction DR1.

[0034] The metal layer 50 is made of a conductive material, such as gold. The metal layer 50 is disposed on the main surface 10b. When a voltage is applied between the metal layer 50 and the metal layer 40 on the mesa structure 24, a current is injected into the mesa structure 24, and laser light is generated. The generated laser light is emitted from an end face of the mesa structure 24 in the first direction DR1.

[0035] The value of the COD (Catastrophic Optical Damage) of the semiconductor light-emitting device 100 divided by the width of the mesa structure 24 in the second direction DR2 is preferably 0.95 W / μm or more. Furthermore, the value of the COD of the semiconductor light-emitting device 100 divided by the width of the mesa structure 24 in the second direction DR2 is preferably 2.0 W / μm or less. FIG. 7 is a schematic graph showing the relationship between the forward current flowing through the mesa structure 24 of the semiconductor light-emitting device 100 and the optical output. The horizontal and vertical axes in FIG. 7 represent the forward current (unit: A) and the optical output (unit: W), respectively. As shown in FIG. 7, the optical output increases as the forward current flowing through the mesa structure 24 increases. After the optical output reaches its peak, the optical output rapidly decreases as the forward current flowing through the mesa structure 24 increases. The peak of the optical output is defined as the COD of the semiconductor light-emitting device 100.

[0036] <Method for Manufacturing Semiconductor Light-Emitting Device 100> A method for manufacturing the semiconductor light-emitting device 100 will now be described.

[0037] 8 is a manufacturing process diagram of the semiconductor light emitting device 100. As shown in FIG. 7, the manufacturing method of the semiconductor light emitting device 100 includes a preparation step S1, a semiconductor layer formation step S2, a groove formation step S3, an insulating film formation step S4, a first metal layer formation step S5, a second metal layer formation step S6, and a cleavage step S7.

[0038] In the preparation step S1, a substrate 10 is prepared. After the preparation step S1, a semiconductor layer formation step S2 is performed.

[0039] 9 is a cross-sectional view illustrating the semiconductor layer forming step S2. As shown in FIG. 8, in the semiconductor layer forming step S2, a semiconductor layer 20 is epitaxially grown on a substrate 10. The semiconductor layer 20 is formed by sequentially depositing each layer constituting the semiconductor layer 20 by, for example, a chemical vapor deposition (CVD) method. After the semiconductor layer forming step S2, a groove forming step S3 is performed.

[0040] FIG. 10 is a cross-sectional view illustrating the groove forming step S3. As shown in FIG. 10, in the groove forming step S3, a first groove 20a and a second groove 20b are formed in the semiconductor layer 20. In the groove forming step S3, first, a resist pattern is formed on the semiconductor layer 20. The resist pattern is formed by applying a photoresist to the semiconductor layer 20 and then exposing and developing the applied photoresist. Second, dry etching is performed on the semiconductor layer 20 using the resist pattern as a mask. This forms the first groove 20a and the second groove 20b. After the dry etching, wet etching is performed on the semiconductor layer 20 to remove damage introduced to the sidewalls of the first groove 20a and the second groove 20b by the dry etching. After the groove forming step S3, an insulating film forming step S4 is performed.

[0041] 11 is a cross-sectional view illustrating the insulating film forming step S4. In the insulating film forming step S4, as shown in FIG. 11, an insulating film 30 is formed on the sidewalls of the first groove 20a, the sidewalls of the second groove 20b, the portion of the substrate 10 exposed from the first groove 20a, the portion of the substrate 10 exposed from the second groove 20b, and the semiconductor layer 20. In the insulating film forming step S4, first, the insulating film 30 is formed by, for example, a CVD method. Second, a resist pattern is formed on the formed insulating film 30. Third, an opening 31 is formed by etching using the resist pattern as a mask. After the insulating film forming step S4, a first metal layer forming step S5 is performed.

[0042] 12 is a cross-sectional view illustrating the first metal layer forming step S5. As shown in FIG. 12, in the first metal layer forming step S5, a metal layer 40 is formed on the insulating film 30. In the first metal layer forming step S5, first, a first layer 41 is formed on the insulating film 30 by, for example, vacuum deposition. Second, a second layer 42 is formed by electrolytic plating using the first layer 41 as a base. After the first metal layer forming step S5, a second metal layer forming step S6 is performed.

[0043] 13 is a cross-sectional view illustrating the second metal layer forming step S6. As shown in FIG. 13, in the second metal layer forming step S6, a metal layer 50 is formed on the main surface 10b by an appropriate method. After the second metal layer forming step S6, a cleaving step S7 is performed. In the cleaving step S7, the substrate 10 and the semiconductor layer 20 are cleaved to separate them into a plurality of semiconductor light emitting devices 100. In this manner, the structure of the semiconductor light emitting device 100 shown in FIGS. 1 to 3 is formed.

[0044] <Effects of Semiconductor Light-Emitting Device 100> The effects of the semiconductor light-emitting device 100 will be described below in comparison with a semiconductor light-emitting device according to a comparative example (semiconductor light-emitting device 100A).

[0045] FIG. 14 is a plan view of the semiconductor light-emitting device 100A. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14 . As shown in FIGS. 14 , 15 , and 16 , in the semiconductor light-emitting device 100A, the end of the first layer 41 in the first direction DR1 is located outside the end of the second layer 42 in the first direction DR1. In addition, in the semiconductor light-emitting device 100A, the end of the opening 31 in the first direction DR1 reaches the end of the mesa structure 24 in the first direction DR1. Except for these points, the configuration of the semiconductor light-emitting device 100A is the same as the configuration of the semiconductor light-emitting device 100.

[0046] In the semiconductor light emitting device 100A, a reverse voltage may be applied between the metal layer 40 and the metal layer 50. Such a reverse voltage may be generated, for example, by undershoot during the off state when the semiconductor light emitting device 100A is driven with a short pulse.

[0047] In the semiconductor light-emitting device 100A, the end of the first layer 41 in the first direction DR1 is located outside the end of the second layer 42 in the first direction DR1, and therefore the thickness of the metal layer 40 is reduced on the insulating film 30 on the substrate 10 that is exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1. In the semiconductor light-emitting device 100A, the reduced thickness of the metal layer 40 makes it difficult to alleviate electric field concentration, and dielectric breakdown may occur in the portion of the insulating film 30 on the substrate 10 that is exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1 (the portion surrounded by the dotted line in FIG. 16 ).

[0048] Similarly, in the semiconductor light-emitting device 100, a reverse voltage may be applied between the metal layer 40 and the metal layer 50. However, because the end of the first layer 41 in the first direction DR1 is located more inward than the end of the second layer 42 in the first direction DR1, the thickness of the metal layer 40 on the insulating film 30 on the substrate 10 exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1 is not reduced compared to the semiconductor light-emitting device 100A. Therefore, in the semiconductor light-emitting device 100, dielectric breakdown is suppressed in the portion of the insulating film 30 on the substrate 10 exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1, and the reverse voltage resistance is improved.

[0049] In addition, since the semiconductor light emitting device 100A lacks reverse voltage resistance, a protective diode must be separately provided. Furthermore, considering the need to reduce the circuit inductance in order to drive the semiconductor light emitting device 100A with short pulses, the protective diode must be placed near the semiconductor light emitting device 100A. As a result, the area in which a heat sink can be placed is narrowed, and the heat dissipation performance of the semiconductor light emitting device 100A is reduced. On the other hand, the semiconductor light emitting device 100 does not require the protective diode, and the area in which a heat sink can be placed can be secured, thereby improving heat dissipation performance.

[0050] When the semiconductor light-emitting device 100 has a high output, a mesa structure 24 having a plurality of light-emitting layers 21 or a light-emitting layer 21 configured with a first n-type cladding layer 21 a, a second n-type cladding layer 21 b, an active layer 21 c, a first p-type cladding layer 21 d, and a second p-type cladding layer 21 e is applied. When such a structure is applied, the electric field concentration described above is likely to occur, but even in such a case, the semiconductor light-emitting device 100 suppresses dielectric breakdown in the portion of the insulating film 30 on the substrate 10 that is exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1.

[0051] In the semiconductor light-emitting device 100A, the end of the opening 31 in the first direction DR1 reaches the end of the mesa structure 24 in the first direction DR1, so injection of forward current is not restricted at the end of the mesa structure 24 in the first direction DR1. On the other hand, in the semiconductor light-emitting device 100, the end of the opening 31 in the first direction DR1 is located inside the end of the mesa structure 24 in the first direction DR1, so injection of forward current is restricted at the end of the mesa structure 24 in the first direction DR1. As a result, in the semiconductor light-emitting device 100, heat generation near the end of the mesa structure 24 in the first direction DR1 is suppressed, and COD is improved.

[0052] 17 is a schematic graph showing the relationship between the forward current flowing through the mesa structure 24 and the optical output power of the semiconductor light emitting device 100 and the semiconductor light emitting device 100A. The horizontal and vertical axes in FIG. 17 represent the forward current (unit: A) and the optical output power (unit: W), respectively. As shown in FIG. 17, the semiconductor light emitting device 100 exhibits an improvement in COD of approximately 15 percent compared to the semiconductor light emitting device 100A.

[0053] Forming a thick metal layer 40 in a single layer increases the cost of forming the metal layer 40. In the semiconductor light emitting device 100, even when the cost of forming the metal layer 40 is reduced by combining a thin first layer 41 and a thick second layer 42, by arranging the end of the first layer 41 in the first direction DR1 more inward than the end of the second layer 42 in the first direction DR1, dielectric breakdown is suppressed in the portion of the insulating film 30 on the substrate 10 that is exposed from the end of the first groove 20 a (second groove 20 b) in the first direction DR1.

[0054] Second Embodiment A semiconductor light emitting device according to a second embodiment (semiconductor light emitting device 200) will be described below. Differences from the semiconductor light emitting device 100 will be mainly described here, and overlapping descriptions will not be repeated.

[0055] <Configuration of Semiconductor Light-Emitting Device 200> The configuration of the semiconductor light-emitting device 200 will be described below.

[0056] The semiconductor light emitting device 200 includes a substrate 10, a semiconductor layer 20, an insulating film 30, a metal layer 40, and a metal layer 50. In this respect, the configuration of the semiconductor light emitting device 200 is common to the configuration of the semiconductor light emitting device 100.

[0057] 18 is a plan view of the semiconductor light emitting device 200. As shown in Fig. 18, in the semiconductor light emitting device 200, the end of the insulating film 30 in the first direction DR1 is located more inward than the end of the mesa structure 24 in the first direction DR1. From another perspective, the end of the semiconductor layer 20 in the first direction DR1 is exposed from the insulating film 30. In this respect, the configuration of the semiconductor light emitting device 200 differs from the configuration of the semiconductor light emitting device 100.

[0058] <Method for Manufacturing Semiconductor Light-Emitting Device 200> A method for manufacturing the semiconductor light-emitting device 200 will now be described.

[0059] The method for manufacturing the semiconductor light emitting device 200 includes a preparation step S1, a semiconductor layer formation step S2, a groove formation step S3, an insulating film formation step S4, a first metal layer formation step S5, a second metal layer formation step S6, and a cleavage step S7. In this respect, the method for manufacturing the semiconductor light emitting device 200 is common to the method for manufacturing the semiconductor light emitting device 100.

[0060] 19 is a cross-sectional view illustrating the insulating film forming step S4 in the manufacturing method of the semiconductor light emitting device 200. The dotted lines in FIG. 19 indicate the positions that become the ends of the mesa structure 24 in the first direction DR1. As shown in FIG. 19 , in the manufacturing method of the semiconductor light emitting device 200, in the insulating film forming step S4, a portion of the insulating film 30 that is near the end of the mesa structure 24 in the first direction DR1 is removed. In this respect, the manufacturing method of the semiconductor light emitting device 200 differs from the manufacturing method of the semiconductor light emitting device 100.

[0061] <Effects of Semiconductor Light-Emitting Device 200> The effects of the semiconductor light-emitting device 200 will be described below.

[0062] In the semiconductor light emitting device 100, the insulating film 30 is present at the cleavage site in the cleavage step S7. On the other hand, in the semiconductor light emitting device 200, the insulating film 30 at the cleavage site is removed in advance in the insulating film forming step S4. Therefore, in the semiconductor light emitting device 200, the insulating film 30 does not hinder the cleavage step S7, and the cleavage step S7 can be performed more easily than in the semiconductor light emitting device 100.

[0063] (Additional Notes) The above embodiments include the following configurations.

[0064] <Supplementary Note 1> A semiconductor device comprising: a substrate; a semiconductor layer; an insulating film; and a metal layer, wherein the semiconductor layer is disposed on the substrate; a first groove and a second groove are formed in the semiconductor layer so as to penetrate the semiconductor layer and expose the substrate; in a plan view, the first groove and the second groove extend along a first direction and are arranged at an interval along a second direction perpendicular to the first direction; the semiconductor layer between the first groove and the second groove forms a mesa structure serving as a light emitting portion; the insulating film is disposed on the substrate exposed from the first groove and the second groove, on sidewalls of the first groove, on sidewalls of the second groove, and on the semiconductor layer; an opening is formed in the insulating film on the mesa structure; the metal layer is disposed on the insulating film and is electrically connected to the mesa structure via the opening; the metal layer has a first layer and a second layer, the first layer is disposed on the insulating film, and the second layer is disposed on the first layer; An end of the first layer in the first direction is located more inward than an end of the second layer in the first direction.

[0065] <Supplementary Note 2> The semiconductor light emitting device according to Supplementary Note 1, wherein an end of the second layer in the first direction is located more inward than an end of the mesa structure in the first direction.

[0066] <Supplementary Note 3> The semiconductor light-emitting device according to Supplementary Note 1 or Supplementary Note 2, wherein the opening extends along the first direction, and an end of the opening in the first direction is located more inward than an end of the mesa structure in the first direction.

[0067] <Supplementary Note 4> The semiconductor light emitting device according to Supplementary Note 3, wherein a value obtained by dividing the COD value by the width of the mesa structure in the second direction is 0.95 W / μm or more and 2.0 W / μm or less.

[0068] <Supplementary Note 5> The semiconductor light emitting device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the thickness of the first layer is smaller than the thickness of the second layer.

[0069] <Supplementary Note 6> The semiconductor light-emitting device according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the first layer is a vapor deposition layer, and the second layer is a plated layer.

[0070] <Supplementary Note 7> The semiconductor light-emitting device according to any one of Supplementary Note 1 to Supplementary Note 6, wherein an end of the insulating film in the first direction is located more inward than an end of the mesa structure in the first direction.

[0071] <Supplementary Note 8> The semiconductor light-emitting device according to any one of Supplementary Note 1 to Supplementary Note 7, wherein the mesa structure has at least one light-emitting layer and a contact layer disposed on an uppermost layer of the at least one light-emitting layer, each of the at least one light-emitting layer having an active layer, a first n-type cladding layer, a second n-type cladding layer, a first p-type cladding layer, and a second p-type cladding layer, the first n-type cladding layer being disposed on the second n-type cladding layer, the active layer being disposed on the first n-type cladding layer, the first p-type cladding layer being disposed on the active layer, and the second p-type cladding layer being disposed on the first p-type cladding layer.

[0072] <Supplementary Note 9> The semiconductor light-emitting device according to any one of Supplementary Notes 1 to 8, wherein the at least one light-emitting layer is a plurality of light-emitting layers.

[0073] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0074] 10 substrate, 10a, 10b main surface, 20 semiconductor layer, 20a first groove, 20b second groove, 21 light emitting layer, 21a first n-type cladding layer, 21b second n-type cladding layer, 21c active layer, 21ca first guide layer, 21cb first well layer, 21cc barrier layer, 21ce second guide layer, 21d first p-type cladding layer, 21e second p-type cladding layer, 22 contact layer, 23 tunnel layer, 23a p-type tunnel layer, 23b n-type tunnel layer, 24 mesa structure, 30 insulating film, 31 opening, 40, 50 metal layer, 41 first layer, 42 second layer, 100, 100A, 200 semiconductor light emitting device, DR1 first direction, DR2 second direction, S1 preparation step, S2 semiconductor layer formation step, S3 Groove formation step, S4 insulating film formation step, S5 first metal layer formation step, S6 second metal layer formation step, S7 cleavage step.

Claims

1. A semiconductor device comprising: a substrate; a semiconductor layer; an insulating film; and a metal layer, the semiconductor layer being disposed on the substrate; a first groove and a second groove being formed in the semiconductor layer so as to penetrate the semiconductor layer and expose the substrate; in a plan view, the first groove and the second groove extend along a first direction and are arranged at an interval along a second direction perpendicular to the first direction; the semiconductor layer between the first groove and the second groove forms a mesa structure serving as a light emitting portion; the insulating film is disposed on the substrate exposed from the first groove and the second groove, on a sidewall of the first groove, on a sidewall of the second groove, and on the semiconductor layer; an opening is formed in the insulating film on the mesa structure; the metal layer is disposed on the insulating film and is electrically connected to the mesa structure via the opening; the metal layer has a first layer and a second layer, the first layer being disposed on the insulating film, and the second layer being disposed on the first layer; A semiconductor light emitting device, wherein an end of the first layer in the first direction is located more inward than an end of the second layer in the first direction.

2. The semiconductor light emitting device according to claim 1, wherein an end of said second layer in said first direction is located inside an end of said mesa structure in said first direction.

3. A semiconductor light-emitting device as described in claim 1 or claim 2, wherein the opening extends along the first direction, and an end of the opening in the first direction is located more inward than an end of the mesa structure in the first direction.

4. The semiconductor light emitting device according to claim 3, wherein the value of the COD divided by the width of the mesa structure in the second direction is equal to or greater than 0.95 W / μm and equal to or less than 2.0 W / μm.

5. The semiconductor light emitting device according to claim 1, wherein the thickness of the first layer is smaller than the thickness of the second layer.

6. The semiconductor light emitting device according to any one of claims 1 to 5, wherein the first layer is a deposition layer, and the second layer is a plating layer.

7. A semiconductor light emitting device according to claim 1, wherein an end of the insulating film in the first direction is located inside an end of the mesa structure in the first direction.

8. The semiconductor light emitting device according to any one of claims 1 to 7, wherein the mesa structure has at least one light emitting layer and a contact layer disposed on a topmost layer of the at least one light emitting layer, each of the at least one light emitting layer having an active layer, a first n-type cladding layer, a second n-type cladding layer, a first p-type cladding layer and a second p-type cladding layer, the first n-type cladding layer being disposed on the second n-type cladding layer, the active layer being disposed on the first n-type cladding layer, the first p-type cladding layer being disposed on the active layer, and the second p-type cladding layer being disposed on the first p-type cladding layer.

9. The semiconductor light emitting device of claim 8, wherein said at least one light emitting layer is a plurality of light emitting layers.

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