External cavity laser and integration process for making the same

Abstract

The invention relates to an external cavity laser and an integration process for making the same. The integration process for making an external cavity laser, comprising steps of: fabricating a III-V semiconductor optical amplifier (SOA) (23) which includes an active layer (19); fabricating a silicon photonic (SiPh) waveguide (24) which includes a passive waveguide layer (20) and an interlayer (22); flipping and aligning the SOA (23) with the waveguide (24) in a passive manner; and connecting the SOA (23) to the waveguide (24) by one or more flip-chip bumps (70, 71), such that when said SOA (23) is powered an evanescent coupling is formed between the SOA (23) and the waveguide (24). The external cavity laser comprising a III-V semiconductor optical amplifier (SOA) (23) and a silicon photonic (SiPh) waveguide (24), wherein said SOA (23) is aligned and connected to said waveguide (24) by one or more flip-chip bumps (70, 71), such that when said SOA (23) is powered an evanescent coupling is formed between said SOA (23) and waveguide (24).

Description

[0001] EXTERNAL CAVITY LASER AND INTEGRATION PROCESS FOR MAKING THE SAME

[0002] FIELD OF THE INVENTION

[0003] This invention relates to an external cavity laser (“ECL”) and an integration process for making the same.

[0004] BACKGROUND OF THE INVENTION

[0005] Compact, small foot-print, light-weight, low relative intensity noise (RIN), narrow Lorentzian line-width and relatively high-power lasers are currently in demand for many applications such as coherent communications using digital coherent optics (DCO) transceivers, RF photonics, distributed sensing systems, spectroscopy, coherent sensing in FMCW-LIDAR and many others. Small form-factor is especially important for narrow-linewidth (NLW) lasers to be integrable in tuneable laser assemblies used in coherent pluggable transceivers that demands reduction in size and power dissipation. In contrast to conventional NLW solid-state lasers and fiber lasers which are too bulky, external cavity semiconductor lasers that employ hybrid integration of III-V semiconductor optical amplifier (SOA) and low-loss photonic integrated circuits (PIC) utilizing planar light-wave circuits (PLC), low- loss silicon nitride or silicon-on-insulator (SOI) waveguides have been demonstrated to give NLW of 10’s kHz while at the same time satisfying requirements for size, weight, power (SWaP) and cost. Recently, a sub-kHz linewidth wavelength-tuneable laser diode was shown to be possible using hybrid integration and butt-coupling of III-V SOA to silicon-photonic-filter PIC chip. The use of silicon-photonics (SiPh) is encouraging since one can leverage on the matured silicon manufacturing ecosystem to bring about lower SiPh chip cost.

[0006] In hybrid integrated III-V-SOA / SiPh-PIC external-cavity laser (ECL), the III-V provides the optical gain medium to the SiPh-PIC to form a laser cavity. Currently, there are three major approaches to III-V / Si chips integration. The first approach is monolithic integration by direct epi-growth of III-V on Si / SOI-substrate. The objective of this approach is to grow crystalline III-V material on Si with low defect density. This method has to address the challenge of lattice mismatch, the thermal expansion mismatch and formation of antiphase domains due to growth of polar III- V materials on non-polar Si substate. Thick buffer has been utilized to overcome lattice mismatch. Special epi-growth techniques have to be employed to overcome antiphase domain problem. This approach has been shown to be somewhat successfully only on small samples for only a subset of the III-V semiconductors. Extending this to large 200mm and 300mm wafers used in industry has been difficult.

[0007] The second commonly accepted approach is hybrid integration of III-V SOA on SiPh-PIC via butt-coupling, achievable either by active alignment or passive alignment. In hybrid integration by active alignment, III-V die to SiPh-PIC die are placed on separate alignment stages. The stages are positionally adjusted with each die electrically powered-up until lasing is detected at the output of either of the dies. Active alignment is labour-intensive, has low production throughput, and is not amenable for mass production. Hybrid integration by passive alignment employs flip-chip bonding of III-V-SOA on SiPh-PIC or interposer without the need to power up the dies . In order to achieve butt-coupling of III-V-SOA waveguide to the SiPh-waveguide with low coupling loss, an expensive specialized tool is needed to achieve submicron alignment precision of III-V to SiPh waveguides in two directions (lateral and longitudinal), with using mechanical alignment pedestal to control vertical alignment to a few 10’s nm. In addition, spot-size converters (SSC) at both the III-V and SiPh waveguides terminations are required to enlarge the buttcoupling mode-size and match the far-fields. Hybrid integration is post-wafer-fab back-end process. While it allows separate optimization of III-V material and SiPh- PIC, it has limited scalability as each laser must be individually assembled.

[0008] The third approach is heterogeneous integration wherein unprocessed and unstructured III-V dies or wafer, with epilayer facing down, is direct covalent-bonded on top of SiPh-PIC by hydrophilic bonding process, with subsequent wafer-level processing of III-V material to form gain on SiPh-PIC. It is wafer-fab level integration approach compatible to 300mm SOI wafer processing. It allows scalability as multiple III-V / Si components can be fabricated at the same time at wafer-scale processing. The active III-V on SOI can be fabricated with lithographic precision and accuracy. However, due to incompatibility of III-V and SOI substrate wafer sizes, heterogeneous integration is usually die-to-wafer covalent bonding. Bonding quality and yield are extremely sensitive to bonding surface cleanliness and availability of channels for outgassing of bonding gaseous by-products. Despite the advantages, heterogeneous integrated III-V / SOI are beset by high device thermal impedance due to the poor thermal conductivity of the SOI buried-oxide (BOX) layer, the inter-oxide layer between bonding surfaces, the absence of InP substrate, which can help thermal dissipation, due to its removal during the wafer- fab device processing. Without the mechanism to assist thermal dissipation, heterogeneous integrated III-V / SOI light emitting devices are capped from operating at high optical power. Another variant of heterogeneous integration of III-V on SOI is by adhesive bonding of III-V on SOI planarized by adhesive such as divinylsiloxane-bis-benzocyclobutene (DVS-BCB), which relaxes both the surface cleanliness and roughness requirement in comparison to direct covalent bonding. The disadvantage of adhesive bonding is its low thermal conductivity which also limits the optical power of lasers and SOA that employs such platform.

[0009] Figure 1 shows the prior-art cross-sectional structure of heterogeneous integration of III-V-SOA on Si-waveguide by direct bonding of III-V epitaxy on patterned SOI substrate. The detailed description of the process and the device structure can be found in the following prior art documents:

[0010] 1. A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “Electrically Pumped Hybrid AlGalnAs-Silicon Evanescent Laser,” Opt. Exp. Vol. 14, No. 20, p. 9203 (2006).

[0011] 2. H. Park, A. W. Fang, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “A Hybrid AlGalnAs-Silicon Evanescent Amplifier,” IEEE Photon. Technol. Lett. Vol. 19, No.4, p.230 (2007).

[0012] 3. X. Luo, Y. Cao, J. Song, X. Hu, Y. Cheng, C. Li, C. Liu, T.Y. Liow, M. Yu, H. Wang, Q. J. Wang, and P. Lo, “High-Throughput Multiple dies-to-wafer Bonding Technology and III / V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits,” Frontiers in Mat. Vol.2, No.28 p. 1 (2015).

[0013] III-V substrate 1 is bonded on patterned SOI substrate 2 by hydrophilic covalent bonding by O2-activation. The SOI substrate 2 is patterned with Si-waveguide 3 formed by fully or partially etched 3pm-wide trenches 4, 5 formed on both sides of the waveguide 3. Fully or partially etched SOI trenches 4, 5 form the Si-strip or Si- rib waveguide 3, respectively. The Si-waveguide 3 has width of 2pm and height of 0.76pm, which is the SOI 6 thickness. The bottom buried-oxide (BOX) 7 has a thickness of either 1pm or 2pm. The III-V epitaxial structure is given in Table-1 of prior art document 2. 2 pairs of N-InP / InGaAsP superlattice 8, 9 is embedded in N- InP to inhibit propagation of defects from bonded interface into the III-V active layer. After bonding, InP-substrate is selectively removed and followed by wet mesa etch which stops on N-InP cladding layer 8. The III-V mesa width is typically 12~14pm wide. The III-V active layer 10 consists of 8-pairs of AlInGaAs-based multiple-quantum-well (MQW) flanked by separate-confinement heterostructure (SCH). After bonding, both the MQW and the SCH form the active layer 10 is separated from Si-waveguide 3 by N-InP -thickness. The bonded interface 11 has 7nm-thick native oxide that holds the III-V epitaxy on the SOI surface. N-contact metal 12, 13 is, then, deposited on the exposed N-InP 8 about 40pm away from the centre of the Si-waveguide 3. 4pm -wide P-contact metal 14 is formed at the centre of the III-V mesa 1. Proton (H+) implantation were done on both sides 15, 16 of the p-mesa forming a 4pm -wide current channel 17 in the centre of the mesa, ensuring maximal optical overlap between carrier in the MQW and the optical mode 18. Current passes from P-contact 14 down the current channel 17 and spreads out through the underlying N-InP 8 channels to the N-contact 12, 13 at both sides of the mesa.

[0014] A fourth approach is micro-transfer printing. The III-V laser or SOA active layer epitaxy incorporates InGaAs or AlInAs release layer in between the active epitaxy and the bottom InP substrate. After formation of laser or SOA ridge-structure devices on the InP substrate, polymeric tethers are formed on the ridge devices. After selective removal of the InGaAs (or AlInAs) release layer by wet etch, the III-V active devices are transferred from native InP onto pre-patterned SiPh-PIC wafer using die pick-up tool. Both butt-coupling or evanescent coupling has been employed in such approach. So far, optical power from III-V / Si lasers by microtransfer printing has not been high and such approach is very much confined to academia.

[0015] In summary, the best acceptable approach for III-V / SOI integration in the industry is heterogeneous integration by die-to-wafer or wafer-to-wafer direct bonding which promises scalability. However, because of the inherently high thermal impedance of the buried oxide (BOX) in SOI-substrate and the removal of the InP native substrate, the maximum light output power is limited in comparison to conventional standard optoelectronic devices that are built on InP native substrate. This is similarly true for III-V / Si heterogeneous integration by DVS-BCB adhesive bonding, the optical power of these devices is bottlenecked by the poor thermal dissipation of adhesive and the underlying BOX. Furthermore, since InP native substrate is removed in heterogeneous integration, the III-V epitaxy is highly strained resulting in performance deviation of the optical gain. Although limited in scalability, hybrid integration by passive-aligned butt-coupling via flip-chip is well accepted in the industry for III-V / SOI devices that do not require multiple III-V flip-chip on SiPh-PIC interposer. Inherent disadvantage of passive-aligned III-V to SiPh via flip-chip is that it is dependent on expensive flip-chip machine to recognise alignment marks on the chips for accurate butt-coupling between III-V and SiPh waveguides. Despite the best performing lateral alignment accuracy of advanced flip-chip machine of ±0.3pm at 3c. there exists a wafer-level distribution of the butt-coupling loss and, hence, limited yield of good performing hybrid integrated III-V / SOI devices. In addition, high power capability of flip-chip devices is dependent on heat-dissipation and, hence, dependent on the size of the flip-chip pads. Since InP substrate is not removed, heat-spreader or thermos-electric cooler (TEC) can be attached to InP-substrate back-side after flip-chip to assist in thermal dissipation and provide high power capability.

[0016] SUMMARY OF THE INVENTION

[0017] The above-mentioned drawbacks and difficulty are overcome by the invention elaborated in the paragraphs that follow.

[0018] One aspect of the invention provides an integration process for making an external cavity laser, comprising steps of: fabricating a III-V semiconductor optical amplifier (SOA) which includes an active layer; fabricating a silicon photonic (SiPh) waveguide which includes a passive waveguide layer and an interlayer; flipping and aligning the SOA with the waveguide in a passive manner; and connecting the SOA to the waveguide by one or more flip-chip bumps, such that when said SOA is powered, an evanescent coupling is formed between the SOA and the waveguide.

[0019] Typically, the step of fabricating the SOA comprises steps of: forming a current channel on the SOA which comprises steps of: defining an opening of the current channel by photolithography; depositing a sacrificial metal on the SOA in a way such that the opening is masked; implanting hydrogen ions (H+) on the masked region of the SOA; and removing the metal from the SOA by wet etching, such that a current channel is formed; depositing a passivation dielectric layer on the side of the SOA proximal to the active layer; and depositing a P-metal contact on the opposing side of the SOA.

[0020] In one embodiment, the step of fabricating the SOA also comprises steps of: forming an opening in the passivation dielectric layer by photolithography; depositing an N-metal contact in the opening; depositing an under-bump metallization (UBM) layer on the N-metal contact; depositing a solder metal as part of a flip-chip bump on the UBM layer.

[0021] In another embodiment, the step of fabricating the SOA also comprises steps of: cleaving the SOA into a plurality of bars; depositing an anti-reflection coating on facets of the bars; and cleaving the plurality of bars into a plurality of dies.

[0022] Typically, the step of fabricating the waveguide comprises steps of: defining and forming by photolithography a ridge capable of transmitting an optical mode in the passive waveguide layer; and subjecting the waveguide to a high temperature annealing such that the propagation loss of the waveguide is reduced.

[0023] In another embodiment, the step of fabricating the waveguide also comprises steps of: defining a channel in the passive waveguide layer and the interlayer by photolithography; forming the channel by dry etching; depositing a trace metal in the channel; depositing an under-bump metallization (UBM) layer on the trace metal; and depositing a solder metal as part of the flip-chip bump on the UBM layer.

[0024] Another aspect of the invention provides an external cavity laser comprising a III- V semiconductor optical amplifier (SOA) and a silicon photonic (SiPh) waveguide, wherein said SOA is aligned and connected to said waveguide by one or more flip- chip bumps, such that when said SOA is powered, an evanescent coupling is formed between said SOA and waveguide.

[0025] Typically, said SOA comprises an N-InP cladding and an N-metal contact, two under-bump metallization (UBM) layers each of which is configured on an opposing end of each of the flip-chip bumps, and said N-metal contact is sandwiched between said N-InP cladding and the UBM layer on the proximal end.

[0026] Typically, a passivation dielectric layer is configured adjacent said N-InP cladding to prevent surface leakage current outside one or more predetermined current channels.

[0027] In one embodiment, said SOA also comprises a P-InP substrate and a P-metal contact configured on said P-InP substrate, said P-InP substrate providing mechanical stability to the flip-chip bumps.

[0028] Typically, said waveguide comprises a passive waveguide layer and an interlayer, configured adjacent each other, said passive waveguide layer being a dielectric, refractive index of which is higher than that of said interlayer.

[0029] In another embodiment, said SOA also comprises a P-InP cladding, and an active layer sandwiched between said P-InP and N-InP claddings; and said waveguide also comprises a silicon substrate configured adjacent said interlayer, a trace metal layer being sandwiched between the UBM layer on the other end and said silicon substrate; such that heat generated from said active layer can be dissipated through said silicon substrate and / or said P-metal contact.

[0030] Typically, said passive waveguide layer is either silicon (Si), silicon nitride (SiN), orthin-film lithium -niobate (TFUN).

[0031] Typically, the passivation dielectric layer has a thickness between 5 to 7 nm.

[0032] Typically, two elongate depressions are defined in said passive waveguide layer, said depressions being open toward two facets of said passive waveguide, a ridge capable of transmitting an optical mode being formed between said depressions, wherein said ridge flares toward the facets such that optical confinement in said SOA is reduced. Typically, said ridge is defined at an angle from the normal incidence, and an antireflection coating is deposited on the input and output facets of said SOA, such that reflection is minimised.

[0033] Another aspect of the invention provides an external cavity laser module comprising: the external cavity laser as described in the preceding paragraphs; a loop or Sagnac reflector being connected to one end of said ridge; and a Vernier filter being connected to the other end of said ridge; such that a low-noise narrow- line-width (NLW) laser can be emitted at the output of the module.

[0034] Another aspect of the invention provides an external cavity laser module comprising: a first external cavity laser as described in the preceding paragraphs; and one or more other external cavity lasers, each as described in the preceding paragraphs, connected to said first external cavity laser in a consecutive manner such that the optical power at the output of the integration is boosted.

[0035] Another aspect of the invention provides a III-V on photonic-circuit integration process comprising steps of: fabricating a III-V semiconductor optical amplifier (SOA); fabricating a photonic circuit on interposer; and connecting the SOA to the photonic circuit on interposer by one or more flip-chip bumps, such that when said SOA is powered, an evanescent coupling is formed between the SOA and the photonic circuit on interposer.

[0036] In contrast to the conventional case of using butt-coupling of III-V and Si-photonics waveguide terminations in hybrid integration, the invention refers to hybrid integration by passive alignment via evanescent coupling which can potentially relax the coupling accuracy requirement in butt-coupling. By relaxing the buttcoupling accuracy requirement, this obviates the need for use of expensive flip-chip machines for accurate III-V-to-SiPh waveguide terminations alignment, as well as the need to design edge-couplers or spot-size-converters on both III-V and SiPh terminations. Conventionally, evanescent coupling has been utilized in heterogeneous-integrated III-V / SOI SOA wherein, only the evanescent tail of the Si-photonic waveguide mode experiences the III-V gain giving rise to low confinement factor and resulting in high saturation output power of the SOA. In the invention, III-V / SOI evanescent-coupling is also enabled and utilized in hybrid integration, wherein the III-V active layer is placed in close proximity to the SiPh- waveguide by physical contact brought together by flip-chip bonding. Light experiences amplification as it passes through the III-V-on-SiPh- waveguide section of the PIC with III-V active layer above it. Current flow in III-V active material is confined and controlled by H+proton-implant, which typically, has a stripe opening width of ~4pm. The width of the SiPh waveguide is typically 1.0-2.5pm. Hence, there is ample misalignment tolerance between SiPh-waveguide and III-V gain section.

[0037] For III-V / SOI PIC that does not require multiple III-V devices on the SiPh circuit, hybrid integration by passive alignment via flip-chip process with relaxed coupling accuracy can prove to be a cost viable solution for a sub-class of SiPh-PIC integrated with a single SOA block for light amplification. This is especially true for NLW SiPh or SiN based external cavity tuneable laser as a component. In contrast to heterogeneous integration, the InP substrate is not removed after hybrid integration by flip-chip to provide the mechanical support for the flip-chip bumps. This also gives additional advantages of better thermal dissipation, lower through- substrate electrical-resistive path, and preserving the III-V epitaxy as it is intended on its native InP substrate. These will be further explained in the next section.

[0038] While reaping the benefits of hybrid integration, evanescent coupling is utilized instead of butt-coupling, to relax the requirement for tight alignment tolerance of III-V to SiPh waveguide terminations. III-V / SOI hybrid integration via flip-chip with passive alignment utilizing evanescent coupling has not been employed in the industry or academia before.

[0039] Advantages and improvements over existing methods, devices or materials

[0040] Passive-aligned III-V / SOI hybrid integration via flip-chip utilizing evanescent coupling is considered an intermediate solution between hybrid integration by passive-aligned butt-coupling and heterogeneous integration. The passive-aligned III-V / SOI hybrid integration via flip-chip utilizing evanescent coupling has the following advantages: a. By using hybrid integration, the III-V epitaxy and the SiPh can be separately optimized so that known-good-dies (KGD) of each type can be selected for III-V- to-Si integration. For example, in hybrid integrated III-V / SOI ECL, the lower the SiPh waveguide propagation loss, the lower is the ECL linewidth. At the front-end of line (FEOL) of wafer-fab processing of SiPh-PIC, the SiPh-PIC can undergo high temperature annealing at temperature of 900~1000°C, which reduces waveguide propagation loss, improves the quality (Q) factor of SiPh resonator in the SiPh-PIC, and lowers the ECL linewidth when integrated to III-V gain-chip. For heterogeneous integration, this may not be conveniently done either before or after III / V-to-Si direct covalent bonding. If high temperature anneal is done prior to bonding, III-V material is difficult to be bonded to SiPh-PIC due to slight deformation of the Si-waveguide after the anneal. Also, high-temperature anneal cannot be done after bonding due to limited thermal budget since III-V material on Si would have changed characteristics due to high temperature process. Hence, hybrid integration offers advantage for high performing integrated III-V / SOI devices employing the best of SiPh and III-V materials. b. In hybrid integration, by employing evanescently coupled III-V gain material to SiPh-waveguide, it relaxes the tight alignment tolerance between III-V gain-chip waveguide and the SiPh-waveguide. The tight alignment tolerance is a key requirement of butt-coupled integration scheme. The typical width of Si waveguide in SiPh-PIC is 0.5pm to 2.5pm. When evanescent coupling is employed, the SiPh-waveguide runs parallel in close physical contact to the III-V active stripe. The III-V active medium is a wide proton (H+)-implanted III-V mesa except rectangular stripe masked off during the H+implant. Current is injected into the wide III-V mesa with H1implant providing current confinement. The typical width of rectangular active stripe without the H+implant is 4±0.5pm. There is ample misalignment tolerance between SiPh-waveguide and III-V gain section. This obviates the need for expensive flip-chip tool for accurate alignment between III-V and SiPh waveguides, as in the case of passive-aligned butt-coupling via flip-chip. For passive-aligned evanescent coupled hybrid-integration via flip-chip, flip-chip machine of lower capital expenditure can be employed. c. In butt-coupling of III-V waveguide to SiPh-waveguide, mode-size and beam divergence mismatch limits the coupling efficiency between III-V and SiPh waveguide terminations. Edge-couplers or SSC’s have to be designed for III-V waveguide and SiPh waveguide terminations to match the mode-size, mode-shape and also the beam divergence angle (or far-fields) to reduce the coupling loss. The best performing butt-coupling loss is 0.8-1.5 dB. Typical butt-coupling loss for most common hybrid-integrated III-V to SiPh waveguide terminations is 2~4dB. High butt-coupling loss results in high threshold current, low slope efficiency, and poor wall-plug-efficiency, for hybrid integrated III-V / SOI ECL. In addition, the designed edge-coupler or SSC are unique to the foundries from which III-V and SiPh-PIC came from. Currently, there is no standardized waveguide edge-coupler or SSC for III-V and SiPh across the industry. In contrast, for passive-aligned hybrid integration through evanescent coupling via flip-chip, evanescent coupling efficiency between III-V to SiPh has efficiency is better than 90%. Evanescent coupling efficiency is controlled by the structural dimensions of SiPh waveguide and the III-V epi-layer thicknesses. For evanescent coupling, since majority of the optical mode resides in the SiPh-waveguide, the mode reflectance at the entrance and exit of the III-V / SOI gain block is minimal and can be reduced by tilting the SiPh waveguide direction away from the normal to the III-V facets. Further elaboration of reflectance will be given in the next section. d. In heterogeneous integration, after direct hydrophilic covalent bonding of III-V epi-wafer to the patterned SOI substrate, the InP substrate is selectively removed leaving the III-V active epi-layers bonded on the patterned SOI substrate through a thin SiO2 interlayer (thickness~7nm). Due to the large mismatch in the coefficients of thermal expansion between III-V epi-layer and Si, the III-V epi-layer can be highly strained results in deviation in gain performance and also possible early degradation. In contrast, for hybrid integration via flip-chip utilizing evanescent coupling, the SiPh waveguide and the III-V epi-structure is kept similar to that of the heterogeneous integration, only that III-V is in close physical contact with the SiPh waveguide but not bonded together. Hence, in the III-V epi-structure, there is no need of the InP / InGaAsP superlattice in the bottom N-InP layer which was utilized to inhibit propagation of defects and dislocations from bond-interface as in the case of direct bonding in heterogeneous integration. Also, there is no concern for large mismatch in the coefficient of thermal expansion between III-V and Si. e. For hybrid integration utilizing evanescent coupling, the InP substrate is not removed after flip-chip bonding of III-V die to patterned SOI substrate. The InP substrate provides mechanical support to the flip-chip bumps so that III-V wafer is not warped by stress / strain due to the flip-chip bumps. In addition, the original characteristics of III-V epitaxy is preserved as it was originally intended since it is maintained on its native InP substrate. Unremoved InP substrate offers further advantages of providing better path for thermal dissipation, improving the thermal conductivity, and potentially allowing higher maximum drive current and higher optical output power, since these are limited by device self-heating. In similarity to the heterogeneous integration, the hybrid integration utilizing evanescent coupling also utilizes P+InP substrate and bottom N-InP in physical contact with SiPh- waveguide. By wire-bonding on the backside of the P+InP substrate with P-contact- metal, the InP substrate also provides lower through-substrate electrical-resistance potentially giving low operating forward voltage. It allows the III-V SOA or gainchip perform almost nearly the same as in original devices on native InP substrate. Alternatively, the back-side of the P+InP substrate deposited with TiAu P-contact metal can be bonded to thermos-electric-cooler (TEC) by conductive epoxy for temperature control and electrical contact. This is elaborated further in the next section.

[0041] The ability to integrate III-V SOA with high gain and saturation power on PIC that bases on Si / SiOa or SiN / SiO2 waveguide is a key significant capability with many possibilities.

[0042] DESCRIPTION OF THE PREFERRED EMBODIMENT

[0043] The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which:

[0044] Fig. 1 is a cross-sectional structure for a heterogeneously integrated III-V Silicon Optical Amplifier (“SOA”) and Silicon-On-Insulator (“SOI”) waveguide of a laser as disclosed in prior art;

[0045] Fig. 2 is a schematic diagram for a cross section of a passively aligned, evanescently coupled, III-V to SOI passive waveguide hybrid integration using flip-chip method, according to the invention; Fig. 3 is a schematic diagram for a cross section of a passively aligned, evanescently coupled, III-V to SiN passive waveguide hybrid integration using flip-chip method, according to the invention;

[0046] Fig. 4 is the top view of a III-V gain chip with an underlying tilted passive waveguide with an enlarged width at the facet-crossing region, according to the invention;

[0047] Fig. 5 is a graph comparing the power reflectance vs waveguide tilt-angle for a Si- waveguide of a width of 2pm and 2.5pm as light passes through a III-V gain block facet;

[0048] Fig. 6 shows a III-V epi-side down to be flip-chipped on an interposer Si-substrate;

[0049] Fig. 7 shows a III-V epi-side down flip-chipped on an interposer Si-substrate, the AuSn-solders having merged into a single solder bump;

[0050] Fig. 8 is a Fabrication Process Flow depicting the preparation of a III-V chip and a Si-interposer substrate for flip-chip bonding;

[0051] Fig. 9 is an integration of a III-V gain block (denoted as 75) having an S-shaped waveguide, and a PIC-based Vernier fdter denoted as 76, to form an external cavity laser (“ECL”);

[0052] Fig. 10 is an integration of a III-V gain block (denoted as 79) having a tilted straight waveguide, and a PIC -based Vernier fdter denoted as 80, to form an ECL;

[0053] Fig. 11 is an integration of a III-V gain block (denoted as 83) having an S-shaped waveguide, a Photonic Integrated Circuit (“PIC”) fdter (denoted as 84) being the back reflector, and a Sagnac reflector being the front reflector;

[0054] Fig. 12 is an integration of two III-V gain blocks denoted as 89 and 87, and a PIC fdter denoted as 90;

[0055] Fig. 13 is an integration of tuneable narrow linewidth (“NLW”) ECL comprising an SOA array for boosting its optical power; Fig. 14 is a schematic diagram showing a side view of a laser module including a stack-up of components which comprises a hybrid integration of a III-V SOA on an interposer Si-substrate; and

[0056] Fig. 15 is a schematic diagram showing a top view of a laser module including a stack-up of components which comprises a hybrid integration of a III-V SOA on an interposer Si-substrate.

[0057] Description of the ECL According to the Invention

[0058] The invention refers the hybrid integration of passively-aligned III-V active medium with passive-waveguide by evanescent coupling via flip-chip bonding, wherein the passive waveguides are formed and patterned on Si-base substrates. In general, the passive waveguide can be based on Si, SiN, thin-fdm lithium niobate (TFLN) or other passive materials formed on buried-SiO2 (BOX) on Si-substrate. In particular, Figure 2 and Figure 3 shows the schematic cross-section of III-V / Si and III-V / SiN waveguides, respectively. The passive-waveguide 48 in Figure 3 can also be TFLN. Conventionally, hybrid integration by passive alignment via flip- chip is through butt-coupling of III-V waveguide to Si or SiN passive waveguide terminations. In this invention, the Si or SiN waveguide on SOI substrate 21, 40 is continuously and evanescently coupled to the III-V strip active medium 19, 38 that runs parallel to it. In contrast to the conventional III-V / Si heterogeneous integration that relies on direct covalent bonding, there is no chemical bond between the III-V

[0059] 23, 42 to the underlying passive waveguide 24, 43 in this invention. The Si or SiN (or other passive materials) waveguide 29, 48 is held in physical contact to the III- V active strip 23, 42 by flip-chip bumps 70, 71, 72, 73. The absence of interfacial chemical bond in this invention allows the coupling of III-V gain-medium 23, 42 to not only Si -waveguide 24, but also other types of passive-waveguide 43 base on materials such as SiN, thin-film lithium-niobates (TFLN), and others. This is advantageous since there is no limitation on maximum optical power in passive waveguide due to two-photon absorption limitation as in the case of Si-waveguide

[0060] 24. Compared to the heterogeneous integration by direct bonding as depicted in Table- 1 of prior art document 2, the III-V epitaxial structure of the invention does not need 2 pairs of InP / InGaAsP superlattice embedded in the N-InP to inhibit upward propagation of defects, since there is no chemical bond between III-V surface with Si or SiN or other passive-material surface, that can induce threading dislocations. For the particular case of III-V / Si (Figure 2), the Si-waveguide 29 is formed by fully or partially etched 3~5pm-wide trenches 30, 31 into the Si device layer 20, with the space between the trenches 30, 31 forming the width of the Sistrip or Si-rib waveguides 29, respectively.

[0061] In this invention, the III-V epitaxy on InP-substrate 32, 33, 51, 52 is flipped episide down and flip-chip bonded to the Si (or SiN or other passive)-waveguide interposer substrate, without removing the InP substrate 32, 33, 51, 52. This is to provide mechanical strength and stability to the flip-chip bumps 70, 71, 72, 73 while allowing the active layer 19, 38 epitaxy to be retained in its original state on its native InP-substrate 32, 33, 51, 52, as shown in Figure 2 and Figure 3. The absence of the chemical bonds at the interface between III-V 23, 42 and underlying passive waveguide 24, 43 also ensures absence of interfacial defects to degrade the active layer 19, 38, e.g. MQW. In conventional heterogeneous integrated III-V / SOI SOA and diode-lasers (LD), the interfacial oxide, the buried-oxide in the SOI, and the absence of InP substrate contributes to high thermal impedance, limits maximum operating current and maximum output power. In contrast, in this invention, the presence of InP substrate 32, 33, 51, 52 and the flip-chip bumps 70, 71, 72, 73 both provide thermal dissipative paths that lower the overall device thermal impedance and potentially can increase the maximum operating current and optical power. In addition, the InP-substrate 32, 33, 51, 52 is P-type with P-metal 33, 52 on the back of the p-InP substrate 32, 51. The InP-substrate 32, 33, 51, 52 provides lower through-substrate electrical-resistance potentially giving low operating forward voltage. In conventional heterogeneous III-V / SOI structure (Figure 1), since the N- metal 12, 13 has to be built outside the 12~14pm-wide III-V mesa 1, electrical current has to travel a long N-InP 8 lateral channel to reach the N-metal 12, 13 outside the mesa 1. In this invention, since the flip-chip bumps 70, 71, 72, 73 that sits on the N-metal 34, 35, 53, 54 that contacts the N-InP 36, 55, are built underneath the III-V mesa 23, 42, the N-InP 36, 55 electrical channel length through which current flows to reach N-metal contact 34, 35, 53, 54 can be designed to be shorter in comparison to conventional heterogeneous integrated III-V / SOI structure. Hence, this invention is likely to offer a lower operating forward voltage. Since in evanescent coupling, majority of the optical mode 37, 56 is in the passivewaveguide 29, 48 (in particular Si or SiN waveguide), facet reflection is minimal when light passes out of the III-V gain block. To further minimize optical feedback due to facet reflection as passive waveguide 29, 48 passes through the III-V gain block facet, the passive waveguide 29, 48 is tilted from normal incidence to the facet, as shown in Figure 4. In addition, the passive waveguide 29, 48 width is enlarged adiabatically to 2.5~3pm at the facet region to reduce the optical mode confinement in the III-V to reduce facet reflection. Figure 5 shows the calculated facet power reflectance vs tilt angle for 700nm-thick Si-waveguide 29, 48 for widths of 2pm and 2.5pm, and using Lumerical Finite-Difference-Time-Domain (FDTD). When 2pm-width Si-waveguide 29, 48 is tilted at 12° from the normal incidence, the facet optical power reflectance is about -28dB. At 12°-tilt, the facet reflection can be further reduced to -29.5dB by increasing the Si-waveguide width to 2.5pm. The Si-waveguide 29, 48 width is tapered back down to 2pm-wide after passing through the facet. Such residual reflectance typically gives typical ripple of 0.1~0.2dB in the optical gain spectrum which is sufficient low for SOA operation. Facet reflection can be even lower if thicker Si thickness is utilized. In addition, anti-reflection (AR) coating (e.g. Ta2Os) can be applied to the SOA facet prior to flip-chip bonding process to further minimize reflectance.

[0062] In this invention, the buried-SiO2 22, 41 thickness is typically 2pm to allow sufficient thickness to accommodate the thicknesses of the trace-metal 57, 58, 63, 64 on the interposer Si-substrate 21, 40, the N-metal 34, 35, 53, 54 on the III-V chip 23, 42, the AuSn solder 70, 71, 72, 73 and the under-bump metallization (UBM) 59, 60, 61, 62, 65, 66, 67, 68 deposited on both the III-V chip 23, 42 and the interposer Si-substrate 21, 40. Figure 6 shows schematically the III-V epi-side down to be flip-chip bonded on the interposer Si-substrate 21. Figure 7 shows post-flip- chip structure at the flip-chip bumps 71. Prior to flip-chip, a 5~7nm-thick passivation dielectric (SiCh or SiN) 69 is deposited on the epi-side of the III-V chip 23. Opening in passivation dielectric 69 is etched and N-metal 35 is formed on the N-InP 36. The 5~7nm thick passivation dielectric 69 is to prevent surface leakage current to ensure current flows only through the N-InP channel. On the patterned interposer Si-substrate 21 , passive-waveguide layer 20 and buried-SiO222 is etched away and followed by trace-metal 58 (typically TiAu) deposition. After deposition of UBM 61, 62 on both sides, AuSn solder 27, 28 are deposited on both the III-V N-metal 35 and the trace-metal 58 on interposer Si-substrate 21. The typical UBM 61, 62 can be TiPtAu, wherein Ti provides adhesion while Pt is a barrier metal. The AuSn thickness must be carefully controlled to ensure bump-bump compression while not overflow to the edge to cause electrical shorts. AuSn should be slightly Sn-rich to offset the amount of Au in the UBM 61, 62 to ensure 80Au-20Sn to meet eutectic requirement.

[0063] Description of the Fabrication Process

[0064] The fabrication process flow is shown in Figure 8. The fabrication process flow consists of two parallel preparation processes for the III-V chip and the interposer Si-substrate, finally ends in flip-chip of III-V die epi-side down on the Si-substrate. The fabrication process herein is described for the particular case of Si-waveguide 20 on interposer substrate 22. In general, SiN, TFUN or other dielectric can also be the material of the passive-waveguide.

[0065] Compared to the III-V epi-wafer as disclosed in Table- 1 of the prior art document 2, the III-V epi-wafer of the invention does not have 2 pairs of InP / InGaAsP superlattice in the N-InP. Also referring to Figure 2 and Figure 3 for the parts, the First step in the III-V wafer processing is the definition and formation of current channel 75, 106 with proton (H+) implanted region 76, 77, 107, 108 being the current blocking region. 4pm-wide sacrificial Ti / Au metal strip is patterned and deposited on the epi-surface. The wafer is sent for H+implantation. The area 76, 77, 107, 108 beneath Ti / Au metal, being the mask for H+implantation, forms the current channel 75, 106. After H+implantation, the TiAu is etched away, followed by deposition of 5~7nm passivation dielectric 69, 74 which can be SiCh or SiN. Both N-metal and fiducial marks are then patterned on the III-V epi-wafer. After dry etch of passivation dielectric 69, 74 in the N-metal region, the N-metal 34, 35, 53, 54 the UBM 59, 61, 65, 67 and the AuSn-solder 25, 27, 44, 46 is deposited and lifted-off. The fiducial marks must be printed on the III-V epi-wafer for each die to facilitate flip-chip of III-V die 23, 42 on interposer Si-substrate 24, 43. After deposition of metals, the III-V wafer is cleaved into bars for anti-reflection coating prior to cleaving into dies for flip-chip. The first step in processing the interposer Si-substrate 24, 43 is the definition and formation of either strip or rib Si (SiN, TFLN or others) waveguide by fully or partially etched trench 30, 31, 49, 50 into the device layer. Typical width of the trench 30, 31, 49, 50 is 3~5pm. For the Si-waveguide 29 interposer substrate, step- 2 consists of subj ecting the wafer through a high temperature H2 annealing to reduce the propagation loss. In general, this step-2 represents generically a process module to refined the passive-waveguide 29 with lower propagation loss. The next step-3 is the definition and formation of trench opening in the interposer Si-substrate for trace-metal 57, 58, 63, 64 (typically, Ti / Au). This trench is formed by etching through the Si (SiN, TFLN or other dielectric) device layer 20, 39, the BOX 22, 41, and stop on the interface between BOX 22, 41 and Si-substrate 21, 40 surface. After deposition and lift-off of trace-metal 57, 58, 63, 64, the UBM 60, 62, 66, 68 and AuSn-solder 26, 28, 45, 47 are deposited and lifted-off using a separate mask such that these are to be localized underneath the III-V chip 23, 42, and matched exactly with the patterns of the N-metal 34, 35, 53, 54 of the III-V chip 23, 42. Fiducial marks are to be formed at the same time as the trace-metal trench. Fiducial marks are for alignment with that of III-V chip 23, 42 during flip-chip process. As shown in Figure 7, after the flip-chip process, the AuSn 27, 28 on both the III-V and Si- interposer substrate 21 merges as a single solder bump 71. The flip-chip can be either die-on-die or die-on-wafer.

[0066] The alignment of fiducial marks on both the III-V chip 23, 42 and the Si-interposer 24, 43 must be accurate enough such that the edge of the H+implant, that defines the current channel 75, 106 on the III-V is within the Si (SiN, TFLN or others)- trench 30, 31, 49, 50 that defines the device-waveguide 29, 48. The geometrical shape of the H+implant defined current channel 75, 106 must follow and match to that of the Si (SiN, TFLN or others) waveguide 29, 48. This alignment is shown in Figure 9, Figure 10, Figure 11 and Figure 13, wherein the fiducial marks 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 are indicated by the dashed-cross signs at the four comers of the die. These fiducial marks are printed and etched on the epi-side of the III-V die, as well as the surface of the SOI of SiPh chip. (These fiducial marks are underneath on the epi-side of the die after the flip-chip process). The passive-aligned hybrid integration of II I / V gain medium 23, 42 with passivewaveguide on interposer Si-substrate 24, 43, wherein there is no limitation on the type of dielectric material for passive-waveguide 20, 39 offers many design and product opportunities. The 11 I / V gain block with well-managed thermal dissipation offers high power capability on PIC. In this specification, embodiments are provided to illustrate its first application in ECL.

[0067] Embodiment 1

[0068] Figure 9 shows an embodiment of hybrid integrated III-V gain block 75 on interposer Si-substrate 78 patterned with block 76, which consists of a generic Si- photonic Vernier filter. The III-V gain-block 75 utilizes waveguide running in the normal incidence direction with bending at 12°-tilt from normal-incidence to the III-V gain block exit facets. The dashed lines in the III-V gain block 75 depicts the H+implant edge that defines the current channel. The Si-waveguide underneath aligns with the current channels. Current flows from back-side of the III-V gain block 75 through the current channel and laterally to the N-contact at the flip-chip bumps 77. In block 75, the waveguide exits left-facet of the III-V gain block 75 and terminates at a loop reflector which gives reflectance of almost 100%. III-V gain block 75 together with the loop-reflector forms the gain-chip for the ECL.

[0069] The design in block 76 (as enclosed by the dashed-box) is generic. In Figure 9, block 76 shows atypical filter which is instanced by dual-micro-ring Vernier filter for narrow-line -width ECL. Block 76 can consist of any other filter design which can be instanced from prior art. In addition, it can also be instanced from a typical triple micro-ring design from prior art. The details of the operation of Vernier filter are reported in prior art.

[0070] The focus of the specification is on hybrid integration of III-V on interposer Si- substrate by evanescent coupling as depicted in block 75.

[0071] Embodiment 2

[0072] Figure 10 shows another embodiment of hybrid integrated III-V gain block 79 on interposer Si-substrate 82 patterned with similar block 80, which consists of a generic PIC Vernier filter. The III-V gain-block 79 utilizes a straight waveguide with a tilt angle of 12° or any other angles from normal incidence to the gain block exit facets, such that the facet reflections is not significant to cause severe optical feedback to bring SOA gain spectral ripple more than 0.5dB. The Si (or SiN, TFLN or other dielectric) waveguide underneath aligns with the current channel as delineated by H+implant boundaries. Similar to the embodiment 1 in Figure 9, the III-V gain block 79 terminates with a loop mirror after exit from the left-facet. The flip-chip bumps 81 are designed to accommodate the geometry of the slanted waveguide.

[0073] For both embodiment 1 (Figure 9) and embodiment 2 (Figure 10), since the optical emission is output from passive-waveguide of block 76, 80 (the PIC -based filter), the near-field profile is almost circular easily coupled to lensed fibre. If Si waveguide is utilized in the interposer substrate, maximum optical power can be limited by 2-photon-absorption. On the other hand, maximum optical power is not capped if SiN-waveguide on the interposer is utilized.

[0074] Embodiment 3

[0075] Figure 11 shows another embodiment of hybrid integrated III-V gain block 83 on interposer Si-substrate 85 patterned with block 84 which is instanced with another type of dual micro-ring Vernier filter. Utilizing a loop-mirror M2, block 84 forms a tuneable back-reflector to III-V gain block 83. Sagnac loop-mirror Ml with controllable reflectance is utilized as the front-reflector 86 to control the desired optical output power, with optical emission coming from the III-V gain block side of the interposer. The Sagnac loop mirror consist of a directional coupler with its branches tied together at one end. The reflectance of the Sagnac loop mirror, and hence, the output power of the ECL, can be accurately tuned by adjusting the length of the directional coupler in the Sagnac loop mirror Ml . The details of the working principle of block 84 can be found in prior art.

[0076] Embodiment 4

[0077] Figure 12 addresses the consideration for the need of high optical power output to satisfy product specifications, with additional integration of III-V gain block 87 to function as booster optical amplifier (BOA). As shown in Figure 12, the ECL laser cavity 88 consists of the left-facet loop-mirror M2, III-V gain block 89, the two micro-rings in the Vernier-filter of block 90. The transmittance (or reflectivity) of directional coupler M3 in block 90 determines how much power is circulating in the laser-cavity, and hence, how much output optical power from the ECL. Specific requirements in ECL laser characteristics such as linewidth, cavity loss, thresholdcurrent and slope-efficiency determine the value of reflectivity or the coupling efficiency of M3, resulting in a low output power. To achieve higher power, additional III-V gain block 87 can be integrated to function as BOA on the interposer Si-substrate 91. This obviates the need to add stand-alone BOA outside the interposer Si-substrate 91 by lens-coupling which can increase packaging cost. The trace-metal in block 89 is not included in Figure 12 for the sake of simplicity.

[0078] Embodiment 5

[0079] The embodiment in Figure 13 shows the advantage of using photonic integrated circuit in conjunction with the hybrid integrated III-V SOA-array in block 92 to boost the optical output power. In this particular example in Figure 13, the Ml loop- reflector, SOA and block 93 forms the laser cavity of the ECL. By looping back the optical power in the waveguide through BOA1 and BOA2, the optical power can be boosted to higher power. The waveguide material in this example is dielectric (preferably SiN) other than Si so that 2-photon absorption is not a power limiter. The dual-ring Vernier filter in block 93 shown in Figure 13 is only a particular instance of passive PIC filter. In general, block 93 can be replaced by more sophisticated functional PIC. The trace-metal in block 92 is not included in Figure 13 for the sake of simplicity.

[0080] Packaging of Hybrid Integrated III-V on Si-Interposer

[0081] The active layer in III-V single-SOA and SOA-array in Figure 9 through Figure 13, which are providing optical gain under laser action, are source of heat generation. Successful thermal dissipation helps to mitigate self-heating and ensures high power operations. Referring to Figure 14 and Figure 15, in this invention of hybrid integrated III-V on interposer Si-substrate 94 by evanescent coupling via flip-chip

[0082] 95, the InP-substrate 96, 97 is not removed. The underlying BOX 98 in the interposer Si-substrate is a highly thermal insulating layer. Both the InP-substrate

[0083] 96, 97 and the flip-chip bumps 95 are the main conduits for thermal dissipation. Figures 14 and 15 show schematic cross-section and top-view, respectively, of the possible layers stack-up in packaging the hybrid integrated III-V chip on interposer Si-substrate. Thermal electric cooler (TEC) 99 can be bonded to the back-side of the P-metal 100 -deposited InP substrate 96, 97 to extract heat from the InP substrate 96, 97. The back-side of the TEC 99 is in contact with the chassis bonded with heat-sink 101. For the case of uncooled laser module, the TEC 99 is replaced by a thermally conductive heat spreader providing thermal path to the heat-sink 101. Wire-bonding 102 is employed to electrically connect the P-contact 100 on the back of InP substrate 96, 97 to a bond-pads 106 on the interposer Si-substrate 94. In addition, the flip-chip bumps 95 in the vicinity of the III-V gain region helps to dissipate heat to the trace-metal 103 on the interposer substrate 94. Since flip-chip bumps 95 are built beneath the III-V mesa 104, the distance of flip-chip bumps 95 to gain region can be as short as possible to shorten not only the electrical channel length in the N-InP 105, it also shortens the thermal dissipative path length.

[0084] Commercial applications of the invention

[0085] The key distinctive advantage of evanescently-coupled hybrid integration of III-V on interposer Si-substrate lies in the potential ability to deliver high optical power since there is no limitation on the type of interposer passive-waveguide to be used in comparison to the conventional heterogeneous integration by direct covalent bonding of III-V on Si. The use of direct covalent bonding requires the use of Si- waveguide in the interposer substrate, and Si-waveguide inherently has optical power limiter due to 2-photon absorption. In comparison to the conventional butt- coupled hybrid-integration (whether by active or passive alignment), evanescently coupled hybrid integration overcomes the difficulty of butt-coupling of III-V to passive-waveguide, enhances the resistance to variation due to shock and vibration, improves coupling repeatability, relaxes the alignment accuracy requirement and hence, improves the manufacturing throughput as well as lower the packaging cost.

[0086] ECL that based on evanescently-coupled hybrid integrated III-V on Si-photonic PIC enjoys the advantages of both hybrid and heterogenous integration approaches while satisfies the requirements for SWaP and cost. The compact footprint coupled with high performance NLW of III-V on Si-photonic ECL potentially can serve the markets of conventional bulky NLW lasers while open new markets that require small form-factor. The immediate application is tuneable NLW laser for pluggable coherent optics transceivers for data-centre interconnect base on coherent communications. In addition, tuneable NLW lasers are increasingly applied in medical application and absorption spectroscopy.

[0087] Although this specification focuses on application of evanescently-coupled hybrid integration of III-V / Si on NLW tuneable ECL, it can also be applied to other PIC- based functional photonic devices that require high power emission. One such possible application is FMCW-LIDAR, which requires not only NLW tuneable laser coupled with optical phase-array, but also needs reasonably high emitted optical power as system detection range scales with emitted power. In prior art, for Si-photonic-PIC based FMCW LIDAR, the laser source is external and coupled to the Si-photonic PIC through grating -coupler which has typical coupling loss of 1 to 2dB but with limited bandwidth 35~40nm. The evanescently coupled hybrid III-V to passive-waveguide integration enables a sub-ldB low coupling loss, allows on- chip laser source integration not just on Si-Photonic but also other passivewaveguide based FMCW LIDAR, able to deliver high emitted power. It will be appreciated by persons skilled in the art that the present invention may also include further additional modifications which does not affect the overall functioning thereof.

Claims

CLAIMS1. An integration process for making an external cavity laser, comprising steps of: fabricating a III-V semiconductor optical amplifier (SOA) (23) which includes an active layer (19); fabricating a silicon photonic (SiPh) waveguide (24) which includes a passive waveguide layer (20) and an interlayer (22); flipping and aligning the SOA (23) with the waveguide (24) in a passive manner; and connecting the SOA (23) to the waveguide (24) by one or more flip-chip bumps (70, 71), such that when said SOA (23) is powered an evanescent coupling is formed between the SOA (23) and the waveguide (24).

2. An integration process for making an external cavity laser as claimed in claim 1, wherein the step of fabricating the SOA (23) comprises steps of: forming a current channel on the SOA (23) which comprises steps of: defining an opening of the current channel (75) by photolithography; depositing a sacrificial metal on the SOA (23) in a way such that the opening is masked; implanting hydrogen ions (H+) on the masked region of the SOA (23); and removing the metal from the SOA (23) by wet etching, such that a current channel (75) is formed; depositing a passivation dielectric layer (69) on the side of the SOA (23) proximal to the active layer (19); and depositing a P-metal contact (33) on the opposing side of the SOA (23).

3. An integration process for making an external cavity laser as claimed in claim 2, wherein the step of fabricating the SOA (23) also comprises steps of:forming an opening in the passivation dielectric layer (69) by photolithography; depositing an N-metal contact (34, 35) in the opening; depositing an under-bump metallization (UBM) layer (59, 61) on the bimetal contact (34, 35); and depositing a solder metal (25, 27) as part of a flip-chip bump (70, 71) on the UBM layer (59, 61).

4. An integration process for making an external cavity laser as claimed in claim 3, wherein the step of fabricating the SOA (23) also comprises steps of: cleaving the SOA (23) into a plurality of bars; depositing an anti-reflection coating on facets of the bars; and cleaving the plurality of bars into a plurality of dies.

5. An integration process for making an external cavity laser as claimed in claim 1, wherein the step of fabricating the waveguide (24) comprises steps of: defining and forming by photolithography a ridge (29) capable of transmitting an optical mode (37) in the passive waveguide layer (20); and subjecting the waveguide (24) to a high temperature annealing such that the propagation loss of the waveguide (24) is reduced.

6. An integration process for making an external cavity laser as claimed in claim 5, wherein the step of fabricating the waveguide (24) also comprises steps of: defining a channel in the passive waveguide layer (20) and the interlayer (22) by photolithography; forming the channel by dry etching; depositing a trace metal (57, 58) in the channel;depositing an under-bump metallization (UBM) layer (60, 62) on the trace metal (57, 58); and depositing a solder metal (26, 28) as part of the flip-chip bump (70, 71) on the UBM layer (60, 62).

7. An external cavity laser comprising a III-V semiconductor optical amplifier (SOA) (23) and a silicon photonic (SiPh) waveguide (24), wherein said SOA(23) is aligned and connected to said waveguide (24) by one or more flip- chip bumps (70, 71), such that when said SOA (23) is powered an evanescent coupling is formed between said SOA (23) and waveguide (24).

8. An external cavity laser as claimed in claim 7, wherein said SOA (23) comprises an N-InP cladding (36) and an N-metal contact (34, 35), two under-bump metallization (UBM) layers (59, 60, 61, 62) each of which is configured on an opposing end of each of the flip-chip bumps (70, 71), and said N-metal contact (34, 35) is sandwiched between said N-InP cladding (36) and the UBM layer (59, 61) on the proximal end.

9. An external cavity laser as claimed in claim 7 or claim 8, wherein a passivation dielectric layer (69) is configured adjacent said N-InP cladding (36) to prevent surface leakage current outside one or more predetermined current channels.

10. An external cavity laser as claimed in claim 9, wherein said SOA (23) also comprises a P-InP substrate (32) and a P-metal contact (33) configured on said P-InP substrate (32), said P-InP substrate (32) providing mechanical stability to the flip-chip bumps (70, 71).

11. An external cavity laser as claimed in claim 10, wherein said waveguide(24) comprises a passive waveguide layer (20) and an interlayer (22), configured adjacent each other, said passive waveguide layer (20) being adielectric, refractive index of which is higher than that of said interlayer (22).

12. An external cavity laser as claimed in claim 11, wherein: said SOA (23) also comprises a P-InP cladding (107), and an active layer (19) sandwiched between said P-InP and N-InP claddings (107, 36); and said waveguide (24) also comprises a silicon substrate (21) configured adjacent said interlayer (22), a trace metal layer (57, 58) being sandwiched between the UBM layer (60, 62) on the other end and said silicon substrate (21); such that heat generated from said active layer (19) can be dissipated through said silicon substrate (21) and / or said P-metal contact (33).

13. An external cavity laser as claimed in claim 12, wherein said passive waveguide layer (20) is either silicon (Si), silicon nitride (SiN), or thin-film lithium-niobate (TFLN).

14. An external cavity laser as claimed in claim 13, wherein the passivation dielectric layer (69) has a thickness between 5 to 7 nm.

15. An external cavity laser as claimed in claim 14, wherein two elongate depressions (30, 31) are defined in said passive waveguide layer (20), said depressions (30, 31) being open toward two facets of said passive waveguide (20), a ridge (29) capable of transmitting an optical mode (37) being formed between said depressions (30, 31), wherein said ridge (29) flares toward the facets such that optical confinement in said SOA (23) is reduced.

16. An external cavity laser as claimed in claim 15, wherein said ridge (29) is defined at an angle from the normal incidence, and an anti-reflection coatingis deposited on the input and output facets of said SOA (23), such that reflection is minimised.

17. An external cavity laser module comprising: the external cavity laser (83) as claimed in claim 16; a loop or Sagnac reflector (86) being connected to one end of said ridge (29); and a Vernier (84) fdter being connected to the other end of said ridge (29); such that a low-noise narrow-line -width (NLW) laser can be emitted at the output of the module.

18. An external cavity laser module comprising: a first external cavity laser as claimed in claim 16; and one or more other external cavity lasers, each as claimed in claim 16, connected to said first external cavity laser in a consecutive manner such that the optical power at the output of the module is boosted.

19. A III-V on photonic-circuit integration process comprising steps of: fabricating a III-V semiconductor optical amplifier (SOA); fabricating a photonic circuit on interposer; and connecting the SOA to the photonic circuit on interposer by one or more flip-chip bumps, such that when said SOA is powered, an evanescent coupling is formed between the SOA and the photonic circuit on interposer.

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