Display substrate, display panel and display apparatus

Abstract

Disclosed are a display substrate, a display panel and a display apparatus. The display substrate comprises: a base substrate, comprising: a display area and a fan-out area located on a side of the display area in a first direction; and a plurality of fan-out lines. The plurality of fan-out lines comprise a plurality of first fan-out lines. Each first fan-out line comprises in its extending direction a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line. In the same first fan-out line, one of the first sub-fan-out line and the third sub-fan-out line at least comprises a first wire, and the other one of the first sub-fan-out line and the third sub-fan-out line at least comprises a second wire, the first wire being located on a first conductive layer, and the second wire being located on a second conductive layer. The orthographic projections of any two adjacent first fan-out lines on the base substrate have an overlapping area, in which one of the first fan-out lines comprises a first wire, and the other first fan-out line comprises a second wire. The resistivity of each second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer.

Description

Display substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display substrate, a display panel and a display device. BACKGROUND

[0002] In the prior art, a display panel is bound with a driving chip (IC). When the number of ICs is large, each IC is electrically connected with a group of fan-out lines, and the length difference and impedance difference between the fan-out lines are small. However, in order to save costs and reduce the number of ICs bound with the display panel, the number of fan-out lines electrically connected with one IC increases, which leads to a large length difference and impedance difference between the fan-out lines, and thus easily causes display defects. The display effect is affected, and the user experience is affected.

[0003] SUMMARY

[0004] The display substrate provided by the embodiments of the present disclosure comprises:

[0005] a substrate; and a display area and a fan-out area located on one side of the display area in a first direction.

[0006] a plurality of fan-out lines arranged in a second direction in the fan-out area; the second direction intersects the first direction; the plurality of fan-out lines comprises a plurality of first fan-out lines; each first fan-out line comprises a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line in the extension direction of the first fan-out line; one of the first sub-fan-out line and the third sub-fan-out line of the same first fan-out line at least comprises a first wire, and the other of the first sub-fan-out line and the third sub-fan-out line at least comprises a second wire; the first wire is located in a first conductive layer, and the second wire is located in a second conductive layer; any two adjacent first fan-out lines have an overlapping area in the orthographic projection of the substrate, and in the overlapping area, one of the first fan-out lines comprises the first wire, and the other of the first fan-out lines comprises the second wire; the resistivity of the second sub-fan-out line is at least smaller than the resistivity of one of the first conductive layer and the second conductive layer.

[0007] In some embodiments, the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer, and the second sub-fan-out line is located in the second conductive layer.

[0008] The orthographic projections of the second sub-fan-out lines of different first fan-out lines on the substrate do not overlap with each other.

[0009] In some embodiments, in the direction of the display area pointing to the fan-out area, the first sub-fan-out line, the second sub-fan-out line and the third sub-fan-out line are electrically connected in sequence.

[0010] In some embodiments, the fan-out area further comprises a binding area.

[0011] The display substrate further includes a plurality of bonding electrodes located in the bonding area, and a plurality of signal lines extending from the display area to the fan-out area.

[0012] The first sub-fan-out line is electrically connected to the signal line away from one end of the third sub-fan-out line, and the third sub-fan-out line is electrically connected to the bonding electrode away from one end of the first sub-fan-out line; the length of the third sub-fan-out line is greater than the length of the first sub-fan-out line.

[0013] In some embodiments, in each first fan-out line, the first sub-fan-out line includes one of the first trace and the second trace, and the third sub-fan-out line includes the other of the first trace and the second trace;

[0014] In the plurality of first sub-fan-out lines, in the second direction, the first traces and the second traces are arranged alternately;

[0015] In the plurality of third sub-fan-out lines, in the second direction, the first traces and the second traces are arranged alternately;

[0016] The first sub-fan-out line including the first trace and / or the third sub-fan-out line including the first trace further includes a third trace in parallel with the first trace;

[0017] The third trace is located in the third conductive layer.

[0018] In some embodiments, the second conductive layer is located on a side of the first conductive layer away from the substrate, and the third conductive layer is located between the first conductive layer and the substrate.

[0019] In some embodiments, the display substrate further includes:

[0020] The plurality of insulating layers include a first insulating layer located between the first conductive layer and the second conductive layer, and a second insulating layer located between the first conductive layer and the third conductive layer;

[0021] The plurality of first vias; the first via penetrates the first insulating layer, the first trace, and the second insulating layer; the second sub-fan-out line or the second trace is electrically connected to the first trace and the third trace through the first via.

[0022] In some embodiments, the third trace is substantially overlapped with the first trace and the first via in the orthographic projection of the substrate.

[0023] In some embodiments, the first sub-fan-out line includes a first part and a second part located in different conductive layers and electrically connected, and the third sub-fan-out line includes a third part and a fourth part located in different conductive layers and electrically connected;

[0024] One of the first part and the second part includes the first trace, and the other of the first part and the second part includes the second trace;

[0025] In the plurality of first portions, the first traces and the second traces are arranged alternately in the second direction; in the plurality of second portions, the first traces and the second traces are arranged alternately in the second direction.

[0026] One of the third portions and the fourth portions comprises the first traces, and the other of the third portions and the fourth portions comprises the second traces; in the plurality of third portions, the first traces and the second traces are arranged alternately in the second direction; in the plurality of fourth portions, the first traces and the second traces are arranged alternately in the second direction.

[0027] In some embodiments, the plurality of fan-out lines further comprises: a plurality of second fan-out lines; in the second direction, the plurality of first fan-out lines is located at least on one side of the plurality of second fan-out lines; a length of the second fan-out line is less than a length of the first fan-out line.

[0028] The second fan-out line comprises: a fourth sub-fan-out line and a fifth sub-fan-out line which are electrically connected in sequence in a direction of the display area pointing to the fan-out area; in each second fan-out line, one of the fourth sub-fan-out line and the fifth sub-fan-out line is the first trace, and the other of the fourth sub-fan-out line and the fifth sub-fan-out line is the second trace.

[0029] In some embodiments, in the plurality of first sub-fan-out lines and the plurality of fourth sub-fan-out lines, the first traces and the second traces are arranged alternately in the second direction; the first trace and the second trace respectively located in adjacent two first sub-fan-out lines have an approximately overlapping area in the orthographic projection of the substrate.

[0030] In the plurality of third sub-fan-out lines and the plurality of fifth sub-fan-out lines, the first traces and the second traces are arranged alternately in the second direction; the first trace and the second trace respectively located in adjacent two third sub-fan-out lines have an approximately overlapping area in the orthographic projection of the substrate.

[0031] In some embodiments, in the direction away from the second fan-out line, the length of the plurality of first fan-out lines gradually increases.

[0032] In some embodiments, each sub-fan-out line is divided into a plurality of sub-segments in the extension direction thereof; the extension directions of adjacent two sub-segments are different.

[0033] The plurality of sub-segments included in the first sub-fan-out line are arranged in sequence in the direction of the display area pointing to the fan-out area, and the plurality of sub-segments included in the second sub-fan-out line are arranged in sequence in the direction of the display area pointing to the fan-out area.

[0034] The third sub-fan-out line comprises: a first sub-segment, a second sub-segment and a third sub-segment; the first sub-segment is located on the side of the binding area facing the display area, and an end of the first sub-segment away from the second sub-segment is electrically connected with the binding electrode; the second sub-segment is located on the side of the first sub-segment away from the display area, and the third sub-segment is located on the side of the second sub-segment away from the display area.

[0035] In some embodiments, the extending direction of the first sub-section and the extending direction of the second sub-section cross, the included angle between the extending direction of the first sub-section, the extending direction of the second sub-section and the first direction is greater than 0, and the included angle between the extending direction of the first sub-section, the extending direction of the second sub-section and the second direction is greater than 0.

[0036] The third sub-section extends along the second direction.

[0037] In the direction away from the second fan-out line, the length of the first sub-section in the orthographic projection of the substrate substrate gradually decreases; in the direction of the display area pointing to the fan-out area, the length of the third sub-section in the orthographic projection of the substrate substrate gradually increases.

[0038] In some embodiments, in adjacent third sub-fan-out lines, the orthographic projection of the two first sub-sections on the substrate substrate has an approximately overlapping area, the orthographic projection of the two second sub-sections on the substrate substrate has an approximately overlapping area, and the orthographic projection of the two third sub-sections on the substrate substrate has an approximately overlapping area.

[0039] In some embodiments, in each first fan-out line, the first sub-fan-out line includes one of the first trace and the second trace, and the third sub-fan-out line includes the other of the first trace and the second trace; the third sub-fan-out line further includes a fourth sub-section between the first sub-section and the binding area; the fourth sub-section extends along the first direction.

[0040] In the direction away from the second fan-out line, the length of the fourth sub-section gradually decreases.

[0041] The orthographic projection of the fourth sub-sections of adjacent two third sub-fan-out lines on the substrate substrate does not overlap.

[0042] In some embodiments, the first sub-fan-out line includes: a fifth sub-section, a sixth sub-section and a seventh sub-section arranged in the first direction in sequence; the fifth sub-section and the seventh sub-section extend along the first direction.

[0043] The included angle between the extending direction of the sixth sub-section and the second direction and the included angle between the second direction are both greater than 0.

[0044] One end of the fifth sub-section away from the sixth sub-section is electrically connected with the signal line, and one end of the seventh sub-section away from the sixth sub-section is electrically connected with the second sub-fan-out line.

[0045] In adjacent two first sub-fan-out lines, the orthographic projection of the two sixth sub-sections on the substrate substrate has an approximately overlapping area, the orthographic projection of the two fifth sub-sections on the substrate substrate does not overlap, and the orthographic projection of the two seventh sub-sections on the substrate substrate does not overlap.

[0046] In the first fan-out line, the extending direction of the sixth sub-section is the same as the extending direction of the first sub-section.

[0047] In some embodiments, the third sub-fanout line includes a third portion and a fourth portion;

[0048] The at least partial first fanout line further includes an eighth sub-segment, a ninth sub-segment, and a tenth sub-segment arranged in sequence in the first direction; the eighth sub-segment and the tenth sub-segment extend along the first direction;

[0049] The third portion includes a first sub-segment, a second sub-segment, and a third sub-segment, and the fourth portion of the at least partial first fanout line includes the eighth sub-segment, the ninth sub-segment, and the tenth sub-segment;

[0050] An included angle between an extension direction of the ninth sub-segment and the second direction and an included angle between the second direction are both greater than 0;

[0051] An end of the eighth sub-segment away from the ninth sub-segment is electrically connected to the first sub-segment, and an end of the tenth sub-segment away from the ninth sub-segment is electrically connected to the bonding electrode;

[0052] In adjacent two fourth portions, the two ninth sub-segments have a substantially overlapping region in the orthographic projection of the substrate, the two eighth sub-segments do not overlap with each other in the orthographic projection of the substrate, and the two tenth sub-segments do not overlap with each other in the orthographic projection of the substrate;

[0053] In the first fanout line, an extension direction of the first sub-segment is the same as an extension direction of the ninth sub-segment.

[0054] In some embodiments, the first sub-fanout line includes a first portion and a second portion;

[0055] The first sub-fanout line includes a fifth sub-segment, two sixth sub-segments, an eleventh sub-segment, and a seventh sub-segment;

[0056] In the first direction, the fifth sub-segment, the sixth sub-segment, the eleventh sub-segment, the sixth sub-segment, and the seventh sub-segment are arranged in sequence; the first portion includes a partial region of the fifth sub-segment, the sixth sub-segment, and the eleventh sub-segment arranged in sequence, and the second portion includes a partial region of the eleventh sub-segment, the sixth sub-segment, and the seventh sub-segment arranged in sequence;

[0057] The fifth sub-segment, the eleventh sub-segment, and the seventh sub-segment extend along the first direction;

[0058] An included angle between an extension direction of the sixth sub-segment and the second direction and an included angle between the second direction are both greater than 0;

[0059] An end of the fifth sub-segment away from the sixth sub-segment is electrically connected to the signal line, and an end of the seventh sub-segment away from the sixth sub-segment is electrically connected to the second sub-fanout line;

[0060] In the two adjacent first parts, the two sixth sub-segments have a substantially overlapping area in the orthographic projection of the substrate substrate, the two fifth sub-segments do not overlap with each other in the orthographic projection of the substrate substrate, and the two eleventh sub-segments do not overlap with each other in the orthographic projection of the substrate substrate; in the two adjacent second parts, the two sixth sub-segments have a substantially overlapping area in the orthographic projection of the substrate substrate, the two eleventh sub-segments do not overlap with each other in the orthographic projection of the substrate substrate, and the two seventh sub-segments do not overlap with each other in the orthographic projection of the substrate substrate.

[0061] In the first fan-out line, the extension direction of the sixth sub-segment is the same as the extension direction of the first sub-segment.

[0062] In some embodiments, in the plurality of first fan-out lines arranged in sequence away from the second fan-out line, the length of the second sub-fan-out line gradually increases.

[0063] At least part of the second sub-fan-out line comprises a twelfth sub-segment.

[0064] The angle between the extension direction of the twelfth sub-segment and the second direction, and the angle between the second direction are both greater than 0.

[0065] In some embodiments, the display substrate further comprises:

[0066] A plurality of thin film transistors are located in the display area; the first conductive layer further comprises a gate of the thin film transistor, and the second conductive layer further comprises a source and a drain of the thin film transistor.

[0067] In some embodiments, the display substrate further comprises:

[0068] A plurality of thin film transistors are located in the display area;

[0069] A plurality of light emitting devices are located on the side of the thin film transistor away from the display panel in the display area; the light emitting device comprises an anode, a light emitting functional layer, and a cathode which are arranged in a stack;

[0070] A plurality of connection electrodes are located between the drain and the anode of the thin film transistor in the display area, and the anode is electrically connected to the drain through the connection electrode.

[0071] The first conductive layer further comprises a gate of the thin film transistor.

[0072] The second conductive layer comprises a source and a drain of the thin film transistor; or the second conductive layer comprises a connection electrode.

[0073] In some embodiments, the display substrate further comprises:

[0074] A plurality of light shielding portions are located between the thin film transistor and the substrate substrate in the display area.

[0075] The first fan-out line further comprises a third trace, and the third trace is arranged in the same layer as the light shielding portion.

[0076] The display panel provided by the embodiment of the present disclosure comprises the display substrate provided by the embodiment of the present disclosure.

[0077] The display device provided by the embodiment of the present disclosure comprises the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0079] FIG. 1 is a structural schematic diagram of a display substrate provided by the related art;

[0080] FIG. 2 is a fan-out line resistance distribution schematic diagram of the display substrate provided by the related art;

[0081] FIG. 3 is a structural schematic diagram of a display substrate provided by the embodiment of the present disclosure;

[0082] FIG. 4 is an enlarged structural schematic diagram of the A area in FIG. 3 provided by the embodiment of the present disclosure;

[0083] FIG. 5 is a sectional view along BB' in FIG. 4 provided by the embodiment of the present disclosure;

[0084] FIG. 6 is a structural schematic diagram of another display substrate provided by the embodiment of the present disclosure;

[0085] FIG. 7 is a structural schematic diagram of still another display substrate provided by the embodiment of the present disclosure;

[0086] FIG. 8 is a structural schematic diagram of still another display substrate provided by the embodiment of the present disclosure;

[0087] FIG. 9 is a structural schematic diagram of still another display substrate provided by the embodiment of the present disclosure;

[0088] FIG. 10 is a structural schematic diagram of still another display substrate provided by the embodiment of the present disclosure;

[0089] FIG. 11 is a fan-out line resistance distribution schematic diagram of a display substrate provided by the embodiment of the present disclosure;

[0090] FIG. 12 is a structural schematic diagram of still another display substrate provided by the embodiment of the present disclosure;

[0091] FIG. 13 is a sectional view along CC' in FIG. 12 provided by the embodiment of the present disclosure;

[0092] Figure 14 is a cross-sectional view along EE' in Figure 12 provided by an embodiment of this disclosure;

[0093] Figure 15 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0094] Figure 16 is a schematic diagram of the fan-out line resistance distribution of another display substrate provided in an embodiment of this disclosure;

[0095] Figure 17 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0096] Figure 18 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0098] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0099] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0100] In the related art, as shown in FIG. 1, from left to right, one half of the fan-out line 2 is a first trace 401, and the other half is a second trace 402. The first trace 401 and the second trace 402 are located at different layers and are electrically connected by a via to realize the electrical connection of different traces of the fan-out line. However, the resistivity of the first trace is relatively large. Setting one half of the fan-out line as the first trace will increase the resistance of the fan-out line, and further increase the impedance of the fan-out line. As shown in FIG. 2, the fan-out line in FIG. 2 needs to correspond to the fan-out line 2 from left to right in FIG. 1. In FIG. 1, the length of the fan-out line from left to right gradually decreases, and the corresponding resistance also gradually decreases. The resistance of the leftmost fan-out line is as high as 8.7 kilo-ohms (KΩ). The resistance difference between the leftmost and rightmost fan-out lines is large, which may cause the risk of insufficient charging. For a touch display product, it may also cause the risk of poor touch.

[0101] The display substrate provided by the embodiments of the present disclosure, as shown in FIG. 3 and FIG. 4, includes:

[0102] a substrate 1; including a display area 101 and a fan-out area 1021 located on one side of the display area 101 in a first direction Y;

[0103] a plurality of fan-out lines 2 arranged in a second direction X in the fan-out area 1021; the second direction X intersects the first direction Y; the fan-out line 2 includes a plurality of sub-fan-out lines 3, and the sub-fan-out line 3 includes a trace 4; the plurality of fan-out lines 2 includes a plurality of first fan-out lines 201; the first fan-out line 201 includes a first sub-fan-out line 301, a second sub-fan-out line 302, and a third sub-fan-out line 303 in its extension direction; in the same first fan-out line 201, one of the first sub-fan-out line 301 and the third sub-fan-out line 303 at least includes the first trace 401, and the other of the first sub-fan-out line 301 and the third sub-fan-out line 303 at least includes the second trace 402; the first trace 401 is located at a first conductive layer 701, and the second trace 402 is located at a second conductive layer 702; any two adjacent first fan-out lines 201 have an overlapping area in the orthographic projection of the substrate 1; in the overlapping area, one of the first fan-out lines 201 includes the first trace 401, and the other of the first fan-out lines 201 includes the second trace 402; the resistivity of the second sub-fan-out line 302 is at least less than the resistivity of one of the first conductive layer 701 and the second conductive layer 702.

[0104] The display substrate provided by the embodiments of the present disclosure is characterized in that the first fan-out lines in the fan-out area include a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line, and the resistivity of the second sub-fan-out line is at least smaller than that of one of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is small. Compared with the prior art in which one half of the fan-out line is the first trace and the other half is the second trace, the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line, which is conducive to reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch.

[0105] It should be noted that FIG. 3 only shows different regions of the substrate, and does not show the fan-out lines. FIG. 4 is an enlarged schematic view of region A in FIG. 3.

[0106] In some embodiments, as shown in FIG. 3, the substrate 1 further includes a peripheral area 102 surrounding the display area 101, and the fan-out area 1021 is located in the peripheral area 102.

[0107] In some embodiments, the resistivity of the second conductive layer is smaller than that of the first conductive layer.

[0108] As shown in FIG. 4, the second sub-fan-out line 302 is located in the second conductive layer 702.

[0109] The second sub-fan-out lines 302 of different first fan-out lines 201 do not overlap in the projection of the substrate 1.

[0110] That is, the display substrate provided by the embodiments of the present disclosure includes second sub-fan-out lines in the same conductive layer in the plurality of first fan-out lines, and the second sub-fan-out lines are located in the second conductive layer with small resistivity. That is, the second sub-fan-out lines are arranged in the same layer as the second traces. In this way, the second sub-fan-out lines can be directly connected to the second traces, which can reduce the resistance of the fan-out lines while avoiding increasing the difficulty of manufacturing the fan-out lines.

[0111] In some embodiments, the material of the first conductive layer includes, for example, molybdenum; and the material of the second conductive layer includes, for example, a titanium / aluminum / titanium stack.

[0112] In some embodiments, as shown in FIG. 4 and FIG. 5, the second conductive layer 702 is located on the side of the first conductive layer 701 away from the substrate 1.

[0113] It should be noted that FIG. 5 is a cross-sectional view along BB' in FIG. 4.

[0114] In some embodiments, as shown in FIG. 6 and FIG. 7, the display substrate further includes:

[0115] The plurality of thin film transistors 6 are located in the display area 101; the first conductive layer 701 further comprises a gate G of the thin film transistor 6, and the second conductive layer 702 further comprises a source S and a drain D of the thin film transistor 6.

[0116] That is, the display substrate provided by the embodiments of the present disclosure has the first trace and the gate arranged in the same layer, and the second trace and the source and the drain arranged in the same layer, so that the second conductive layer is close to the first conductive layer, the second trace and the first trace can be easily connected through the via hole, and the disconnection of the connection can be avoided.

[0117] In some embodiments, in the display area, the display substrate comprises a plurality of sub-pixels arranged in a first direction Y and a second direction X; each sub-pixel comprises at least one thin film transistor. The display substrate further comprises a plurality of scanning lines and a plurality of data lines; the scanning lines extend along the first direction Y, the data lines extend along the second direction X, the scanning lines are arranged in the same layer as the gates of the thin film transistors and are electrically connected, and the data lines are arranged in the same layer as the sources of the thin film transistors and are electrically connected.

[0118] In some embodiments, as shown in FIGS. 6 and 7, the thin film transistor 6 further comprises an active layer 601. Taking the thin film transistor 6 as an example in a top-gate structure, the active layer 601 is located between the substrate 1 and the gate G, and the source S and the drain D are located on the side of the gate G away from the substrate 1.

[0119] In some embodiments, as shown in FIGS. 6 and 7, the display substrate further comprises:

[0120] The plurality of insulating layers 11 comprise a first insulating layer 1101 located between the first conductive layer 701 and the second conductive layer 702, and the first insulating layer 1101 is an interlayer insulating layer.

[0121] As shown in FIGS. 4 and 5, in the fan-out area, the first insulating layer 1101 comprises a plurality of second vias 15 penetrating through the thickness thereof, and the second sub-fan-out line 302 is electrically connected with the first trace 401 through the second via 15.

[0122] It should be noted that in FIG. 4, in the region of the second via 15, the line width of the second sub-fanout line 302 is equal to the line width of the first trace 401, and the line width of this region is equal to the line width of the second sub-fanout line 302 and the line width of the first trace 401 in the remaining regions. In specific implementation, the size of the second via in the direction perpendicular to the extension direction of the fanout line does not exceed the line width of the fanout line, as shown in FIG. 9, the line width h1 of the fanout line 2 in the region of the second via 15 can be greater than the line width h2 in the remaining regions. In FIG. 9, the orthographic projection of the second via 15 on the substrate is located within the orthographic projection of the F region of the fanout line 2 on the substrate. In the F region, the line width of the second sub-fanout line 302 is equal to the line width of the first trace 401, the line width h1 of the second sub-fanout line 302 in the F region is greater than the line width h2 of the second sub-fanout line 302 in the region outside the F region, and the line width of the first trace 401 in the F region is greater than the line width of the first trace 401 in the region outside the F region. In specific implementation, the line width of the fanout line in the F region can be specifically set according to the wiring space. As shown in FIG. 9, in some embodiments, the second sub-fanout line 302 is electrically connected to the first trace 401 through one second via 15. Of course, in the case that the line width of the fanout line in the F region is relatively wide, as shown in FIG. 10, the second sub-fanout line 302 can be electrically connected to the first trace 401 through multiple second vias 15, further improving the electrical connection performance of the two.

[0123] In the remaining regions of the second sub-fanout line 302 and the first trace 401

[0124] In some embodiments, as shown in FIGS. 6 and 7, the display substrate further comprises a buffer layer 1102-1 located between the active layer 601 and the substrate 1, and a gate insulating layer 1102-2 located between the active layer 601 and the first conductive layer 701.

[0125] In some embodiments, the display substrate provided by the embodiments of the present disclosure is applied to liquid crystal display, that is, the display substrate is an array substrate. As shown in FIG. 6, the display substrate further comprises a pixel electrode 16 and a common electrode 17. The pixel electrode 16 is electrically connected to the drain D. In FIG. 6, the common electrode 17 is located on the side of the pixel electrode 16 away from the substrate 1, and the display substrate further comprises a first passivation layer 1103 located between the source S and the drain D and the pixel electrode 16, and a second passivation layer 1104 located between the common electrode 17 and the pixel electrode 16.

[0126] Of course, in specific implementation, the pixel electrode can also be located on the side of the common electrode away from the substrate.

[0127] In some embodiments, as shown in FIG. 6, the display substrate further comprises a third conductive layer 703; the third conductive layer 703 comprises:

[0128] A plurality of light shielding portions 14 are located between the thin film transistor 6 and the substrate 1 in the display area 101; the light shielding portion 14 covers the active layer 601 in the orthographic projection of the substrate 1;

[0129] Specifically, the third conductive layer 703 is located between the buffer layer 1102-1 and the substrate 1.

[0130] In some embodiments, when the display substrate is an array substrate, the display substrate can further include a touch electrode and a touch signal line electrically connected to the touch electrode; the touch electrode can be multiplexed with the pixel electrode, or the touch electrode can be located in one of the conductive layers as shown in FIG. 6, or an additional conductive layer can be added to provide the touch electrode.

[0131] In some embodiments, the display substrate provided by the embodiments of the present disclosure is applied to electroluminescent display. As shown in FIG. 7, the display substrate further includes:

[0132] A plurality of light emitting devices 8 are located on the side of the thin film transistor 6 away from the display panel in the display area 101; the light emitting device 8 includes an anode 801, a light emitting functional layer 802, and a cathode 803 which are stacked.

[0133] In some embodiments, as shown in FIG. 7, the display substrate further includes: a planarization layer 1105 located between the anode 801 and the drain D, a pixel definition layer 18 located on the side of the planarization layer 1105 away from the substrate 1 and covering the edge of the anode 801; and an encapsulation layer 19 located on the side of the cathode 803 away from the substrate 1.

[0134] In specific implementation, the light emitting functional layer includes, for example, an organic light emitting layer, and can further include at least one of the following: an electron transport layer, a hole blocking layer, an electron injection layer, a hole injection layer, and an electron blocking layer. The encapsulation layer includes, for example, an inorganic encapsulation layer / organic encapsulation layer / inorganic encapsulation layer which are stacked.

[0135] Alternatively, the display substrate is applied to electroluminescent display, and in some embodiments, the first insulating layer between the gate and the source and the drain is a first interlayer insulating layer, as shown in FIG. 8, the display substrate further includes:

[0136] A plurality of connection electrodes 13 are located between the drain of the thin film transistor 6 and the anode 801 in the display area 101, and the anode 801 is electrically connected to the drain D through the connection electrode 13; the planarization layer 1105 is located between the connection electrode 13 and the anode 801

[0137] A second interlayer insulating layer 1106 is located between the connection electrode 13 and the drain D.

[0138] The first conductive layer 701 further includes the gate G of the thin film transistor 6.

[0139] The second conductive layer 702 further includes a source S and a drain D of the thin film transistor 6. That is, the first trace is arranged in the same layer as the gate, and the second trace is arranged in the same layer as the source and the drain.

[0140] Alternatively, in some embodiments, the first conductive layer further includes a gate of the thin film transistor, and the second conductive layer further includes a connection electrode. That is, the first trace is arranged in the same layer as the gate, and the second trace is arranged in the same layer as the connection electrode.

[0141] Of course, in specific implementation, the first trace and the second trace can be arranged in two conductive layers from the following: the conductive layer where the gate is located, the conductive layer where the source and the drain are located, the conductive layer where the connection electrode is located, the conductive layer where the anode is located, and the conductive layer where the cathode is located.

[0142] In specific implementation, but the display substrate is applied to electroluminescent display, the display substrate can further include a touch electrode and a touch signal line; for example, the display substrate further includes a touch layer located on the side of the encapsulation layer away from the substrate substrate, and the touch layer includes the touch electrode and the touch signal line.

[0143] In some embodiments, as shown in FIG. 4, in the direction of the display area (not shown) pointing to the fan-out area 1021, that is, the negative Y- of the first direction Y, the first sub-fan-out line 301, the second sub-fan-out line 302, and the third sub-fan-out line 303 are electrically connected in sequence.

[0144] In some embodiments, as shown in FIG. 3 and FIG. 4, the fan-out area 1021 further includes a binding area 10211;

[0145] The display substrate further includes a plurality of binding electrodes 9 located in the binding area 10211 (as shown in FIG. 4), and a plurality of signal lines 10 extending from the display area 101 to the fan-out area 1021 (as shown in FIG. 3);

[0146] The first sub-fan-out line 301 is electrically connected to the signal line 10 at the end away from the third sub-fan-out line 303, and the third sub-fan-out line 303 is electrically connected to the binding electrode 9 at the end away from the first sub-fan-out line 301; the length of the third sub-fan-out line 303 is greater than the length of the first sub-fan-out line 301.

[0147] It should be noted that the binding electrode is used for binding with the driving chip, and the driving chip is in the orthographic projection of the substrate substrate and the binding area. In this way, the signal of the driving chip can transmit the signal to the signal line through the binding electrode and the fan-out line. The signal line includes, for example, a data line, a touch signal line, and the like.

[0148] In some embodiments, as shown in FIG. 3, the peripheral area 101 includes one binding area 10211; that is, the display substrate is bound with one driving chip.

[0149] It should be noted that, as shown in FIG. 3, in the second direction X, the width of the binding area 10211 is much smaller than the width of the display area 101; the symmetry axis of the binding area 10211 extending along the first direction Y is located on the same line as the symmetry axis of the display area 101 extending along the first direction Y. The plurality of signal lines 10 extend along the first direction Y and are arranged along the second direction X. Correspondingly, in the second direction X, the length of the plurality of fan-out lines electrically connected with the binding electrode in one binding area first decreases and then increases in the positive direction X+ of the second direction X.

[0150] In some embodiments, as shown in FIG. 4, the plurality of fan-out lines 2 further include: a plurality of second fan-out lines 202; in the second direction X, the plurality of first fan-out lines 201 is located at least on one side of the plurality of second fan-out lines 202; the length of the second fan-out line 202 is smaller than the length of the first fan-out line 201.

[0151] The second fan-out line 202 includes: a fourth sub-fan-out line 304 and a fifth sub-fan-out line 305 electrically connected in sequence in the negative direction Y- of the first direction Y, i.e., the direction of the display area pointing to the fan-out area 1021; in each second fan-out line 202, one of the fourth sub-fan-out line 304 and the fifth sub-fan-out line 305 is the first wire 401, and the other is the second wire 402.

[0152] That is, the second fan-out line is divided into two parts located in different conductive layers. It should be noted that only part of the first fan-out line 201 and part of the second fan-out line 202 are shown in FIG. 4. In specific implementation, in the second direction X, the plurality of first fan-out lines 201 is included on both sides of the plurality of second fan-out lines 202.

[0153] In specific implementation, the length of the second fan-out line is smaller and the resistance is smaller, and the half of the second fan-out line as the first wire and the other half as the second wire will not cause too large resistance difference between adjacent fan-out lines.

[0154] The display substrate provided by the embodiments of the present disclosure is provided. The first fan-out line located in the fan-out area includes a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line. The second sub-fan-out line is arranged to reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line. The resistance difference and the impedance difference between the first fan-out line and the second fan-out line can also be reduced, and problems such as uneven charging or poor touch can be avoided.

[0155] In specific implementation, in the same second fan-out line, the second wire is electrically connected with the first wire through the via hole penetrating the first insulating layer.

[0156] In some embodiments, as shown in FIG. 4, in the plurality of first sub-fanout lines 301 and the plurality of fourth sub-fanout lines 304, in the second direction X, the first traces 401 and the second traces 402 are arranged alternately; the first trace 401 and the second trace 402 located in adjacent two first sub-fanout lines 301 have an approximately overlapped area in the orthographic projection of the substrate 1.

[0157] In the plurality of third sub-fanout lines 303 and the plurality of fifth sub-fanout lines 305, in the second direction X, the first traces 401 and the second traces 402 are arranged alternately; the first trace 401 and the second trace 402 located in adjacent two third sub-fanout lines 303 have an approximately overlapped area in the orthographic projection of the substrate 1.

[0158] That is, any adjacent two fanout lines have an approximately overlapped area in the orthographic projection of the substrate, and the traces of the two fanout lines in the approximately overlapped area in the orthographic projection are the first trace and the second trace, that is, the traces of the two fanout lines in the approximately overlapped area in the orthographic projection are located in different conductive layers, so that even if the orthographic projection is approximately overlapped, the short circuit will not occur, which is beneficial to save the wiring space.

[0159] It should be noted that the first trace and the second trace have an approximately overlapped area in the orthographic projection of the substrate means that the two have an overlapped area in the orthographic projection, and the distance between the edge of the orthographic projection of the first trace and the edge of the orthographic projection of the second trace is less than the error range, that is, the first trace and the second trace are considered to have an overlapped area in the orthographic projection of the substrate.

[0160] In some embodiments, as shown in FIG. 4, in the direction away from the second fanout line 202, the length of the plurality of first fanout lines 201 gradually increases.

[0161] Specifically, as shown in FIG. 4, the plurality of first fanout lines 201 located on one side of the plurality of second fanout lines 202 in the negative direction X- of the second direction X is a first fanout line group 20, and the plurality of first fanout lines 201 in the first fanout line group 20 are sequentially numbered as Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 in the arrangement in the negative direction X- of the second direction X, and the lengths of Q1 to Q8 gradually increase. The plurality of first fanout lines (not shown) located on one side of the plurality of second fanout lines in the positive direction X+ of the second direction X is a second fanout line group, and the plurality of first fanout lines 2 in the second fanout line group gradually increase in the length in the positive direction X+ of the second direction X.

[0162] In some embodiments, as shown in FIG. 4, in each first fanout line 201, the first sub-fanout line 301 includes one of the first trace 401 and the second trace 402, and the third sub-fanout line 303 includes the other of the first trace 401 and the second trace 402.

[0163] In the plurality of first sub-fanout lines 301, in the second direction X, the first traces 401 and the second traces 402 are arranged alternately.

[0164] In the plurality of third sub-fanout lines 303, in the second direction X, the first traces 401 and the second traces 402 are arranged alternately.

[0165] That is, in a specific implementation, as shown in FIG. 4, in two adjacent first fanout lines 201, in one of the two first fanout lines 201, the first sub-fanout line 301 is the first trace 401, and the third sub-fanout line 303 is the second trace 402; in the other of the two first fanout lines 201, the first sub-fanout line 301 is the second trace 402, and the third sub-fanout line 303 is the first trace 401.

[0166] The display substrate as shown in FIG. 4 provided by the embodiment of the present disclosure can reduce the resistance of the first fanout line, because the plurality of first fanout lines 201 each includes the second sub-fanout line with a small resistivity. However, because the plurality of first fanout lines are provided with the second sub-fanout line located in the middle region of the fanout area, the second sub-fanout lines of the plurality of first fanout lines do not overlap each other in the orthographic projection of the substrate. In this way, compared with the scheme of half first traces and half second traces in the related art, the space required to be occupied by the area corresponding to the plurality of second sub-fanout lines is increased, and in order to facilitate wiring, the third sub-fanout line needs to be arranged to lead to one side of the first binding area, thereby causing the length of the third sub-fanout line to be large. The resistance of part of the first fanout line and the second fanout line provided by the embodiment of the present disclosure is shown in FIG. 11, and only part of the fanout line is shown in FIG. 11. As can be seen from FIG. 11, the overall resistance of the first fanout line is reduced, and the resistance of the first fanout line at the farthest end is reduced to 5.07KΩ compared with 8.7KΩ in FIG. 2. However, because the middle region of the fanout area is replaced by a single-layer wiring and the length of the third sub-fanout line is increased, in the two adjacent first fanout lines, the length of the first trace of the first sub-fanout line is much smaller than the length of the first trace of the third sub-fanout line of the other fanout line, which can cause a large difference in the length of the first trace between the two adjacent first fanout lines, and further cause a large difference in the resistance between the two adjacent first fanout lines, that is, the ΔR area in FIG. 11 is generated. For a touch display product, the existence of ΔR affects the touch accuracy.

[0167] In some embodiments, as shown in FIG. 12, the first sub-fanout line 301 including the first trace 401 and / or the third sub-fanout line 303 including the first trace 401 further includes a third trace 403 connected in parallel with the first trace 401.

[0168] The third trace 403 is located in the third conductive layer 703.

[0169] The display substrate provided by the embodiments of the present disclosure can reduce the resistance of the first trace by arranging the third trace in parallel with the first trace of the third conductive layer, thereby reducing the resistance difference between the two adjacent first fan-out lines.

[0170] The first sub-fan-out line 301 including the first trace 401 and the third sub-fan-out line 303 including the first trace 401 in FIG. 12 are taken as examples. In some embodiments, as shown in FIG. 12, each first trace 401 is in parallel with the third trace 403, i.e., the first trace 401 included in the second fan-out line 202 is also in parallel with the third trace 403, thereby reducing the resistance of the second fan-out line 202 and facilitating the reduction of the resistance difference between the second fan-out line 202 and the first fan-out line 201.

[0171] In some embodiments, as shown in FIG. 13 and FIG. 14, the third conductive layer 703 is located between the first conductive layer 701 and the substrate 1.

[0172] It should be noted that FIG. 13 is a cross-sectional view along CC' in FIG. 12, and FIG. 14 is a cross-sectional view along EE' in FIG. 12.

[0173] In some embodiments, when the display substrate is an array substrate, as shown in FIG. 6, the third trace 403 is arranged in the same layer as the light shielding part 14, i.e., the third conductive layer 703 includes a plurality of light shielding parts 14 and a plurality of third traces 403.

[0174] The display substrate provided by the embodiments of the present disclosure has the third trace arranged in the same layer as the light shielding part, so that the distance between the third conductive layer and the first conductive layer is relatively short, the third trace and the first trace can be easily connected through the via, and the disconnection of the connection can be avoided.

[0175] In some embodiments, as shown in FIG. 13 and FIG. 14, the multilayer insulating layer 11 includes: a second insulating layer 1102 located between the first conductive layer 701 and the third conductive layer 703; the second insulating layer 1102 includes a buffer layer 1102-1 and a gate insulating layer 1102-2.

[0176] The display substrate further includes:

[0177] The display substrate further includes:

[0178] Specifically, in FIG. 13, the second sub-fanout line 302 is electrically connected to the first trace 401 and the third trace 403 through the first via 12, and in FIG. 14, the second trace 402 of the second fanout line 202 is electrically connected to the first trace 401 and the third trace 403 through the first via 12.

[0179] In a specific implementation, as shown in FIG. 13 and FIG. 14, at the first via 12, the first trace 401 includes a first sub-via 4011. After forming the second insulating layer 1102, a via penetrating through the second insulating layer 1102 can not be formed in the region corresponding to the first via 12. Instead, after forming the second insulating layer 1102, a first conductive layer is formed, and the first conductive layer is patterned to form the pattern of the first trace 401 and the first sub-via 4011. Then, the first insulating layer 1101 is formed, covering the first sub-via 4011. The first insulating layer 1101 and the second insulating layer 1102 are then patterned in the region corresponding to the first via 12 to form the first via 12. This can save the manufacturing process of the first via and save costs.

[0180] In some embodiments, when the display substrate is an electroluminescent display panel, the first trace is arranged in the same layer as the gate electrode, the second trace is arranged in the same layer as the source electrode and the drain electrode, and the third trace is arranged in the same layer as the connecting electrode. When the display substrate is an electroluminescent display panel, the first trace is arranged in the same layer as the gate electrode, the second trace is arranged in the same layer as the connecting electrode, and the third trace is arranged in the same layer as the source electrode and the drain electrode.

[0181] In some embodiments, as shown in FIG. 12, the third trace 403 is substantially overlapped with the first trace 401 and the first via 12 in the orthographic projection of the substrate 1. This can save wiring space.

[0182] In some embodiments, as shown in FIG. 15, the first sub-fanout line 301 includes a first part 3011 and a second part 3012 located in different conductive layers 7 and electrically connected, and the third sub-fanout line 303 includes a third part 3031 and a fourth part 3032 located in different conductive layers 7 and electrically connected.

[0183] One of the first part 3011 and the second part 3012 includes the first trace 401, and the other of the first part 3011 and the second part 3012 includes the second trace 402; that is, the two parts included in the first sub-fanout line 301 are located in different conductive layers 7.

[0184] In the plurality of first parts 3011, the first trace 401 and the second trace 402 are arranged alternately in the second direction X; in the plurality of second parts 3012, the first trace 401 and the second trace 402 are arranged alternately in the second direction X.

[0185] One of the third part 3031 and the fourth part 3032 includes the first trace 401, and the other of the third part 3031 and the fourth part 3032 includes the second trace 402; that is, the two parts included in the third sub-fanout line 303 are located in different conductive layers 7.

[0186] In the plurality of third parts 3031, the first trace 401 and the second trace 402 are arranged alternately in the second direction X; in the plurality of fourth parts 3032, the first trace 401 and the second trace 402 are arranged alternately in the second direction X.

[0187] The display substrate provided by the embodiments of the present disclosure is provided, the first sub-fanout line and the third sub-fanout line each include two parts located in different conductive layers, that is, the first sub-fanout line and the third sub-fanout line each include the first trace and the second trace, so that even if the total length of the third sub-fanout line is longer than the total length of the first sub-fanout line, the length difference of the first trace in the adjacent two first fanout lines can be reduced, and then the resistance difference and the impedance difference of the adjacent two first fanout lines are reduced, and the touch accuracy is improved.

[0188] The resistance of part of the first fanout line and the second fanout line provided by the embodiments of the present disclosure is shown in FIG. 16, wherein the first fanout line includes a first part, a second part, a second sub-fanout line, a third part, and a fourth part, and the second fanout line includes a fourth sub-fanout line and a fifth sub-fanout line, and only part of the fanout line is shown in FIG. 16. As can be seen from FIG. 16, the overall resistance of the first fanout line is reduced, and the resistance of the first fanout line at the farthest end is reduced to 4.2KΩ compared with 8.7KΩ of FIG. 2, and the resistance difference between the adjacent fanout lines is also greatly reduced compared with FIG. 11.

[0189] In specific implementation, the first trace and the second trace included in the first sub-fanout line are electrically connected through the via hole penetrating the first insulating layer, and the first trace and the second trace included in the third sub-fanout line are electrically connected through the via hole penetrating the first insulating layer. In specific implementation, in the sub-fanout line, due to the need to set the region where the first trace and the second trace are electrically connected, and in order to avoid the risk of short circuit between adjacent sub-fanout lines, the first trace and the second trace are electrically connected, and the normal projection of the adjacent two sub-fanout lines on the substrate does not overlap each other, and the region where the first trace and the second trace are electrically connected needs to be set to extend to part of the first direction. In specific implementation, in the first direction, the sum of the width of the region where the first trace and the second trace are electrically connected in the first sub-fanout line and the width of the region where the first trace and the second trace are electrically connected in the third sub-fanout line is about 40 microns.

[0190] In some embodiments, as shown in FIG. 15, in the same first fanout line 201, the two ends of the second sub-fanout line 302 are electrically connected with the same kind of trace 4.

[0191] In some embodiments, as shown in FIG. 4, FIG. 12, FIG. 15, the fan-out line 2 is divided into a plurality of sub-segments 5 in the extending direction thereof; the extending directions of two adjacent sub-segments 5 are different; that is, the upward projection of the sub-fan-out line 3 on the substrate 1 can be divided into a plurality of sub-segments 5 according to the extending direction;

[0192] The plurality of sub-segments 5 included in the first sub-fan-out line 301 are arranged in sequence in the direction (that is, the negative direction Y- of the first direction Y) in which the display area (not shown) points to the fan-out area 1021, and the plurality of sub-segments 5 included in the second sub-fan-out line 302 are arranged in sequence in the direction (that is, the negative direction Y- of the first direction Y) in which the display area (not shown) points to the fan-out area 1021.

[0193] In some embodiments, as shown in FIG. 4, FIG. 12, FIG. 15, the third sub-fan-out line 303 includes a first sub-segment 501, a second sub-segment 502, and a third sub-segment 503; the first sub-segment 501 is located on the side of the binding area 10211 facing the display area 101, and the end of the first sub-segment 501 away from the second sub-segment 502 is electrically connected to the binding electrode 9; the second sub-segment 502 is located on the side of the first sub-segment 501 away from the display area 101, and the third sub-segment 503 is located on the side of the second sub-segment 502 away from the display area 101.

[0194] It should be noted that only part of the second fan-out line 202 and 8 first fan-out lines 201 located on one side of the plurality of second fan-out lines 202 in the negative direction X- of the second direction X are shown in FIG. 4, FIG. 12, FIG. 15; in the partial area of the plurality of first sub-fan-out lines 301 and the partial area of the plurality of third sub-fan-out lines 303, there is an area where the first wire 401 and the second wire 402 overlap, so this area only needs to occupy the area of 4 wires, while the plurality of second sub-fan-out lines 302 do not overlap each other, and the plurality of second sub-fan-out lines 302 need to occupy the area of 8 wires, compared with the setting mode of the first wire, the second wire and the jumper, the setting of the plurality of second sub-fan-out lines needs more wiring space.

[0195] The display substrate provided by the embodiments of the present disclosure, the third sub-fan-out line includes a first sub-segment, a second sub-segment, and a third sub-segment. That is, the third sub-fan-out line extends upward (that is, in the positive direction Y+ of the first direction Y) from the binding area and then extends downward (that is, in the negative direction of the first direction Y), which can make full use of the wiring space around the binding area, set the plurality of second sub-fan-out lines while avoiding excessive increase in the wiring space, avoiding the increase in the size of the fan-out area in the first direction, and further avoiding the increase in the width of the peripheral area.

[0196] In some embodiments, as shown in FIG. 4, FIG. 12, in the second direction X, the upward projection of the third sub-segment 503 on the substrate 1 is located on one side of the binding area 10211.

[0197] The display substrate provided by the embodiments of the present disclosure can make full use of the space on both sides of the binding area, avoid excessive increase of the wiring space, avoid increase of the size of the fan-out area in the first direction, and further avoid increase of the width of the peripheral area.

[0198] In some embodiments, as shown in FIG. 4, FIG. 12 and FIG. 15, the extension direction of the first sub-section 501 intersects with the extension direction of the second sub-section 502, the included angle between the extension direction of the first sub-section 501, the extension direction of the second sub-section 502 and the first direction Y is greater than 0, and the included angle between the extension direction of the first sub-section 501, the extension direction of the second sub-section 502 and the second direction X is greater than 0.

[0199] The third sub-section 503 extends along the second direction X.

[0200] In the direction away from the second fan-out line 202, the length of the first sub-section 501 in the orthographic projection of the substrate substrate 1 gradually decreases; in the direction of the display area (not shown) pointing to the fan-out area 1021 (i.e. the negative direction of the first direction Y), the length of the third sub-section 503 in the orthographic projection of the substrate substrate 1 gradually increases.

[0201] It should be noted that, as shown in FIG. 4, FIG. 12 and FIG. 15, the same sub-section 5 in the same conductive layer 7 satisfies: in the direction away from the second fan-out line 202, the length of the first sub-section 501 in the orthographic projection of the substrate substrate 1 gradually decreases, and in the direction of the display area (not shown) pointing to the fan-out area 1021 (i.e. the negative direction of the first direction Y), the length of the third sub-section 503 in the orthographic projection of the substrate substrate 1 gradually increases. For the same sub-section 5 located in different conductive layers 7 and not overlapping in orthographic projection, it also satisfies: in the direction away from the second fan-out line 202, the length of the first sub-section 501 in the orthographic projection of the substrate substrate 1 gradually decreases, and in the direction of the display area (not shown) pointing to the fan-out area 1021 (i.e. the negative direction of the first direction Y), the length of the third sub-section 503 in the orthographic projection of the substrate substrate 1 gradually increases.

[0202] In some embodiments, as shown in FIG. 4 and FIG. 12, the third sub-fan-out line 303 further includes a fourth sub-section 504; the fourth sub-section 504 extends along the first direction Y.

[0203] In the direction away from the second fan-out line 202, the length of the fourth sub-section 504 gradually decreases.

[0204] The fourth sub-section 504 of the adjacent two third sub-fan-out lines 303 does not overlap in the orthographic projection of the substrate substrate 1.

[0205] The display substrate provided by the embodiments of the present disclosure has the following advantages: a plurality of fourth sub-segments are arranged along the second direction X, and the length of the fourth sub-segment gradually decreases in the direction away from the second fan-out line; correspondingly, the first sub-segment extending in the direction intersecting the first direction and the second direction is connected with the fourth sub-segment, and the length of the first sub-segment gradually decreases in the direction away from the second fan-out line, so that the length variation of the first sub-segment and the fourth sub-segment is matched, which is conducive to reasonably utilizing the wiring space and avoiding increasing the size of the fan-out area.

[0206] In some embodiments, as shown in FIG. 4 and FIG. 12, the third sub-fan-out line 303 further includes a thirteenth sub-segment 513; the thirteenth sub-segment 513 extends along the first direction Y;

[0207] In the direction away from the second fan-out line 202, the length of the thirteenth sub-segment 513 gradually decreases; the thirteenth sub-segments 513 of adjacent two third sub-fan-out lines 303 do not overlap in the orthographic projection of the substrate substrate 1.

[0208] The display substrate provided by the embodiments of the present disclosure has the following advantages: a plurality of fourth sub-segments are arranged along the second direction X, and the length of the fourth sub-segment gradually decreases in the direction away from the second fan-out line; correspondingly, the first sub-segment extending in the direction intersecting the first direction and the second direction is connected with the fourth sub-segment, and the length of the first sub-segment gradually decreases in the direction away from the second fan-out line, so that the length variation of the first sub-segment and the fourth sub-segment is matched, which is conducive to reasonably utilizing the wiring space and avoiding increasing the size of the fan-out area.

[0209] In some embodiments, as shown in FIG. 15, the third sub-fan-out line 303 includes a third part 3031 and a fourth part 3032; the third part 3031 includes the first sub-segment 501, the second sub-segment 502 and the third sub-segment 503;

[0210] The fourth part 3032 includes a part extending along the first direction Y; and in the direction away from the second fan-out line 202, the length of the fourth part 3032 gradually decreases.

[0211] The display substrate provided by the embodiments of the present disclosure has the following advantages: a plurality of fourth sub-segments are arranged along the second direction X, and the length of the fourth sub-segment gradually decreases in the direction away from the second fan-out line; correspondingly, the first sub-segment extending in the direction intersecting the first direction and the second direction is connected with the fourth sub-segment, and the length of the first sub-segment gradually decreases in the direction away from the second fan-out line, so that the length variation of the first sub-segment and the fourth sub-segment is matched, which is conducive to reasonably utilizing the wiring space and avoiding increasing the size of the fan-out area.

[0212] In some embodiments, as shown in FIG. 15, the second sub-fan-out line 302 further includes a fourteenth sub-segment 514; the fourteenth sub-segment 514 extends along the first direction Y;

[0213] The length of the fourteenth sub-section 514 gradually increases in a direction away from the second fan-out line 202.

[0214] The display substrate provided by the embodiments of the present disclosure has the following advantages. The plurality of fourteenth sub-sections are arranged along the second direction X, and the length of the fourteenth sub-section gradually increases in a direction away from the second fan-out line. Correspondingly, the third sub-section extending along the second direction is connected with the fourteenth sub-section, and the length of the positive projection of the third sub-section on the substrate gradually increases in the negative direction of the first direction Y. Thus, the length of the third sub-section and the fourteenth sub-section changes in a matched manner, which is conducive to reasonably utilizing the wiring space and avoiding increasing the size of the fan-out area.

[0215] In some embodiments, as shown in FIG. 15, the at least part of the first fan-out line 201 further includes an eighth sub-section 508, a ninth sub-section 509 and a tenth sub-section 510 arranged in sequence along the first direction Y; the eighth sub-section 508 and the tenth sub-section 510 extend along the first direction Y;

[0216] The at least fourth part 3032 includes the eighth sub-section 508, the ninth sub-section 509 and the tenth sub-section 510;

[0217] The angle between the extension direction of the ninth sub-section 509 and the second direction X and the angle between the second direction X are both greater than 0;

[0218] One end of the eighth sub-section 508 away from the ninth sub-section 509 is electrically connected with the first sub-section 501, and one end of the tenth sub-section 510 away from the ninth sub-section 509 is electrically connected with the binding electrode 9;

[0219] In the two adjacent fourth parts 3032, the positive projections of the two ninth sub-sections 509 on the substrate 1 have an area of substantial overlap, the positive projections of the two eighth sub-sections 508 on the substrate 1 do not overlap with each other, and the positive projections of the two tenth sub-sections 510 on the substrate 1 do not overlap with each other.

[0220] It should be noted that the positive projections of the two sub-sections on the substrate have an area of substantial overlap means that the distance between the edges of the positive projections of the two sub-sections on the substrate is less than the error range, and the two sub-sections can be regarded as having an area of overlap in the positive projection on the substrate.

[0221] It should be noted that, compared with the case where the sub-sections extend along the first direction Y, the extension direction of the sub-sections intersects the first direction Y, which is conducive to reducing the size of the fan-out area in the first direction Y. However, if the plurality of sub-sections extending in the direction intersecting the first direction Y are arranged in sequence along the second direction X, a large wiring space will be occupied, resulting in an increase in the size of the fan-out area in the second direction X. The display substrate provided by the embodiments of the present disclosure has the following advantages. The ninth sub-sections in the adjacent third fan-out lines have an area of substantial overlap, which is conducive to saving wiring space.

[0222] In some embodiments, as shown in FIG. 15, in the first fan-out line 201, the extension direction of the first sub-section 501 is the same as the extension direction of the ninth sub-section 509.

[0223] In some embodiments, as shown in FIG. 4, FIG. 12, and FIG. 15, the first sub-section 501, the second sub-section 502, and the third sub-section 503 are arranged in sequence in the direction away from the second fan-out line 202 (the negative direction X- of the second direction X in the figure), that is, the third sub-fan-out line extends in the direction away from the second fan-out line, which can make full use of the space of the fan-out area.

[0224] In some embodiments, as shown in FIG. 4, FIG. 12, and FIG. 15, in the adjacent third sub-fan-out line 303, the two first sub-sections 501 have an approximately overlapping area in the orthographic projection of the substrate substrate 1, the two second sub-sections 502 have an approximately overlapping area in the orthographic projection of the substrate substrate 1, and the two third sub-sections 503 have an approximately overlapping area in the orthographic projection of the substrate substrate 1.

[0225] The display substrate provided by the embodiments of the present disclosure has the advantages that the extension directions of the first sub-section, the second sub-section, and the third sub-section all cross the first direction, and in the adjacent third sub-fan-out line, the first sub-section has an approximately overlapping area, the second sub-section has an approximately overlapping area, and the third sub-section has an approximately overlapping area, which is beneficial to saving the wiring space. For example, as shown in FIG. 4, FIG. 12, and FIG. 15, in the first direction Y, the eight first sub-sections 501, the eight second sub-sections 502, and the eight third sub-sections 503 all only need to occupy the wiring space of four wires, which can avoid increasing the size of the fan-out area in the first direction Y.

[0226] In some embodiments, as shown in FIG. 4 and FIG. 12, the first sub-fan-out line 301 includes: a fifth sub-section 505, a sixth sub-section 506, and a seventh sub-section 507 arranged in sequence in the first direction Y; the fifth sub-section 505 and the seventh sub-section 507 extend along the first direction Y;

[0227] The included angle between the extension direction of the sixth sub-section 506 and the second direction X and the included angle between the second direction X are both greater than 0;

[0228] One end of the fifth sub-section 505 away from the sixth sub-section 506 is electrically connected with the signal line 10, and one end of the seventh sub-section 507 away from the sixth sub-section 506 is electrically connected with the second sub-fan-out line 302;

[0229] In the adjacent two first sub-fan-out lines 301, the two sixth sub-sections 506 have an approximately overlapping area in the orthographic projection of the substrate substrate 1, the two fifth sub-sections 505 do not overlap in the orthographic projection of the substrate substrate 1, and the two seventh sub-sections 507 do not overlap in the orthographic projection of the substrate substrate 1.

[0230] The display substrate provided by the embodiment of the present disclosure has the sixth sub-segment with the approximately overlapped area in the adjacent first sub-fanout line, which is beneficial to save the wiring space.

[0231] In some embodiments, as shown in FIG. 15, the first sub-fanout line 301 includes a fifth sub-segment 505, two sixth sub-segments 506, an eleventh sub-segment 511, and a seventh sub-segment 507.

[0232] In the first direction Y, the fifth sub-segment 505, the sixth sub-segment 506, the eleventh sub-segment 511, the sixth sub-segment 506, and the seventh sub-segment 507 are arranged in sequence.

[0233] The first part 3011 includes a part of the area where the fifth sub-segment 505, the sixth sub-segment 506, and the eleventh sub-segment 511 are arranged in sequence; the second part 3012 includes a part of the area where the eleventh sub-segment 511, the sixth sub-segment 506, and the seventh sub-segment 507 are arranged in sequence; the fifth sub-segment 505, the eleventh sub-segment 511, and the seventh sub-segment 507 extend along the first direction Y.

[0234] The angle between the extension direction of the sixth sub-segment 506 and the second direction X and the angle between the second direction X are both greater than 0.

[0235] One end of the fifth sub-segment 505 away from the sixth sub-segment 506 is electrically connected with the signal line 10; one end of the seventh sub-segment 507 away from the sixth sub-segment 506 is electrically connected with the second sub-fanout line 302.

[0236] In the adjacent two first parts 3011, the two sixth sub-segments 506 have the approximately overlapped area in the orthographic projection of the substrate 1, the two fifth sub-segments 505 do not overlap with each other in the orthographic projection of the substrate 1, and the two eleventh sub-segments 511 do not overlap with each other in the orthographic projection of the substrate 1.

[0237] In the adjacent two second parts 3012, the two sixth sub-segments 506 have the approximately overlapped area in the orthographic projection of the substrate 1, the two eleventh sub-segments 511 do not overlap with each other in the orthographic projection of the substrate 1, and the two seventh sub-segments 507 do not overlap with each other in the orthographic projection of the substrate 1.

[0238] The display substrate provided by the embodiment of the present disclosure has the sixth sub-segment with the approximately overlapped area in the adjacent first sub-fanout line, which is beneficial to save the wiring space.

[0239] In some embodiments, as shown in FIG. 4, FIG. 12, and FIG. 15, the extension direction of the sixth sub-segment 506 is the same as the extension direction of the first sub-segment 501.

[0240] In specific implementation, as shown in FIG. 4, FIG. 12 and FIG. 15, the second fan-out line 202 includes a fifteenth sub-section 515 which has the same extension direction as the sixth sub-section 506 of the first sub-fan-out line 301, and the fifteenth sub-section 515 of the second fan-out line 202 adjacent to the first fan-out line 201 is adjacent to the first sub-section 501; the extension direction of the sixth sub-section 506 is the same as the extension direction of the first sub-section 501, and the extension direction of the corresponding fifteenth sub-section 515 is the same as the extension direction of the first sub-section 501, which is conducive to reasonable utilization of the wiring space.

[0241] In some embodiments, as shown in FIG. 4, FIG. 12 and FIG. 15, in the plurality of first fan-out lines 201 arranged in sequence in the direction away from the second fan-out line 202, the length of the second sub-fan-out line 302 gradually increases;

[0242] At least part of the second sub-fan-out line 302 includes a twelfth sub-section 512.

[0243] The angle between the extension direction of the twelfth sub-section 512 and the second direction X and the angle between the second direction X are both greater than 0.

[0244] The display substrate provided by the embodiments of the present disclosure has the twelfth sub-section in the second sub-fan-out line, and the extension direction of the twelfth sub-section intersects with the first direction and the second direction, which can reduce the resistance of the first fan-out line by arranging the second sub-fan-out line, avoid excessive increase of the size of the fan-out area in the first direction, and is conducive to saving the wiring space.

[0245] Based on the same inventive concept, the embodiments of the present disclosure also provide a display panel, as shown in FIG. 17, which includes the display substrate 20 provided by the embodiments of the present disclosure.

[0246] The display panel provided by the embodiments of the present disclosure includes the above-mentioned display substrate provided by the embodiments of the present disclosure, the first fan-out line in the fan-out area includes the first sub-fan-out line, the second sub-fan-out line and the third sub-fan-out line, and the resistivity of the second sub-fan-out line is at least smaller than the resistivity of one of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is small. Compared with the prior art in which half of the fan-out line is the first trace and half of the fan-out line is the second trace, arranging the second sub-fan-out line can reduce the resistance of the fan-out line, and further reduce the impedance of the fan-out line, which is conducive to reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch. In addition, the orthogonal projection of any two adjacent first fan-out lines on the substrate has an overlapping area, and the traces of the two first fan-out lines in the overlapping area are the first trace and the second trace, that is, the traces of the two first fan-out lines in the overlapping area are located in different conductive layers, so that even if there is an overlap, short circuit will not occur, which is conducive to saving the wiring space.

[0247] In some embodiments, the display panel is a liquid crystal display panel, and the display substrate is an array substrate; as shown in FIG. 17, the display panel further includes: a counter substrate 21 arranged opposite to the display substrate 20, and a liquid crystal layer 22 between the display substrate 20 and the counter substrate 21.

[0248] The display device provided by the embodiments of the present disclosure is shown in FIG. 18. The display device includes the display panel 23 provided by the embodiments of the present disclosure.

[0249] In some embodiments, the display panel is a liquid crystal display panel, and as shown in FIG. 18, the display device further includes: a backlight module 24; and the display panel 23 is located on the light-emitting side of the backlight module 24.

[0250] The display device provided by the embodiments of the present disclosure is: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those skilled in the art, and are not described here to avoid repetition. The implementation of the display device can refer to the embodiments of the display substrate and the display panel described above, and repeated descriptions are omitted.

[0251] In summary, the display substrate, the display panel, and the display device provided by the embodiments of the present disclosure have the following advantages. The first fan-out line in the fan-out area includes a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The resistivity of the second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is small. Compared with the prior art in which half of the fan-out line is the first trace and the other half is the second trace, the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line, which is beneficial to reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch. In addition, the orthogonal projection of any two adjacent first fan-out lines on the substrate has an overlapping area, and the traces of the two first fan-out lines in the overlapping area are the first trace and the second trace, respectively. That is, the traces of the two first fan-out lines in the overlapping area are located in different conductive layers, so that even if there is an overlap, short circuit does not occur, which is beneficial to saving wiring space.

[0252] Although the preferred embodiments of the present application have been described, those skilled in the art who have the basic inventive concept can make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0253] It will be apparent to those skilled in the art that various modifications and variations can be made to the present embodiments without departing from the spirit or scope of the present embodiments. Thus, it is intended that the present embodiments cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; comprising: a display area, and a fan-out area located on one side of the display area in a first direction; a plurality of fan-out lines arranged in a second direction in the fan-out area; the second direction intersects the first direction; the plurality of fan-out lines comprises a plurality of first fan-out lines; the first fan-out line comprises a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line in its extension direction; in the same first fan-out line, one of the first sub-fan-out line and the third sub-fan-out line at least comprises a first wire, and the other of the first sub-fan-out line and the third sub-fan-out line at least comprises a second wire; the first wire is located in a first conductive layer, and the second wire is located in a second conductive layer; any two adjacent first fan-out lines have an overlapping area in the orthographic projection of the substrate substrate; in the overlapping area, one of the first fan-out lines comprises the first wire, and the other of the first fan-out lines comprises the second wire; the resistivity of the second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer. 2.The display substrate of claim 1, wherein, The resistivity of the second conductive layer is less than the resistivity of the first conductive layer, and the second sub-fan-out line is located in the second conductive layer. The orthographic projections of the second sub-fan-out lines of different first fan-out lines do not overlap each other. 3.The display substrate according to claim 1 or 2, wherein, In the direction of the display area pointing to the fan-out area, the first sub-fan-out line, the second sub-fan-out line and the third sub-fan-out line are electrically connected in sequence. 4.The display substrate of claim 3, wherein, The fan-out area further comprises a binding area; The display substrate further comprises a plurality of binding electrodes located in the binding area, and a plurality of signal lines extending from the display area to the fan-out area; The end of the first sub-fan-out line away from the third sub-fan-out line is electrically connected to the signal line, and the end of the third sub-fan-out line away from the first sub-fan-out line is electrically connected to the binding electrode; the length of the third sub-fan-out line is greater than the length of the first sub-fan-out line. 5.The display substrate of claim 4, wherein, In each first fan-out line, the first sub-fan-out line comprises one of the first wire and the second wire, and the third sub-fan-out line comprises the other of the first wire and the second wire; In a plurality of first sub-fan-out lines, the first wire and the second wire are arranged alternately in the second direction; In a plurality of third sub-fan-out lines, the first wire and the second wire are arranged alternately in the second direction; The first sub-fan-out line comprising the first wire and / or the third sub-fan-out line comprising the first wire further comprises a third wire in parallel with the first wire; The third wire is located in a third conductive layer. 6.The display substrate of claim 5, wherein, The second conductive layer is located on the side of the first conductive layer away from the substrate substrate, and the third conductive layer is located between the first conductive layer and the substrate substrate. 7.The display substrate of claim 6, wherein, The display substrate further comprises: a plurality of insulating layers, comprising a first insulating layer located between the first conductive layer and the second conductive layer, and a second insulating layer located between the first conductive layer and the third conductive layer; A plurality of first vias; the first vias penetrating the first insulating layer, the first trace and the second insulating layer; the second sub-fanout line or the second trace is electrically connected with the first trace, the third trace through the first via. 8.The display substrate of claim 7, wherein, The third trace is substantially overlapped with the first trace and the first via in the orthographic projection of the substrate. 9.The display substrate of claim 4, wherein, The first sub-fanout line comprises a first part and a second part located at different conductive layers and electrically connected, and the third sub-fanout line comprises a third part and a fourth part located at different conductive layers and electrically connected. One of the first part and the second part comprises the first trace, and the other of the first part and the second part comprises the second trace. In the plurality of first parts, the first trace and the second trace are alternately arranged in the second direction; in the plurality of second parts, the first trace and the second trace are alternately arranged in the second direction. One of the third part and the fourth part comprises the first trace, and the other of the third part and the fourth part comprises the second trace; in the plurality of third parts, the first trace and the second trace are alternately arranged in the second direction; in the plurality of fourth parts, the first trace and the second trace are alternately arranged in the second direction.

10. The display substrate according to any one of claims 1-9, wherein, The plurality of fanout lines further comprises a plurality of second fanout lines; in the second direction, the plurality of first fanout lines is located at least on one side of the plurality of second fanout lines; the length of the second fanout line is less than the length of the first fanout line. The second fanout line comprises a fourth sub-fanout line and a fifth sub-fanout line electrically connected in sequence in the direction of the display area pointing to the fanout area; in each second fanout line, one of the fourth sub-fanout line and the fifth sub-fanout line is the first trace, and the other of the fourth sub-fanout line and the fifth sub-fanout line is the second trace. 11.The display substrate of claim 10, wherein, In the plurality of first sub-fanout lines and the plurality of fourth sub-fanout lines, the first trace and the second trace are alternately arranged in the second direction; the orthographic projection of the first trace and the second trace located in adjacent two first sub-fanout lines on the substrate has an area of substantial overlap. In the plurality of third sub-fanout lines and the plurality of fifth sub-fanout lines, the first trace and the second trace are alternately arranged in the second direction; the orthographic projection of the first trace and the second trace located in adjacent two third sub-fanout lines on the substrate has an area of substantial overlap. 12.The display substrate according to claim 10 or 11, wherein In the direction away from the second fanout line, the length of the plurality of first fanout lines gradually increases. 13.The display substrate of claim 12, wherein, Each fanout line is divided into a plurality of sub-segments in its extension direction; the extension directions of adjacent two sub-segments are different; The plurality of sub-segments included in the first sub-fanout line are arranged in sequence in the direction of the display area pointing to the fanout area, and the plurality of sub-segments included in the second sub-fanout line are arranged in sequence in the direction of the display area pointing to the fanout area. The third sub-fanout line comprises a first sub-section, a second sub-section and a third sub-section; the first sub-section is located on a side of the binding area facing the display area, and an end of the first sub-section away from the second sub-section is electrically connected with the binding electrode; the second sub-section is located on a side of the first sub-section away from the display area, and the third sub-section is located on a side of the second sub-section away from the display area. 14.The display substrate of claim 13, wherein, An extension direction of the first sub-section and an extension direction of the second sub-section are crossed, and an included angle between the extension direction of the first sub-section, the extension direction of the second sub-section and the first direction is greater than 0, and an included angle between the extension direction of the first sub-section, the extension direction of the second sub-section and the second direction is greater than 0; The third sub-section extends along the second direction; In a direction away from the second fanout line, a length of the first sub-section in the orthographic projection of the substrate substrate gradually decreases; in a direction of the display area pointing to the fanout area, a length of the third sub-section in the orthographic projection of the substrate substrate gradually increases. 15.The display substrate of claim 14, wherein, In adjacent third sub-fanout lines, two first sub-sections have an approximately overlapping area in the orthographic projection of the substrate substrate, two second sub-sections have an approximately overlapping area in the orthographic projection of the substrate substrate, and two third sub-sections have an approximately overlapping area in the orthographic projection of the substrate substrate. 16.The display substrate according to claim 14 or 15, wherein, In each first fanout line, the first sub-fanout line comprises one of the first trace and the second trace, and the third sub-fanout line comprises the other one of the first trace and the second trace; the third sub-fanout line further comprises a fourth sub-section between the first sub-section and the binding area; the fourth sub-section extends along the first direction; In a direction away from the second fanout line, a length of the fourth sub-section gradually decreases; The fourth sub-sections of adjacent two third sub-fanout lines do not overlap in the orthographic projection of the substrate substrate. 17.The display substrate of claim 16, wherein, The first sub-fanout line comprises a fifth sub-section, a sixth sub-section and a seventh sub-section arranged in sequence in the first direction; the fifth sub-section and the seventh sub-section extend along the first direction; An included angle between an extension direction of the sixth sub-section and the second direction and an included angle between the second direction are both greater than 0; An end of the fifth sub-section away from the sixth sub-section is electrically connected with the signal line, and an end of the seventh sub-section away from the sixth sub-section is electrically connected with the second sub-fanout line; In adjacent two first sub-fanout lines, two sixth sub-sections have an approximately overlapping area in the orthographic projection of the substrate substrate, two fifth sub-sections do not overlap in the orthographic projection of the substrate substrate, and two seventh sub-sections do not overlap in the orthographic projection of the substrate substrate; In the first fanout line, the extension direction of the sixth sub-section is the same as the extension direction of the first sub-section. 18.The display substrate according to claim 14 or 15, wherein, The third sub-fanout line comprises a third part and a fourth part; At least part of the first fanout line further comprises an eighth sub-section, a ninth sub-section and a tenth sub-section arranged in sequence in the first direction; the eighth sub-section and the tenth sub-section extend along the first direction; The third portion includes the first sub-section, the second sub-section and the third sub-section, and at least part of the fourth portion of the first fan-out line includes the eighth sub-section, the ninth sub-section and the tenth sub-section; An included angle between an extension direction of the ninth sub-section and the second direction, and an included angle between the second directions are both greater than 0; An end of the eighth sub-section away from the ninth sub-section is electrically connected with the first sub-section, and an end of the tenth sub-section away from the ninth sub-section is electrically connected with the bonding electrode; In two adjacent fourth portions, the two ninth sub-sections have a substantially overlapping area in a projection of the substrate, the two eighth sub-sections do not overlap with each other in the projection of the substrate, and the two tenth sub-sections do not overlap with each other in the projection of the substrate; In the first fan-out line, an extension direction of the first sub-section is the same as an extension direction of the ninth sub-section.

19. The display substrate of claim 18, wherein, The first sub-fan-out line includes a first portion and a second portion; the first sub-fan-out line includes a fifth sub-section, two sixth sub-sections, an eleventh sub-section and a seventh sub-section; In the first direction, the fifth sub-section, the sixth sub-section, the eleventh sub-section, the sixth sub-section and the seventh sub-section are arranged in sequence; the first portion includes the fifth sub-section, the sixth sub-section and a partial area of the eleventh sub-section arranged in sequence, and the second portion includes a partial area of the eleventh sub-section, the sixth sub-section and the seventh sub-section arranged in sequence; The fifth sub-section, the eleventh sub-section and the seventh sub-section extend along the first direction; An included angle between an extension direction of the sixth sub-section and the second direction, and an included angle between the second directions are both greater than 0; An end of the fifth sub-section away from the sixth sub-section is electrically connected with the signal line, and an end of the seventh sub-section away from the sixth sub-section is electrically connected with the second sub-fan-out line; In two adjacent first portions, the two sixth sub-sections have a substantially overlapping area in a projection of the substrate, the two fifth sub-sections do not overlap with each other in the projection of the substrate, and the two eleventh sub-sections do not overlap with each other in the projection of the substrate; in two adjacent second portions, the two sixth sub-sections have a substantially overlapping area in a projection of the substrate, the two eleventh sub-sections do not overlap with each other in the projection of the substrate, and the two seventh sub-sections do not overlap with each other in the projection of the substrate; In the first fan-out line, an extension direction of the sixth sub-section is the same as an extension direction of the first sub-section.

20. The display substrate according to any one of claims 13-19, wherein, In a plurality of first fan-out lines arranged in sequence away from the second fan-out line, lengths of the second sub-fan-out lines gradually increase; At least part of the second sub-fan-out line includes a twelfth sub-section; An included angle between an extension direction of the twelfth sub-section and the second direction, and an included angle between the second directions are both greater than 0.

21. The display substrate according to any one of claims 1-20, wherein, The display substrate further includes: A plurality of thin film transistors located in the display area; the first conductive layer further includes a gate electrode of the thin film transistor, and the second conductive layer further includes a source electrode and a drain electrode of the thin film transistor.

22. The display substrate according to any one of claims 1-20, wherein, The display substrate further comprises: a plurality of thin film transistors located in the display area; a plurality of light emitting devices located in the display area on a side of the thin film transistors away from the display panel, the light emitting devices comprising an anode, a light emitting functional layer, and a cathode arranged in a stack; a plurality of connecting electrodes located in the display area between the anodes and the drains of the thin film transistors, the anodes being electrically connected to the drains through the connecting electrodes; the first conductive layer further comprises gates of the thin film transistors; the second conductive layer comprises sources and drains of the thin film transistors; or the second conductive layer comprises the connecting electrodes.

23. The display substrate of claim 21 or 22, wherein, The display substrate further comprises: a plurality of light shielding portions located in the display area between the thin film transistors and the substrate; the first fan-out line further comprises a third trace, the third trace being arranged in a same layer as the light shielding portions.

24. A display panel, wherein, The display panel comprises the display substrate according to any one of claims 1-23.

25. A display device comprising: The display device comprises the display panel according to claim 24.

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