Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises a plurality of rows and columns of sub-pixels, a plurality of rows of scanning lines, a first driving module and a light-emitting control signal generation module, wherein the sub-pixels are electrically connected to the scanning lines and are used for accessing a display data voltage under the control of scanning signals provided by the scanning lines; the first driving module comprises multiple stages of first driving circuits; the light-emitting control signal generation module comprises multiple stages of generation circuits; the first driving circuits are used for providing scanning signals for two adjacent rows of sub-pixels; the generation circuits are used for providing light-emitting control signals for at least two rows of sub-pixels; and the plurality of rows and columns of sub-pixels comprise a plurality of first-type sub-pixel rows and a plurality of second-type sub-pixel rows, the type of the first-type sub-pixel rows being different from the type of the second-type sub-pixel rows. The embodiments of the present disclosure can increase the charging time and save the power consumption of a data voltage.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] When implementing an anti-peeping design, only the sub-pixels in the anti-peeping rows can be illuminated in anti-peeping mode, and only the sub-pixels in the shared rows can be illuminated in shared mode. Based on these two modes, the number of sub-pixel rows included in the display panel can be doubled. Since the number of sub-pixel rows included in the display panel is doubled and the display frequency is fixed, if a row-by-row scanning method is used, the time required to charge the sub-pixels with the data voltage is half that of a normal display panel sub-pixel charging time, which may cause uneven display due to insufficient charging time.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display panel comprising a plurality of rows and columns of sub-pixels, a plurality of rows of scan lines, a first driving module, and a light emitting control signal generating module;

[0005] The sub-pixel is electrically connected to the scan line and is used to receive a display data voltage under the control of a scan signal provided by the scan line;

[0006] The first driving module includes a multi-stage first driving circuit; the light emitting control signal generating module includes a multi-stage generating circuit;

[0007] The first driving circuit is used to provide scanning signals for two adjacent rows of sub-pixels;

[0008] The generating circuit is used to provide light emitting control signals for at least two rows of sub-pixels;

[0009] The multiple rows and columns of sub-pixels include multiple rows of first-type sub-pixels and multiple rows of second-type sub-pixels;

[0010] The type of the first-type sub-pixel row is different from the type of the second-type sub-pixel row.

[0011] Optionally, the first type of sub-pixel rows and the second type of sub-pixel rows are alternately arranged.

[0012] Optionally, the first type of sub-pixel row is an anti-peeping row sub-pixel, and the second type of sub-pixel row is a shared row sub-pixel; or, the first type of sub-pixel row is a shared row sub-pixel, and the second type of sub-pixel row is an anti-peeping row sub-pixel.

[0013] Optionally, the display panel further includes a substrate and a light-collecting structure;

[0014] The sub-pixels, the light-focusing structure, the scanning lines, the first driving module and the light-emitting control signal generating module are all arranged on the substrate;

[0015] The light-gathering structure is disposed on a side of the anti-peeping sub-pixel away from the substrate, and is used to gather light emitted by the anti-peeping sub-pixel.

[0016] Optionally, the sub-pixels are arranged in a display area; and the first driving module is arranged in a peripheral area;

[0017] The display panel includes a first driving module, and the first driving module is arranged on the first side or the second side of the display area; or,

[0018] The display panel includes a first first driving module and a second first driving module, wherein the first first driving module is arranged on a first side of the display area, and the second first driving module is arranged on a second side of the display area;

[0019] The first side and the second side are opposite sides.

[0020] Optionally, the display panel according to at least one embodiment of the present disclosure further includes a plurality of rows of reset control lines and a second driving module; the second driving module includes an N-stage second driving circuit; the sub-pixel includes a reset circuit, a driving circuit, and a light-emitting element; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of its control terminal;

[0021] The reset circuit is electrically connected to the reset control line, and is used to provide an initial voltage to the control terminal of the driving circuit under the control of a reset control signal provided by the reset control line;

[0022] The n-th stage second driving circuit is electrically connected to the 2n-1th row reset control line and the 2nth row reset control line, respectively, for providing an n-th reset control signal to the 2n-1th row reset control line and the 2nth reset control line;

[0023] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0024] Optionally, the sub-pixels are arranged in a display area; and the second driving module is arranged in a peripheral area;

[0025] The display panel includes a second driving module, and the second driving module is arranged on the first side or the second side of the display area; or,

[0026] The display panel includes a first second driving module and a second second driving module, wherein the first second driving module is arranged on a first side of the display area, and the second second driving module is arranged on a second side of the display area;

[0027] The first side and the second side are opposite sides.

[0028] Optionally, the generating circuit includes a first generating circuit and a second generating circuit;

[0029] The first generating circuit is used to provide a light emitting control signal for at least one row of sub-pixels of the first type;

[0030] The second generating circuit is used to provide a light emitting control signal for at least one row of sub-pixels of the second type.

[0031] Optionally, the sub-pixels are arranged in a display area; and the light emitting control signal generating module is arranged in a peripheral area;

[0032] The display panel includes a light-emitting control signal generating module, and the light-emitting control signal generating module is arranged on the first side or the second side of the display area; or,

[0033] The display panel includes a first light control signal generating module and a second light control signal generating module; the first light control signal generating module is arranged on a first side of the display area; the second light control signal generating module is arranged on a second side of the display area;

[0034] The first side and the second side are opposite to each other.

[0035] Optionally, the sub-pixel includes a driving circuit and a light-emitting element; the driving circuit is used to drive the light-emitting element to emit light under the control of the potential of its control terminal;

[0036] The sub-pixel further includes a first light emitting control circuit and / or a second light emitting control circuit;

[0037] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0038] The second light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the drive circuit and the light-emitting element respectively, and is used to control the connection or disconnection between the second end of the drive circuit and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line.

[0039] Optionally, the n-th stage first generating circuit is electrically connected to the 2n-1-th row light emitting control line, and is configured to provide the 2n-1-th row light emitting control line with the 2n-1-th row light emitting control signal;

[0040] The n-th stage second generating circuit is electrically connected to the 2n-th row of light-emitting control lines, and is used to provide the 2n-th row of light-emitting control lines with the 2n-th row of light-emitting control signals;

[0041] n is a positive integer less than or equal to N, and N is an integer greater than 1;

[0042] The 2n-1th row of light emitting control lines is electrically connected to the 2n-1th row of sub-pixels, and the 2nth row of light emitting control lines is electrically connected to the 2nth row of sub-pixels;

[0043] The 2n-1th row of sub-pixels is a first type of sub-pixel row, and the 2nth row of sub-pixels is a second type of sub-pixel row.

[0044] Optionally, the first generation circuit of the ath stage is electrically connected to the light emitting control line in the 4a-3 row and the light emitting control line in the 4a-1 row, respectively, for providing light emitting control signals for the light emitting control line in the 4a-3 row and the light emitting control line in the 4a-1 row;

[0045] The a-th level second generating circuit is electrically connected to the 4a-2 row light control line and the 4a row light control line, respectively, for providing light control signals to the 4a-2 row light control line and the 4a row light control line; a is a positive integer;

[0046] The light emitting control line in row 4a-1 is electrically connected to the sub-pixels in row 4a-1, the light emitting control line in row 4a-2 is electrically connected to the sub-pixels in row 4a-2, the light emitting control line in row 4a-3 is electrically connected to the sub-pixels in row 4a-3, and the light emitting control line in row 4a is electrically connected to the sub-pixels in row 4a;

[0047] The 4a-1th row of sub-pixels and the 4a-3th row of sub-pixels are first-type sub-pixel rows, and the 4a-2th row of sub-pixels and the 4ath row of sub-pixels are second-type sub-pixel rows.

[0048] Optionally, the first generation circuit of the ath stage is electrically connected to the 6a-5th row light control line, the 6a-3th row light control line, and the 6a-5th light control line, respectively, for providing light control signals for the 6a-5th row light control line, the 6a-3th row light control line, and the 6a-5th light control line;

[0049] The second generation circuit of the ath stage is electrically connected to the light-emitting control line of the 6a-4th row, the light-emitting control line of the 6a-2th row, and the light-emitting control line of the 6ath row, respectively, and is used to provide light-emitting control signals for the light-emitting control line of the 6a-4th row, the light-emitting control line of the 6a-2th row, and the light-emitting control line of the 6ath row; a is a positive integer;

[0050] The light-emitting control line in the 6a-5 row is electrically connected to the sub-pixels in the 6a-5 row, the light-emitting control line in the 6a-4 row is electrically connected to the sub-pixels in the 6a-4 row, the light-emitting control line in the 6a-3 row is electrically connected to the sub-pixels in the 6a-3 row, the light-emitting control line in the 6a-2 row is electrically connected to the sub-pixels in the 6a-2 row, the light-emitting control line in the 6a-1 row is electrically connected to the sub-pixels in the 6a-1 row, and the light-emitting control line in the 6a row is electrically connected to the sub-pixels in the 6a row; the sub-pixels in the 6a-5 row, the sub-pixels in the 6a-3 row and the sub-pixels in the 6a-1 row are sub-pixels of the first type, and the sub-pixels in the 6a-4 row, the sub-pixels in the 6a-2 row and the sub-pixels in the 6a row are sub-pixels of the second type.

[0051] Optionally, the first generation circuit of the ath stage is electrically connected to the light-emitting control line in row 8a-7, the light-emitting control line in row 8a-5, the light-emitting control line in row 8a-3, and the light-emitting control line in row 8a-1, respectively, for providing light-emitting control signals for the light-emitting control line in row 8a-7, the light-emitting control line in row 8a-5, the light-emitting control line in row 8a-3, and the light-emitting control line in row 8a-1;

[0052] The second generation circuit of the ath level is electrically connected to the light-emitting control line of the 8a-6th row, the light-emitting control line of the 8a-4th row, the light-emitting control line of the 8a-2th row, and the light-emitting control line of the 8ath row, respectively, and is used to provide light-emitting control signals for the light-emitting control line of the 8a-6th row, the light-emitting control line of the 8a-4th row, the light-emitting control line of the 8a-2th row, and the light-emitting control line of the 8ath row; a is a positive integer;

[0053] The light emitting control line in row 8a-7 is electrically connected to the sub-pixels in row 8a-7, the light emitting control line in row 8a-6 is electrically connected to the sub-pixels in row 8a-6, the light emitting control line in row 8a-5 is electrically connected to the sub-pixels in row 8a-5, the light emitting control line in row 8a-4 is electrically connected to the sub-pixels in row 8a-4, the light emitting control line in row 8a-3 is electrically connected to the sub-pixels in row 8a-3, the light emitting control line in row 8a-2 is electrically connected to the sub-pixels in row 8a-2, and the light emitting control line in row 8a-3 is electrically connected to the sub-pixels in row 8a-3. The 8a-1 row light-emitting control line is electrically connected to the 8a-1 row sub-pixels, and the 8a row light-emitting control line is electrically connected to the 8a row sub-pixels; the 8a-7 row sub-pixels, the 8a-5 row sub-pixels, the 8a-3 row sub-pixels and the 8a-1 row sub-pixels are first-type sub-pixel rows, and the 8a-6 row sub-pixels, the 8a-4 row sub-pixels, the 8a-2 row sub-pixels and the 8a row sub-pixels are second-type sub-pixel rows.

[0054] Optionally, the generating circuit is used to provide light emitting control signals for at least one first type sub-pixel row and at least one second type sub-pixel row.

[0055] Optionally, the n-th level generating circuit includes an n-th level generating unit and an n-th level output control unit;

[0056] The n-th generation unit is used to generate an n-th light emitting control signal and output the n-th light emitting control signal through the n-th light emitting control signal output terminal;

[0057] The input end of the n-th level output control unit is electrically connected to the n-th light-emitting control signal output end, the first output end of the n-th level output control unit is electrically connected to the 2n-1-th row light-emitting control line, the second output end of the n-th level output control unit is electrically connected to the 2n-th row light-emitting control line, and the n-th level output control unit is used to provide effective light-emitting control signals to the 2n-1-th row light-emitting control line and the 2n-th row light-emitting control line in a time-sharing manner according to the n-th light-emitting control signal provided by the n-th light-emitting control signal output end; n is an integer less than or equal to N, and N is an integer greater than 1.

[0058] Optionally, the light emitting control line in the 2n-1th row is electrically connected to the sub-pixels in the 2n-1th row, and the light emitting control line in the 2nth row is electrically connected to the sub-pixels in the 2nth row;

[0059] The 2n-1th row of sub-pixels is a first type of sub-pixel row, and the 2nth row of sub-pixels is a second type of sub-pixel row.

[0060] Optionally, the output control unit includes a first control module, a second control module, a third control module and a fourth control module;

[0061] The first control module is electrically connected to the first control terminal, the input terminal of the output control unit, and the first output terminal of the output control unit, respectively, and is used to control the communication between the input terminal and the first output terminal under the control of a first control signal provided by the first control terminal;

[0062] The second control module is electrically connected to the second control terminal, the first voltage line and the first output terminal of the output control unit respectively, and is used to control the communication between the first voltage line and the first output terminal under the control of the second control signal provided by the second control terminal;

[0063] The third control module is electrically connected to the first control terminal, the first voltage line and the second output terminal of the output control unit respectively, and is used to control the communication between the first voltage line and the second output terminal under the control of the first control signal provided by the first control terminal;

[0064] The fourth control module is electrically connected to the second control end, the input end and the second output end respectively, and is used to control the communication between the input end and the second output end under the control of the second control signal provided by the second control end.

[0065] Optionally, the first control module includes a first control transistor, the second control module includes a second control transistor, the third control module includes a third control transistor, and the fourth control module includes a fourth control transistor;

[0066] The gate of the first control transistor is electrically connected to the first control terminal, the first electrode of the first control transistor is electrically connected to the input terminal of the output control unit, and the second electrode of the first control transistor is electrically connected to the first output terminal of the output control unit;

[0067] The gate of the second control transistor is electrically connected to the second control terminal, the first electrode of the second control transistor is electrically connected to the first voltage line, and the second electrode of the second control transistor is electrically connected to the first output terminal of the output control unit;

[0068] The gate of the third control transistor is electrically connected to the first control terminal, the first electrode of the third control transistor is electrically connected to the first voltage line, and the second electrode of the third control transistor is electrically connected to the second output terminal of the output control unit;

[0069] The gate of the fourth control transistor is electrically connected to the second control terminal, the first electrode of the fourth control transistor is electrically connected to the input terminal of the output control unit, and the second electrode of the fourth control transistor is electrically connected to the second output terminal of the output control unit.

[0070] Optionally, the sub-pixel includes a light-emitting element, a driving circuit, a data writing circuit, a reset circuit, a first light-emitting control circuit, and a second light-emitting control circuit;

[0071] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node;

[0072] The data writing circuit is electrically connected to the scan line, the data line and the second node N2 respectively, and is used to write the display data voltage provided by the data line into the second node under the control of the scan signal provided by the scan line;

[0073] The reset circuit is electrically connected to the reset control line, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal provided by the reset control line RE;

[0074] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0075] The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0076] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0077] Optionally, the light-focusing structure includes a microlens and / or a light-shielding structure;

[0078] The light shielding structure surrounds an opening area corresponding to the anti-peeping row sub-pixel.

[0079] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] FIG1 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0081] FIG2 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0082] FIG3 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0083] FIG4 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0084] FIG5 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0085] FIG6 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0086] FIG7 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0087] FIG8 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0088] FIG9 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0089] FIG10 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0090] FIG11 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0091] FIG12 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0092] FIG13 is a block diagram of at least one embodiment of an output control unit;

[0093] FIG14 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0094] FIG15 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0095] FIG16 is a circuit diagram of at least one embodiment of the output control unit;

[0096] FIG17 is a structural diagram of at least one embodiment of a sub-pixel;

[0097] FIG. 18 is a circuit diagram of at least one embodiment of the sub-pixel. DETAILED DESCRIPTION

[0098] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0099] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0100] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0101] The display panel according to the embodiment of the present disclosure includes multiple rows and columns of sub-pixels, multiple rows of scan lines, a first driving module and a light emitting control signal generating module;

[0102] The sub-pixel is electrically connected to the scan line and is used to receive a display data voltage under the control of a scan signal provided by the scan line;

[0103] The first driving module includes a multi-stage first driving circuit; the light emitting control signal generating module includes a multi-stage generating circuit;

[0104] The first driving circuit is used to provide scanning signals for two adjacent rows of sub-pixels;

[0105] The generating circuit is used to provide light emitting control signals for at least two rows of sub-pixels;

[0106] The multiple rows and columns of sub-pixels include multiple rows of first-type sub-pixels and multiple rows of second-type sub-pixels;

[0107] The type of the first-type sub-pixel row is different from the type of the second-type sub-pixel row.

[0108] Optionally, the first type of sub-pixel row may be an anti-peeping row sub-pixel, and the second type of sub-pixel row may be a shared row sub-pixel; or, the first type of sub-pixel row may be a shared row sub-pixel, and the second type of sub-pixel row may be an anti-peeping row sub-pixel.

[0109] The display panel according to at least one embodiment of the present disclosure may further include a substrate and a light-collecting structure;

[0110] The sub-pixels, the light-focusing structure, the scanning lines, the first driving module and the light-emitting control signal generating module are all arranged on the substrate;

[0111] The light-gathering structure is disposed on a side of the anti-peeping sub-pixel away from the substrate, and is used to gather light emitted by the anti-peeping sub-pixel.

[0112] When performing anti-peeping design, six sub-pixels can be designed in two rows and three columns within one pixel space. The three columns of sub-pixels in the first row are red, green, and blue sub-pixels respectively, and the three columns of sub-pixels in the second row are red, green, and blue sub-pixels respectively.

[0113] In the anti-peeping mode, only the anti-peeping row sub-pixels are lit, and in the sharing mode, only the shared row sub-pixels are lit; the anti-peeping row sub-pixels may be the first row sub-pixels or the second row sub-pixels, and the shared row sub-pixels may be the second row sub-pixels or the first row sub-pixels;

[0114] A microlens and other structures are designed in the encapsulation layer above the light-emitting elements in the anti-peeping row sub-pixels to gather the light emitted by the light-emitting elements. At the same time, a light-shielding layer is provided above the anti-peeping row sub-pixels. The light-shielding layer surrounds the corresponding pixel opening area to reduce the light emission angle of the light-emitting elements in the anti-peeping row sub-pixels, thereby achieving an anti-peeping effect. There is no focusing structure designed above the light-emitting elements of the shared row sub-pixels, so the light emission of the shared row sub-pixels can achieve a large angle, thereby achieving a sharing effect.

[0115] Based on the above two modes, the number of rows of sub-pixels included in the display panel can be doubled, and the sub-pixels in the odd-numbered rows can be set as anti-peeping sub-pixels, and the sub-pixels in the even-numbered rows can be set as shared sub-pixels; or the sub-pixels in the even-numbered rows can be set as anti-peeping sub-pixels, and the sub-pixels in the odd-numbered rows can be set as shared sub-pixels;

[0116] When the resolution of the display panel is N×M (N and M are positive integers), the display panel may be configured to include 2N rows of sub-pixels;

[0117] Since the number of rows of sub-pixels included in the display panel is doubled and the display frequency is fixed, if a row-by-row scanning method is adopted, the time for charging the sub-pixels through the data voltage is half the charging time of the sub-pixels of a normal display panel, and the problem of uneven display caused by insufficient charging time may be encountered; when the anti-peep row sub-pixels or the shared row sub-pixels are lit, they need to be lit alternately, so that the data voltage needs to be adjusted to the black screen voltage alternately, and the power consumption of the data voltage will increase.

[0118] In at least one embodiment of the present disclosure, the odd-numbered row sub-pixels refer to the sub-pixels located in the odd-numbered rows counted from the sub-pixels that actually emit light, and the even-numbered row sub-pixels refer to the sub-pixels located in the even-numbered rows counted from the sub-pixels that actually emit light, without counting the number of rows of dummy sub-pixels.

[0119] Based on the above issues, the display panel described in at least one embodiment of the present disclosure includes multiple rows of scan lines and a first driver module. The first driver module includes N stages of first driver circuits. The nth stage first driver circuit provides the nth scan signal to the 2n-1th scan line and the 2nth scan line. The same scan signal is provided to two adjacent rows of sub-pixels via the first stage first driver circuit. Under the control of the scan signal, the sub-pixels are connected to the display data voltage. This doubles the charging time for each row of sub-pixels. During the light-emitting phase, in anti-peeping mode, a light-emitting control signal generation module for light-emitting control controls the light emission of the sub-pixels in the anti-peeping row. In shared mode, a light-emitting control signal generation module for light-emitting control controls the light emission of the sub-pixels in the shared row. The disclosed embodiments can increase charging time and save power consumption of the data voltage.

[0120] In at least one embodiment of the present disclosure, the first-type sub-pixel rows and the second-type sub-pixel rows may be alternately arranged, but the present invention is not limited thereto.

[0121] Optionally, the light-focusing structure may include a microlens and / or a light-shielding structure;

[0122] The light shielding structure surrounds an opening area corresponding to the anti-peeping row sub-pixel.

[0123] In at least one embodiment of the present disclosure, compared with a related display panel, the number of rows of sub-pixels used is doubled, and the height of each row of sub-pixels is reduced.

[0124] For example, when the PPI (pixel density) of the relevant display panel is 208, the height of each row of sub-pixels can be 122.1 μm. When the technology in at least one embodiment of the present disclosure is adopted, the height of each row of sub-pixels can be reduced to half of the original height, that is, the height of each row of sub-pixels can be 62.05 μm.

[0125] As shown in Figure 1, the area labeled A0 is the display area;

[0126] The pixels labeled R1 are the sub-pixels in the first row, the pixels labeled R2 are the sub-pixels in the second row, the pixels labeled R3 are the sub-pixels in the third row, the pixels labeled R4 are the sub-pixels in the fourth row, the pixels labeled R2N-3 are the sub-pixels in the 2N-3th row, the pixels labeled R2N-2 are the sub-pixels in the 2N-2th row, the pixels labeled R2N-1 are the sub-pixels in the 2N-1th row, and the pixels labeled R2N are the sub-pixels in the 2Nth row.

[0127] The display panel according to at least one embodiment of the present disclosure may include a first row of scan lines GL1, a second row of scan lines GL2, a third row of scan lines GL3, a fourth row of scan lines GL4, a 2N-3th row of scan lines GL2N-3, a 2N-2th row of scan lines GL2N-2, a 2N-1th row of scan lines GL2N-1, and a 2Nth row of scan lines GL2N;

[0128] As shown in FIG1 , the display panel according to at least one embodiment of the present disclosure may include a first driving module, which may include a first-stage first driving circuit GT1, a second-stage first driving circuit GT2, an N-1th-stage first driving circuit GTN-1, and an Nth-stage first driving circuit GTN;

[0129] The first-stage first driving circuit GT1, the second-stage first driving circuit GT2, the N-1th-stage first driving circuit GTN-1 and the Nth-stage first driving circuit GTN are arranged on the left side of the display area A0;

[0130] GT1 is electrically connected to GL1 and GL2, GT2 is electrically connected to GL3 and GL4, GTN-1 is electrically connected to GL2N-3 and GL2N-2, and GTN is electrically connected to GL2N-1 and GL2N;

[0131] GT1 is used to provide the first scanning signal for GL1 and GL2;

[0132] GT2 is used to provide the second scanning signal for GL3 and GL4;

[0133] GTN-1 is used to provide the N-1 scanning signal for GL2N-3 and GL2N-2;

[0134] GTN is used to provide the Nth scanning signal for GL2N-1 and GL2N.

[0135] As shown in FIG2 , based on at least one embodiment of the display panel shown in FIG1 , the display panel according to at least one embodiment of the present disclosure may include a light emitting control signal generating module;

[0136] The light emitting control signal generating module may include a first-level generating circuit EMR1, a second-level generating circuit EMR2, an N-1th-level generating circuit EMRN-1, and an N-level generating circuit EMRN;

[0137] EMR1, EMR2, EMRN-1, and EMRN are all set to the left of display area A0;

[0138] EMR1 is electrically connected to the first row of light emitting control lines EM1 and the second row of light emitting control lines EM2, and is used to provide light emitting control signals to the first row of light emitting control lines EM1 and the second row of light emitting control lines EM2;

[0139] EMR2 is electrically connected to the third row of light emitting control lines EM3 ​​and the fourth row of light emitting control lines EM4, and is used to provide light emitting control signals to the third row of light emitting control lines EM3 ​​and the fourth row of light emitting control lines EM4;

[0140] EMRN-1 is electrically connected to the 2N-3-th row of light-emitting control line EM2N-3 and the 2N-2-th row of light-emitting control line EM2N-2, and is used to provide light-emitting control signals to the 2N-3-th row of light-emitting control line EM2N-3 and the 2N-2-th row of light-emitting control line EM2N-2;

[0141] EMRN is electrically connected to the 2N-1th row of light emitting control line EM2N-1 and the 2Nth row of light emitting control line EM2N, and is used to provide light emitting control signals to the 2N-1th row of light emitting control line EM2N-1 and the 2Nth row of light emitting control line EM2N.

[0142] As shown in FIG3 , based on at least one embodiment of the display panel shown in FIG1 , the display panel according to at least one embodiment of the present disclosure may include a light emitting control signal generating module;

[0143] The light emitting control signal generating module may include a first-level generating circuit EMR1 and a B-level generating circuit EMRB; B is a positive integer;

[0144] Both EMR1 and EMRB are set to the left of display area A0;

[0145] EMR1 is electrically connected to the first row of light-emitting control lines EM1, the second row of light-emitting control lines EM2, the third row of light-emitting control lines EM3, and the fourth row of light-emitting control lines EM4, and is used to provide light-emitting control signals to the first row of light-emitting control lines EM1, the second row of light-emitting control lines EM2, the third row of light-emitting control lines EM3, and the fourth row of light-emitting control lines EM4;

[0146] EMRB is electrically connected to the 2N-3rd row light-emitting control line EM2N-3, the 2N-2nd row light-emitting control line EM2N-2, the 2N-1st row light-emitting control line EM2N-1, and the 2Nth row light-emitting control line EM2N, and is used to provide light-emitting control signals for the 2N-3rd row light-emitting control line EM2N-3, the 2N-2nd row light-emitting control line EM2N-2, the 2N-1st row light-emitting control line EM2N-1, and the 2Nth row light-emitting control line EM2N.

[0147] In at least one embodiment of the present disclosure, the sub-pixels are disposed in a display area; the first driving module is disposed in a peripheral area;

[0148] The display panel includes a first driving module, and the first driving module is arranged on the first side or the second side of the display area; or,

[0149] The display panel includes a first first driving module and a second first driving module, wherein the first first driving module is arranged on a first side of the display area, and the second first driving module is arranged on a second side of the display area;

[0150] The first side and the second side are opposite sides.

[0151] In at least one embodiment shown in FIG1 , a first-level driving circuit is used to provide scanning signals for two adjacent rows of scanning lines, so as to increase the charging time for each row of sub-pixels, thereby doubling the charging time for each row of sub-pixels, and the data voltage does not need to jump to the black screen voltage every other row, thereby saving power consumption of the data voltage.

[0152] In a specific implementation, the sub-pixel can be set in the display area, the first driving module can be set in the peripheral area, and the peripheral area surrounds the display area; the display panel can include a first driving module, and the first driving module can be set on the left or right side of the display area; or, the display panel can include a first first driving module and a second first driving module, the first first driving module is set on the left side of the display area, and the second first driving module is set on the right side of the display area.

[0153] As shown in FIG4 , the area labeled A0 is the display area;

[0154] The pixels labeled R1 are the sub-pixels in the first row, the pixels labeled R2 are the sub-pixels in the second row, the pixels labeled R3 are the sub-pixels in the third row, the pixels labeled R4 are the sub-pixels in the fourth row, the pixels labeled R2N-3 are the sub-pixels in the 2N-3th row, the pixels labeled R2N-2 are the sub-pixels in the 2N-2th row, the pixels labeled R2N-1 are the sub-pixels in the 2N-1th row, and the pixels labeled R2N are the sub-pixels in the 2Nth row.

[0155] The display panel according to at least one embodiment of the present disclosure may include a first row of scan lines GL1, a second row of scan lines GL2, a third row of scan lines GL3, a fourth row of scan lines GL4, a 2N-3th row of scan lines GL2N-3, a 2N-2th row of scan lines GL2N-2, a 2N-1th row of scan lines GL2N-1, and a 2Nth row of scan lines GL2N;

[0156] The sub-pixel R1 in the first row is electrically connected to GL1, the sub-pixel R2 in the second row is electrically connected to GL2, the sub-pixel R3 in the third row is electrically connected to GL3, the sub-pixel R4 in the fourth row is electrically connected to GL4, the sub-pixel R2N-3 in the 2N-3 row is electrically connected to GL2N-3, the sub-pixel R2N-2 in the second row is electrically connected to GL2N-2, the sub-pixel R2N-1 in the third row is electrically connected to GL2N-1, and the sub-pixel R2N in the fourth row is electrically connected to GL2N;

[0157] The display panel according to at least one embodiment of the present disclosure may include a first first driving module and a second first driving module;

[0158] The first-stage first driving circuit included in the first first driving module is labeled GT11, the second-stage first driving module included in the first first driving circuit is labeled GT12, the N-1th-stage first driving circuit included in the first first driving module is labeled GT1N-1, and the Nth-stage first driving circuit included in the first first driving module is labeled GT1N;

[0159] The first-stage first driving circuit included in the second first driving module is labeled GT21, the second-stage first driving circuit included in the second first driving module is labeled GT22, the N-1th-stage first driving circuit included in the second first driving module is labeled GT2N-1, and the Nth-stage first driving circuit included in the second first driving module is labeled GT2N;

[0160] The first first driving module is disposed on the left side of the display area A0, and the second first driving module is disposed on the right side of the display area A0;

[0161] GT11 is used to provide the first scanning signal for GL1 and GL2; GT21 is used to provide the second scanning signal for GL1 and GL2;

[0162] GT12 is used to provide the first second scanning signal for GL3 and GL4; GT22 is used to provide the second second scanning signal for GL3 and GL4;

[0163] GT1N-1 is used to provide the first N-1 scanning signal for GL2N-3 and GL2N-2; GT2N-1 is used to provide the second N-1 scanning signal for GL2N-3 and GL2N-2;

[0164] GT1N is used to provide the first Nth scanning signal for GL2N-1 and GL2N; GT2N is used to provide the second Nth scanning signal for GL2N-1 and GL2N.

[0165] In at least one embodiment shown in FIG. 4 , a first driving circuit located on the left side of the display area and a first driving circuit located on the right side of the display area simultaneously provide scanning signals to two adjacent rows of scanning lines, so as to increase the charging time for each row of sub-pixels, thereby doubling the charging time for each row of sub-pixels, and the data voltage does not need to jump to the black screen voltage every other row, thereby saving power consumption of the data voltage.

[0166] The display panel according to at least one embodiment of the present disclosure further includes a plurality of rows of reset control lines and a second driving module; the second driving module includes an N-stage second driving circuit; the sub-pixel includes a reset circuit, a driving circuit, and a light-emitting element; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of its control terminal;

[0167] The reset circuit is electrically connected to the reset control line, and is used to provide an initial voltage to the control terminal of the driving circuit under the control of a reset control signal provided by the reset control line;

[0168] The nth stage second driving circuit is electrically connected to the 2n-1th row reset control line and the 2nth row reset control line respectively, and is used to provide the nth reset control signal to the 2n-1th row reset control line and the 2nth reset control line.

[0169] In at least one embodiment of the present disclosure, the display panel may further include multiple rows of reset control lines and a second driving module, the second driving module including N levels of second driving circuits, the nth level second driving circuit providing an nth reset control signal for the 2n-1th row reset control line and the 2nth reset control line, and providing the same reset control signal for two adjacent rows of reset control lines through a first-level second driving circuit, so as to reduce the number of levels of the second driving circuits used, thereby facilitating the realization of a narrow frame; the reset circuit in the sub-pixel writes an initial voltage into the control end of the driving circuit in the sub-pixel under the control of the reset control signal to reset the potential of the control end of the driving circuit.

[0170] As shown in FIG5 , based on at least one embodiment of the display panel shown in FIG1 , the display panel according to at least one embodiment of the present disclosure further includes a second driving module;

[0171] The display panel according to at least one embodiment of the present disclosure further includes a first row reset control line RL1, a second row reset control line RL2, a third row reset control line RL3, a fourth row reset control line RL4, a 2N-3 row reset control line RL2N-3, a 2N-2 row reset control line RL2N-2, a 2N-1 row reset control line RL2N-1, and a 2N row reset control line RL2N;

[0172] The second driving module includes a first-stage second driving circuit RE1, a second-stage second driving circuit RE2, an N-1th-stage second driving circuit REN-1 and an Nth-stage second driving circuit REN;

[0173] The second driving module is arranged on the left side of the display area A0;

[0174] RE1 is used to provide a first reset control signal for RL1 and RL2;

[0175] RE2 is used to provide a second reset control signal for RL3 and RL4;

[0176] REN-1 is used to provide the N-1th reset control signal to RL2N-3 and RL2N-2;

[0177] REN is used to provide the Nth reset control signal for RL2N-1 and RL2N.

[0178] In at least one embodiment of the display panel shown in FIG5 , a reset control signal is provided to two adjacent rows of sub-pixels via a first-level second driving circuit, so as to cooperate with the scan signal and increase the charging time of the sub-pixels.

[0179] Optionally, the sub-pixels are arranged in a display area; and the second driving module is arranged in a peripheral area;

[0180] The display panel includes a second driving module, and the second driving module is arranged on the first side or the second side of the display area; or,

[0181] The display panel includes a first second driving module and a second second driving module, wherein the first second driving module is arranged on a first side of the display area, and the second second driving module is arranged on a second side of the display area;

[0182] The first side and the second side are opposite sides.

[0183] In a specific implementation, the display panel may include a second driving module, which is arranged on the left or right side of the display area; or, the display panel may include a first second driving module and a second second driving module, the first second driving module is arranged on the left side of the display area, and the second second driving module is arranged on the right side of the display area.

[0184] As shown in FIG6 , based on at least one embodiment of the display panel shown in FIG4 ,

[0185] The display panel according to at least one embodiment of the present disclosure further includes a first second driving module and a second second driving module;

[0186] The display panel according to at least one embodiment of the present disclosure further includes a first row reset control line RL1, a second row reset control line RL2, a third row reset control line RL3, a fourth row reset control line RL4, a 2N-3 row reset control line RL2N-3, a 2N-2 row reset control line RL2N-2, a 2N-1 row reset control line RL2N-1, and a 2N row reset control line RL2N;

[0187] The first-stage second driving circuit included in the first second driving module is labeled RE11, the first-stage second driving circuit included in the first second driving module is labeled RE12, the N-1th-stage second driving circuit included in the first second driving module is labeled RE1N-1, and the Nth-stage second driving circuit included in the first second driving module is labeled RE1N;

[0188] The first-stage second driving circuit included in the second second driving module is labeled RE21, the first-stage second driving circuit included in the second second driving module is labeled RE22, the N-1th-stage second driving circuit included in the second second driving module is labeled RE2N-1, and the Nth-stage second driving circuit included in the second second driving module is labeled RE2N;

[0189] The first second driving module is disposed on the left side of the display area A0, and the second second driving module is disposed on the right side of the display area A0;

[0190] RE11 is used to provide a first reset control signal for RL1 and RL2; RE21 is used to provide a second first reset control signal for RL1 and RL2;

[0191] RE12 is used to provide a first second reset control signal for RL3 and RL4; RE22 is used to provide a second second reset control signal for RL3 and RL4;

[0192] RE1N-1 is used to provide the first N-1th reset control signal to RL2N-3 and RL2N-2; RE2N-1 is used to provide the second N-1th reset control signal to RL2N-3 and RL2N-2;

[0193] RE1N is used to provide the first Nth reset control signal for RL2N-1 and RL2N; RE2N is used to provide the second Nth reset control signal for RL2N-1 and RL2N.

[0194] In at least one embodiment of the display panel shown in FIG6 , a reset control signal is provided to two adjacent rows of sub-pixels simultaneously by a first-level second driving circuit located on the left side of the display area and a first-level second driving circuit located on the right side of the display area, so as to cooperate with the scanning signal to improve the charging time of the sub-pixels.

[0195] In at least one embodiment of the present disclosure, the generating circuit may include a first generating circuit and a second generating circuit;

[0196] The first generating circuit is used to provide a light emitting control signal for at least one row of sub-pixels of the first type;

[0197] The second generating circuit is used to provide a light emitting control signal for at least one row of sub-pixels of the second type.

[0198] In a specific implementation, the generating circuit may include a first generating circuit and a second generating circuit; the first generating circuit provides a light emitting control signal for a first type of sub-pixel row; the second generating circuit provides a light emitting control signal for a second type of sub-pixel row.

[0199] For example, when the first type of sub-pixel row is an anti-peeping row sub-pixel, and the second type of sub-pixel row is a shared row sub-pixel, the first generation circuit provides a light-emitting control signal for the anti-peeping row sub-pixel; and the second generation circuit provides a light-emitting control signal for the shared row sub-pixel. The first generation circuit and the second generation circuit can provide effective light-emitting control signals to the anti-peeping row light-emitting control line and the shared row light-emitting control line in a time-sharing manner to control the anti-peeping row sub-pixel and the shared row sub-pixel to emit light in a time-sharing manner, so as to realize the anti-peeping mode and the shared mode in a time-sharing manner.

[0200] When the first type of sub-pixel behavior is a shared row sub-pixel and the second type of sub-pixel behavior is an anti-peep row sub-pixel, the first generating circuit provides a light-emitting control signal for the shared row sub-pixel; the second generating circuit provides a light-emitting control signal for the anti-peep row sub-pixel; the first generating circuit and the second generating circuit can provide effective light-emitting control signals to the shared row light-emitting control line and the anti-peep row light-emitting control line in a time-sharing manner to control the shared row sub-pixels and the anti-peep row sub-pixels to emit light in a time-sharing manner, so as to be able to realize the shared mode and the anti-peep mode in a time-sharing manner.

[0201] In a specific implementation, the sub-pixel is electrically connected to a light emitting control line; when the light emitting control line receives a valid light emitting control signal, the transistor for light emitting control in the sub-pixel electrically connected to the light emitting control line is turned on.

[0202] In at least one embodiment of the present disclosure, the sub-pixels are disposed in the display area; the light emitting control signal generating module is disposed in the peripheral area;

[0203] The display panel includes a light-emitting control signal generating module, and the light-emitting control signal generating module is arranged on the first side or the second side of the display area; or,

[0204] The display panel includes a first light control signal generating module and a second light control signal generating module; the first light control signal generating module is arranged on a first side of the display area; the second light control signal generating module is arranged on a second side of the display area;

[0205] The first side and the second side are opposite to each other.

[0206] In a specific implementation, the display panel may include a light-emitting control signal generating module, which may be arranged on the left or right side of the display area; or, the display panel may include a first light-emitting control signal generating module and a second light-emitting control signal generating module; the first light-emitting control signal generating module may be arranged on the left side of the display area; the second light-emitting control signal generating module may be arranged on the right side of the display area.

[0207] Optionally, the sub-pixel includes a driving circuit and a light-emitting element; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of its control terminal;

[0208] The sub-pixel further includes a first light emitting control circuit and / or a second light emitting control circuit;

[0209] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0210] The second light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the drive circuit and the light-emitting element respectively, and is used to control the connection or disconnection between the second end of the drive circuit and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line.

[0211] In a specific implementation, the sub-pixel may include a first light-emitting control circuit and / or a second light-emitting control circuit. The first light-emitting control circuit controls the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of a light-emitting control signal. The second light-emitting control circuit controls the connection or disconnection between the second terminal of the driving circuit and the light-emitting element under the control of the light-emitting control signal to perform light-emitting control.

[0212] When the sub-pixel receives a valid light-emitting control signal, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal, and the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the light-emitting element under the control of the light-emitting control signal.

[0213] In at least one embodiment of the present disclosure, the n-th stage first generating circuit is electrically connected to the 2n-1-th row light emitting control line, and is configured to provide the 2n-1-th row light emitting control line with the 2n-1-th row light emitting control signal;

[0214] The n-th stage second generating circuit is electrically connected to the 2n-th row of light-emitting control lines, and is used to provide the 2n-th row of light-emitting control lines with the 2n-th row of light-emitting control signals;

[0215] n is a positive integer less than or equal to N, and N is an integer greater than 1;

[0216] The 2n-1th row of light emitting control lines is electrically connected to the 2n-1th row of sub-pixels, and the 2nth row of light emitting control lines is electrically connected to the 2nth row of sub-pixels;

[0217] The 2n-1th row of sub-pixels is a first type of sub-pixel row, and the 2nth row of sub-pixels is a second type of sub-pixel row.

[0218] In a specific implementation, the n-th level first generating circuit provides the 2n-1th row light-emitting control signal for the 2n-1th row light-emitting control line; the n-th level second generating circuit provides the 2nth row light-emitting control signal for the 2nth row light-emitting control line, that is,

[0219] When the 2n-1th row light control line is the anti-peeping row light control line and the 2nth row light control line is the shared row light control line, the nth-stage first generation circuit provides a corresponding light control signal for the anti-peeping row light control line, and the nth-stage second generation circuit provides a corresponding light control signal for the shared row light control line;

[0220] When the 2n-1th row light control line is a shared row light control line and the 2nth row light control line is an anti-peeping row light control line, the nth-level first generation circuit provides a corresponding light control signal for the shared row light control line, and the nth-level second generation circuit provides a corresponding light control signal for the anti-peeping row light control line.

[0221] The anti-peeping row light-emitting control line is electrically connected to the anti-peeping row sub-pixel, and the shared row light-emitting control line is electrically connected to the shared row sub-pixel.

[0222] As shown in FIG7 , in at least one embodiment of the display panel shown in FIG5 , the display panel according to at least one embodiment of the present disclosure further includes a light emitting control signal generating module;

[0223] The display panel according to at least one embodiment of the present disclosure further includes a first row of light emitting control lines EM1, a second row of light emitting control lines EM2, a third row of light emitting control lines EM3, a fourth row of light emitting control lines EM4, a 2N-3 row of light emitting control lines EM2N-3, a 2N-2 row of light emitting control lines EM2N-2, a 2N-1 row of light emitting control lines EM2N-1, and a 2N row of light emitting control lines EM2N.

[0224] The light emitting control signal generating module includes a first-level generating circuit, a second-level generating circuit, an N-1th-level generating circuit and an Nth-level generating circuit;

[0225] The first-stage generating circuit includes a first-stage first generating circuit EMO1 and a first-stage second generating circuit EME1, the second-stage generating circuit includes a second-stage first generating circuit EMO2 and a second-stage second generating circuit EME2, the N-1-th-stage generating circuit includes an N-1-th-stage first generating circuit EMO N-1 and an N-1-th-stage second generating circuit EMEN-1, and the N-stage generating circuit includes an N-stage first generating circuit EMO N and an N-stage second generating circuit EMEN;

[0226] The light emitting control signal generating module is arranged on the left side of the display area A0;

[0227] EMO1 is used to provide a first light-emitting control signal for EM1, and EME1 is used to provide a second light-emitting control signal for EM2;

[0228] EMO2 is used to provide a third light-emitting control signal to EM3, and EME2 is used to provide a fourth light-emitting control signal to EM4;

[0229] EMON-1 is used to provide EM2N-3 with the 2N-3 light control signal, and EMEN-1 is used to provide EM2N-2 with the 2N-2 light control signal.

[0230] EMON is used to provide EM2N-1 with a 2N-1 light control signal, and EMEN is used to provide EM2N with a 2N-1 light control signal.

[0231] In at least one embodiment of the display panel shown in FIG. 7 ,

[0232] When EM1, EM3, EM2N-3, and EM2N-1 are anti-peeping row light-emitting control lines, and EM2, EM4, EM2N-2, and EM2N are shared row light-emitting control lines, the first generation circuits at each level provide corresponding light-emitting control signals for the anti-peeping row light-emitting control lines, and the second generation circuits at each level provide corresponding light-emitting control signals for the shared row light-emitting control lines, so as to control the time-sharing opening of the anti-peeping row sub-pixels and the shared row sub-pixels, thereby realizing the anti-peeping mode and the shared mode while improving the charging time of the sub-pixels;

[0233] When EM1, EM3, EM2N-3 and EM2N-1 are shared row light-emitting control lines, and EM2, EM4, EM2N-2 and EM2N are anti-peeping row light-emitting control lines, the first generating circuits at each level provide corresponding light-emitting control signals for the shared row light-emitting control lines, and the second generating circuits at each level provide corresponding light-emitting control signals for the anti-peeping row light-emitting control lines, so as to control the time-sharing opening of the shared row sub-pixels and the anti-peeping row sub-pixels, thereby realizing the shared mode and the anti-peeping mode while improving the charging time of the sub-pixels.

[0234] As shown in FIG8 , in at least one embodiment of the display panel shown in FIG6 , the display panel according to at least one embodiment of the present disclosure includes a first light control signal generating module and a second light control signal generating module; the first light control signal generating module is disposed on the left side of the display area; and the second light control signal generating module is disposed on the right side of the display area;

[0235] The display panel according to at least one embodiment of the present disclosure further includes a first row of light emitting control lines EM1, a second row of light emitting control lines EM2, a third row of light emitting control lines EM3, a fourth row of light emitting control lines EM4, a 2N-3 row of light emitting control lines EM2N-3, a 2N-2 row of light emitting control lines EM2N-2, a 2N-1 row of light emitting control lines EM2N-1, and a 2N row of light emitting control lines EM2N.

[0236] The first-stage first generation circuit included in the first light-emitting control signal generation module is labeled EMO11, the second-stage first generation circuit included in the first light-emitting control signal generation module is labeled EMO12, the N-1th-stage first generation circuit included in the first light-emitting control signal generation module is labeled EMO1N-1, and the Nth-stage first generation circuit included in the first light-emitting control signal generation module is labeled EMO1N;

[0237] The first-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME11, the second-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME12, the N-1th-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME1N-1, and the Nth-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME1N;

[0238] The first-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO21, the second-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO22, the N-1th-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO2N-1, and the Nth-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO2N;

[0239] The first-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME21, the second-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME22, the N-1th-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME2N-1, and the Nth-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME2N;

[0240] EMO11 is used to provide a first light-emitting control signal for EM1, and EMO21 is used to provide a second first light-emitting control signal for EM1;

[0241] EME11 is used to provide a first second light-emitting control signal to EM2, and EME21 is used to provide a second second light-emitting control signal to EM2;

[0242] EMO12 is used to provide the first to third light-emitting control signals for EM3, and EMO22 is used to provide the second to third light-emitting control signals for EM3;

[0243] EME12 is used to provide a first fourth light-emitting control signal to EM4, and EME22 is used to provide a second fourth light-emitting control signal to EM4;

[0244] EMO1N-1 is used to provide the first 2N-3 light control signal to EM2N-3, and EMO2N-1 is used to provide the second 2N-3 light control signal to EM2N-3;

[0245] EME1N-1 is used to provide the first 2N-2 light control signal to EM2N-2, and EME2n-1 is used to provide the second 2N-2 light control signal to EM2N-2;

[0246] EMO1N is used to provide the first 2N-1 light-emitting control signal to EM2N-1, and EMO2N is used to provide the second 2N-1 light-emitting control signal to EM2N-1;

[0247] EME1N is used to provide a first 2Nth light-emitting control signal to EM2N, and EME2n is used to provide a second 2Nth light-emitting control signal to EM2N.

[0248] In at least one embodiment of the display panel shown in FIG8 , when EM1, EM3, EM2N-3, and EM2N-1 are anti-peeping row light-emitting control lines, and EM2, EM4, EM2N-2, and EM2N are shared row light-emitting control lines, the first generation circuits at each level provide corresponding light-emitting control signals for the anti-peeping row light-emitting control lines, and the second generation circuits at each level provide corresponding light-emitting control signals for the shared row light-emitting control lines, thereby controlling the time-sharing opening of the anti-peeping row sub-pixels and the shared row sub-pixels, thereby achieving an anti-peeping mode and a shared mode while improving the charging time of the sub-pixels.

[0249] When EM1, EM3, EM2N-3 and EM2N-1 are shared row light-emitting control lines, and EM2, EM4, EM2N-2 and EM2N are anti-peeping row light-emitting control lines, the first generating circuits at each level provide corresponding light-emitting control signals for the shared row light-emitting control lines, and the second generating circuits at each level provide corresponding light-emitting control signals for the anti-peeping row light-emitting control lines, so as to control the time-sharing opening of the shared row sub-pixels and the anti-peeping row sub-pixels, thereby realizing the shared mode and the anti-peeping mode while improving the charging time of the sub-pixels.

[0250] Optionally, the first generation circuit of the ath stage is electrically connected to the light emitting control line in the 4a-3 row and the light emitting control line in the 4a-1 row, respectively, for providing light emitting control signals for the light emitting control line in the 4a-3 row and the light emitting control line in the 4a-1 row;

[0251] The a-th level second generating circuit is electrically connected to the 4a-2 row light control line and the 4a row light control line, respectively, for providing light control signals to the 4a-2 row light control line and the 4a row light control line; a is a positive integer;

[0252] The light emitting control line in row 4a-1 is electrically connected to the sub-pixels in row 4a-1, the light emitting control line in row 4a-2 is electrically connected to the sub-pixels in row 4a-2, the light emitting control line in row 4a-3 is electrically connected to the sub-pixels in row 4a-3, and the light emitting control line in row 4a is electrically connected to the sub-pixels in row 4a;

[0253] The 4a-1th row of sub-pixels and the 4a-3th row of sub-pixels are first-type sub-pixel rows, and the 4a-2th row of sub-pixels and the 4ath row of sub-pixels are second-type sub-pixel rows.

[0254] In a specific implementation, when the 4a-3 row light control line and the 4a-1 row light control line are anti-peep row light control lines, and the 4a-2 row light control line and the 4a row light control line are shared row light control lines, the first generation circuits at each level can provide light control signals for the two anti-peep row light control lines, and the second generation circuits at each level can provide light control signals for the two shared row light control lines.

[0255] When the 4a-3 row light-emitting control line and the 4a-1 row light-emitting control line are shared row light-emitting control lines, and the 4a-2 row light-emitting control line and the 4a row light-emitting control line are anti-peeping row light-emitting control lines, the first generating circuits at each level can provide light-emitting control signals for the two rows of shared row light-emitting control lines, and the second generating circuits at each level can provide light-emitting control signals for the two rows of anti-peeping row light-emitting control lines.

[0256] Optionally, the first generation circuit of the ath stage is electrically connected to the 6a-5th row light control line, the 6a-3th row light control line, and the 6a-5th light control line, respectively, for providing light control signals for the 6a-5th row light control line, the 6a-3th row light control line, and the 6a-5th light control line;

[0257] The second generation circuit of the ath stage is electrically connected to the light-emitting control line of the 6a-4th row, the light-emitting control line of the 6a-2th row, and the light-emitting control line of the 6ath row, respectively, and is used to provide light-emitting control signals for the light-emitting control line of the 6a-4th row, the light-emitting control line of the 6a-2th row, and the light-emitting control line of the 6ath row; a is a positive integer;

[0258] The light-emitting control line in the 6a-5 row is electrically connected to the sub-pixels in the 6a-5 row, the light-emitting control line in the 6a-4 row is electrically connected to the sub-pixels in the 6a-4 row, the light-emitting control line in the 6a-3 row is electrically connected to the sub-pixels in the 6a-3 row, the light-emitting control line in the 6a-2 row is electrically connected to the sub-pixels in the 6a-2 row, the light-emitting control line in the 6a-1 row is electrically connected to the sub-pixels in the 6a-1 row, and the light-emitting control line in the 6a row is electrically connected to the sub-pixels in the 6a row; the sub-pixels in the 6a-5 row, the sub-pixels in the 6a-3 row and the sub-pixels in the 6a-1 row are sub-pixels of the first type, and the sub-pixels in the 6a-4 row, the sub-pixels in the 6a-2 row and the sub-pixels in the 6a row are sub-pixels of the second type.

[0259] In a specific implementation, when the 6a-5 row light control line, the 6a-3 row light control line, and the 6a-5 row light control line are anti-peep row light control lines, and the 6a-4 row light control line, the 6a-2 row light control line, and the 6a row light control line are shared row light control lines, the first generation circuits at each level can provide light control signals for the three anti-peep row light control lines, and the second generation circuits at each level can provide light control signals for the three shared row light control lines.

[0260] When the 6a-5 row light-emitting control line, the 6a-3 row light-emitting control line and the 6a-5 row light-emitting control line are shared row light-emitting control lines, and the 6a-4 row light-emitting control line, the 6a-2 row light-emitting control line and the 6a row light-emitting control line are anti-peeping row light-emitting control lines, the first generating circuits at each level can provide light-emitting control signals for the three rows of shared row light-emitting control lines, and the second generating circuits at each level can provide light-emitting control signals for the three rows of anti-peeping row light-emitting control lines.

[0261] Optionally, the first generation circuit of the ath stage is electrically connected to the light-emitting control line in row 8a-7, the light-emitting control line in row 8a-5, the light-emitting control line in row 8a-3, and the light-emitting control line in row 8a-1, respectively, for providing light-emitting control signals for the light-emitting control line in row 8a-7, the light-emitting control line in row 8a-5, the light-emitting control line in row 8a-3, and the light-emitting control line in row 8a-1;

[0262] The second generation circuit of the ath level is electrically connected to the light-emitting control line of the 8a-6th row, the light-emitting control line of the 8a-4th row, the light-emitting control line of the 8a-2th row, and the light-emitting control line of the 8ath row, respectively, and is used to provide light-emitting control signals for the light-emitting control line of the 8a-6th row, the light-emitting control line of the 8a-4th row, the light-emitting control line of the 8a-2th row, and the light-emitting control line of the 8ath row; a is a positive integer;

[0263] The light emitting control line in row 8a-7 is electrically connected to the sub-pixels in row 8a-7, the light emitting control line in row 8a-6 is electrically connected to the sub-pixels in row 8a-6, the light emitting control line in row 8a-5 is electrically connected to the sub-pixels in row 8a-5, the light emitting control line in row 8a-4 is electrically connected to the sub-pixels in row 8a-4, the light emitting control line in row 8a-3 is electrically connected to the sub-pixels in row 8a-3, the light emitting control line in row 8a-2 is electrically connected to the sub-pixels in row 8a-2, and the light emitting control line in row 8a-3 is electrically connected to the sub-pixels in row 8a-3. The 8a-1 row light-emitting control line is electrically connected to the 8a-1 row sub-pixels, and the 8a row light-emitting control line is electrically connected to the 8a row sub-pixels; the 8a-7 row sub-pixels, the 8a-5 row sub-pixels, the 8a-3 row sub-pixels and the 8a-1 row sub-pixels are first-type sub-pixel rows, and the 8a-6 row sub-pixels, the 8a-4 row sub-pixels, the 8a-2 row sub-pixels and the 8a row sub-pixels are second-type sub-pixel rows.

[0264] In a specific implementation, when the 8a-7 row light control line, the 8a-5 row light control line, the 8a-3 row light control line, and the 8a-1 row light control line are anti-peep row light control lines, and the 8a-6 row light control line, the 8a-4 row light control line, the 8a-2 row light control line, and the 8a row light control line are light control lines, the first generation circuits at each level can provide light control signals for the four anti-peep row light control lines, and the second generation circuits at each level can provide light control signals for the four shared row light control lines.

[0265] When the 8a-7 row light control line, the 8a-5 row light control line, the 8a-3 row light control line and the 8a-1 row light control line are shared row light control lines, the 8a-6 row light control line, the 8a-4 row light control line, the 8a-2 row light control line and the 8a row light control line, the first generation circuits at each level can provide light control signals for the four rows of shared row light control lines, and the second generation circuits at each level can provide light control signals for the four rows of anti-peep row light control lines.

[0266] As shown in FIG9 , based on at least one embodiment of the sub-pixel shown in FIG5 , the display panel according to at least one embodiment of the present disclosure further includes a light emitting control signal generating module;

[0267] The display panel according to at least one embodiment of the present disclosure further includes a first row of light emitting control lines EM1, a second row of light emitting control lines EM2, a third row of light emitting control lines EM3, a fourth row of light emitting control lines EM4, a 2N-3 row of light emitting control lines EM2N-3, a 2N-2 row of light emitting control lines EM2N-2, a 2N-1 row of light emitting control lines EM2N-1, and a 2N row of light emitting control lines EM2N.

[0268] The light emitting control signal generating module includes a first-level generating circuit and a B-level generating circuit;

[0269] The first-stage generating circuit includes a first-stage first generating circuit EMO1 and a first-stage second generating circuit EME1; the B-stage generating circuit includes a first-stage first generating circuit EMO1 and a first-stage second generating circuit EMEB;

[0270] B is a positive integer;

[0271] 2B equals N;

[0272] EMO1 is used to provide lighting control signals for EM1 and EM3;

[0273] EMOB is used to provide lighting control signals for EM2N-3 and EM2N-1;

[0274] EME1 is used to provide lighting control signals for EM2 and EM4;

[0275] EMEB is used to provide lighting control signals for EM2N-2 and EM2N;

[0276] The light emitting control signal generating module is disposed on the left side of the display area A0.

[0277] In at least one embodiment of the display panel shown in FIG9 , when EM1, EM3, EM2N-3, and EM2N-1 are anti-peeping row light-emitting control lines, and EM2, EM4, EM2N-2, and EM2N are shared row light-emitting control lines, the first generation circuits of each stage provide corresponding light-emitting control signals for the light-emitting control lines of two adjacent anti-peeping row rows, and the second generation circuits of each stage provide corresponding light-emitting control signals for the light-emitting control lines of two adjacent shared rows, so as to control the time-sharing opening of the sub-pixels in the anti-peeping row and the sub-pixels in the shared row. This improves the charging time of the sub-pixels, thereby achieving an anti-peeping mode and a shared mode. Furthermore, the number of first generation circuit stages and the number of second generation circuit stages used can be reduced, thereby facilitating the realization of a narrow bezel.

[0278] When EM1, EM3, EM2N-3 and EM2N-1 are shared row light control lines, and EM2, EM4, EM2N-2 and EM2N are anti-peep row light control lines, the first generation circuits at each level provide corresponding light control signals for the shared row light control lines of two adjacent rows, and the second generation circuits at each level provide corresponding light control signals for the light control lines of two adjacent anti-peep rows, so as to control the time-sharing opening of the shared row sub-pixels and the anti-peep row sub-pixels. On the premise of improving the charging time of the sub-pixels, the shared mode and the anti-peep mode are realized, and the number of levels of the first generation circuits used can be reduced, and the number of levels of the second generation circuits used can be reduced, which is conducive to achieving a narrow frame.

[0279] As shown in FIG10 , based on at least one embodiment of the display panel shown in FIG6 , the display panel according to at least one embodiment of the present disclosure further includes a first light emission control signal generating module and a second light emission control signal generating module;

[0280] The display panel according to at least one embodiment of the present disclosure further includes a first row of light emitting control lines EM1, a second row of light emitting control lines EM2, a third row of light emitting control lines EM3, a fourth row of light emitting control lines EM4, a 2N-3 row of light emitting control lines EM2N-3, a 2N-2 row of light emitting control lines EM2N-2, a 2N-1 row of light emitting control lines EM2N-1, and a 2N row of light emitting control lines EM2N.

[0281] The first-stage first generating circuit included in the first light-emitting control signal generating module is labeled EMO11, and the B-stage first generating circuit included in the first light-emitting control signal generating module is labeled EMO1B, where B is a positive integer;

[0282] The first-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO21, and the B-stage first generating circuit included in the second light-emitting control signal generating module is labeled EMO2B;

[0283] The first-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME11, and the B-stage second generation circuit included in the first light-emitting control signal generation module is labeled EME1B;

[0284] The first-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME21, and the B-stage second generation circuit included in the second light-emitting control signal generation module is labeled EME2B;

[0285] 2B equals N;

[0286] EMO11 is used to provide lighting control signals for EM1 and EM3; EMO21 is used to provide lighting control signals for EM1 and EM3;

[0287] EMO1B is used to provide lighting control signals for EM2N-3 and EM2N-1; EMO2B is used to provide lighting control signals for EM2N-3 and EM2N-1;

[0288] EME11 is used to provide lighting control signals for EM2 and EM4; EME21 is used to provide lighting control signals for EM2 and EM4;

[0289] EME1B is used to provide lighting control signals for EM2N-2 and EM2N; EME2B is used to provide lighting control signals for EM2N-2 and EM2N;

[0290] The first light emitting control signal generating module is arranged on the left side of the display area A0;

[0291] The second light emitting control signal generating module is disposed on the right side of the display area A0.

[0292] In at least one embodiment of the display panel shown in FIG10 , when EM1, EM3, EM2N-3, and EM2N-1 are anti-peeping row light-emitting control lines, and EM2, EM4, EM2N-2, and EM2N are shared row light-emitting control lines, the first generation circuit of each stage provides corresponding light-emitting control signals for two adjacent anti-peeping row light-emitting control lines, and the second generation circuit of each stage provides corresponding light-emitting control signals for two adjacent shared row light-emitting control lines, so as to control the time-sharing opening of the anti-peeping row sub-pixels and the shared row sub-pixels. This improves the charging time of the sub-pixels, thereby achieving an anti-peeping mode and a shared mode. Furthermore, the number of first generation circuit stages and the number of second generation circuit stages used can be reduced, thereby facilitating the realization of a narrow bezel.

[0293] When EM1, EM3, EM2N-3 and EM2N-1 are shared row light-emitting control lines, and EM2, EM4, EM2N-2 and EM2N are anti-peeping row light-emitting control lines, the first generating circuits at each level provide corresponding light-emitting control signals for the shared row light-emitting control lines of two adjacent rows, and the second generating circuits at each level provide corresponding light-emitting control signals for the anti-peeping row light-emitting control lines of two adjacent rows, so as to control the time-sharing opening of the shared row sub-pixels and the anti-peeping row sub-pixels. On the premise of improving the charging time of the sub-pixels, the shared mode and the anti-peeping mode are realized, and the number of levels of the first generating circuits used can be reduced, and the number of levels of the second generating circuits used can be reduced, which is conducive to achieving a narrow frame.

[0294] In at least one embodiment of the present disclosure, the generating circuit may be configured to provide light emitting control signals for at least one first-type sub-pixel row and at least one second-type sub-pixel row.

[0295] In at least one embodiment of the present disclosure, the n-th level generating circuit includes an n-th level generating unit and an n-th level output control unit;

[0296] The n-th generation unit is used to generate an n-th light emitting control signal and output the n-th light emitting control signal through the n-th light emitting control signal output terminal;

[0297] The input end of the n-th level output control unit is electrically connected to the n-th light-emitting control signal output end, the first output end of the n-th level output control unit is electrically connected to the 2n-1-th row light-emitting control line, the second output end of the n-th level output control unit is electrically connected to the 2n-th row light-emitting control line, and the n-th level output control unit is used to provide effective light-emitting control signals to the 2n-1-th row light-emitting control line and the 2n-th row light-emitting control line in a time-sharing manner according to the n-th light-emitting control signal provided by the n-th light-emitting control signal output end; n is an integer less than or equal to N, and N is an integer greater than 1.

[0298] In a specific implementation, the n-th level generating circuit may include an n-th level generating unit and an n-th level output control unit; the n-th level generating circuit may provide an n-th light-emitting control signal at the n-th light-emitting control signal output terminal, and the n-th level output control unit may provide an effective light-emitting control signal to the 2n-1-th row light-emitting control line and the 2n-th row light-emitting control line in a time-sharing manner according to the n-th light-emitting control signal provided at the n-th light-emitting control signal output terminal.

[0299] As shown in FIG11 , based on at least one embodiment of the display panel shown in FIG5 , the display panel according to at least one embodiment of the present disclosure further includes a first row of light-emitting control lines EM1, a second row of light-emitting control lines EM2, a third row of light-emitting control lines EM3, a fourth row of light-emitting control lines EM4, a 2N-3 row of light-emitting control lines EM2N-3, a 2N-2 row of light-emitting control lines EM2N-2, a 2N-1 row of light-emitting control lines EM2N-1, and a 2N row of light-emitting control lines EM2N.

[0300] The display panel according to at least one embodiment of the present disclosure further includes a light emitting control signal generating module;

[0301] The light emitting control signal generating module includes a first-level generating circuit, a second-level generating circuit, an N-1th-level generating circuit and an Nth-level generating circuit;

[0302] The first-stage generating circuit includes a first-stage generating unit EMG1 and a first-stage output control unit OC1; the second-stage generating circuit includes a second-stage generating unit EMG2 and a second-stage output control unit OC2; the N-1-stage generating circuit includes an N-1-stage generating unit EMG N-1 and an N-1-stage output control unit OC N-1; the N-stage generating circuit includes an N-stage generating unit EMGN and an N-stage output control unit OCN;

[0303] The output end of EMG1 is the first light control signal output end, the output end of EMG2 is the second light control signal output end, the output end of EMGN-1 is the N-1th light control signal output end, and the output end of EMGN is the Nth light control signal output end;

[0304] An input terminal of the first-stage output control unit OC1 is electrically connected to the first light-emission control signal output terminal. A first output terminal of the first-stage output control unit OC1 is electrically connected to the first-row light-emission control line EM1. A second output terminal of the first-stage output control unit OC1 is electrically connected to the second-row light-emission control line EM2. OC1 is used to provide corresponding light-emission control signals to EM1 and EM2, controlling the time-sharing turning on of EM1 and EM2.

[0305] An input terminal of the second-stage output control unit OC2 is electrically connected to the second light-emission control signal output terminal. A first output terminal of the second-stage output control unit OC2 is electrically connected to the third row of light-emission control lines EM3. A second output terminal of the second-stage output control unit OC2 is electrically connected to the fourth row of light-emission control lines EM4. OC2 is used to provide corresponding light-emission control signals to EM3 and EM4, controlling the time-sharing turning-on of EM3 and EM4.

[0306] The input terminal of the N-1th output control unit OCN-1 is electrically connected to the N-1th light control signal output terminal. The first output terminal of the N-1th output control unit OCN-1 is electrically connected to the light control line EM2N-3 in the 2N-3th row. The second output terminal of the N-1th output control unit OCN-1 is electrically connected to the light control line EM2N-2 in the 2N-2th row. OCN-1 is used to provide corresponding light control signals to EM2N-3 and EM2N-2, controlling the time-sharing operation of EM2N-3 and EM2N-2.

[0307] The input end of the N-th level output control unit OCN is electrically connected to the N-th light-emitting control signal output end, the first output end of the N-th level output control unit OCN is electrically connected to the 2N-1 row light-emitting control line EM2N-1, and the second output end of the second-level output control unit OC2 is electrically connected to the fourth row light-emitting control line EM2N; OCN is used to provide corresponding light-emitting control signals to EM2N-1 and EM2N, controlling EM2N-1 and EM2N to turn on in a time-sharing manner.

[0308] When at least one embodiment of the display panel shown in Figure 11 is in operation, when EM1, EM3, EM2N-3 and EM2N-1 are anti-peeping row light-emitting control lines, and EM2, EM4, EM2N-2 and EM2N are shared row light-emitting control lines, or when EM1, EM3, EM2N-3 and EM2N-1 are shared row light-emitting control lines, and EM2, EM4, EM2N-2 and EM2N are anti-peeping row light-emitting control lines, the output control units of each level can control the adjacent row light-emitting control lines to be turned on in time-sharing manner, so as to be able to control the anti-peeping row light-emitting control lines and the shared row light-emitting control lines to be turned on in time-sharing manner, and control the anti-peeping row sub-pixels and the shared row sub-pixels to be turned on in time-sharing manner, thereby realizing the anti-peeping mode and the shared mode while improving the charging time of the sub-pixels, and being able to reduce the number of stages of the first generation circuit used and the number of stages of the second generation circuit used, thereby facilitating the realization of a narrow bezel.

[0309] As shown in FIG12 , based on at least one embodiment of the display panel shown in FIG6 , the display panel according to at least one embodiment of the present disclosure further includes a first row of light emitting control lines EM1, a second row of light emitting control lines EM2, a third row of light emitting control lines EM3, a fourth row of light emitting control lines EM4, a 2N-3 row of light emitting control lines EM2N-3, a 2N-2 row of light emitting control lines EM2N-2, a 2N-1 row of light emitting control lines EM2N-1, and a 2N row of light emitting control lines EM2N.

[0310] The display panel according to at least one embodiment of the present disclosure further includes a first light emitting control signal generating module and a second light emitting control signal generating module;

[0311] The first light emitting control signal generating module is disposed on the left side of the display area A0, and the second light emitting control signal generating module is disposed on the right side of the display area A0;

[0312] The first-stage generating unit included in the first light-emitting control signal generating module is labeled EMG11, the second-stage generating unit included in the first light-emitting control signal generating module is labeled EMG12, the N-1th-stage generating unit included in the first light-emitting control signal generating module is labeled EMG1N-1, and the Nth-stage generating unit included in the first light-emitting control signal generating module is labeled EMG1N;

[0313] The first-stage generating unit included in the second light-emitting control signal generating module is labeled EMG21, the second-stage generating unit included in the second light-emitting control signal generating module is labeled EMG22, the N-1th-stage generating unit included in the second light-emitting control signal generating module is labeled EMG2N-1, and the Nth-stage generating unit included in the second light-emitting control signal generating module is labeled EMG2N;

[0314] The first-stage output control unit included in the first light-emitting control signal generation module is labeled OC11, the second-stage output control unit included in the first light-emitting control signal generation module is labeled OC12, the N-1th-stage output control unit included in the first light-emitting control signal generation module is labeled OC1N-1, and the Nth-stage output control unit included in the first light-emitting control signal generation module is labeled OC1N;

[0315] The first-stage output control unit included in the second light-emitting control signal generation module is labeled OC21, the second-stage output control unit included in the second light-emitting control signal generation module is labeled OC22, the N-1-th stage output control unit included in the second light-emitting control signal generation module is labeled OC2N-1, and the N-th stage output control unit included in the second light-emitting control signal generation module is labeled OC2N;

[0316] The input terminal of OC11 is electrically connected to the output terminal of EMG11. The first output terminal of OC11 is electrically connected to the first row of light control lines EM1, and the second output terminal of OC11 is electrically connected to the second row of light control lines EM2. OC11 is used to provide corresponding light control signals to EM1 and EM2, controlling the time-sharing turning on of EM1 and EM2.

[0317] The input end of OC21 is electrically connected to the output end of EMG21. The first output end of OC21 is electrically connected to the first row of light control lines EM1, and the second output end of OC21 is electrically connected to the second row of light control lines EM2. OC11 is used to provide corresponding light control signals to EM1 and EM2, controlling the time-sharing turning on of EM1 and EM2.

[0318] The input end of OC12 is electrically connected to the output end of EMG12. The first output end of OC12 is electrically connected to the third row of light control lines EM3. The second output end of OC12 is electrically connected to the fourth row of light control lines EM4. OC12 is used to provide corresponding light control signals to EM3 and EM4, controlling the time-sharing turn-on of EM3 and EM4.

[0319] The input end of OC22 is electrically connected to the output end of EMG22. The first output end of OC22 is electrically connected to the third row of light control lines EM3. The second output end of OC22 is electrically connected to the fourth row of light control lines EM4. OC22 is used to provide corresponding light control signals to EM3 and EM4, controlling the time-sharing turn-on of EM3 and EM4.

[0320] The input terminal of OC1N-1 is electrically connected to the output terminal of EMG1N-1. The first output terminal of OC1N-1 is electrically connected to the light-emitting control line EM2N-3 in the 2N-3 row. The second output terminal of OC1N-1 is electrically connected to the light-emitting control line EM2N-2 in the 2N-2 row. OC1N-1 is used to provide corresponding light-emitting control signals to EM2N-3 and EM2N-2, controlling the time-sharing operation of EM2N-3 and EM2N-2.

[0321] The input terminal of OC2N-1 is electrically connected to the output terminal of EMG2N-1. The first output terminal of OC2N-1 is electrically connected to the light-emitting control line EM2N-3 in the 2N-3 row. The second output terminal of OC2N-1 is electrically connected to the light-emitting control line EM2N-2 in the 2N-2 row. OC2N-1 is used to provide corresponding light-emitting control signals to EM2N-3 and EM2N-2, controlling the time-sharing operation of EM2N-3 and EM2N-2.

[0322] The input terminal of OC1N is electrically connected to the output terminal of EMG1N. The first output terminal of OC1N is electrically connected to the light-emitting control line EM2N-1 in the 2N-1 row. The second output terminal of OC1N is electrically connected to the light-emitting control line EM2N in the 2N row. OC1N-1 is used to provide corresponding light-emitting control signals to EM2N-1 and EM2N, controlling the time-sharing operation of EM2N-1 and EM2N.

[0323] The input end of OC2N is electrically connected to the output end of EMG2N, the first output end of OC2N is electrically connected to the light-emitting control line EM2N-1 in the 2N-1 row, and the second output end of OC2N is electrically connected to the light-emitting control line EM2N in the 2N row. OC2N-1 is used to provide corresponding light-emitting control signals to EM2N-1 and EM2N, controlling the time-sharing opening of EM2N-1 and EM2N.

[0324] In at least one embodiment of the present disclosure, the output control unit includes a first control module, a second control module, a third control module, and a fourth control module;

[0325] The first control module is electrically connected to the first control terminal, the input terminal of the output control unit, and the first output terminal of the output control unit, respectively, and is used to control the communication between the input terminal and the first output terminal under the control of a first control signal provided by the first control terminal;

[0326] The second control module is electrically connected to the second control terminal, the first voltage line and the first output terminal of the output control unit respectively, and is used to control the communication between the first voltage line and the first output terminal under the control of the second control signal provided by the second control terminal;

[0327] The third control module is electrically connected to the first control terminal, the first voltage line and the second output terminal of the output control unit respectively, and is used to control the communication between the first voltage line and the second output terminal under the control of the first control signal provided by the first control terminal;

[0328] The fourth control module is electrically connected to the second control end, the input end and the second output end respectively, and is used to control the communication between the input end and the second output end under the control of the second control signal provided by the second control end.

[0329] In a specific implementation, the output control unit may include a first control module, a second control module, a third control module and a fourth control module; the first control module controls the connection between the input end and the first output end under the control of a first control signal; the second control module controls the connection between the first voltage line and the first output end under the control of a second control signal; the third control module controls the connection between the first voltage line and the second output end under the control of the first control signal; and the fourth control module controls the connection between the input end and the second output end under the control of a second control signal.

[0330] In at least one embodiment of the present disclosure, the first voltage line may be a high voltage line, but is not limited thereto.

[0331] As shown in FIG13 , the output control unit includes a first control module 111 , a second control module 112 , a third control module 113 and a fourth control module 114 ;

[0332] The first control module 111 is electrically connected to the first control terminal A, the input terminal I0 of the output control unit, and the first output terminal O1 of the output control unit, respectively, and is used to control the communication between the input terminal I0 and the first output terminal O1 under the control of the first control signal provided by the first control terminal A;

[0333] The second control module 112 is electrically connected to the second control terminal B, the first voltage line V1 and the first output terminal O1 of the output control unit, and is used to control the connection between the first voltage line V1 and the first output terminal O1 under the control of the second control signal provided by the second control terminal B;

[0334] The third control module 113 is electrically connected to the first control terminal A, the first voltage line V1, and the second output terminal O2 of the output control unit, respectively, and is used to control the communication between the first voltage line V1 and the second output terminal O2 under the control of the first control signal provided by the first control terminal A;

[0335] The fourth control module 114 is electrically connected to the second control terminal B, the input terminal I0 and the second output terminal O2 respectively, and is used to control the connection between the input terminal I0 and the second output terminal O2 under the control of the second control signal provided by the second control terminal B.

[0336] In a specific implementation, the first voltage line may be a high voltage line.

[0337] As shown in FIG14 , based on at least one embodiment of the display panel shown in FIG11 , at least one embodiment of the display panel further includes a first high voltage line VGH1 ;

[0338] OC1 , OC2 , OCN- 1 and OCN are all electrically connected to the first high voltage line VGH1 , and are configured to generate corresponding light emitting control signals according to a high voltage signal provided by the first high voltage line VGH1 .

[0339] As shown in FIG15 , based on at least one embodiment of the display panel shown in FIG12 , at least one embodiment of the display panel further includes a first high voltage line VGH1 and a second high voltage line VGH2 ;

[0340] OC11, OC12, OC1N-1 and OC1N are all electrically connected to the first high voltage line VGH1, and are used to generate corresponding light emitting control signals according to the high voltage signal provided by the first high voltage line VGH1;

[0341] OC21 , OC22 , OC2N- 1 and OC2N are all electrically connected to the second high voltage line VGH2 , and are configured to generate corresponding light emitting control signals according to a high voltage signal provided by the second high voltage line VGH2 .

[0342] Optionally, the first control module includes a first control transistor, the second control module includes a second control transistor, the third control module includes a third control transistor, and the fourth control module includes a fourth control transistor;

[0343] The gate of the first control transistor is electrically connected to the first control terminal, the first electrode of the first control transistor is electrically connected to the input terminal of the output control unit, and the second electrode of the first control transistor is electrically connected to the first output terminal of the output control unit;

[0344] The gate of the second control transistor is electrically connected to the second control terminal, the first electrode of the second control transistor is electrically connected to the first voltage line, and the second electrode of the second control transistor is electrically connected to the first output terminal of the output control unit;

[0345] The gate of the third control transistor is electrically connected to the first control terminal, the first electrode of the third control transistor is electrically connected to the first voltage line, and the second electrode of the third control transistor is electrically connected to the second output terminal of the output control unit;

[0346] The gate of the fourth control transistor is electrically connected to the second control terminal, the first electrode of the fourth control transistor is electrically connected to the input terminal of the output control unit, and the second electrode of the fourth control transistor is electrically connected to the second output terminal of the output control unit.

[0347] As shown in FIG16 , based on at least one embodiment of the output control unit shown in FIG13 , the first control module includes a first control transistor TC1, the second control module includes a second control transistor TC2, the third control module includes a third control transistor TC3, and the fourth control module includes a fourth control transistor TC4;

[0348] The gate of the first control transistor TC1 is electrically connected to the first control terminal A, the source of the first control transistor TC1 is electrically connected to the input terminal I0 of the output control unit, and the drain of the first control transistor TC1 is electrically connected to the first output terminal O1 of the output control unit;

[0349] The gate of the second control transistor TC2 is electrically connected to the second control terminal B, the source of the second control transistor TC2 is electrically connected to the high voltage line VGH, and the drain of the second control transistor TC2 is electrically connected to the first output terminal O1 of the output control unit;

[0350] The gate of the third control transistor TC3 is electrically connected to the first control terminal A, the source of the third control transistor TC3 is electrically connected to the high voltage line VGH, and the drain of the third control transistor TC3 is electrically connected to the second output terminal O2 of the output control unit;

[0351] The gate of the fourth control transistor TC4 is electrically connected to the second control terminal B, the source of the fourth control transistor TC4 is electrically connected to the input terminal I0 of the output control unit, and the drain of the fourth control transistor TC4 is electrically connected to the second output terminal O2 of the output control unit.

[0352] In at least one embodiment of the output control unit shown in FIG. 16 , TC1 , TC2 , TC3 , and TC4 may all be p-type transistors.

[0353] At least one embodiment of the output control unit shown in FIG16 is in operation.

[0354] When A provides a low voltage signal and B provides a high voltage signal, TC1 is turned on, TC2 is turned off, TC3 is turned on, TC4 is turned off, I0 is connected to O1, and VGH is connected to O2. When I0 provides a low voltage signal, O1 provides a low voltage signal and O2 provides a high voltage signal.

[0355] When A provides a high voltage signal and B provides a low voltage signal, TC1 is turned off, TC2 is turned on, TC3 is turned off, TC4 is turned on, VGH is connected to O1, and I0 is connected to O2. When I0 provides a low voltage signal, O1 provides a high voltage signal and O2 provides a low voltage signal.

[0356] When at least one embodiment of the output control unit shown in FIG16 is in operation, when A provides a low voltage signal, the potential of A is a second low voltage Vgl2, and when A provides a high voltage signal, the potential of A is a second high voltage Vgh2;

[0357] When B provides a low voltage signal, the potential of B is the second low voltage Vgl2; when B provides a high voltage signal, the potential of B is the second high voltage Vgh2;

[0358] When I0 provides a low voltage signal, the potential of I0 is a first low voltage Vgl1, and the voltage value of the high voltage signal provided by VGH is a first high voltage Vgh1;

[0359] Vgh2 is greater than Vgh1 and Vgl2 is less than Vgl1, so that when each transistor is turned off, the transistor can be completely turned off, and when each transistor is turned on, the transistor can be completely turned on.

[0360] Optionally, at least one embodiment of the sub-pixel includes a light-emitting element, a driving circuit, a data writing circuit, a reset circuit, a first light-emitting control circuit, and a second light-emitting control circuit;

[0361] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node;

[0362] The data writing circuit is electrically connected to the scan line, the data line and the second node N2 respectively, and is used to write the display data voltage provided by the data line into the second node under the control of the scan signal provided by the scan line;

[0363] The reset circuit is electrically connected to the reset control line, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal provided by the reset control line;

[0364] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0365] The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0366] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0367] In at least one embodiment of the present disclosure, the first voltage terminal may be a low voltage terminal, but is not limited thereto.

[0368] Optionally, at least one embodiment of the sub-pixel may further include a compensation control circuit, an initialization circuit, and an energy storage circuit;

[0369] The compensation control circuit is electrically connected to the scan line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the scan signal provided by the scan line;

[0370] The initialization circuit is electrically connected to the scan line, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the scan signal;

[0371] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0372] As shown in FIG17 , in a display panel according to at least one embodiment of the present disclosure, at least one embodiment of a sub-pixel includes a light-emitting element E0, a driving circuit 150, a data writing circuit 151, a compensation control circuit 152, a reset circuit 153, a first light-emitting control circuit 154, a second light-emitting control circuit 155, an initialization circuit 156, and an energy storage circuit 157.

[0373] The control terminal of the driving circuit 150 is electrically connected to the first node N1, the first terminal of the driving circuit 150 is electrically connected to the second node N2, and the second terminal of the driving circuit 150 is electrically connected to the third node N3;

[0374] The data writing circuit 151 is electrically connected to the scan line GL, the data line DT and the second node N2 respectively, and is used to write the display data voltage provided by the data line DT into the second node N2 under the control of the scan signal provided by the scan line GL;

[0375] The compensation control circuit 152 is electrically connected to the scan line GL, the first node N1 and the third node N3, respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the scan signal provided by the scan line GL;

[0376] The reset circuit 53 is electrically connected to the reset control line RE, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage provided by the first initial voltage terminal I1 into the first node N1 under the control of the reset control signal provided by the reset control line RE;

[0377] The first light emitting control circuit 154 is electrically connected to the light emitting control line EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line EM;

[0378] The second light emitting control circuit 155 is electrically connected to the light emitting control line EM, the third node N3 and the first electrode of the light emitting element E0, respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light emitting element E0 under the control of the light emitting control signal;

[0379] The initialization circuit 156 is electrically connected to the scan line GL, the second initial voltage terminal I2 and the first electrode of the light-emitting element E0, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E0 under the control of the scan signal;

[0380] The energy storage circuit 157 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0381] The second electrode of the light emitting element E0 is electrically connected to the low voltage terminal VSS.

[0382] As shown in FIG18 , based on at least one embodiment of the sub-pixel shown in FIG17 , the reset circuit includes a first transistor T1, the compensation control circuit includes a second transistor T2, the drive circuit includes a third transistor T3, the data write circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, and the initialization circuit includes a seventh transistor T7; the energy storage circuit includes a storage capacitor Cst; and the light-emitting element is an organic light-emitting diode O1.

[0383] The gate of T1 is electrically connected to the reset control line RE, the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1;

[0384] The gate of T2 is electrically connected to the scan line GL, the source of T2 is electrically connected to the second node N2, and the drain of T2 is electrically connected to the third node N3;

[0385] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3;

[0386] The gate of T4 is electrically connected to the scan line GL, the source of T4 is electrically connected to the data line DT, and the drain of T4 is electrically connected to the second node N2;

[0387] The gate of T5 is electrically connected to the light emitting control line EM, the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2;

[0388] The gate of T6 is electrically connected to the light emitting control line EM, the source of T6 is electrically connected to the third node N3, and the drain of T6 is electrically connected to the anode of the organic light emitting diode O1;

[0389] The cathode of O1 is electrically connected to the low voltage terminal VSS;

[0390] The gate of T7 is electrically connected to the scan line GL, the source of T7 is electrically connected to the second initial voltage terminal I2, and the drain of T7 is electrically connected to the anode of O1;

[0391] A first terminal of Cst is electrically connected to the first node N1 , and a second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0392] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0393] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display panel, comprising a plurality of rows and columns of sub-pixels, a plurality of scan lines, a first driving module, and a light-emitting control signal generation module; The sub-pixels are electrically connected to the scan lines, and are configured to access a display data voltage under the control of a scan signal provided by the scan lines; The first driving module includes a plurality of levels of first driving circuits; The light-emitting control signal generation module includes a plurality of levels of generation circuits; The first driving circuit is configured to provide a scan signal for adjacent two rows of sub-pixels; The generation circuit is configured to provide a light-emitting control signal for at least two rows of sub-pixels; The plurality of rows and columns of sub-pixels include a plurality of first-type sub-pixel rows and a plurality of second-type sub-pixel rows; The type of the first-type sub-pixel rows is different from the type of the second-type sub-pixel rows.

2. The display panel according to claim 1, wherein, The first-type sub-pixel rows and the second-type sub-pixel rows are alternately arranged.

3. The display panel according to claim 1, wherein, The first-type sub-pixel rows are anti-peeping sub-pixels, and the second-type sub-pixel rows are shared sub-pixels; or, the first-type sub-pixel rows are shared sub-pixels, and the second-type sub-pixel rows are anti-peeping sub-pixels.

4. The display panel according to claim 1, wherein, The display panel further includes a substrate and a light condensing structure; The sub-pixels, the light condensing structure, the scan lines, the first driving module, and the light-emitting control signal generation module are all disposed on the substrate; The light condensing structure is disposed on a side of the anti-peeping sub-pixels away from the substrate, and is configured to condense light emitted by the anti-peeping sub-pixels.

5. The display panel according to any one of claims 1 to 4, wherein, The sub-pixels are disposed in a display area; the first driving module is disposed in a peripheral area; The display panel includes one first driving module, and the first driving module is disposed on a first side or a second side of the display area; or, The display panel includes a first first driving module and a second first driving module, the first first driving module is disposed on a first side of the display area, and the second first driving module is disposed on a second side of the display area; The first side and the second side are opposite sides.

6. The display panel according to any one of claims 1 to 4, wherein, It further includes a plurality of reset control lines and a second driving module; the second driving module includes N levels of second driving circuits; the sub-pixels include a reset circuit, a driving circuit, and a light-emitting element; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of its control terminal; The reset circuit is electrically connected to the reset control lines, and is configured to provide an initial voltage to the control terminal of the driving circuit under the control of a reset control signal provided by the reset control lines; The nth-level second driving circuit is electrically connected to the (2n - 1)th row reset control line and the 2nth row reset control line respectively, and is configured to provide an nth reset control signal for the (2n - 1)th row reset control line and the 2nth reset control line; N is an integer greater than 1, and n is a positive integer less than or equal to N.

7. The display panel according to claim 6, wherein, The sub-pixels are disposed in a display area; the second driving module is disposed in a peripheral area; The display panel includes one second driving module, and the second driving module is disposed on a first side or a second side of the display area; or, The display panel includes a first second driving module and a second second driving module. The first second driving module is disposed on a first side of the display area, and the second second driving module is disposed on a second side of the display area; The first side and the second side are opposite sides.

8. The display panel according to any one of claims 1 to 4, wherein, The generating circuit includes a first generating circuit and a second generating circuit; The first generating circuit is configured to provide a light emission control signal for at least one row of first type sub-pixel rows; The second generating circuit is configured to provide a light emission control signal for at least one row of second type sub-pixel rows.

9. The display panel according to claim 8, wherein, The sub-pixels are disposed in the display area; the light emission control signal generating module is disposed in the peripheral area; The display panel includes a light emission control signal generating module, and the light emission control signal generating module is disposed on the first side or the second side of the display area; or, The display panel includes a first light emission control signal generating module and a second light emission control signal generating module; the first light emission control signal generating module is disposed on the first side of the display area; The second light emission control signal generating module is disposed on the second side of the display area; The first side and the second side are opposite sides.

10. The display panel according to claim 8, wherein, The sub-pixel includes a driving circuit and a light emitting element; the driving circuit is configured to drive the light emitting element to emit light under the control of the potential of its control terminal; The sub-pixel further includes a first light emission control circuit and / or a second light emission control circuit; The first light emission control circuit is electrically connected to the light emission control line, the power voltage terminal, and a first end of the driving circuit respectively, and is configured to control the connection or disconnection between the power voltage terminal and the first end of the driving circuit under the control of the light emission control signal provided by the light emission control line; The second light emission control circuit is electrically connected to the light emission control line, a second end of the driving circuit, and the light emitting element respectively, and is configured to control the connection or disconnection between the second end of the driving circuit and the light emitting element under the control of the light emission control signal provided by the light emission control line.

11. The display panel according to claim 8, wherein, The nth-level first generating circuit is electrically connected to the (2n - 1)th row light emission control line, and is configured to provide the (2n - 1)th row light emission control signal for the (2n - 1)th row light emission control line; The nth-level second generating circuit is electrically connected to the 2nth row light emission control line, and is configured to provide the 2nth row light emission control signal for the 2nth row light emission control line; n is a positive integer less than or equal to N, and N is an integer greater than 1; The (2n - 1)th row light emission control line is electrically connected to the (2n - 1)th row sub-pixels, and the 2nth row light emission control line is connected to the 2nth row sub-pixels; The (2n - 1)th row sub-pixels are first type sub-pixel rows, and the 2nth row sub-pixels are second type sub-pixel rows.

12. The display panel according to claim 8, wherein, The ath-level first generating circuit is electrically connected to the (4a - 3)th row light emission control line and the (4a - 1)th row light emission control line respectively, and is configured to provide light emission control signals for the (4a - 3)th row light emission control line and the (4a - 1)th row light emission control line; The second generation circuit of the a-th level is electrically connected to the light-emitting control lines of the (4a - 2)-th row and the 4a-th row respectively, and is used to provide light-emitting control signals for the light-emitting control lines of the (4a - 2)-th row and the 4a-th row; a is a positive integer; The light-emitting control line of the (4a - 1)-th row is electrically connected to the sub-pixels of the (4a - 1)-th row, the light-emitting control line of the (4a - 2)-th row is electrically connected to the sub-pixels of the (4a - 2)-th row, the light-emitting control line of the (4a - 3)-th row is electrically connected to the sub-pixels of the (4a - 3)-th row, and the light-emitting control line of the 4a-th row is electrically connected to the sub-pixels of the 4a-th row; The sub-pixels of the (4a - 1)-th row and the sub-pixels of the (4a - 3)-th row are the first type of sub-pixel rows, and the sub-pixels of the (4a - 2)-th row and the sub-pixels of the 4a-th row are the second type of sub-pixel rows.

13. The display panel according to claim 8, wherein, The first generation circuit of the a-th level is electrically connected to the light-emitting control lines of the (6a - 5)-th row, the (6a - 3)-th row and the (6a - 5)-th row respectively, and is used to provide light-emitting control signals for the light-emitting control lines of the (6a - 5)-th row, the (6a - 3)-th row and the (6a - 5)-th row; The second generation circuit of the a-th level is electrically connected to the light-emitting control lines of the (6a - 4)-th row, the (6a - 2)-th row and the 6a-th row respectively, and is used to provide light-emitting control signals for the light-emitting control lines of the (6a - 4)-th row, the (6a - 2)-th row and the 6a-th row; a is a positive integer; The light-emitting control line of the (6a - 5)-th row is electrically connected to the sub-pixels of the (6a - 5)-th row, the light-emitting control line of the (6a - 4)-th row is electrically connected to the sub-pixels of the (6a - 4)-th row, the light-emitting control line of the (6a - 3)-th row is electrically connected to the sub-pixels of the (6a - 3)-th row, the light-emitting control line of the (6a - 2)-th row is electrically connected to the sub-pixels of the (6a - 2)-th row, the light-emitting control line of the (6a - 1)-th row is electrically connected to the sub-pixels of the (6a - 1)-th row, and the light-emitting control line of the 6a-th row is electrically connected to the sub-pixels of the 6a-th row; the sub-pixels of the (6a - 5)-th row, the sub-pixels of the (6a - 3)-th row and the sub-pixels of the (6a - 1)-th row are the first type of sub-pixel rows, and the sub-pixels of the (6a - 4)-th row, the sub-pixels of the (6a - 2)-th row and the sub-pixels of the 6a-th row are the second type of sub-pixel rows.

14. The display panel according to claim 8, wherein, The first generation circuit of the a-th level is electrically connected to the light-emitting control lines of the (8a - 7)-th row, the (8a - 5)-th row, the (8a - 3)-th row and the (8a - 1)-th row respectively, and is used to provide light-emitting control signals for the light-emitting control lines of the (8a - 7)-th row, the (8a - 5)-th row, the (8a - 3)-th row and the (8a - 1)-th row; The second generation circuit of the a-th level is electrically connected to the light-emitting control lines of the (8a - 6)-th row, the (8a - 4)-th row, the (8a - 2)-th row and the 8a-th row respectively, and is used to provide light-emitting control signals for the light-emitting control lines of the (8a - 6)-th row, the (8a - 4)-th row, the (8a - 2)-th row and the 8a-th row; a is a positive integer; The 8a-7 row light-emitting control line is electrically connected to the 8a-7 row sub-pixel, the 8a-6 row light-emitting control line is electrically connected to the 8a-6 row sub-pixel, the 8a-5 row light-emitting control line is electrically connected to the 8a-5 row sub-pixel, the 8a-4 row light-emitting control line is electrically connected to the 8a-4 row sub-pixel, the 8a-3 row light-emitting control line is electrically connected to the 8a-3 row sub-pixel, the 8a-2 row light-emitting control line is electrically connected to the 8a-2 row sub-pixel, the 8a-1 row light-emitting control line is electrically connected to the The 8a-1 row of sub-pixels are electrically connected, and the 8a row of light-emitting control lines are electrically connected to the 8a row of sub-pixels; the 8a-7 row of sub-pixels, the 8a-5 row of sub-pixels, the 8a-3 row of sub-pixels and the 8a-1 row of sub-pixels are first type of sub-pixel rows, and the 8a-6 row of sub-pixels, the 8a-4 row of sub-pixels, the 8a-2 row of sub-pixels and the 8a row of sub-pixels are second type of sub-pixel rows.

15. The display panel according to any one of claims 1 to 4, wherein: The generating circuit is used for providing a light emitting control signal for at least one first type sub-pixel row and at least one second type sub-pixel row.

16. The display panel according to claim 15, wherein, The n-th level generating circuit comprises an n-th level generating unit and an n-th level output controlling unit; The n-th generation unit is used to generate an n-th light emitting control signal, and output the n-th light emitting control signal through the n-th light emitting control signal output terminal; The input end of the n-th level output control unit is electrically connected to the n-th light-emitting control signal output end, the first output end of the n-th level output control unit is electrically connected to the 2n-1-th row of light-emitting control lines, the second output end of the n-th level output control unit is electrically connected to the 2n-th row of light-emitting control lines, and the n-th level output control unit is used to provide effective light-emitting control signals to the 2n-1-th row of light-emitting control lines and the 2n-th row of light-emitting control lines in a time-sharing manner according to the n-th light-emitting control signal provided by the n-th light-emitting control signal output end; n is an integer less than or equal to N, and N is an integer greater than 1.

17. The display panel according to claim 16, wherein, The 2n-1th row of light emitting control lines is electrically connected to the 2n-1th row of sub-pixels, and the 2nth row of light emitting control lines is electrically connected to the 2nth row of sub-pixels; The 2n-1th row of sub-pixels is a first type of sub-pixel row, and the 2nth row of sub-pixels is a second type of sub-pixel row.

18. The display panel according to claim 16, wherein, The output control unit includes a first control module, a second control module, a third control module and a fourth control module; The first control module is electrically connected to the first control end, the input end of the output control unit and the first output end of the output control unit respectively, and is used to control the connection between the input end and the first output end under the control of the first control signal provided by the first control end; The second control module is electrically connected to the second control terminal, the first voltage line and the first output terminal of the output control unit respectively, and is used to control the connection between the first voltage line and the first output terminal under the control of the second control signal provided by the second control terminal; The third control module is electrically connected to the first control terminal, the first voltage line, and the second output terminal of the output control unit respectively, and is configured to control the connection between the first voltage line and the second output terminal under the control of the first control signal provided by the first control terminal; The fourth control module is electrically connected to the second control terminal, the input terminal, and the second output terminal respectively, and is configured to control the connection between the input terminal and the second output terminal under the control of the second control signal provided by the second control terminal.

19. The display panel according to claim 18, wherein, The first control module includes a first control transistor, the second control module includes a second control transistor, the third control module includes a third control transistor, and the fourth control module includes a fourth control transistor; The gate of the first control transistor is electrically connected to the first control terminal, the first pole of the first control transistor is electrically connected to the input terminal of the output control unit, and the second pole of the first control transistor is electrically connected to the first output terminal of the output control unit; The gate of the second control transistor is electrically connected to the second control terminal, the first pole of the second control transistor is electrically connected to the first voltage line, and the second pole of the second control transistor is electrically connected to the first output terminal of the output control unit; The gate of the third control transistor is electrically connected to the first control terminal, the first pole of the third control transistor is electrically connected to the first voltage line, and the second pole of the third control transistor is electrically connected to the second output terminal of the output control unit; The gate of the fourth control transistor is electrically connected to the second control terminal, the first pole of the fourth control transistor is electrically connected to the input terminal of the output control unit, and the second pole of the fourth control transistor is electrically connected to the second output terminal of the output control unit.

20. The display panel according to any one of claims 1 to 4, wherein, The sub-pixel includes a light-emitting element, a driving circuit, a data writing circuit, a reset circuit, a first light-emitting control circuit, and a second light-emitting control circuit; The control terminal of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, and the second end of the driving circuit is electrically connected to the third node; The data writing circuit is electrically connected to the scanning line, the data line, and the second node N2 respectively, and is configured to write the display data voltage provided by the data line into the second node under the control of the scanning signal provided by the scanning line; The reset circuit is electrically connected to the reset control line, the first initial voltage terminal, and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal provided by the reset control line RE; The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal, and the second node respectively, and is configured to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line; The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the first pole of the light-emitting element respectively, and is configured to control the connection or disconnection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal; The second pole of the light-emitting element is electrically connected to the first voltage terminal.

21. The display panel according to claim 4, wherein, The light condensing structure includes a microlens and / or a light shielding structure; The light shielding structure surrounds an opening area corresponding to the anti-peeking sub-pixel.

22. A display device, comprising a display panel according to any one of claims 1 to 21.

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