Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises two pixel driving circuits which are adjacent and symmetrically arranged; the pixel driving circuits are electrically connected to data lines; two first power supply signal lines are provided between two data lines corresponding to the two pixel driving circuits; and a second connecting line is provided between the two first power supply signal lines. According to the present application, the problem of interference between the second connecting line and the first power supply signal lines can be eliminated, thereby reducing the lap joint difficulty of first connecting lines and the second connecting lines.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with liquid crystal displays, organic light-emitting diode (OLED) display panels have the advantages of being thinner and lighter, having better display effects, higher resolution, wider color gamut, lower power consumption, and flexible display. As a result, they have developed rapidly in recent years and have become the preferred display panel type for mobile terminals.

[0003] To improve edge display effects, researchers have developed a fan-out routing in the display area (FIAA) architecture, which connects the data lines in the edge display area and the fan-out routing in the non-display area through the fan-out routing in the display area. The fan-out wiring of the display area usually includes a first connection line with a different extension direction from the data line and a second connection line with the same extension direction as the data line. In order to improve the off-screen mura problem, the first connection line and the second connection line are usually arranged in different metal layers. For example, the first connection line is arranged in a first metal layer including the source and drain of multiple transistors, and the second connection line is arranged in the second metal layer. At the same time, in order to avoid interference between the second connection line and the first power signal line of the block structure, the first power signal line is also arranged in an independent metal layer. In order to meet the design requirements of the first power signal line, the first power signal line is usually arranged adjacent to the first metal layer, which makes the first power signal line arranged in a third metal layer between the first metal layer and the second metal layer. Therefore, the first connection line and the second connection line are separated by the third metal layer and at least two insulating layers, which greatly increases the difficulty of overlapping the first connection line and the second connection line. This problem needs to be solved urgently. SUMMARY OF THE INVENTION

[0004] The present application provides a display panel and a display device, which can eliminate the interference problem between the second connection line and the first power signal line in the fan-out routing of the display area, while improving the problem of increased difficulty in overlapping the first connection line and the second connection line.

[0005] In a first aspect, the present application provides a display panel, comprising a display area, the display panel comprising: a substrate; a first source / drain metal layer disposed on one side of the substrate, the portion of the first source / drain metal layer disposed in the display area comprising a plurality of first connecting lines, the first connecting lines extending along a first direction; a first planar layer disposed on a surface of the first source / drain metal layer facing away from the substrate; and a second source / drain metal layer disposed on a surface of the first planar layer facing away from the substrate, the portion of the second source / drain metal layer disposed in the display area comprising: a plurality of data lines, a plurality of first power signal lines, and a plurality of second connecting lines, the data lines, the first power signal lines, and the second connecting lines all extending along a second direction, wherein one of the second connecting lines and the data line is electrically connected to the same first connecting line via a via penetrating the first planar layer; wherein the display panel in the display area comprises two pixel driving circuits adjacent and symmetrically disposed in the first direction, each of the pixel driving circuits being electrically connected to one of the data lines; wherein two first power signal lines are disposed between two of the data lines corresponding to the two pixel driving circuits, and at least one second connecting line is disposed between two of the first power signal lines.

[0006] In a second aspect, the present application provides a display device, comprising a housing and the display panel described above, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] FIG1 is a schematic diagram of a film layer structure of a display panel provided in some embodiments of the present application.

[0009] FIG2 is a schematic plan view of a display panel provided in some embodiments of the present application.

[0010] FIG3 is a schematic diagram of the planar distribution of a first power signal line and a second connection line between two adjacent data lines provided by some embodiments of the present application.

[0011] FIG. 4 is a plan view schematically showing a plurality of film layers in a region between two adjacent data lines provided by some embodiments of the present application.

[0012] FIG5 a is a schematic diagram of the planar structure of a first source-drain metal layer in a display area provided by some embodiments of the present application.

[0013] FIG5 b is a schematic diagram of the planar structure of the second source-drain metal layer in the display area provided by some embodiments of the present application.

[0014] FIG5 c is a schematic diagram of a planar structure of a first gate layer in a display area provided by some embodiments of the present application.

[0015] FIG5 d is a schematic diagram of a planar structure of a second gate layer in a display area provided by some embodiments of the present application.

[0016] FIG5e is a schematic diagram of a planar structure of a third gate layer in a display area provided by some embodiments of the present application.

[0017] FIG5 f is a schematic diagram of the planar structure of the metal oxide semiconductor layer in the display area provided by some embodiments of the present application.

[0018] FIG5 g is a schematic diagram of the planar structure of a low-temperature polysilicon semiconductor layer in a display area provided in some embodiments of the present application.

[0019] FIG6 a is a plan view of signal routing in an edge region and signal routing in a middle region in the related art.

[0020] FIG6 b is a waveform diagram of data signals outputted by the signal routing in the edge area and the signal routing in the middle area to the corresponding data lines in the high refresh rate mode in the related art.

[0021] FIG7 is an equivalent circuit diagram of a pixel driving circuit in a display area provided in an embodiment of the present application.

[0022] FIG8 is a schematic diagram of the planar structure of a light-shielding metal layer provided in some embodiments of the present application.

[0023] Description of reference numerals:

[0024] Display panel 01; display area 02; non-display area 03; substrate 10; first source-drain metal layer 20; first connecting line 21; parallel signal line 22; first planarization layer 30; second source-drain metal layer 40; data line group 401; data line 41; first power signal line 42; second connecting line 43; first portion 431; second portion 432; gate layer 50; first signal trace 51; second signal trace 52; metal oxide semiconductor layer 60; first active layer 61; second active layer 62; light shielding metal layer 70; light shielding portion 71; buffer layer 80; low-temperature polysilicon semiconductor layer 90; first gate insulating layer 100; first gate layer 110; second type scan line 111; second gate insulating layer 120; second gate layer 130; first interlayer dielectric layer 140; third gate insulating layer 150; third gate layer 160; shielding line 161; second interlayer dielectric layer 170; second planarization layer 180; Anode layer 190; pixel definition layer 200; spacer layer 210; first thin film transistor T1; second thin film transistor T2; third thin film transistor T3; fourth thin film transistor T4; fifth thin film transistor T5; sixth thin film transistor T6; seventh thin film transistor T7; eighth thin film transistor T8; first capacitor C1; second capacitor C2; data signal access terminal DATA; gate reset signal line access terminal ViG; anode reset signal access terminal ViA; enable signal access terminal EM; first type first scan signal access terminal Nscan1; first type second scan signal access terminal Nscan2; second type first scan signal access terminal Pscan1; second type second scan signal access terminal Pscan2; second power signal access terminal VSS; signal trace M1 in the edge region; signal trace M2 in the middle region; first direction X; second direction Y; perpendicular bisector L1; pixel driving circuit XQ; Modes for Carrying Out the Invention

[0025] In a first aspect, the present application provides a display panel, comprising a display area, the display panel comprising: a substrate; a first source / drain metal layer disposed on one side of the substrate, the portion of the first source / drain metal layer disposed in the display area comprising a plurality of first connecting lines, the first connecting lines extending along a first direction; a first planar layer disposed on a surface of the first source / drain metal layer facing away from the substrate; and a second source / drain metal layer disposed on a surface of the first planar layer facing away from the substrate, the portion of the second source / drain metal layer disposed in the display area comprising: a plurality of data lines, a plurality of first power signal lines, and a plurality of second connecting lines, the data lines, the first power signal lines, and the second connecting lines all extending along a second direction, wherein one of the second connecting lines and the data line is electrically connected to the same first connecting line via a via penetrating the first planar layer; wherein the display panel in the display area comprises two pixel driving circuits adjacent and symmetrically disposed in the first direction, each of the pixel driving circuits being electrically connected to one of the data lines; wherein two first power signal lines are disposed between two of the data lines corresponding to the two pixel driving circuits, and at least one second connecting line is disposed between two of the first power signal lines.

[0026] Optionally, the plurality of data lines in the portion of the display area where the second source / drain metal layer is arranged are evenly divided into a plurality of data line groups, each of the data line groups including two adjacent data lines; wherein, two adjacent first power signal lines are arranged between two of the data lines in at least one of the data line groups, and two adjacent second connection lines are arranged between the two first power signal lines.

[0027] Optionally, the display panel has a non-display area, and the display panel further includes: a gate layer, the gate layer is arranged between the substrate and the first source and drain metal layer, the portion of the gate layer arranged in the non-display area includes a plurality of first signal lines, and the data line is electrically connected to the first signal line through the first connecting line and the second connecting line; wherein, in a direction perpendicular to the substrate, the portion of the second source and drain metal layer arranged in the non-display area overlaps with at least part of the first signal line, the portion of the first source and drain metal layer arranged in the non-display area overlaps with at least part of the first signal line, and the resistivity of the gate layer is greater than the resistivity of the first source and drain metal layer, and the resistivity of the gate layer is greater than the resistivity of the second source and drain metal layer.

[0028] Optionally, the display panel also includes: a metal oxide semiconductor layer, arranged between the substrate and the first source and drain metal layer, and the portion of the metal oxide semiconductor layer arranged in the display area includes multiple first active layers; wherein the second connecting line includes a first portion and a second portion extending along a second direction, and in a direction perpendicular to the substrate, at least a portion of the first portion overlaps with the first active layer, and the second portion does not overlap with the first active layer; wherein, in the first direction, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

[0029] Optionally, a groove is formed on the first power signal line at a side close to the second connecting line and at a position corresponding to the first portion.

[0030] Optionally, the portion of the metal oxide semiconductor layer disposed in the display area further includes a plurality of second active layers, wherein the first power signal line covers the second active layers in a direction perpendicular to the substrate.

[0031] Optionally, the display panel also includes: a light-shielding metal layer, arranged on the side of the second source-drain metal layer facing away from the substrate; wherein the light-shielding metal layer includes a plurality of light-shielding portions, and each of the light-shielding portions is electrically connected to two adjacent first power signal lines, and the orthographic projection of the light-shielding portion on the second source-drain metal layer covers the first active layer and the second active layer.

[0032] Optionally, the display panel includes a plurality of first thin film transistors and a plurality of second thin film transistors arranged in the display area, the first thin film transistor includes the first active layer, the second thin film transistor includes the second active layer, and one end of the source or drain of the second thin film transistor is electrically connected to the gate reset signal line, and the other end of the source or drain of the second thin film transistor is electrically connected to one end of the source or drain of the first thin film transistor.

[0033] Optionally, the display panel also includes a low-temperature polycrystalline silicon semiconductor layer, and the display panel also includes a plurality of third thin-film transistors, a plurality of fourth thin-film transistors, a plurality of fifth thin-film transistors, a plurality of sixth thin-film transistors, a plurality of seventh thin-film transistors, and a plurality of eighth thin-film transistors arranged in the display area, wherein the low-temperature polycrystalline silicon semiconductor layer includes the channel of the third thin-film transistor, the channel of the fourth thin-film transistor, the channel of the fifth thin-film transistor, the channel of the sixth thin-film transistor, the channel of the seventh thin-film transistor, and the channel of the eighth thin-film transistor, and the source and drain of the third thin-film transistor, the source and drain of the fourth thin-film transistor, the source and drain of the fifth thin-film transistor, the source and drain of the sixth thin-film transistor, the source and drain of the seventh thin-film transistor, and the source and drain of the eighth thin-film transistor are all located in the first source-drain metal layer.

[0034] Optionally, the display panel includes a second type of scan line electrically connected to the gate of the seventh thin film transistor and the gate of the eighth thin film transistor, and in a direction perpendicular to the substrate, the second type of scan line at least partially overlaps with the first connecting line; wherein, the display panel also includes a shielding line arranged between the second type of scan line and the first connecting line.

[0035] Optionally, the width of the shielding line in the second direction is greater than the width of the second type scanning line and the first connecting line in the second direction.

[0036] Optionally, the orthographic projection of the second connecting line on the substrate covers the orthographic projections of the sixth thin film transistor and the seventh thin film transistor on the substrate.

[0037] Optionally, the first source-drain metal layer further includes a parallel signal line, and the parallel signal line is connected in parallel with the first power signal line.

[0038] Optionally, an area proportion of the parallel signal line in the first source-drain metal layer is greater than an area proportion of the first connecting line in the first source-drain metal layer.

[0039] Optionally, the resistivity of the second source-drain metal layer is smaller than the resistivity of the first source-drain metal layer.

[0040] In a second aspect, the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space.

[0041] The present application provides a display panel and a display device. In the display panel, since the portion of the second source-drain metal layer arranged in the display area includes multiple data lines, multiple first power signal lines and multiple second connection lines, the data lines, the first power signal lines and the second connection lines are arranged on the same layer, and the second connection lines are separated from the first connection lines by only the first flat layer. This enables one of the second connection lines and one of the data lines to be electrically connected to the same first connection line through a via hole passing through the first flat layer, thereby forming a FIAA architecture and effectively reducing the difficulty of overlapping the first connection line and the second connection line. In addition, the present application patterns the first power signal line between the two data lines under a specific pixel architecture. The specific pixel architecture is two pixel driving circuits adjacent and symmetrically arranged in the first direction. The two data lines under the specific pixel architecture are respectively electrically connected to the two pixel driving circuits. The present application forms two first power signal lines between the two data lines corresponding to the two pixel driving circuits, thereby being able to utilize the gap area between the pattern differentiated into the two first power signal lines to form a second connecting line, thereby avoiding the interference problem between the first power signal line and the second connecting line, so that the second connecting line and the first power signal line can both be arranged on the second source and drain metal layer on the surface of the first flat layer on the side facing away from the substrate.

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0043] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] Example 1

[0045] Figure 1 is a schematic diagram of the film layer structure of the display panel provided in some embodiments of the present application; Figure 2 is a planar schematic diagram of the display panel provided in some embodiments of the present application; Figure 3 is a planar distribution schematic diagram of the first power signal line and the second connection line between two adjacent data lines provided in some embodiments of the present application; Figure 4 is a planar schematic diagram of multiple film layers in the area between two adjacent data lines provided in some embodiments of the present application; Figure 5a is a planar structural schematic diagram of the first source and drain metal layer in the display area provided in some embodiments of the present application; Figure 5b is a planar structural schematic diagram of the second source and drain metal layer in the display area provided in some embodiments of the present application. With reference to Figures 1, 2, 3, 4, 5a, and 5b, in a first aspect, an embodiment of the present application provides a display panel 01, wherein the display panel 01 has a display area 02, and the display panel 01 includes a substrate 10, a first source-drain metal layer 20, a first planar layer 30, and a second source-drain metal layer 40, wherein the first source-drain metal layer 20 is arranged on one side of the substrate 10, and the portion of the first source-drain metal layer 20 arranged in the display area 02 includes a plurality of first connecting lines 21, and the first connecting lines 21 extend along a first direction X; the first planar layer 30 is arranged on a surface of the first source-drain metal layer 20 on a side away from the substrate 10; the second source-drain metal layer 40 is arranged on a surface of the first planar layer 30 on a side away from the substrate 10; wherein the second source-drain metal layer 40 is arranged on the Part of the display area 02 includes: multiple data lines 41, multiple first power signal lines 42 and multiple second connection lines 43, wherein the data lines 41, the first power signal lines 42 and the second connection lines 43 all extend along the second direction Y, wherein one of the second connection lines 43 and one of the data lines 41 are respectively electrically connected to the same first connection line 21 through a via hole penetrating the first flat layer 30; wherein, the display panel 01 of the display area 02 includes two pixel driving circuits XQ adjacent and symmetrically arranged in the first direction X, and each of the pixel driving circuits XQ is electrically connected to one of the data lines 41; wherein, two first power signal lines 42 are arranged between the two data lines 41 corresponding to the two pixel driving circuits XQ, and at least one second connection line 43 is arranged between the two first power signal lines 42.

[0046] In the display panel 01 provided in the present application, since the second source-drain metal layer 40 is arranged in the portion of the display area 02 including multiple data lines 41, multiple first power signal lines 42 and multiple second connection lines 43, the data lines 41, the first power signal lines 42 and the second connection lines 43 are arranged on the same layer, and the second connection lines 43 and the first connection lines 21 are separated only by the first flat layer 30. This enables one of the second connection lines 43 and one of the data lines 41 to be electrically connected to the same first connection line 21 through a via passing through the first flat layer 30, thereby forming a FIAA architecture and effectively reducing the difficulty of overlapping the first connection line 21 and the second connection line 43.

[0047] In addition, the present application has patterned the first power signal line 42 between two data lines 41 under a specific pixel architecture. Specifically, the specific pixel architecture comprises two pixel drive circuits XQ adjacent and symmetrically arranged in the first direction X, and the two data lines 41 under the specific pixel architecture are respectively electrically connected to the two pixel drive circuits XQ. The present application forms two first power signal lines 42 between the two data lines 41 corresponding to the two pixel drive circuits XQ, thereby utilizing the gap area between the pattern differentiated into the two first power signal lines 42 to form the second connection line 43, thereby avoiding interference between the first power signal line 42 and the second connection line 43, so that the second connection line 43 and the first power signal line 42 can both be arranged on the second source-drain metal layer 40 on the surface of the first planar layer 30 on the side facing away from the substrate 10.

[0048] Continuing with reference to Figure 2, in some embodiments of the present application, the plurality of data lines 41 arranged in the portion of the display area 02 in the second source-drain metal layer 40 are evenly divided into a plurality of data line groups 401, and each of the data line groups 401 includes two adjacent data lines 41; wherein, two adjacent first power signal lines 42 are arranged between two of the data lines 41 in at least one of the data line groups 401, and two adjacent second connection lines 43 are arranged between the two first power signal lines 42.

[0049] In the display panel 01 provided in the present application, the layout of the multiple data lines 41 of the display area 02 is in groups of two, so that the multiple data lines 41 are evenly divided into multiple data line groups 401, and each data line group 401 includes two adjacent data lines 41. Through this layout of the data lines 41, the present application can ensure that there is a larger gap space between the two adjacent data lines 41 in each data line group 401, and thus can form a wiring structure in which two adjacent second connection lines 43 are sandwiched between the two adjacent first power signal lines 42 while meeting the wiring requirements of the first power signal line 42, so that the number of wiring of the second connection lines 43 that can be set in the display area 02 is increased, thereby increasing the fan-out routing of the display area 02, and further enhancing the ability of the fan-out routing of the display area 02 to optimize edge display.

[0050] In some embodiments of the present application, the two data lines 41 in the data line group 401 are symmetrically arranged, and the two pixel driving circuits XQ electrically connected to the two data lines 41 in the data line group 401 and adjacent to each other in the first direction X are symmetrically arranged, so as to optimize the layout of the patterns corresponding to the data lines 41 and the patterns corresponding to the pixel driving circuits XQ, so that there is space between the two adjacent data lines 41 in the data line group 401 for setting two adjacent first power signal lines 42 and two adjacent second connection lines 43.

[0051] Figure 5c is a schematic diagram of the planar structure of the first gate layer in the display area provided in some embodiments of the present application; Figure 5d is a schematic diagram of the planar structure of the second gate layer in the display area provided in some embodiments of the present application; Figure 5e is a schematic diagram of the planar structure of the third gate layer in the display area provided in some embodiments of the present application. In combination with Figures 1 and 5c, 5d, and 5e, in some embodiments of the present application, the display panel 01 has a non-display area 03, and the display panel 01 also includes a gate layer 50, the gate layer 50 is arranged between the substrate 10 and the first source and drain metal layer 20, the portion of the gate layer 50 arranged in the non-display area 03 includes a plurality of first signal lines 51, and the data line 41 is electrically connected to the first signal line 51 through the first connecting line 21 and the second connecting line 43; wherein, in a direction perpendicular to the substrate, the portion of the second source and drain metal layer arranged in the non-display area overlaps with at least part of the first signal line, the portion of the first source and drain metal layer arranged in the non-display area overlaps with at least part of the first signal line, and the resistivity of the gate layer 50 is greater than the resistivity of the first source and drain metal layer 20, and the resistivity of the gate layer 50 is greater than the resistivity of the second source and drain metal layer 40.

[0052] As shown in Figure 1, the display panel 01 provided in the present application includes a first gate insulating layer 100, a first gate layer 110, a second gate insulating layer 120, a second gate layer 130, a first interlayer dielectric layer 140, a third gate insulating layer 150, and a third gate layer 160 stacked in sequence on one side of the substrate 10.

[0053] In the display panel 01 provided in the present application, the gate layer 50 includes at least one of the first gate layer 110, the second gate layer 130, and the third gate layer 160. Optionally, the gate layer 50 includes the first gate layer 110 and the second gate layer 130, that is, the first signal trace 51 includes a portion located in the first gate layer 110 and a portion located in the second gate layer 130, so as to reduce the wiring difficulty of the first signal trace 51. On the basis of ensuring safety, the first signal trace 51 can be spaced smaller than the adjacent second signal trace 52 or other signal traces.

[0054] In the display panel 01 provided in the present application, in a direction perpendicular to the substrate 10, the second source-drain metal layer 40 is arranged in a portion of the non-display area 03 (such as the first power signal line 42 in the non-display area 03) that overlaps with at least part of the first signal routing line 51, and the first source-drain metal layer 20 is arranged in a portion of the non-display area 03 (such as a routing line parallel to the first power signal line 42 in the non-display area 03) that overlaps with at least part of the first signal routing line 51, which makes it impossible for the first signal routing line 51 electrically connected to the data line 41 to be located in the first source-drain metal layer 20 or the second source-drain metal layer 40, and thus the first signal routing line 51 needs to be arranged in the gate layer 50.

[0055] However, no matter whether the gate layer 50 is one or more of the first gate layer 110, the second gate layer 130, and the third gate layer 160, the resistivity of the gate layer 50 is greater than the resistivity of the first source-drain metal layer 20 and the second source-drain metal layer 40, that is, the resistance-capacitance delay when the electrical signal is transmitted in the gate layer 50 is large. Figure 6a is a planar schematic diagram of the signal routing in the edge area and the signal routing in the middle area in the related art, and Figure 6b is a waveform diagram of the data signals output by the signal routing in the edge area and the signal routing in the middle area to the corresponding data lines in the high refresh rate mode in the related art. Referring to Figures 6a and 6b, the refresh rate corresponding to the high refresh rate mode is, for example, greater than or equal to 90HZ. In the high refresh rate mode, the scanning time of each pixel row is compressed, which further highlights the resistance-capacitance delay problem when the electrical signal is transmitted in the gate layer 50. Specifically, because the length of the signal line M1 in the edge area is longer and the length of the signal line M2 in the middle area is shorter, the voltage charged into the display pixel through the data line 41 in the edge area is different from the voltage charged into the display pixel through the data line 41 in the middle area, which leads to display abnormality and causes fine vertical lines to appear in the edge area of ​​the display panel 01. In the display panel 01 provided in the present application, the first signal line electrically connected to the data line 41 in the edge area and the second signal line 52 electrically connected to the data line 41 in the middle area are the same length. The difference between the data line 41 in the edge area and the data line 41 in the middle area is whether they are electrically connected to the signal line in the non-display area 03 through the first connection line 21 and the second connection line 43. As mentioned above, since the resistivity of the first source and drain metal layer 20 and the resistivity of the second source and drain metal layer 40 are both lower than the resistivity of the gate layer 50, the resistance-capacitance delay of the first connection line 21 and the second connection line 43 can be reduced, thereby optimizing the display effect of the display panel 01 in the edge area in high refresh rate mode.

[0056] Figure 5f is a schematic planar structure diagram of a metal oxide semiconductor layer within the display area provided in some embodiments of the present application. Referring to Figures 1 and 5f, in some embodiments of the present application, the display panel 01 further includes a metal oxide semiconductor layer 60, disposed between the substrate 10 and the first source / drain metal layer 20. Specifically, the metal oxide semiconductor layer 60 is disposed between the first interlayer dielectric layer 140 and the third gate insulating layer 150. The portion of the metal oxide semiconductor layer 60 disposed within the display area 02 includes a plurality of first active layers 61. The second connecting line 43 includes a first portion 431 and a second portion 432 extending along a second direction Y. In a direction perpendicular to the substrate 10, at least a portion of the first portion 431 overlaps with the first active layer 61, while the second portion 432 does not overlap with the first active layer 61. In the first direction X, the first portion 431 has a first width, and the second portion 432 has a second width, and the first width is greater than the second width.

[0057] In the related art, the first active layer 61 formed by the metal oxide semiconductor layer 60 has relatively obvious photosensitive properties. For example, when irradiated with white light, the effective field-effect mobility of the thin-film transistor used in the first active layer 61 is significantly improved, thereby affecting the switching characteristics of the thin-film transistor used in the first active layer 61. In the display panel 01 provided in the present application, since at least a portion of the first portion 431 overlaps with the first active layer 61 in a direction perpendicular to the substrate 10, and the second portion 432 does not overlap with the first active layer 61, and in the first direction X, the first portion 431 has a first width and the second portion 432 has a second width, and the first width is greater than the second width, the shielding effect of the second connecting line 43 on the first active layer 61 can be enhanced, thereby improving the switching characteristics of the thin-film transistor used in the first active layer 61.

[0058] In some embodiments of the present application, a groove is formed on the first power signal line 42 at a side close to the second connection line 43 and at a position corresponding to the first portion 431 .

[0059] In the display panel provided herein, a groove is formed on the first power signal line 42 on a side adjacent to the second connecting line 43 and corresponding to the first portion 431. The groove serves to avoid the first portion 431, thereby ensuring a greater spacing between the first power signal line 42 and the second connecting line 43, reducing signal crosstalk, and improving safety. Specifically, because the first portion 431 of the second connecting line 43 is wider than the second portion 432 in the first direction X, if the first power signal line 42 is not modified, the spacing between the first portion 431 and the first power signal line 42 in the first direction X will be smaller than the spacing between the second portion 432 and the first power signal line 42, thereby causing signal crosstalk and safety issues. To address these issues, the present invention provides a groove on the first power signal line 42 on a side adjacent to the second connecting line 43 and corresponding to the first portion 431.

[0060] In some embodiments of the present application, the portion of the metal oxide semiconductor layer 60 disposed in the display area 02 further includes a plurality of second active layers 62 , and in a direction perpendicular to the substrate 10 , the first power signal line 42 covers the second active layers 62 .

[0061] In related art, the second active layer 62 formed by the metal oxide semiconductor layer 60 has relatively significant photosensitive properties. For example, when irradiated with white light, the effective field-effect mobility of the thin-film transistor used in the second active layer 62 is significantly improved, thereby affecting the switching characteristics of the thin-film transistor used in the second active layer 62. In the display panel 01 provided in the present application, because the first power signal line 42 covers the second active layer 62 in a direction perpendicular to the substrate 10, the first power signal line 42 can be used to shield the second active layer 62, thereby improving the switching characteristics of the thin-film transistor used in the second active layer 62.

[0062] FIG7 is an equivalent circuit diagram of a pixel driving circuit in a display area provided in an embodiment of the present application. Referring to FIG1 and FIG7 , in some embodiments of the present application, the display panel 01 includes a plurality of first thin-film transistors T1 and a plurality of second thin-film transistors T2 disposed in the display area 02 . The first thin-film transistors T1 include the first active layer 61 , the second thin-film transistors T2 include the second active layer 62 , and one end of the source or drain of the second thin-film transistor T2 is electrically connected to the gate reset signal line access terminal ViG, and the other end of the source or drain of the second thin-film transistor T2 is electrically connected to one end of the source or drain of the first thin-film transistor T1 .

[0063] In the display panel 01 provided in the present application, the first thin film transistor T1 includes the first active layer 61, and the second thin film transistor T2 includes the second active layer 62. The first active layer 61 and the second active layer 62 are both located in the metal oxide semiconductor layer 60. Therefore, the first thin film transistor T1 and the second thin film transistor T2 are both metal oxide thin film transistors.

[0064] FIG5 g is a schematic diagram of the planar structure of a low-temperature polysilicon semiconductor layer in a display area provided in some embodiments of the present application. 1 and 5 g , in some embodiments of the present application, the display panel 01 further includes a low-temperature polycrystalline silicon semiconductor layer 90 , and the display panel 01 further includes a plurality of third thin-film transistors T3 , a plurality of fourth thin-film transistors T4 , a plurality of fifth thin-film transistors T5 , a plurality of sixth thin-film transistors T6 , a plurality of seventh thin-film transistors T7 , and a plurality of eighth thin-film transistors T8 arranged in the display area 02 , wherein the low-temperature polycrystalline silicon semiconductor layer 90 includes a channel of the third thin-film transistor T3 , a channel of the fourth thin-film transistor T4 , a channel of the fifth thin-film transistor T5 , a channel of the sixth thin-film transistor T6 , a channel of the seventh thin-film transistor T7 , and a channel of the eighth thin-film transistor T8 , and the source and drain of the third thin-film transistor T3 , the source and drain of the fourth thin-film transistor T4 , the source and drain of the fifth thin-film transistor T5 , the source and drain of the sixth thin-film transistor T6 , the source and drain of the seventh thin-film transistor T7 , and the source and drain of the eighth thin-film transistor T8 are all located in the first source-drain metal layer 20 .

[0065] In the display panel 01 provided in the present application, the low-temperature polycrystalline silicon semiconductor layer 90 includes the channel of the third thin film transistor T3, the channel of the fourth thin film transistor T4, the channel of the fifth thin film transistor T5, the channel of the sixth thin film transistor T6, the channel of the seventh thin film transistor T7, and the channel of the eighth thin film transistor T8, that is, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are all low-temperature polycrystalline silicon thin film transistors.

[0066] In addition, since the source and drain of the third thin-film transistor T3, the source and drain of the fourth thin-film transistor T4, the source and drain of the fifth thin-film transistor T5, the source and drain of the sixth thin-film transistor T6, the source and drain of the seventh thin-film transistor T7, and the source and drain of the eighth thin-film transistor T8 in each pixel driving circuit XQ are all located in the first source-drain metal layer 20, a large number of via-hole overlapping structures need to be provided on the first source-drain metal layer 20. This is also a major reason why the difficulty of overlapping the first connecting line and the second connecting line is greatly increased when the third metal layer and at least two insulating layers are separated between the first connecting line and the second connecting line in the display panel of the related art. That is, the present application can reduce the difficulty of overlapping the first connecting line 21 and the second connecting line 43 while eliminating the interference problem between the first power signal line 42 and the second connecting line 43 for the pixel driving circuit XQ including eight thin-film transistors.

[0067] In some embodiments of the present application, the display panel 01 includes a pixel driving circuit XQ corresponding to each display pixel. The pixel driving circuit XQ includes a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, and an eighth thin-film transistor T8. That is, the pixel driving circuit XQ includes two different types of thin-film transistors. The pixel driving circuit XQ is a low-temperature polycrystalline oxide (LTPO) pixel driving circuit XQ, which can significantly improve the refresh rate applicability and driving performance of the display panel 01 and reduce power consumption.

[0068] In some embodiments of the present application, the pixel driving circuit XQ further includes a first capacitor C1 and a second capacitor C2, and the pixel driving circuit XQ further includes a data signal access terminal DATA, an anode reset signal access terminal ViA, an enable signal access terminal EM, a first type first scan signal access terminal Nscan1, a first type second scan signal access terminal Nscan2, a second type first scan signal access terminal Pscan1, a second type second scan signal access terminal Pscan2, a second power signal access terminal VSS, and a third reset signal access terminal Vi3, wherein the data signal access terminal DATA is electrically connected to the data line 41, and the anode reset signal access terminal ViA is electrically connected to the The anode reset signal line is electrically connected, the enable signal access terminal EM is electrically connected to the enable signal line, the first type first scan signal access terminal Nscan1 is electrically connected to one of the first type scan lines, the first type second scan signal access terminal Nscan2 is electrically connected to another first type scan line, the second type first scan signal access terminal Pscan1 is electrically connected to one of the second type scan lines 111, the second type second scan signal access terminal Pscan2 is typically connected to another second type scan line 111, the second power signal access terminal VSS is electrically connected to the second power signal line, and the third reset signal access terminal Vi3 is electrically connected to the third reset signal line.

[0069] In some embodiments of the present application, the second type scan line 111 electrically connected to the second type second scan signal access terminal Pscan2 is electrically connected to the gate of the seventh thin film transistor T7 and the gate of the eighth thin film transistor T8, and in a direction perpendicular to the substrate 10, the second type scan line 111 at least partially overlaps with the first connection line 21; wherein, the display panel 01 also includes a shielding line 161 arranged between the second type scan line 111 and the first connection line 21.

[0070] In the display panel provided by the present application, the signal transmitted by the second-type scan line 111 electrically connected to the second-type second scan signal access terminal Pscan2 is different from the signal transmitted by the first connection line 21. Since the second-type scan line 111 electrically connected to the second-type second scan signal access terminal Pscan2 overlaps at least partially with the first connection line 21, during the operation of the display panel 01, a coupling capacitance is generated between the second-type scan line 111 electrically connected to the second-type second scan signal access terminal Pscan2 and the first connection line 21, thereby affecting the display effect of the display panel 01. The present application provides a shielding line 161 between the second-type scan line 111 electrically connected to the second-type second scan signal access terminal Pscan2 and the first connection line 21, thereby effectively improving the crosstalk problem between the second-type scan line 111 and the first connection line 21, thereby improving the display effect of the display panel 01.

[0071] In some embodiments of the present application, the second type scan line 111 electrically connected to the second type second scan signal access terminal Pscan2 is located in the first gate layer 110 , and the shielding line 161 is located in the third gate layer 160 .

[0072] In some embodiments of the present application, the width of the shielding line 161 in the second direction Y is greater than the width of the second type scan line 111 electrically connected to the second type second scan signal access terminal Pscan2 and the first connection line 21 in the second direction Y.

[0073] In the display panel provided in the present application, since the width of the shielding line 161 in the second direction Y is greater than the width of the second type scanning line 111 and the first connecting line 21 in the second direction Y, the shielding effect of the shielding line 161 can be further enhanced, and the crosstalk problem between the second type scanning line 111 and the first connecting line 21 can be further improved.

[0074] In some embodiments of the present application, the orthographic projection of the second connecting line 43 on the substrate 10 covers the orthographic projections of the sixth thin film transistor T6 and the seventh thin film transistor T7 on the substrate 10 .

[0075] In some embodiments of the present application, the first source-drain metal layer 20 further includes a parallel signal line 22 , and the parallel signal line 22 is connected in parallel with the first power signal line 42 .

[0076] In the display panel provided by the present application, when at least one second connection line 43 is provided between two adjacent first power signal lines 42, the first power signal lines 42 cannot form a large-area block structure, thereby reducing the signal transmission efficiency of the first power signal lines 42. By forming a parallel signal line 22 in parallel with the first power signal line 42 in the first source / drain metal layer 20, the present application can effectively reduce the resistance of the first power signal line 42 and improve the signal transmission efficiency of the first power signal line 42 without affecting the circuit layout of other components.

[0077] In some embodiments of the present application, the area proportion of the parallel signal line 22 in the first source-drain metal layer 20 is greater than the area proportion of the first connection line 21 in the first source-drain metal layer 20 .

[0078] In the display panel provided in the present application, since the area proportion of the parallel signal line 22 in the first source and drain metal layer 20 is greater than the area proportion of the first connecting line 21 in the first source and drain metal layer 20, the setting area of ​​the parallel signal line 22 can be effectively guaranteed, thereby improving the parallel signal line 22 to reduce the resistance of the first power signal line 42 and improve the signal transmission efficiency of the first power signal line 42.

[0079] In some embodiments of the present application, the resistivity of the second source / drain metal layer 40 is less than the resistivity of the first source / drain metal layer 20 .

[0080] In the related art, the material of the first source-drain metal layer 20 and the material of the second source-drain metal layer 40 are the same, and accordingly, the resistivity of the first source-drain metal layer 20 and the resistivity of the second source-drain metal layer 40 are also the same. However, the applicant has found that in the display panel 01 of the above-mentioned architecture, when at least one second connecting line 43 is provided between two adjacent first power signal lines 42, this makes it impossible for the first power signal line 42 to form a large-area block structure, and the first power signal line 42 has high requirements for signal transmission efficiency. In order to further improve the signal transmission efficiency of the first power signal line 42, the present application makes the resistivity of the second source-drain metal layer 40 lower than the resistivity of the first source-drain metal layer 20, that is, the first power signal line 42 in the second source-drain metal layer 40 is formed using a material with a higher conductive efficiency than the first source-drain metal layer 20. Optionally, the first power signal line 42 is a VDD power signal line.

[0081] In some embodiments of the present application, the display panel 01 further includes a buffer layer 80 , and the buffer layer 80 is disposed between the substrate 10 and the low-temperature polysilicon semiconductor layer 90 .

[0082] In some embodiments of the present application, the display panel 01 also includes a second interlayer dielectric layer 170, which is arranged on the side of the third gate layer 160 away from the substrate 10, and the first source and drain metal layer 20 is arranged on the side of the second interlayer dielectric layer 170 away from the substrate 10.

[0083] In some embodiments of the present application, the display panel 01 further includes a second planarizing layer 180, an anode layer 190, a pixel definition layer 200, and a spacer layer 210. The second planarizing layer 180 is disposed on a side of the second source / drain metal layer 40 facing away from the substrate 10. The anode layer 190 is disposed on a side of the second planarizing layer 180 facing away from the substrate 10. The pixel definition layer 200 is disposed on a side of the anode layer 190 facing away from the substrate 10. The spacer layer 210 is disposed on a side of the pixel definition layer 200 facing away from the substrate 10. Optionally, the pixel definition layer 200 and the spacer layer 210 are integrally formed.

[0084] In some embodiments of the present application, a perpendicular bisector L1 extending along the second direction Y is defined, and the perpendicular bisector L1 divides the display area 02 into two symmetrical parts in the first direction X. When the two second connecting lines 43 between two data lines 41 in the data line group 401 are respectively located on either side of the perpendicular bisector L1, the distance between the data line 41 electrically connected to one of the second connecting lines 43 and the data line 41 electrically connected to the other second connecting line 43 is greater than the distance between the two data lines 41 in the data line group 401; when the two second connecting lines 43 between two data lines 41 in the data line group 401 are both located on the same side of the perpendicular bisector L1, the distance between the data line 41 electrically connected to one of the second connecting lines 43 and the data line 41 electrically connected to the other second connecting line 43 is smaller than the distance between the two data lines 41 in the data line group 401.

[0085] In a second aspect, an embodiment of the present application provides a display device, comprising a housing and a display panel 01 as described above, wherein the housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0086] Example 2

[0087] FIG8 is a schematic diagram of the planar structure of the light-shielding metal layer provided by some embodiments of the present application. In conjunction with FIG1 to FIG8 , in the first aspect, the embodiment of the present application provides a display panel 01, the display panel 01 having a display area 02, the display panel 01 comprising a substrate 10, a first source-drain metal layer 20, a first flat layer 30, and a second source-drain metal layer 40, wherein the first source-drain metal layer 20 is arranged on one side of the substrate 10, the portion of the first source-drain metal layer 20 arranged in the display area 02 comprises a plurality of first connecting lines 21, and the first connecting lines 21 extend along a first direction X; the first flat layer 30 is arranged on the surface of the first source-drain metal layer 20 on the side away from the substrate 10; the second source-drain metal layer 40 is arranged on the surface of the first flat layer 30 on the side away from the substrate 10; wherein the second source-drain metal layer 40 is arranged in the display area 02 The portion includes: a plurality of data lines 41, a plurality of first power signal lines 42 and a plurality of second connection lines 43, wherein the data lines 41, the first power signal lines 42 and the second connection lines 43 all extend along the second direction Y, wherein one of the second connection lines 43 and one of the data lines 41 are electrically connected to the same first connection line 21 through a via hole penetrating the first flat layer 30 respectively; wherein the display panel 01 of the display area 02 includes two pixel driving circuits XQ adjacent and symmetrically arranged in the first direction X, and each of the pixel driving circuits XQ is electrically connected to one of the data lines 41; wherein two first power signal lines 42 are arranged between the two data lines 41 corresponding to the two pixel driving circuits XQ, and at least one second connection line 43 is arranged between the two first power signal lines 42.

[0088] It should be noted that the structure of the display panel 01 provided in the second embodiment of the present application is similar to the structure of the display panel 01 provided in the first embodiment of the present application, and the same parts will not be described in detail in the second embodiment of the present application.

[0089] In some embodiments of the present application, the display panel 01 also includes a light-shielding metal layer 70, which is arranged on the side of the second source-drain metal layer 40 facing away from the substrate 10, wherein the light-shielding metal layer 70 includes a plurality of light-shielding portions 71, and each of the light-shielding portions 71 is electrically connected to two adjacent first power signal lines 42, and the orthographic projection of the light-shielding portion 71 on the second source-drain metal layer 40 covers the first active layer 61 and the second active layer 62.

[0090] In the display panel 01 provided in the present application, since each of the light-shielding portions 71 in the light-shielding metal layer 70 is electrically connected to two adjacent first power signal lines 42, and the orthographic projection of the light-shielding portion 71 on the second source-drain metal layer 40 covers the first active layer 61 and the second active layer 62, on the one hand, the light-shielding portion 71 can be connected in parallel with the first power signal line 42, thereby reducing the resistance of the first power signal line 42; on the other hand, the light-shielding portion 71 can also cover the first active layer 61 and the second active layer 62, thereby improving the switching characteristics of the thin-film transistor used in the first active layer 61 and improving the switching characteristics of the thin-film transistor used in the second active layer 62.

[0091] In a second aspect, an embodiment of the present application provides a display device, comprising a housing and a display panel 01 as described above, wherein the housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0092] In summary, the embodiment of the present application provides a display panel, the display panel having a display area, the display panel including a substrate, a first source-drain metal layer, a first planar layer, and a second source-drain metal layer, wherein the first source-drain metal layer is arranged on one side of the substrate, the portion of the first source-drain metal layer arranged in the display area includes a plurality of first connecting lines, the first connecting lines extending along a first direction; the first planar layer is arranged on a surface of the first source-drain metal layer on a side facing away from the substrate; the second source-drain metal layer is arranged on a surface of the first planar layer on a side facing away from the substrate; wherein the portion of the second source-drain metal layer arranged in the display area includes: a plurality of first connecting lines extending in a first direction; The display panel of the present application includes a plurality of data lines, a plurality of first power signal lines, and a plurality of second connection lines, wherein the data lines, the first power signal lines, and the second connection lines all extend in the second direction, wherein one of the second connection lines and one of the data lines are respectively electrically connected to the same first connection line through a via hole penetrating the first planar layer; wherein the display panel in the display area includes two pixel driving circuits adjacent and symmetrically arranged in the first direction, each pixel driving circuit is electrically connected to one data line; wherein two first power signal lines are arranged between the two data lines corresponding to the two pixel driving circuits, and at least one second connection line is arranged between the two first power signal lines. In the display panel provided by the present application, since the portion of the second source-drain metal layer arranged in the display area includes the plurality of data lines, the plurality of first power signal lines, and the plurality of second connection lines, the data lines, the first power signal lines, and the second connection lines are arranged in the same layer, and the second connection lines are separated from the first connection lines by only the first planar layer, which enables one of the second connection lines and one of the data lines to be respectively electrically connected to the same first connection line through a via hole penetrating the first planar layer, thereby forming a FIAA architecture and effectively reducing the difficulty of overlapping the first connection line and the second connection line. In addition, the present application has patterned a first power signal line between two data lines in a specific pixel architecture. The specific pixel architecture comprises two pixel driving circuits arranged adjacently and symmetrically in a first direction, and the two data lines in the specific pixel architecture are electrically connected to the two pixel driving circuits, respectively. The present application forms two first power signal lines spaced apart between the two data lines corresponding to the two pixel driving circuits, thereby utilizing the gap region between the pattern of the two first power signal lines to form a second connecting line, thereby avoiding interference between the first power signal line and the second connecting line. This allows both the second connecting line and the first power signal line to be disposed on the second source / drain metal layer on the surface of the first planar layer facing away from the substrate.

[0093] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, wherein, The display panel has a display area, and the display panel includes: a substrate; a first source-drain metal layer disposed on one side of the substrate. The portion of the first source-drain metal layer disposed in the display area includes a plurality of first connection lines that extend in a first direction; a first planarization layer disposed on the surface of the first source-drain metal layer facing away from the substrate; a second source-drain metal layer disposed on the surface of the first planarization layer facing away from the substrate. The portion of the second source-drain metal layer disposed in the display area includes: a plurality of data lines, a plurality of first power signal lines, and a plurality of second connection lines. The data lines, the first power signal lines, and the second connection lines all extend in a second direction. One of the second connection lines and one of the data lines are electrically connected to the same first connection line through vias penetrating the first planarization layer; Wherein, the display panel in the display area includes two pixel driving circuits that are adjacent and symmetrically arranged in the first direction, and each pixel driving circuit is electrically connected to one of the data lines; Wherein, two first power signal lines are provided between the two data lines corresponding to the two pixel driving circuits, and at least one second connection line is provided between the two first power signal lines.

2. The display panel according to claim 1, wherein, The plurality of data lines in the portion of the second source-drain metal layer disposed in the display area are evenly divided into a plurality of data line groups, and each data line group includes two adjacent data lines; Wherein, two adjacent first power signal lines are provided between the two data lines in at least one of the data line groups, and two adjacent second connection lines are provided between the two first power signal lines.

3. The display panel according to claim 2, wherein, The display panel has a non-display area, and the display panel further includes: a gate layer disposed between the substrate and the first source-drain metal layer. The portion of the gate layer disposed in the non-display area includes a plurality of first signal traces, and the data lines are electrically connected to the first signal traces through the first connection lines and the second connection lines; Wherein, in the direction perpendicular to the substrate, the portion of the second source-drain metal layer disposed in the non-display area at least partially overlaps with the first signal trace, the portion of the first source-drain metal layer disposed in the non-display area at least partially overlaps with the first signal trace, and the resistivity of the gate layer is greater than the resistivity of the first source-drain metal layer, and the resistivity of the gate layer is greater than the resistivity of the second source-drain metal layer.

4. The display panel according to claim 2, wherein, The display panel further includes: a metal oxide semiconductor layer disposed between the substrate and the first source-drain metal layer. The portion of the metal oxide semiconductor layer disposed in the display area includes a plurality of first active layers; Wherein, the second connection line includes a first portion and a second portion that extend in the second direction. In the direction perpendicular to the substrate, at least a portion of the first portion overlaps with the first active layer, and the second portion does not overlap with the first active layer; Wherein, in the first direction, the first part has a first width, the second part has a second width, and the first width is greater than the second width.

5. The display panel according to claim 4, wherein, A groove is formed in a position of the first power signal line on a side close to the second connection line and corresponding to the first part.

6. The display panel according to claim 4, wherein, The portion of the metal oxide semiconductor layer disposed in the display area further includes a plurality of second active layers. Wherein, in a direction perpendicular to the substrate, the first power signal line covers the second active layers.

7. The display panel according to claim 6, wherein, The display panel further includes: A light-shielding metal layer disposed on a side of the second source-drain metal layer away from the substrate; Wherein, the light-shielding metal layer includes a plurality of light-shielding portions, and each light-shielding portion is electrically connected to two adjacent first power signal lines, and a positive projection of the light-shielding portion on the second source-drain metal layer covers the first active layer and the second active layer.

8. The display panel according to claim 6, wherein, The display panel includes a plurality of first thin film transistors and a plurality of second thin film transistors disposed in the display area. The first thin film transistor includes the first active layer, the second thin film transistor includes the second active layer, and one end of the source or drain of the second thin film transistor is electrically connected to the gate reset signal line, and the other end of the source or drain of the second thin film transistor is electrically connected to one end of the source or drain of the first thin film transistor.

9. The display panel according to claim 8, wherein, The display panel further includes a low-temperature polycrystalline silicon semiconductor layer. The display panel further includes a plurality of third thin film transistors, a plurality of fourth thin film transistors, a plurality of fifth thin film transistors, a plurality of sixth thin film transistors, a plurality of seventh thin film transistors, and a plurality of eighth thin film transistors disposed in the display area. Wherein, the low-temperature polycrystalline silicon semiconductor layer includes the channels of the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, and the eighth thin film transistor, and the sources and drains of the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, and the eighth thin film transistor are all located in the first source-drain metal layer.

10. The display panel according to claim 9, wherein, The display panel includes a second type of scan line electrically connected to the gates of the seventh thin film transistor and the eighth thin film transistor, and in a direction perpendicular to the substrate, at least a part of the second type of scan line overlaps with the first connection line; Wherein, the display panel further includes a shielding line disposed between the second type of scan line and the first connection line.

11. The display panel according to claim 10, wherein, The width of the shielding line in the second direction is greater than the widths of the second type of scan line and the first connection line in the second direction.

12. The display panel according to claim 9, wherein, A positive projection of the second connection line on the substrate covers positive projections of the sixth thin film transistor and the seventh thin film transistor on the substrate.

13. The display panel according to claim 1, wherein, The first source-drain metal layer further includes a parallel signal line, and the parallel signal line is in parallel with the first power signal line.

14. In the display panel according to claim 13, wherein, The area ratio of the parallel signal lines in the first source-drain metal layer is greater than the area ratio of the first connection lines in the first source-drain metal layer.

15. The display panel according to claim 1, wherein, The resistivity of the second source-drain metal layer is less than the resistivity of the first source-drain metal layer.

16. A display device, wherein, The display device includes a housing and a display panel. Among them, the housing has an accommodation space, the display panel is disposed in the accommodation space, the display panel has a display area, and the display panel includes: A substrate; A first source-drain metal layer disposed on one side of the substrate. The portion of the first source-drain metal layer disposed in the display area includes a plurality of first connection lines that extend in a first direction; A first planarization layer disposed on the surface of the first source-drain metal layer facing away from the substrate; A second source-drain metal layer disposed on the surface of the first planarization layer facing away from the substrate. The portion of the second source-drain metal layer disposed in the display area includes: a plurality of data lines, a plurality of first power signal lines, and a plurality of second connection lines. The data lines, the first power signal lines, and the second connection lines all extend in a second direction. One of the second connection lines and one of the data lines are electrically connected to the same first connection line through vias penetrating the first planarization layer; Among them, the display panel in the display area includes two pixel driving circuits that are adjacent and symmetrically disposed in the first direction, and each pixel driving circuit is electrically connected to one of the data lines; Among them, two first power signal lines are disposed between the two data lines corresponding to the two pixel driving circuits, and at least one of the second connection lines is disposed between the two first power signal lines.

17. The display device according to claim 16, wherein, The plurality of data lines in the portion of the second source-drain metal layer disposed in the display area are evenly divided into a plurality of data line groups, and each data line group includes two adjacent data lines; Among them, two adjacent first power signal lines are disposed between the two data lines in at least one of the data line groups, and two adjacent second connection lines are disposed between the two first power signal lines.

18. The display device according to claim 17, wherein, The display panel has a non-display area, and the display panel further includes: A gate layer disposed between the substrate and the first source-drain metal layer. The portion of the gate layer disposed in the non-display area includes a plurality of first signal traces, and the data lines are electrically connected to the first signal traces through the first connection lines and the second connection lines; Among them, in the direction perpendicular to the substrate, the portion of the second source-drain metal layer disposed in the non-display area overlaps at least part of the first signal traces, the portion of the first source-drain metal layer disposed in the non-display area overlaps at least part of the first signal traces, and the resistivity of the gate layer is greater than the resistivity of the first source-drain metal layer, and the resistivity of the gate layer is greater than the resistivity of the second source-drain metal layer.

19. The display device according to claim 17, wherein, The display panel further includes: a metal oxide semiconductor layer disposed between the substrate and the first source-drain metal layer, and a portion of the metal oxide semiconductor layer disposed in the display area includes a plurality of first active layers; Wherein, the second connection line includes a first portion and a second portion extending in a second direction. In a direction perpendicular to the substrate, at least a portion of the first portion overlaps with the first active layer, and the second portion does not overlap with the first active layer; Wherein, in the first direction, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

20. The display device according to claim 19, wherein, The portion of the metal oxide semiconductor layer disposed in the display area further includes a plurality of second active layers. Wherein, in a direction perpendicular to the substrate, the first power signal line covers the second active layer.

Images