Chip performance and power consumption analysis method and apparatus, storage medium, and computer device

Abstract

Embodiments of the present disclosure provide a chip performance and power consumption analysis method and apparatus, a storage medium, and a computer device. The chip performance and power consumption analysis method comprises: simulating a standard cell model to obtain a first set of influence parameters characterizing the influences of different types of transistors on the performance and power consumption of a standard cell; on the basis of the first set of influence parameters and a usage ratio of the standard cell, obtaining a second set of influence parameters characterizing the influences of the different type of transistors on the performance and power consumption of a chip; and on the basis of the second set of influence parameters and usage ratios of the different types of transistors, obtaining a third set of influence parameters characterizing the influences of different product device target values on the performance and power consumption of the chip, to determine the influences of the product device target values on the performance and power consumption of the chip. According to the embodiments of the present disclosure, the resource consumption during chip performance analysis before a chip sample is obtained is reduced, and test data required during the chip performance analysis is reduced, thereby reducing the resource investment for chip performance analysis in the early stage of chip production and manufacturing while ensuring the timeliness.

Description

Chip performance and power consumption analysis method and device, storage medium and computer equipment

[0001] This application claims priority to Chinese Patent Application No. 202311846245.1 filed on December 28, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a chip performance and power consumption analysis method and apparatus, a storage medium, and a computer device. Background Art

[0003] Chip performance analysis in the early stages of chip manufacturing requires extensive post-silicon data to support judgments, necessitating significant investment in early-stage chip production. However, much of this test data is not always up-to-date, and current pre-silicon test procedures lack sufficient completeness and coverage. Therefore, how to reduce the resource investment in chip performance analysis during the early stages of chip manufacturing while ensuring timeliness has become a pressing challenge for those skilled in the art.

[0004] Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure provide a chip performance analysis method and apparatus, a storage medium, and a computer device to reduce the resource investment in chip performance analysis in the early stages of chip production while ensuring timeliness.

[0006] To achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] The present disclosure provides a chip performance analysis method, including:

[0008] Constructing a standard cell model for simulating the standard cell of the chip to be analyzed;

[0009] By simulating the standard cell model and simulating the adjustment of the product device target value, a first influencing parameter group of the influence of each type of transistor on the standard cell performance and power consumption under different product device target values ​​is obtained; based on the first influencing parameter group and the standard cell usage ratio, a second influencing parameter group of the influence of each type of transistor on the chip performance and power consumption under different product device target values ​​is obtained;

[0010] Based on the second influencing parameter group and the usage ratio of different types of transistors, a third influencing parameter group is obtained to determine the impact of different product device target values ​​on chip performance and power consumption; the third influencing parameter group is used to determine the impact of product device target values ​​on the chip performance and power consumption.

[0011] Optionally, the first influencing parameter group includes: a standard performance parameter value of the standard cell performance at a standard threshold voltage and a standard power consumption parameter value of the standard cell power consumption; and a general performance parameter value of the standard cell performance during threshold voltage variation and a general power consumption parameter value of the standard cell power consumption. Optionally, the standard cell performance includes: a standard cell frequency; and the standard cell power consumption includes: a standard cell static power consumption and a standard cell dynamic power consumption.

[0012] Optionally, the step of simulating the standard cell model and simulating the adjustment of the product device target value to obtain a first influencing parameter group of the impact of each type of transistor on the standard cell performance and power consumption under different product device target values ​​includes:

[0013] By detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage, the standard performance parameter value and the standard power consumption parameter value of the standard cell under the target value of the standard product device are simulated.

[0014] The threshold voltage of the transistor in the standard cell model is adjusted, and the general performance parameter value and the general power consumption parameter value of the standard cell under different threshold voltage changes are detected to obtain a first influencing parameter group.

[0015] Optionally, the standard cell usage ratio includes: a usage ratio of the standard cell in the chip or a usage ratio of the standard cell in a critical path of the chip.

[0016] Optionally, the usage ratio of transistors of different types includes: the usage ratio of transistors of different types to all transistors of the chip, or the usage ratio of transistors of different types to the critical path of the chip.

[0017] Optionally, the third influencing parameter group includes: a dynamic power consumption influencing parameter group;

[0018] The dynamic power consumption influencing parameter group includes: a standard value of the dynamic power consumption of the chip under a standard threshold voltage, and a general dynamic power consumption parameter group of the dynamic power consumption of the chip during a threshold voltage change;

[0019] The step of obtaining a third group of influencing parameters indicating the impact of different types of transistors on chip performance based on the second group of influencing parameters and the usage ratios of different types of transistors includes:

[0020] A dynamic power consumption influencing parameter group is obtained according to the second influencing parameter group, usage ratios of different types of transistors, and a static-dynamic power consumption ratio.

[0021] Optionally, the usage ratios of different types of transistors further include: a chip power consumption ratio group.

[0022] Optionally, the third influencing parameter group includes: a static power consumption influencing parameter group;

[0023] The static power consumption influencing parameter group includes: a standard value of the static power consumption of the chip under a standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during a threshold voltage change;

[0024] The step of obtaining a third group of influencing parameters indicating the impact of different types of transistors on chip performance based on the second group of influencing parameters and the usage ratios of different types of transistors includes:

[0025] A static power consumption influencing parameter group is obtained according to the second influencing parameter group and usage ratios of transistors of different types.

[0026] Optionally, the third influencing parameter group includes: a frequency influencing parameter group;

[0027] The frequency influencing parameter group includes: a frequency standard value of the chip under a standard threshold voltage, and a general frequency parameter group of a change in the frequency of the chip relative to the frequency standard value when the threshold voltage changes;

[0028] The step of obtaining a third group of influencing parameters indicating the impact of different types of transistors on chip performance based on the second group of influencing parameters and the usage ratios of different types of transistors includes:

[0029] A frequency influencing parameter group is obtained according to the second influencing parameter group and usage ratios of transistors of different types occupying the critical path of the chip.

[0030] Optionally, the method further includes drawing a two-dimensional contour map using the third influencing parameter group to demonstrate the influence of different types of transistors on the performance of the chip.

[0031] The present disclosure also provides a chip performance analysis device, including:

[0032] A model building module is configured to build a standard cell model for simulating a standard cell of a chip to be analyzed;

[0033] a first parameter group acquisition module configured to simulate the standard cell model and simulate the adjustment of the product device target value to obtain a first influencing parameter group of the influence of each type of transistor on the performance and power consumption of the standard cell under different product device target values;

[0034] A second parameter group acquisition module is configured to obtain a second influencing parameter group of the impact of each type of transistor on chip performance and power consumption under different product device target values ​​based on the first influencing parameter group and the standard cell usage ratio;

[0035] The third parameter group acquisition module is configured to obtain a third influencing parameter group of the impact of different product device target values ​​on chip performance and power consumption based on the second influencing parameter group and the usage ratio of different types of transistors; the third influencing parameter group is used to judge the impact of the product device target value on the chip performance and power consumption.

[0036] Optionally, the first influencing parameter group includes: standard performance parameter values ​​of the standard cell performance under standard threshold voltage and standard power consumption parameter values ​​of the standard cell power consumption; and general performance parameter values ​​of the standard cell performance and general power consumption parameter values ​​of the standard cell power consumption during threshold voltage changes.

[0037] Optionally, acquiring the first parameter group includes:

[0038] The standard parameter value acquisition module is configured to simulate the standard performance parameter value and standard power consumption parameter value of the standard unit under the target value of the standard product device by detecting the standard performance parameter value and standard power consumption parameter value of the standard unit under the standard threshold voltage.

[0039] The change parameter value acquisition module adjusts the threshold voltage of the transistor in the standard cell model, detects the general performance parameter value and the general power consumption parameter value of the standard cell under different threshold voltage changes, and obtains a first influencing parameter group.

[0040] Optionally, the usage ratio of transistors of different types includes: the usage ratio of transistors of different types to all transistors of the chip or the usage ratio of transistors of different types to the critical path of the chip.

[0041] Optionally, the third influencing parameter group includes: a dynamic power consumption influencing parameter group;

[0042] The dynamic power consumption influencing parameter group includes: a standard value of the dynamic power consumption of the chip under a standard threshold voltage, and a general dynamic power consumption parameter group of the dynamic power consumption of the chip during a threshold voltage change;

[0043] The third parameter group acquisition module includes a dynamic power consumption acquisition module, which is configured to acquire a dynamic power consumption impact parameter group according to the second impact parameter group, the usage ratio of different types of transistors, and the static-dynamic power consumption ratio.

[0044] Optionally, the third influencing parameter group includes: a static power consumption influencing parameter group;

[0045] The static power consumption influencing parameter group includes: a standard value of the static power consumption of the chip under a standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during a threshold voltage change;

[0046] The third parameter group acquisition module includes a static power consumption acquisition module configured to acquire a static power consumption influencing parameter group according to the second influencing parameter group and usage ratios of different types of transistors.

[0047] Optionally, the third influencing parameter group includes: a frequency influencing parameter group;

[0048] The frequency influencing parameter group includes: a standard frequency value of the chip under a standard threshold voltage, and a general frequency parameter group of the chip frequency when the threshold voltage changes;

[0049] The third parameter group acquisition module includes a frequency acquisition module, which acquires a frequency impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors in the critical path of the chip.

[0050] Optionally, the method further includes a drawing module configured to draw a two-dimensional contour map using the third influencing parameter group.

[0051] An embodiment of the present disclosure further provides a storage medium, which stores a chip design program, and when the design program is executed, the chip performance analysis method as described above is implemented.

[0052] An embodiment of the present disclosure further provides a computer device, comprising the chip performance analysis apparatus as described above.

[0053] The chip performance analysis method provided by the embodiment of the present disclosure first constructs a standard cell model for simulating the standard cell of the chip to be analyzed, and simulates the standard cell model to obtain a first influencing parameter group of the transistor's impact on the standard cell performance. In order to obtain the impact of the transistor on the chip performance, a second influencing parameter group is obtained based on the first influencing parameter group and the standard cell usage ratio. Finally, in order to obtain the impact of different types of transistors on the chip performance, a third influencing parameter group is obtained based on the second influencing parameter group and the usage ratio of different types of transistors to determine the impact of different types of transistors on the chip performance.

[0054] It can be seen that by simulating only standard cells with low resource consumption during simulation, the impact of transistors on chip performance and power consumption is obtained, and then the impact of different types of transistors on the chip performance and power consumption is obtained. In other words, the simulation of the complete chip with high resource consumption is avoided, and standard cells with low resource consumption are simulated. Then, the impact of different product device target values ​​on the chip performance and power consumption is calculated based on the usage ratio between transistors, standard cells and chips. This reduces the resource consumption during chip performance and power consumption analysis before obtaining chip samples, and reduces the test data during chip performance analysis. Therefore, while ensuring timeliness, the resource investment in chip performance analysis in the early stages of chip production and manufacturing is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are merely embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0056] FIG1 is a schematic diagram showing the distribution of target values ​​of product devices of a chip;

[0057] FIG2 is a schematic diagram of a process flow of a chip performance analysis method provided by an embodiment of the present disclosure;

[0058] FIG3 is another schematic diagram of a process flow of a chip performance analysis method according to an embodiment of the present disclosure;

[0059] FIG4a and FIG4b are schematic diagrams of two-dimensional contour maps drawn by the chip performance analysis method provided by an embodiment of the present disclosure;

[0060] FIG5 is a schematic diagram of a ratio acquisition method for chip performance analysis according to an embodiment of the present disclosure;

[0061] FIG6a, FIG6b, and FIG6c are schematic diagrams of drawing another set of two-dimensional contour maps using the chip performance analysis method provided by an embodiment of the present disclosure;

[0062] FIG7a, FIG7b, FIG7c, and FIG7d are schematic diagrams of coordinate graphs plotted using data from a chip performance analysis method according to an embodiment of the present disclosure;

[0063] FIG8 is a schematic diagram of power consumption analysis of a chip;

[0064] FIG9 is a schematic structural diagram of a chip performance analysis device provided by an embodiment of the present disclosure; and

[0065] FIG10 is another schematic diagram of the structure of the chip performance analysis device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0067] The product device target value (Device Target) is an important indicator for chip designers to communicate with wafer fabs for production. In actual production, the driving current value of chip transistors will show a normal distribution around the product device target value. Furthermore, the driving current of the chip transistor is related to the threshold voltage used by the transistor. The smaller the driving current of the transistor, the higher the threshold voltage of the transistor, and the larger the driving current of the transistor, the lower the threshold voltage of the transistor. It should be noted that the product in the product device target value refers to the chip, and the device refers to the transistor. As shown in Figure 1, Figure 1 shows a chip anchor point and distribution diagram. The horizontal axis in the figure is the driving current value of different NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) transistors, and the vertical axis is the driving current value of different PMOS (Positive channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor) transistors. The coordinate corresponding to each cross point in the figure is the driving current value of the transistor used by a different chip. The center point of the area with the densest cross points in the figure, that is, point TT, corresponds to the NMOS and PMOS drive current values, which are the product device target values ​​of the chip, while SF, FF, SS, and FS are the four process corners of the chip. The process corner is the range of transistor drive current values. In addition, the drive current value of the transistor will also affect the performance and power consumption of the transistor. Therefore, the product device target value affects the performance and power consumption of the transistor, where the performance of the transistor includes the frequency of the transistor. Furthermore, the chip is composed of transistors, so the performance and power consumption of the transistor will also affect the performance and power consumption of the chip. The product device target value also affects the performance and power consumption of the chip.

[0068] Because product device target values ​​affect the overall transistor design within a chip, determining these values ​​is crucial for actual production. One method for determining these values ​​uses device-level (or transistor-level) WAT (Wafer Acceptance Test) parameters as a benchmark. WAT is a test performed on specialized test patterns to obtain electrical parameters that characterize device performance. However, device-level WAT parameters make it difficult to intuitively predict the overall performance of a complete chip.

[0069] Furthermore, during the actual manufacturing process, market demands often shift, leading to different requirements for chip performance and power consumption, necessitating adjustments to product device target values. For example, high-performance computing chips are typically used under high temperature and high pressure. With the evolution of process nodes, static power consumption accounts for an increasing proportion, and power consumption requirements also increase accordingly. Therefore, it is even more important to determine product device target values ​​based on demand to meet stringent performance and power requirements.

[0070] A method for adjusting product device target values ​​primarily considers factors such as their impact on chip yield, performance, and power consumption. The impact of the target value on chip yield can be more intuitively determined using EDA (Electronic Design Automation) tools; however, the impact of the target value on chip performance and power consumption is less correlated with WAT parameters. Therefore, a method for adjusting product device target values ​​often relies on developer experience or intuition combined with correlation to test data to meet product requirements.

[0071] Because the aforementioned method for adjusting target device values ​​involves a high degree of subjective judgment and personal factors, it lacks objectivity and professionalism. Therefore, another method for adjusting target device values ​​involves testing actual chip samples after production, and adjusting the target device values ​​based on the test data.

[0072] According to the aforementioned method for adjusting target device values, chip samples are tested after production. Because adjusting target device values ​​requires extensive test data to support judgment, significant resources must be invested in the early stages of chip production. Furthermore, during these early stages, the completeness and coverage of the test procedures for chip samples may not be high enough, requiring time for program completion, resulting in poor testing timeliness.

[0073] Based on this, the embodiments of the present disclosure consider simulating the chip model in the design and introducing the basic concept of process evaluation PPA (power, performance, area) into the adjustment process of the product device target value, so as to quantitatively reflect the impact of the adjustment of the product device target value on the overall performance and power consumption of the chip, so as to adjust the product device target value according to the quantitative data, and thus reduce the resource investment in the adjustment process of the product device target value in the early stage of chip production and manufacturing while ensuring timeliness.

[0074] Based on the above ideas, the embodiment of the present disclosure provides a chip performance and power consumption analysis method. As an optional implementation, FIG2 shows a flow chart of the chip performance and power consumption analysis method provided by the embodiment of the present disclosure. As shown in FIG2, the chip performance and power consumption analysis method provided by the embodiment of the present disclosure includes:

[0075] Step S1: Constructing a standard cell model for simulating the standard cell of the chip to be analyzed.

[0076] It should be noted that if the circuit level simulation of the complete chip is directly performed to obtain the accurate performance and power consumption of the complete chip, this method is difficult to implement because the circuit of the complete chip is too complex and the simulation scale is too large. A complete chip is composed of a plurality of standard cells. In an optional implementation, the standard cells include NOT gates, AND gates, NAND gates and NOR gates. The performance and power consumption of each of the above standard cells are fixed parameters. The accurate performance and power consumption of the standard cells can be obtained by performing circuit level simulation on the standard cells, and the performance and power consumption of the complete chip can be calculated based on the performance and power consumption of the standard cells. After that, by performing data processing on the performance and power consumption of the complete chip, the parameters of the influence of different types of transistors on the various performance and power consumption of the chip after the target value of the product device is adjusted can be obtained.

[0077] In this way, by simulating standard cells, the amount of data required for testing can be reduced, thereby improving the timeliness of chip performance analysis and power consumption analysis.

[0078] Step S2: By simulating the standard cell model and simulating the adjustment of the product device target value, a first influencing parameter group of each type of transistor on the performance and power consumption of the standard cell under different product device target values ​​is obtained. It should be noted that the standard cell is composed of devices, that is, different transistors. The characteristics of the transistor are affected by its threshold voltage. By adjusting the threshold voltage of the transistor in the standard cell model, the performance parameter value of the standard cell after the adjustment of the product device target value and the power consumption parameter value of the standard cell can be simulated. Therefore, in an optional real-time method, the step of simulating the standard cell model to obtain the first influencing parameter group of the transistor on the performance and power consumption of the standard cell is shown in Figure 3, including:

[0079] Step S21: By detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage, the standard performance parameter value and the standard power consumption parameter value of the standard cell under the target value of the standard product device are simulated. Step S22: Adjust the threshold voltage of the transistor in the standard cell model, detect the general performance parameter value and the general power consumption parameter value of the standard cell under the threshold voltage change of different amplitudes, and obtain the first influencing parameter group. It should be noted that a standard cell includes a variety of different transistors. Therefore, in the process of adjusting the threshold voltage of the transistor in the standard cell model, it is necessary to adjust the threshold voltage of each transistor separately, and further obtain the performance and power consumption of the standard cell under different threshold voltage combinations of various transistors, thereby obtaining the first influencing parameter group reflecting the performance and power consumption of the standard cell under different transistor states.

[0080] Specifically, in an optional implementation, the method for implementing the above steps S21 and S22 is ergodic simulation. For example, ergodic simulation is performed by performing combined simulations on NMOS transistors under 10 different threshold voltage conditions and PMOS transistors under 10 different threshold voltage conditions, obtaining simulation results for a total of 100 combinations of conditions for the two transistors. This can simulate the changes in standard cell performance and power consumption under different product device target values ​​after the product device target value is adjusted.

[0081] Furthermore, it can be seen from the above steps S21 and S22 that in an optional implementation, the first influencing parameter group includes: standard performance parameter values ​​of standard cell performance under standard threshold voltage and standard power consumption parameter values ​​of standard cell power consumption; and general performance parameter values ​​of standard cell performance during threshold voltage changes and general power consumption parameter values ​​of standard cell power consumption.

[0082] Furthermore, in order to introduce the PPA concept into the adjustment of the target value of product devices, since the area of ​​the chip is determined, it is necessary to obtain parameters that can characterize the performance and power consumption of the chip, where the performance of the chip can be determined by the frequency of the transistor or standard cell. Therefore, in an optional implementation, the standard cell performance includes: the standard cell frequency and; the standard cell power consumption includes: the standard cell static power consumption and the standard cell dynamic power consumption.

[0083] Please refer to Figure 4a and Figure 4b. Figure 4a is a frequency and threshold voltage change relationship diagram obtained by the chip performance and power consumption detection method provided by the present disclosure. As shown in Figure 4a, the product device target value is obtained by adjusting the threshold voltage of the transistor in the standard cell model, detecting the change parameter value of the standard cell performance and power consumption relative to the standard parameter value under different threshold voltage changes, and obtaining the first influencing parameter group. The (0,0) point in the figure is the standard parameter value of the standard cell frequency. At this time, the threshold voltage does not change, so the threshold voltage change value is 0. Taking (-20,40) in the figure as an example, it is the general frequency parameter value of the standard cell when the NMOS transistor threshold voltage is reduced by 20mv relative to the standard threshold voltage and the PMOS transistor threshold voltage is increased by 40mv relative to the standard threshold voltage. Figure 4b is a static power consumption and threshold voltage change relationship diagram obtained by the chip performance and power consumption detection method provided by the present disclosure. As shown in Figure 4b, the product device target value is obtained by adjusting the threshold voltage of the transistor in the standard cell model, detecting the change parameter value of the standard cell performance and power consumption relative to the standard parameter value under different threshold voltage changes, and obtaining the first influencing parameter group. The (0,0) point in the figure represents the standard static power consumption parameter value for a standard cell. At this point, the threshold voltage remains unchanged, so the threshold voltage change value is 0. For example, the (-20,40) point in the figure represents the typical static power consumption parameter value for a standard cell when the NMOS transistor threshold voltage is reduced by 20mV relative to the standard threshold voltage, and the PMOS transistor threshold voltage is increased by 40mV relative to the standard threshold voltage.

[0084] Please continue to refer to Figure 2, which also includes step S3: based on the first influencing parameter group and the standard cell usage ratio, obtain the second influencing parameter group of the impact of each type of transistor on chip performance and power consumption under different product device target values. Furthermore, in an optional implementation, the standard cell usage ratio includes: the usage ratio of the standard cell in the chip or the usage ratio in the critical path of the chip. It should be noted that after the chip is powered on, all standard cells in the chip are in operation and have power consumption, so the power consumption of the chip can be obtained by calculating the usage ratio of the standard cell in the chip and the power consumption of each standard cell. In the chip, the frequency of the chip is related to the frequency of the critical path that realizes different functions of the chip. Therefore, the frequency of the chip can be obtained by calculating the usage ratio of the standard cell in the critical path of the chip and the frequency of the standard cell.

[0085] Furthermore, the standard cell usage ratio is calculated by counting all types of standard cells used within the chip, obtaining the number of standard cells of each type, and dividing the result by the total number of standard cells. Therefore, the sum of the number of all standard cells of each type is equal to the total number of standard cells, and the sum of the utilization ratios of all different types of standard cells in all transistors on the chip is 100%. For example, a chip includes 20 NOT gates, 50 OR AND gates, 45 NAND gates, and 25 NOR gates, totaling 140. It can be calculated that the NOT gates account for 14.3%, the OR AND gates account for 35.7%, the NAND gates account for 32.1%, and the NOR gates account for 17.9%, for a total of 100%. Furthermore, since the first influencing parameter group includes standard performance parameter values ​​for standard cell performance at a standard threshold voltage and standard power consumption parameter values ​​for standard cell power consumption; as well as general performance parameter values ​​for standard cell performance during threshold voltage variations and general power consumption parameter values ​​for standard cell power consumption. Furthermore, standard cell performance includes standard cell frequency; and standard cell power consumption includes: standard cell static power consumption and standard cell dynamic power consumption. Therefore, in an optional implementation, the second influencing parameter group includes standard chip performance parameter values ​​of chip performance under standard threshold voltage and standard chip power consumption parameter values ​​of chip; as well as general chip performance parameter values ​​of chip performance and general chip power consumption parameter values ​​of chip power consumption during threshold voltage changes; chip performance includes chip frequency of the chip; chip power consumption includes: chip static power consumption and chip dynamic power consumption.

[0086] It should be noted that by weighting and multiplying the first influencing parameter values ​​of different standard cells at each threshold voltage change value according to the standard cell usage ratio, a second influencing parameter set of the transistor's impact on chip performance and power consumption can be obtained. For example, at the standard threshold voltage, the first influencing parameter value of the first standard cell * 45% + the first influencing parameter value of the second standard cell * 30% + the first influencing parameter value of the third standard cell * 15% + the first influencing parameter value of the fourth standard cell * 10% = the second influencing parameter set at the standard threshold voltage.

[0087] Step S4: Based on the second influencing parameter group and the usage ratios of different types of transistors, a third influencing parameter group is obtained to determine the impact of different product device target values ​​on chip performance and power consumption. The third influencing parameter group is used to determine the impact of product device target values ​​on chip performance and power consumption.

[0088] It should be noted that by weighting and multiplying the second influencing parameter value at each threshold voltage change value according to the usage ratio of different types of transistors, a third influencing parameter group that reflects the impact of transistors on chip performance and power consumption can be obtained. For example, at a standard threshold voltage, the second influencing parameter value of the first transistor * 45% + the second influencing parameter value of the second transistor * 30% + the second influencing parameter value of the third transistor * 15% + the second influencing parameter value of the fourth transistor * 10% = the third influencing parameter group at the standard threshold voltage.

[0089] Furthermore, as shown in FIG5 , within the solid-line box in the center of FIG5 , by adjusting the threshold voltage of the transistor, the effect of the transistor on the performance and power consumption of the standard cell can be obtained, that is, the effect of the transistor on the NOT gate, NAND gate, OR AND gate, and NOR gate within the chip. Then, as shown in the five dashed boxes in FIG5 , a two-level weight multiplication is performed, combining the effect of the transistor on the performance and power consumption of the standard cell, the standard cell usage ratio, the usage ratio of different types of transistors to all transistors on the chip, and the usage ratio of different types of transistors to the chip's critical paths, to determine the effect of different product device target values ​​on chip performance and power consumption. Determining the effect of the transistor on chip performance and power consumption based on the transistor's effect on standard cell performance and power consumption and the standard cell usage ratio is the first-level weight algorithm. Determining the static power consumption impact parameter group and the dynamic power consumption impact parameter group based on the transistor's effect on chip performance and power consumption and the usage ratio of different types of transistors to all transistors on the chip is the second-level weight multiplication. It should be noted that the usage ratio of standard cells in the chip, the usage ratio of standard cells in the critical path of the chip, the usage ratio of different types of transistors to all transistors in the chip, and the usage ratio of different types of transistors to the critical path of the chip are parameters that can be determined when the chip is designed to obtain a complete chip circuit. It should be noted that there are different requirements for the speed of NMOS transistors and PMOS transistors at different positions in the chip. In order to make the operating speeds of NMOS transistors and PMOS transistors different at the same threshold voltage, a variety of different NMOS transistors and a variety of different PMOS transistors are provided in the chip. The second influencing parameter group is the impact of transistors on chip performance and power consumption when all transistors are regarded as a whole. In order to further reflect the impact of different types of transistors on the chip when the target value of the product device is adjusted, it is necessary to combine the second influencing parameter group with the usage ratio of different types of transistors, so as to obtain the third influencing parameter group to obtain the impact of each type of transistor on chip performance and power consumption at different threshold voltages.

[0090] Furthermore, since the chip's frequency is related to the frequencies of the critical paths that implement its various functions, the chip's frequency can be calculated by combining the usage ratio of standard cells within the chip's critical paths and the frequencies of the standard cells. In one optional implementation, the usage ratio of transistors of different performance levels includes the usage ratio of different transistor types relative to all transistors on the chip, or the usage ratio of different transistor types relative to the chip's critical paths.

[0091] Furthermore, the method for obtaining the usage ratio of standard cells in the chip and the usage ratio in the critical path of the chip is shown in Figure 5. The usage ratio of different types of transistors to all transistors in the chip is obtained by counting all types of transistors used in the chip, obtaining the number of transistors of each type, and dividing it by the total number of transistors. Therefore, the sum of the number of all types of transistors is equal to the total number of transistors, and the sum of the usage ratios of all different types of transistors to all transistors in the chip is 100%. As shown in Figure 5, for example, the transistor types in the chip include 168,206,099 nrvt_ckt (standard threshold voltage NMOS) transistors, 305,385,094 nlvt_ckt (low threshold voltage NMOS) transistors, 176,619,982 nhvt_ckt (high threshold voltage NMOS) transistors, 191,776,668 prvt_ckt (standard threshold voltage NMOS) transistors, and 3 plvt_ckt (low threshold voltage NMOS) transistors. There are 251695945 05845324 and phvt_ckt (standard threshold voltage NMOS) transistors in total, and the total number of all transistors is 1399529112. Therefore, by dividing the number of different types of transistors by the total number of all transistors, we can get rvt_ckt (normal voltage device circuit) transistors account for 25.7%, hvt_ckt (high voltage device circuit) transistors account for 30.6%, and lvt_ckt (low voltage device circuit) transistors account for 43.7%, totaling 100%. Further, the usage ratio of different types of transistors in the chip's critical path and the standard unit usage ratio are obtained using the same method and technology. As shown in Figure 5, the usage ratio of different types of transistors in the chip's critical path is the usage ratio of rvt_ckt, hvt_ckt, and lvt_ckt transistors.

[0092] It should be noted that in the analysis of chip performance and power consumption, commonly used analysis indicators are the chip's static power consumption, the chip's dynamic power consumption and the chip's frequency. Therefore, the third influencing parameter group includes parameter values ​​related to the above three analysis indicators.

[0093] Furthermore, in an optional implementation, the third influencing parameter group includes a dynamic power influencing parameter group; the dynamic power influencing parameter group includes a standard value of dynamic power consumption of a chip at a standard threshold voltage and a general dynamic power consumption parameter group for dynamic power consumption of a chip during a threshold voltage change. As shown in FIG3 , step S4 includes step S41 : obtaining the dynamic power influencing parameter group based on the second influencing parameter group and the utilization ratio of different transistor types.

[0094] It should be noted that, in one optional implementation, the ratio of different transistor types further includes a chip power consumption ratio group. Specifically, in one optional implementation, the chip power consumption ratio group includes the ratio of the chip's dynamic power consumption to its static power consumption and the ratio of the chip's internal power consumption to its net power consumption. For example, if the ratio of dynamic power consumption to static power consumption is 3:1, the ratio of the chip's internal power consumption to its net power consumption is 3:2.

[0095] It should be noted that by weighting and multiplying the second influencing parameter value at each threshold voltage change value according to the usage ratio of different types of transistors, a third influencing parameter group of the transistor's impact on chip performance and power consumption can be obtained. For example, under the standard threshold voltage, (static power consumption impact parameter of the first transistor * 45% + static power consumption impact parameter value of the second transistor * 30% + static power consumption impact parameter value of the third transistor * 15% + static power consumption impact parameter value of the fourth transistor * 10%) * 3 / 2 * 3 = dynamic power consumption impact parameter group under the standard threshold voltage. The result is shown in Figure 6a.

[0096] Furthermore, in an optional implementation, the third influencing parameter group includes: a static power consumption influencing parameter group; the static power consumption influencing parameter group includes: a standard value of static power consumption of the chip under a standard threshold voltage, and a general static power consumption parameter group of the static power consumption of the chip during threshold voltage variation. As shown in FIG3 , step S4 includes step S42: obtaining a static power consumption influencing parameter group based on the second influencing parameter group and the usage ratio of different types of transistors. It should be noted that by weighting the second influencing parameter value under each threshold voltage variation value according to the usage ratio of different types of transistors, a third influencing parameter group of the impact of transistors on chip performance and power consumption can be obtained. For example, under the standard threshold voltage, the static power consumption influencing parameter of the first transistor * 45% + the static power consumption influencing parameter value of the second transistor * 30% + the static power consumption influencing parameter value of the third transistor * 15% + the static power consumption influencing parameter value of the fourth transistor * 10% = the static power consumption influencing parameter group under the standard threshold voltage. The result is shown in FIG6 b.

[0097] Furthermore, in an optional implementation, the third influencing parameter group includes a frequency influencing parameter group; the frequency influencing parameter group includes a standard value of the chip's frequency at a standard threshold voltage and a general frequency parameter group for the chip's frequency during threshold voltage variations. As shown in FIG3 , step S4 includes step S43 : obtaining the frequency influencing parameter group based on the second influencing parameter group and the usage ratio of different transistor types in the chip's critical path.

[0098] It should be noted that by weighting the second impact parameter value at each threshold voltage change value according to the usage ratio of different types of transistors, a third impact parameter group that reflects the impact of transistors on chip performance and power consumption can be obtained. For example, at a standard threshold voltage, the frequency impact parameter value of the first transistor * 45% + the frequency impact parameter value of the second transistor * 30% + the frequency impact parameter value of the third transistor * 15% + the frequency impact parameter value of the fourth transistor * 10% = the frequency impact parameter group at the standard threshold voltage. The result is shown in Figure 6c.

[0099] In this way, the chip performance and power consumption analysis method provided by the embodiment of the present disclosure simulates only the standard cells with low resource consumption during simulation, then obtains the impact of transistors on chip performance and power consumption, and then obtains the impact of different types of transistors on chip performance and power consumption. In other words, it avoids simulating the complete chip with high resource consumption, and simulates the standard cells with low resource consumption. And through the usage ratio between transistors, standard cells and chips, it calculates the impact of different product device target values ​​on chip performance and power consumption, so as to reduce the resource consumption during chip performance analysis before obtaining chip samples, and reduce the test data during chip performance and power consumption analysis, thereby reducing the resource investment in chip performance analysis in the early stage of chip production and manufacturing while ensuring timeliness.

[0100] Furthermore, as shown in FIG3 , in an optional implementation, the chip performance and power consumption analysis method provided by the present disclosure further includes step S5: using the third influencing parameter group to draw a two-dimensional contour map to demonstrate the impact of different types of transistors on chip performance and power consumption. Since the calculated third influencing parameter group is a set of data, it is not possible to directly determine the impact of different types of transistors on chip performance and power consumption based on the parameter values ​​therein. Instead, determination must be made based on the changing relationship between the parameter values. Using the third influencing parameter group to draw a two-dimensional contour map can improve the readability of the third influencing parameter group and facilitate determination using the third influencing parameter group.

[0101] In one optional implementation, the above parameter values ​​can be directly obtained using an EDA tool. In another optional implementation, the ratio of a chip's dynamic power consumption to static power consumption and the ratio of a chip's net power consumption to device power consumption are obtained by simulating other chips using the EDA tool. It should be noted that for chips of similar designs, their dynamic power consumption to static power consumption ratios and net power consumption to device power consumption ratios are similar, so the calculations can be performed using simulation results from other chips.

[0102] Specifically, the two-dimensional contour map obtained by the chip performance and power consumption analysis method provided by the embodiment of the present disclosure includes a dynamic power consumption and transistor threshold voltage change relationship diagram as shown in Figure 6a, a static power consumption and transistor threshold voltage change relationship diagram as shown in Figure 6b, and a frequency and transistor threshold voltage change relationship diagram as shown in Figure 6c. Among them, the data with coordinates (0, 0) in each figure is the parameter value under the standard threshold voltage; the parameter value under the standard threshold voltage in the dynamic power consumption diagram in Figure 5 is 3.00 at point (0, 0); the parameter value under the standard threshold voltage in the static power consumption diagram is 1.00 at point (0, 0); and the parameter value under the standard threshold voltage in the frequency diagram is 1.00 at point (0, 0). Through the data in the three figures under the same coordinates, it is possible to judge the impact of different types of transistors on chip performance and power consumption under different product device target values, and then determine the product device target value based on this. Taking point (-0.04, -0.02) in Figure 4 as an example, the value of point (-0.04, -0.02) in the dynamic power graph is 3.27, the value of point (-0.04, -0.02) in the static power graph is 2.01, and the value of point (-0.04, -0.02) in the frequency graph is 1.06. The difference between point (-0.04, -0.02) and point (0, 0) in the dynamic power graph is 0.27, the difference between point (-0.04, -0.02) and point (0, 0) in the static power graph is 1.01, and the difference between point (-0.04, -0.02) and point (0, 0) in the frequency graph is 0.06. These differences represent the impact of changes in transistor threshold voltage on the chip's dynamic power consumption, static power consumption, and frequency, respectively. When determining the target values ​​of product devices, for example, the values ​​at (-0.04, -0.02) in each figure are more in line with our expectations, so we choose to use the performance and power consumption of the transistor when the threshold voltage change value is (-0.04, -0.02) as the target values ​​of the product device.

[0103] Specifically, to demonstrate the accuracy of the chip performance and power consumption analysis method provided by the embodiments of the present disclosure, taking the static power consumption and threshold voltage change relationship diagrams and the frequency and threshold voltage change relationship diagrams shown in Figures 4a and 4b as examples, first, according to the parameters in the figures, frequency and threshold voltage change value relationship diagrams and static power consumption and threshold voltage change value relationship diagrams of different types of transistors as shown in Figures 7a, 7b, 7c, and 7d are drawn. Among them, Figure 7a is a frequency and threshold voltage change value relationship diagram of different types of NMOS transistors, Figure 7c is a static power consumption and threshold voltage change value relationship diagram of different types of NMOS transistors, Figure 7b is a frequency and threshold voltage change value relationship diagram of different types of PMOS transistors, and Figure 7d is a static power consumption and threshold voltage change value relationship diagram of different types of PMOS transistors. Taking the two static power consumption and threshold voltage change value relationship diagrams in Figures 7c and 7d as examples, when the threshold voltage change value is -0.04, it can be seen that when the speed of the PMOS transistor is faster, the device static power consumption is higher, while the speed of the NMOS transistor has little effect on the static power consumption. It can be judged that when the speed of the PMOS transistor is faster and the speed of the NMOS transistor is slower, the static power consumption value of the chip is significantly higher. Furthermore, Figure 8 shows the data results obtained using sample tests on chips of the same design, where the circle is the leakage data of the SF process corner. It can be seen that the static power consumption of the SF process corner is significantly higher than the values ​​of other test points, that is, when the speed of the PMOS transistor is faster and the speed of the NMOS transistor is slower, the static power consumption value of the chip is significantly higher, which is consistent with the analysis expectations of Figure 7. Therefore, the results of Figures 7 and 8 are consistent, indicating that the chip performance and power consumption analysis method provided by the present disclosure can accurately obtain the impact of different product device target values ​​on chip performance and power consumption.

[0104] The present disclosure also provides a chip performance analysis device, as shown in FIG9 . FIG9 is a schematic structural diagram of the chip performance analysis device provided by the present disclosure, including:

[0105] The model building module 100 is configured to build a standard cell model for simulating a standard cell of a chip to be analyzed;

[0106] The first parameter group acquisition module 200 is configured to simulate the standard cell model and simulate the adjustment of the product device target value to obtain a first influencing parameter group of the influence of each type of transistor on the performance and power consumption of the standard cell under different product device target values;

[0107] The second parameter group acquisition module 300 is configured to obtain a second influencing parameter group of the impact of each type of transistor on chip performance and power consumption under different product device target values ​​based on the first influencing parameter group and the standard cell usage ratio;

[0108] The third parameter group acquisition module 400 is configured to obtain a third influencing parameter group affecting chip performance and power consumption under different product device target values ​​based on the second influencing parameter group and usage ratios of different types of transistors.

[0109] Furthermore, in an optional implementation, the first influencing parameter group includes: standard performance parameter values ​​of standard cell performance under standard threshold voltage and standard power consumption parameter values ​​of standard cell power consumption; and general performance parameter values ​​of standard cell performance and general power consumption parameter values ​​of standard cell power consumption during threshold voltage changes.

[0110] Furthermore, as shown in FIG10 , in an optional implementation, the first parameter group acquisition module 200 includes: a standard parameter value acquisition module 210 configured to simulate the general performance parameter values ​​and general power consumption parameter values ​​of the standard cell at target values ​​of a standard product device by detecting the general performance parameter values ​​and general power consumption parameter values ​​of the standard cell at a standard threshold voltage; and a variable parameter value acquisition module configured to adjust the voltage of the transistor within the standard cell model and detect the general performance parameter values ​​and general power consumption parameter values ​​of the standard cell at threshold voltage variations of different magnitudes to obtain a first impact parameter group.

[0111] Furthermore, in an optional implementation, the usage ratio of different types of transistors includes: the usage ratio of different types of transistors to all transistors on the chip or the usage ratio of different types of transistors to the critical path of the chip.

[0112] Furthermore, as shown in FIG10 , in an optional implementation, the third influencing parameter group includes a dynamic power consumption influencing parameter group, which includes a standard value of dynamic power consumption of a chip at a standard threshold voltage and a general dynamic power consumption parameter group for dynamic power consumption of a chip during a threshold voltage change. The third parameter group acquisition module 400 includes a dynamic power consumption acquisition module 410 configured to acquire the dynamic power consumption influencing parameter group based on the second influencing parameter group, the utilization ratio of different types of transistors, and the static-dynamic power consumption ratio.

[0113] Furthermore, as shown in FIG10 , in an optional implementation, the third influencing parameter group includes a static power consumption influencing parameter group; the static power consumption influencing parameter group includes a standard value of static power consumption of a chip at a standard threshold voltage and a general static power consumption parameter group for static power consumption of a chip during a threshold voltage change. The third parameter group acquisition module 400 includes a static power consumption acquisition module 420 configured to acquire the static power consumption influencing parameter group based on the second influencing parameter group and the usage ratio of different types of transistors.

[0114] Furthermore, as shown in FIG10 , in an optional implementation, the third influencing parameter group includes a frequency influencing parameter group, which includes a standard frequency value for the chip at a standard threshold voltage and a general frequency parameter group for the chip frequency during threshold voltage variations. The third parameter group acquisition module 400 includes a frequency acquisition module 430 configured to acquire the frequency influencing parameter group based on the second influencing parameter group and the usage ratios of different transistor types in the chip's critical paths.

[0115] Furthermore, as shown in FIG10 , in an optional implementation, the chip performance analysis apparatus provided by the embodiment of the present disclosure further includes a drawing module 500 configured to draw a two-dimensional contour map using the third influencing parameter group.

[0116] It can be seen that by simulating only standard cells with low resource consumption during simulation, the impact of transistors on chip performance and power consumption is obtained, and then the impact of different types of transistors on chip performance and power consumption is obtained. In other words, the simulation of complete chips with high resource consumption is avoided, and standard cells with low resource consumption are simulated. Then, through the usage ratio between transistors, standard cells and chips, the impact of target values ​​of different product devices on chip performance and power consumption is calculated, so as to reduce resource consumption during chip performance and power consumption analysis before obtaining chip samples, and reduce test data during chip performance analysis, thereby reducing the resource investment in chip performance analysis in the early stages of chip production while ensuring timeliness.

[0117] The embodiment of the present disclosure further provides a storage medium, which stores a design program of a chip, and when the design program is executed, the chip performance analysis method as described above is implemented.

[0118] An embodiment of the present disclosure further provides a computer device, comprising the above chip performance analysis device.

[0119] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A method for analyzing chip performance and power consumption, comprising: Constructing a standard cell model for simulating the standard cells of the chip to be analyzed; Through simulating the standard cell model and simulating the adjustment of the target values of product devices, obtaining a first set of influence parameters of various types of transistors on the performance and power consumption of the standard cell under different target values of product devices; According to the first set of influence parameters and the standard cell usage ratio, obtaining a second set of influence parameters of various types of transistors on the performance and power consumption of the chip under different target values of product devices; According to the second set of influence parameters and the usage ratios of different types of transistors, obtaining a third set of influence parameters of different target values of product devices on the performance and power consumption of the chip; the third set of influence parameters is used to judge the influence of the target values of product devices on the performance and power consumption of the chip.

2. The chip performance and power consumption analysis method according to claim 1, wherein, The first set of influence parameters includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and, the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the change of the threshold voltage.

3. The chip performance and power consumption analysis method according to claim 2, wherein, The standard cell performance includes: the standard cell frequency; the standard cell power consumption includes: the standard cell static power consumption and the standard cell dynamic power consumption.

4. The method for analyzing chip performance and power consumption according to claim 3, wherein, The step of obtaining a first set of influence parameters of various types of transistors on the performance and power consumption of the standard cell under different target values of product devices by simulating the standard cell model and simulating the adjustment of the target values of product devices includes: By detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage, simulating the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard target value of the product device; Adjusting the threshold voltage of the transistors in the standard cell model, and detecting the general performance parameter value and the general power consumption parameter value of the standard cell under different amplitudes of threshold voltage change to obtain the first set of influence parameters.

5. The chip performance and power consumption analysis method according to claim 4, wherein, The standard cell usage ratio includes: the usage ratio of the standard cell in the chip or the usage ratio of the standard cell in the critical path of the chip.

6. The method for analyzing chip performance and power consumption according to claim 5, wherein, The usage ratios of different types of transistors include: the usage ratio of different types of transistors in all transistors of the chip, or the usage ratio of different types of transistors in the critical path of the chip.

7. The chip performance and power consumption analysis method according to claim 6, wherein, The third set of influence parameters includes: a dynamic power consumption influence parameter set; The dynamic power consumption influence parameter set includes: the standard value of the dynamic power consumption of the chip under the standard threshold voltage, and the general dynamic power consumption parameter set of the dynamic power consumption of the chip during the change of the threshold voltage; The step of obtaining a third set of influence parameters of different types of transistors on the chip performance according to the second set of influence parameters and the usage ratios of different types of transistors includes: Obtaining a dynamic power consumption influence parameter set according to the second set of influence parameters and the usage ratios of different types of transistors.

8. The chip performance and power consumption analysis method according to claim 7, wherein, The usage ratios of different types of transistors also include: a chip power consumption ratio set.

9. The method for analyzing chip performance and power consumption according to claim 6, wherein, The third set of influence parameters includes: a static power consumption influence parameter set; The static power consumption impact parameter group includes: the standard value of the static power consumption of the chip under the standard threshold voltage, and the general static power consumption parameter group of the static power consumption of the chip during the change of the threshold voltage; The step of obtaining a third impact parameter group of the impact of different types of transistors on the chip performance according to the second impact parameter group and the usage ratio of different types of transistors includes: Obtaining the static power consumption impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors.

10. The chip performance and power consumption analysis method according to claim 6, wherein, The third impact parameter group includes: a frequency impact parameter group; The frequency impact parameter group includes: the standard frequency value of the chip under the standard threshold voltage, and the general frequency parameter group of the frequency of the chip during the change of the threshold voltage; The step of obtaining a third impact parameter group of the impact of different types of transistors on the chip performance according to the second impact parameter group and the usage ratio of different types of transistors includes: Obtaining the frequency impact parameter group according to the second impact parameter group and the usage ratio of different types of transistors in the critical path of the chip.

11. The method for analyzing chip performance and power consumption according to claim 8, wherein, The chip power consumption ratio group includes: the ratio of the dynamic power consumption to the static power consumption of the chip, and the ratio of the internal power consumption of the chip components to the effective power consumption of the chip.

12. The chip performance and power consumption analysis method according to claim 1 further includes: Using the third impact parameter group to draw a two-dimensional contour map to show the impact of different types of transistors on the chip performance.

13. A chip performance and power consumption analysis device, comprising: A model construction module configured to construct a standard cell model for simulating the standard cells of the chip to be analyzed; A first parameter group acquisition module configured to obtain a first impact parameter group of the impact of each type of transistor on the performance and power consumption of the standard cell under different product device target values by simulating the standard cell model and simulating the adjustment of the product device target value; A second parameter group acquisition module configured to obtain a second impact parameter group of the impact of each type of transistor on the chip performance and power consumption under different product device target values according to the first impact parameter group and the standard cell usage ratio; And A third parameter group acquisition module configured to obtain a third impact parameter group of the impact of different product device target values on the chip performance and power consumption according to the second impact parameter group and the usage ratio of different types of transistors; the third impact parameter group is used to judge the impact of the product device target value on the chip performance and power consumption.

14. The chip performance and power consumption analysis device according to claim 13, wherein, The first impact parameter group includes: the standard performance parameter value of the standard cell performance and the standard power consumption parameter value of the standard cell power consumption under the standard threshold voltage; and, the general performance parameter value of the standard cell performance and the general power consumption parameter value of the standard cell power consumption during the change of the threshold voltage.

15. The chip performance and power consumption analysis device according to claim 13, wherein, The first parameter group acquisition module includes: A standard parameter value acquisition module configured to simulate the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard product device target value by detecting the standard performance parameter value and the standard power consumption parameter value of the standard cell under the standard threshold voltage; and A variable parameter value acquisition module, configured to adjust the threshold voltage of transistors in the standard cell model, detect the general performance parameter values and general power consumption parameter values of the standard cell under different magnitudes of threshold voltage changes, and obtain a first influence parameter group.

16. The chip performance and power consumption analysis device according to claim 13, wherein, The usage ratios of different types of transistors include: the usage ratio of different types of transistors in all transistors of the chip or the usage ratio of different types of transistors in the critical path of the chip.

17. The chip performance and power consumption analysis device according to claim 16, wherein, The third influence parameter group includes: a dynamic power consumption influence parameter group; The dynamic power consumption influence parameter group includes: the standard dynamic power consumption value of the chip under the standard threshold voltage, and the general dynamic power consumption parameter group of the dynamic power consumption of the chip during the threshold voltage change; The third parameter group acquisition module includes: a dynamic power consumption acquisition module, configured to obtain a dynamic power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors.

18. The chip performance and power consumption analysis device according to claim 16, wherein, The third influence parameter group includes: a static power consumption influence parameter group; The static power consumption influence parameter group includes: the standard static power consumption value of the chip under the standard threshold voltage, and the general static power consumption parameter group of the static power consumption of the chip during the threshold voltage change; The third parameter group acquisition module includes: a static power consumption acquisition module, configured to obtain a static power consumption influence parameter group according to the second influence parameter group and the usage ratios of different types of transistors.

19. The chip performance and power consumption analysis device according to claim 16, wherein, The third influence parameter group includes: a frequency influence parameter group; The frequency influence parameter group includes: the standard frequency value of the chip under the standard threshold voltage, and the general frequency parameter group of the frequency of the chip during the threshold voltage change; The third parameter group acquisition module includes: a frequency acquisition module, configured to obtain a frequency influence parameter group according to the second influence parameter group and the usage ratio of different types of transistors in the critical path of the chip.

20. The chip performance and power consumption analysis device according to claim 13 further includes: A plotting module, configured to plot a two-dimensional contour map using the third influence parameter group.

21. A storage medium, wherein, The storage medium stores a design program of the chip, and when the design program is executed, it implements the chip performance and power consumption analysis method according to any one of claims 1-12.

22. A computer device, including the chip performance and power consumption analysis device according to any one of claims 13-20.

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