Symmetry adjustment module and symmetry adjustment method

Abstract

The present invention relates to a symmetry adjustment module, which is used for adjusting the symmetry between a first output driver stage and a second output driver stage. The symmetry adjustment module comprises: a sampling circuit, which is coupled to the first output driver stage and the second output driver stage and is configured to output a sampling voltage related to a first equivalent impedance of the first output driver stage and a second equivalent impedance of the second output driver stage; reference-voltage generation circuits, which are configured to generate reference voltages; and a comparison circuit, which is coupled to the sampling circuit and the reference-voltage generation circuits and is configured to compare the sampling voltage with the reference voltages, so as to output control signals. The symmetry adjustment module generates an adjustment signal on the basis of the control signals, wherein the adjustment signal is used for adjusting the first equivalent impedance and / or the second equivalent impedance until symmetry between the first output driver stage and the second output driver stage is realized.

Description

Symmetry adjustment module and method for adjusting symmetry

[0001] This invention claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311868672.X and invention name “Symmetry Adjustment Module and Method for Adjusting Symmetry”. The entire contents of this application are incorporated herein by reference. Technical Field

[0002] The present invention relates to a symmetry adjustment module and a method for adjusting symmetry. More specifically, the present invention relates to a symmetry adjustment module for a transmitter of a bus system that transmits signals in a differential manner, and a method for adjusting the symmetry of a first output driver stage and a second output driver stage of the transmitter. Background Art

[0003] A bus system is a communication system used in various electronic devices to transmit data and control signals. It typically consists of a set of parallel or serial lines that connect various devices, enabling communication and coordination between them. Buses typically use differential transmission signaling technology because of its advantages, such as strong interference resistance, long transmission distance, and high transmission speed. Differential transmission refers to the transmission of signals on two signal lines, with the two signals having equal amplitude and opposite phase. The signals transmitted on these two signal lines are usually called differential signals. In differential signaling, one signal line carries a positive signal and the other carries a negative signal. The difference between these two signals constitutes the effective signal, known as the differential-mode voltage. The average of the voltages on these two signal lines is the common-mode voltage. Common-mode voltage is often caused by interference or signal line imbalance, and it can interfere with or damage signal transmission. Therefore, in differential signaling, common-mode voltage is often suppressed or shielded to ensure reliable and stable signal transmission.

[0004] Bus systems typically utilize various communication protocols to transmit signals between nodes. For example, in various industries today, particularly the automotive industry, a wide variety of electronic control systems have been developed to meet the demands of safety, comfort, convenience, low pollution, and low cost. Because the types of data used and reliability requirements for communication between these systems vary, and they often involve multiple buses, the number of wiring harnesses increases. To reduce the number of wiring harnesses and address the need for high-speed communication of large amounts of data across multiple LANs (Local Area Networks), German electrical manufacturer Bosch developed the CAN communication protocol for automotive communications in 1986. CAN, short for Controller Area Network (hereinafter referred to as CAN), is an ISO-standardized serial communication protocol. CAN has since been standardized through standards such as ISO 11898 and ISO 11519, and has become a widely adopted standard protocol for automotive networks. CAN FD (CAN with Flexible Data rate) has also been proposed as a derivative of CAN. These two protocols will be collectively referred to as CAN below, without distinction.

[0005] For bus systems that transmit signals differentially, transmitter symmetry must meet certain requirements to achieve the desired signal transmission level. For example, the CAN bus system, a bus interface with differential inputs and outputs, has clear requirements for symmetry in CAN transmitters according to the ISO 11898-2 standard. For example, ISO 11898-2 specifies that to achieve acceptable transmission levels, transmitters must meet specific criteria for signal symmetry: Vsym = (VCAN_H + VCAN_L) / VCC must be within the range of 0.9 to 1.1, where VCC is the transmitter's supply voltage.

[0006] However, during signal transmission in such bus systems, the common-mode voltage of the bus output signal may shift. For example, in the case of the CAN bus, during the switching process of the two driver transistors P0 and N0, non-ideal factors such as asymmetric on-resistance between the two bus terminals CANH and CANL, unequal parasitic capacitance of the driver transistors, asymmetric switching signal transmission, and asymmetric switching control caused by the current limiting circuit can cause the two bus terminals CANH and CANL to respond asynchronously. This can cause the common-mode voltage of the bus output signal to shift, potentially exceeding the symmetry requirements of the ISO 11898-2 standard and even impacting the application and electromagnetic compatibility (EMC) of the CAN bus in high-speed scenarios. Furthermore, ISO 11898-2 allows for the use of a 4.7nF common-mode capacitor during symmetry testing, and this generally results in better output symmetry. However, in practical applications, there is a growing trend to eliminate the use of common-mode capacitors to save costs. Without the filtering provided by common-mode capacitors, the output stage circuitry of traditional transmitters suffers from poor bus output symmetry, failing to meet the standard requirements and impacting communication quality.

[0007] Therefore, there is a need to be able to adjust and improve the symmetry of the bus system's output. Some existing solutions are costly or may experience issues during long-term use. Other solutions rely on detecting asymmetry on the CANH and CANL buses before adjusting the symmetry. However, this approach is slow and unsatisfactory. Summary of the Invention

[0008] In view of the above, one of the objectives of the present disclosure is to resolve or at least alleviate the aforementioned problems. To this end, the present invention provides a symmetry adjustment module and a method for adjusting the signal symmetry of a bus system to ensure good symmetry, thereby meeting the requirements of the communication protocol and guaranteeing communication quality. The present invention also allows for rapid and cost-effective symmetry adjustment. Compared to prior art adjustments, the present invention allows for faster dynamic adjustment of symmetry, thereby ensuring symmetry of the differential output stage.

[0009] According to a first aspect of the present invention, a symmetry adjustment module is provided for adjusting the symmetry between a first output driver stage and a second output driver stage. The symmetry adjustment module includes: a sampling circuit coupled to the first output driver stage and the second output driver stage and configured to output a sampled voltage related to a first equivalent impedance of the first output driver stage and a second equivalent impedance of the second output driver stage; a reference voltage generation circuit configured to generate a reference voltage; and a comparison circuit coupled to the sampling circuit and the reference voltage generation circuit and configured to compare the sampled voltage with the reference voltage to output a control signal. The symmetry adjustment module generates an adjustment signal based on the control signal, the adjustment signal being used to adjust the first equivalent impedance and / or the second equivalent impedance until symmetry is achieved between the first output driver stage and the second output driver stage.

[0010] According to an exemplary aspect of the present disclosure, a symmetry adjustment module is used in a CAN transmitter, which includes a first bus terminal and a second bus terminal. A first terminal of a first output driver stage is coupled to a power supply voltage VCC, and a second terminal of the first output driver stage is coupled to the first bus terminal and the second bus terminal. A first terminal of a second output driver stage is coupled to a reference potential, and a second terminal of the second output driver stage is coupled to the first bus terminal and the second bus terminal. This symmetry adjustment module ensures symmetry of the differential output stage.

[0011] According to an exemplary aspect of the present disclosure, a first output driver stage includes a first driver transistor, and a sampling circuit includes a first sampling transistor coupled to the gate of the first driver transistor. The size of the first sampling transistor is reduced by a first ratio based on the size of the first driver transistor. According to an exemplary aspect of the present disclosure, a second output driver stage includes a second driver transistor, and the sampling circuit includes a second sampling transistor coupled to the gate of the second driver transistor, wherein the size of the second sampling transistor is reduced by a second ratio based on the size of the second driver transistor. According to an example of the present disclosure, the first ratio is equal to the second ratio.

[0012] According to an exemplary aspect of the present disclosure, the second end of the first sampling transistor and the second end of the second sampling transistor are coupled to a sampling node, and the sampling node is used to output a sampling voltage.

[0013] According to an exemplary aspect of the present disclosure, a first terminal of the first sampling transistor is coupled to a power supply voltage VCC, a control terminal is coupled to the control terminal of the first driver transistor, and receives a regulation signal. According to an exemplary aspect of the present disclosure, a first terminal of the second sampling transistor is coupled to a reference potential, a control terminal is coupled to the control terminal of the second driver transistor, and receives a regulation signal.

[0014] According to an exemplary aspect of the present disclosure, a reference voltage includes a first reference voltage VREF1 and a second reference voltage VREF2. A reference voltage generation circuit includes a first reference voltage generation circuit for generating the first reference voltage VREF1 and a second reference voltage generation circuit for generating the second reference voltage VREF2. A symmetry adjustment module includes a power supply voltage VCC coupled to the sampling circuit and the first output driver stage. According to an exemplary aspect of the present invention, the first reference voltage VREF1, the second reference voltage VREF2, and the power supply voltage VCC satisfy the following relationship: VREF1>VCC / 2>VREF2.

[0015] According to an exemplary aspect of the present disclosure, a comparison circuit includes a first operational amplifier and a second operational amplifier. An input of the first operational amplifier is coupled to a first reference voltage generating circuit and a sampling circuit to compare a sampled voltage with the first reference voltage to output a first control signal. An input of the second operational amplifier is coupled to a second reference voltage generating circuit to compare the sampled voltage with a second reference voltage VREF2 to output a second control signal. A symmetry adjustment module generates an adjustment signal based on the first control signal and / or the second control signal.

[0016] According to an exemplary aspect of the present disclosure, the symmetry adjustment module further includes a switch configured to turn the symmetry adjustment module on or off.

[0017] According to an exemplary aspect of the present disclosure, a symmetry adjustment module is implemented in a CAN transmitter to control the on / off switching of a switch based on a switch control signal. The switch control signal is generated based on a pulse signal received by the CAN transmitter. Upon a rising edge of the pulse signal, the switch control signal transitions from a first state to a second state. After a delay, the switch control signal is flipped.

[0018] The symmetry adjustment module according to the present invention effectively controls the common-mode voltage of the bus output within a narrow range, even when there are significant differences in control signals and device characteristics on either side of the transmitter output stage bus. In a CAN transmitter application, considering an extreme case where there is a 30% mismatch between the current limiting circuit and the gate voltage control signal of the switch driver, without the proposed symmetry adjustment module, the bus output exhibits significant asymmetry, with the output common-mode voltage significantly deviating from VCC / 2. However, with the symmetry adjustment module according to the present invention, the bus output maintains desired symmetry even in the presence of a larger mismatch.

[0019] Furthermore, the optimization of symmetry greatly improves the electromagnetic compatibility (EMC) of the transceiver used in the bus system, ensures the symmetry of the impedance at both ends of the bus system, and ensures that the receiving end of the bus will not output glitches even if it is disturbed.

[0020] At the same time, CAN is developing towards high-speed applications, and the higher the speed of communication, the higher the requirement for symmetry. The optimization of symmetry by the present invention greatly improves the application rate of CAN.

[0021] Furthermore, the symmetry adjustment module according to the present invention optimizes bus symmetry, ensuring good bus output symmetry even in applications without common-mode capacitors. Therefore, the present invention improves symmetry while reducing system application costs at minimal cost.

[0022] According to another aspect of the present disclosure, a method for adjusting symmetry is provided. The method includes collecting a sampled voltage associated with a first equivalent impedance of a first output driver stage and a second equivalent impedance of a second output driver stage. The method also includes comparing the sampled voltage with a reference voltage to generate a control signal. The method also includes generating an adjustment signal based on the control signal to adjust the first equivalent impedance and / or the second equivalent impedance until symmetry is achieved between the first output driver stage and the second output driver stage.

[0023] According to an exemplary aspect of the present disclosure, a method for adjusting symmetry is used to adjust the symmetry between a first output driver stage and a second output driver stage of a CAN transmitter.

[0024] The methods according to the present disclosure achieve the same advantages as set forth above with reference to the symmetry adjustment module.

[0025] The invention summary is provided to introduce the principles of the present invention in a simplified form, which will be further described in the detailed description below. The invention summary is not intended to define the key features or main features of the present disclosure, nor is it intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] For a better understanding of the present invention, some embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0027] FIG1 exemplarily illustrates a simplified block diagram of a transmitter including a symmetry adjustment module according to an embodiment of the present invention.

[0028] FIG2 exemplarily illustrates a transmitter including a symmetry adjustment module according to another embodiment of the present invention.

[0029] FIG3 exemplarily illustrates a transmitter including a symmetry adjustment module according to yet another embodiment of the present invention.

[0030] FIG4 schematically illustrates a method for adjusting symmetry according to the present invention.

[0031] FIG5 schematically illustrates various signals in a transmitter including a symmetry adjustment module according to the present invention.

[0032] FIG6 schematically illustrates various signals in a transmitter, wherein the upper diagram shows a signal response obtained without a symmetry adjustment module, and the lower diagram shows a signal response obtained with a symmetry adjustment module. DETAILED DESCRIPTION

[0033] The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the inventive concept can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art. Throughout this specification, like reference numerals refer to like parts. Moreover, in describing the preferred embodiments illustrated in the drawings, specific terms are employed for the sake of clarity. However, the disclosure of this patent application is not intended to be limited to the specific terms mentioned, and it should be understood that each specific element includes all technical equivalents that work in a similar manner.

[0034] The term "including" and its variations used in this document represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. The term "module" may refer to a unit that includes one or a combination of hardware, software, and firmware. For example, the term "module" may be used interchangeably with the terms "unit", "logic", "logic block", "component", or "circuit".

[0035] The terms "coupled" or "connected" herein encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium such as a conductor, where the electrically conductive medium may contain parasitic inductance or capacitance, or a connection through an intermediate circuit or component as described in the embodiments of the specification. An indirect connection may also include a connection through other active or passive devices that can achieve the same or similar functions.

[0036] Embodiments of the present disclosure relate to bus systems that transmit signals using a differential transmission method, including but not limited to bus systems such as CAN and FlexRay. For simplicity, the following description uses the CAN bus as an example. However, as those skilled in the art will readily appreciate, the scope of this application is not intended to be limited to the CAN bus and is applicable to any suitable bus system that transmits signals using a differential transmission method.

[0037] Figure 1 schematically illustrates a transmitter 10 of a bus system (not shown). The following embodiments will be described using the CAN bus as an example, but other bus systems are also possible. Transmitter 10 receives a TXD signal from a microcontroller unit (MCU, not shown) and then drives two signal lines of the CAN bus. Transmitter 10 typically includes a common-mode voltage (VCM) generation circuit 11, a transmit data logic circuit 12, a first output driver stage 13, and a second output driver stage 14. A first terminal of the first output driver stage 13 is coupled to a power supply voltage VCC, and a first terminal of the second output driver stage 14 is coupled to a reference potential. In some embodiments, as shown in Figure 1, the first output driver stage 13 includes a first driver transistor P0. The second output driver stage 14 includes a second driver transistor N0.

[0038] Transmitter 10 also includes positive and negative voltage protection diodes D1 and D2. Figure 1 only schematically illustrates examples of these diodes. In some embodiments, diodes D1 and D2 can each be implemented as a single device, such as an LDMOS (Lateral Double-Diffused Metal Oxide Semiconductor) transistor, a diode, or a parasitic diode. In other embodiments, diodes D1 and D2 can each be implemented as a combination of multiple devices, including LDMOS transistors, diodes, or parasitic diodes. In yet other embodiments, diodes D1 and D2 can be MOS (Metal Oxide Semiconductor) diodes formed by parasitic diodes or body diodes. In a preferred embodiment, for example, D1 can include an NLDMOS (N-channel Lateral Double-Diffused Metal Oxide Semiconductor) transistor and a PLDMOS (P-channel Lateral Double-Diffused Metal Oxide Semiconductor) transistor.

[0039] In addition, transmitter 10 includes a bus differential input resistor Rin. Transmitter 10 includes a first bus terminal CANH and a second bus terminal CANL, respectively coupled to two signal lines of a CAN bus. A second end of a first output driver stage 13 is coupled to the first bus terminal CANH and the second bus terminal CANL. A second end of a second output driver stage 14 is coupled to the first bus terminal CANH and the second bus terminal CANL. In some embodiments, transmitter 10 may further include a driver circuit 15 for controlling the output driver stage.

[0040] The dashed box in FIG1 shows a simplified block diagram of a symmetry adjustment module 100 according to the present invention. Due to process variations, control signal asynchrony, or other non-ideal factors, a certain degree of asymmetry may occur between the first output driver stage 13 and the second output driver stage 14. This can cause the two bus terminals CANH and CANL to not respond synchronously, resulting in a shift in the common-mode voltage of the bus output signal, which can adversely affect communication quality. Therefore, a symmetry adjustment module 100 is provided to adjust the symmetry between the first output driver stage 13 and the second output driver stage 14 so that the symmetry meets the requirements of communication standards.

[0041] As shown in Figure 1, the symmetry adjustment module 100 includes a power supply voltage VCC, a sampling circuit 101, a reference voltage generating circuit 102, and a comparison circuit 103. The sampling circuit 101 is coupled to a first output driver stage 13 and a second output driver stage 13. In some embodiments, the sampling circuit 101 may also be coupled to a driver circuit 15. In other embodiments, the sampling circuit may be directly coupled to the transmit data logic circuit 12. The sampling circuit 101 is configured to sample the voltages of the first and second output driver stages and output a sampled voltage VOC_SENSE. This sampled voltage VOC_SENSE is related to a first equivalent impedance of the first output driver stage and a second equivalent impedance of the second output driver stage. The first equivalent impedance of the first output driver stage includes the equivalent impedance of the first driver transistor P0 and the diode D1. In some embodiments, the first equivalent impedance is primarily determined by the equivalent impedance of the first driver transistor P0. The second equivalent impedance of the second output driver stage includes the equivalent impedance of the second driver transistor N0 and the diode D2. In some embodiments, the second equivalent impedance is primarily determined by the equivalent impedance of the second driver transistor N0. The sampling voltage VOC_SENSE collected by the sampling circuit can quickly reflect the asymmetry occurring between the first output driver stage and the second output driver stage, even before the asymmetry occurs between the first bus terminal CANH and the second bus terminal CANL.

[0042] The reference voltage generation circuit 102 is configured to generate a reference voltage. In a preferred embodiment, the reference voltage includes a first reference voltage VREF1 and a second reference voltage VREF2. As shown in FIG. 1, the reference voltage generation circuit 102 may include a first reference voltage generation circuit for generating the first reference voltage VREF1 and a second reference voltage generation circuit for generating the second reference voltage VREF2. The settings of the first and second reference voltages VREF1 and VREF2 may refer to the power supply voltage VCC. The settings of the first and second reference voltages VREF1 and VREF2 affect the sensitivity of the symmetry adjustment module 100. The first and second reference voltages VREF1 and VREF2 can be set according to the desired sensitivity and stability. In some embodiments, the first reference voltage VREF1 is set to satisfy: VREF1 > VCC / 2. In a preferred embodiment, the first reference voltage VREF1 is set to be slightly greater than VCC / 2. In some embodiments, the second reference voltage VREF2 is set to satisfy: VREF2 < VCC / 2. In a preferred embodiment, the second reference voltage VREF2 is set to be slightly less than VCC / 2. In some examples, when VCC is 5V, VREF1 can be 2.6V and VREF2 can be 2.4V. In another example, when VCC is 5V, VREF1 can be 3V and VREF2 can be 2V.

[0043] The comparison circuit 103 is coupled to the sampling circuit 101 and the reference voltage generation circuit 102. The sampled voltage VOC_SENSE collected by the sampling circuit and the reference voltage are input into the comparison circuit 103 for comparison. The comparison circuit 103 outputs control signals C1 and C2 based on the comparison result between the sampled voltage VOC_SENSE and the reference voltage. In some embodiments, the control signals C1 and C2 can be input into the driving circuit 15. In other embodiments, the control signals C1 and C2 can be input into the transmit data logic circuit 12. The symmetry adjustment module 100 generates an adjustment signal based on the control signals C1 and C2. The adjustment signal is used to adjust the first equivalent impedance and / or the second equivalent impedance until symmetry between the first output driving stage and the second output driving stage is achieved. In this way, the symmetry of the differential output stage is achieved. The adjustment signal acts on the first output driving stage 13 and / or the second output driving stage 14, such that the equivalent impedances on both sides of VOC_SENSE become equal.

[0044] The adjustment process of the symmetry adjustment module 100 is described by way of example. When the sampled voltage VOC_SENSE is detected to be greater than the first reference voltage VREF1, the equivalent impedance of the first output driver side is greater than the equivalent impedance of the second output driver side. The symmetry adjustment module 100 outputs an adjustment signal to pull up the gate voltages of the first driver transistor P0 and the second driver transistor N0. This negative feedback reduces the equivalent impedance of the first driver transistor P0 and increases the equivalent impedance of the second driver transistor N0 until the equivalent impedances on both sides of VOC_SENSE are equal. Consequently, the equivalent impedances of the first and second driver transistors P0 and N0 are also equal. At this point, the common-mode voltage of the two bus terminals CANH and CANL is near VCM. This achieves good symmetry of the bus output. The adjustment process is similar when the sampled voltage VOC_SENSE is less than the second reference voltage VREF2 and will not be further described here.

[0045] FIG2 schematically illustrates a transmitter 10 including a symmetry adjustment module 100, which illustrates an exemplary embodiment of a sampling circuit. For simplicity, portions similar to FIG1 may be referred to as previously described and will not be further described herein. The sampling circuit includes a first sampling transistor P1 and a second sampling transistor N1. The first sampling transistor P1 is coupled to a first output driver stage 13. In some embodiments, the first sampling transistor P1 may be coupled to the gate of a first driver transistor. In some more specific embodiments, a first terminal of the first sampling transistor P1 is coupled to a power supply voltage VCC, a second terminal is coupled to a sampling node SN, and a control terminal is coupled to a control terminal of the first driver transistor P0 and receives an adjustment signal. The size of the first sampling transistor P1 is reduced by a first ratio based on the size of the first driver transistor P0.

[0046] The second sampling transistor N1 is coupled to the second output driver stage 14. In some embodiments, the second sampling transistor N1 is coupled to the gate of the second driver transistor N0. In some embodiments, the first terminal of the second sampling transistor N1 is coupled to a reference potential, the second terminal is coupled to the sampling node SN, and the control terminal is coupled to the control terminal of the second driver transistor and receives a regulation signal. The size of the second sampling transistor N1 is reduced by a second ratio based on the size of the second driver transistor N0, where the first ratio is equal to the second ratio.

[0047] The first output driver stage 13 and the second output driver stage 14 are replicated using the first sampling transistor P1 and the second sampling transistor N1. Furthermore, because the sizes of the first and second sampling transistors P1 and N1 are scaled down based on the sizes of the first and second driver transistors P0 and N0 at a first ratio, when asymmetry occurs, the response of the first and second sampling transistors P1 and N1 is even faster than the outputs of the first and second driver transistors P0 and N0. Once asymmetry occurs between the first and second output driver stages, the sampled voltage VOC_SENSE collected at the sampling node SN immediately reflects the asymmetry, before any asymmetry appears at the bus terminals CANH and CANL.

[0048] In the embodiment shown in Figure 2, a comparison circuit compares the sampled voltage VOC_SENSE with a first reference voltage VREF1 and a second reference voltage VREF2. When the sampled voltage VOC_SENSE is between the first reference voltage VREF1 and the second reference voltage VREF2, it indicates that the symmetry meets expectations. At this point, the value of the sampled voltage VOC_SENSE is close to VCC / 2. If VOC_SENSE is greater than VREF1, asymmetry is determined. If VOC_SENSE is less than VREF2, asymmetry is also determined. Once asymmetry is determined, symmetry adjustment is required. At this point, the comparison circuit outputs a control signal. The symmetry adjustment module 100 generates an adjustment signal based on this control signal.

[0049] In some embodiments, taking the asynchronous turn-on timing of the driver transistors as an example, when VOC_SENSE is greater than VREF1, it indicates that the first driver transistor P0 may turn on too early compared to the second driver transistor N0. In this case, the regulation signal pulls up the voltage at the gate of the first driver transistor P0 and the gate of the second driver transistor N0, reducing the equivalent impedance of the first output driver stage and increasing the equivalent impedance of the second output driver stage through negative feedback until the equivalent impedances on both sides of VOC_SENSE are equal. In some embodiments, when VOC_SENSE is less than VREF2, it indicates that the first driver transistor P0 may turn on too late compared to the second driver transistor N0. In this case, the regulation signal pulls down the voltage at the gate of the first driver transistor P0 and the gate of the second driver transistor N0, increasing the equivalent impedance of the first output driver stage and reducing the equivalent impedance of the second output driver stage through negative feedback until the equivalent impedances on both sides of VOC_SENSE are equal.

[0050] FIG3 exemplarily illustrates an embodiment of a reference voltage generation circuit. The first reference voltage generation circuit for generating a first reference voltage VREF1 includes a current source I1 coupled to a power supply voltage VCC and a first resistor R1. A comparator circuit 103 is coupled between the current source I1 and the first resistor R1 to input the first reference voltage VREF1 into the comparator circuit. A second reference voltage generation circuit for generating a second reference voltage VREF2 includes a current source I2 coupled to the power supply voltage VCC and a second resistor R2. A comparator circuit 103 is coupled between the second current source I2 and the second resistor R2 to input the second reference voltage VREF2 into the comparator circuit. A common-mode voltage generation circuit 11 and a bus differential input resistor Rin may be coupled between the first resistor R1 and the second resistor R2. Other embodiments of the reference voltage generation circuit are also feasible, as long as they can generate a suitable reference voltage.

[0051] In some embodiments, the comparison circuit 103 includes an operational amplifier configured to compare the sampled voltage VOC_SENSE with a reference voltage to detect asymmetry between the first and second output driver circuits. In some embodiments, as shown in FIG3 , the operational amplifier is a three-input operational amplifier, with its two negative input terminals coupled to the first and second reference voltage generation circuits, respectively. The positive input terminal of the three-input operational amplifier is coupled to the sampling circuit. Specifically, the positive input terminal of the three-input operational amplifier may be coupled to a sampling node SN. The output terminal of the three-input operational amplifier is coupled to the transmit data logic circuit 12. In another embodiment, the output terminal of the three-input operational amplifier may be coupled to the driver circuit 15. The three-input operational amplifier may compare the sampled voltage VOC_SENSE with a first reference voltage VREF1 to output a first control signal C1. The three-input operational amplifier may compare the sampled voltage VOC_SENSE with a second reference voltage VREF2 to output a second control signal C2. The symmetry adjustment module generates an adjustment signal based on the first control signal C1 and / or the second control signal C2.

[0052] In some embodiments, the comparison circuit includes a first operational amplifier and a second operational amplifier (not shown). The input of the first operational amplifier is coupled to a first reference voltage generation circuit and a sampling circuit to compare the sampled voltage VOC_SENSE with a first reference voltage VREF1 to output a first control signal C1. The input of the second operational amplifier is coupled to a second reference voltage generation circuit to compare the sampled voltage VOC_SENSE with a second reference voltage VREF2 to output a second control signal C2. The symmetry adjustment module generates an adjustment signal based on the first control signal C1 and / or the second control signal C2.

[0053] In some embodiments, the symmetry adjustment module 100 may further include switches S1 and S2. Switches S1 and S2 are configured to turn the symmetry adjustment module on and off. When the symmetry adjustment module is used in a CAN transmitter, the on and off of switches S1 and S2 are controlled based on a switch control signal. In some embodiments, the switch control signal can be generated based on a pulse signal received by the CAN transmitter. When the rising edge of the pulse signal arrives, the switch control signal transitions from a first state to a second state. The switch control signal can be flipped after a delay. Switches S1 and S2 can control the duration of the symmetry adjustment circuit. For example, in some embodiments, switches S1 and S2 are only open when the transmitter switches between states. Switches S1 and S2 are opened when the transmitter is in the dominant or recessive state, thereby disabling the symmetry adjustment module. This prevents interference with VOC_SENSE during the voltage level stabilization phase, which could cause the symmetry adjustment module to remain active. In this way, the switches are only opened when symmetry adjustment is required, which also saves power.

[0054] Figure 4 schematically illustrates a method 400 for adjusting symmetry according to an embodiment of the present invention. Method 400 includes step S401, where a sampled voltage VOC_SENSE related to a first equivalent impedance of a first output driver stage and a second equivalent impedance of a second output driver stage is collected. Method 400 may proceed to step S402, where the sampled voltage VOC_SENSE is compared with a reference voltage to generate a control signal. Method 400 may then proceed to step S403, where an adjustment signal is generated based on the control signal in step S402 to adjust the first equivalent impedance and the second equivalent impedance until symmetry is achieved between the first and second output driver stages. This allows for rapid symmetry of differential output stages. Method 400 can be used to adjust the symmetry between the first and second driver stages of a CAN transmitter. Method 400 may also be used to adjust other bus systems that transmit signals differentially. Method 400 may also include any other suitable steps, and is not limited to the steps shown in the figure.

[0055] Figure 5 schematically illustrates various signals in a transmitter including the symmetry adjustment module according to Figure 3 . The top diagram includes a curve 501 for the sampled voltage VOC_SENSE at the sampling node SN, a curve 502 for the first reference voltage VREF1, and a curve 503 for the second reference voltage. The middle diagram shows curves 511 and 512 for the gate voltages VPB and VNB of the driver transistors P0 and N0, respectively. VPB and VNB may also represent the voltages at the gates of the first sampling transistor P1 and the second sampling transistor N1, respectively. The bottom diagram shows curves 521 and 522 for the voltages CAN_H and CAN_L at the two bus terminals CANH and CANL. As shown in Figure 5 , when VOC_SENSE is detected to exceed reference voltages VREF1 and VREF2, as shown in the top diagram of Figure 5 , in the presence of a significant mismatch (as evidenced by the distinct peaks and valleys of curve 501 ), gate voltages VPB and VNB can immediately respond by adjusting the voltages at the gates of first sampling transistor P1 and second sampling transistor N1, thereby equalizing the equivalent impedances of first driver transistor P0 and second driver transistor N0, which are amplified in equal proportions. As a result, curves 521 and 522 are relatively symmetrical, achieving the desired symmetry. As shown in Figure 5 , there is little or no delay.

[0056] The following compares the voltage responses obtained when the transmitter has and does not have a symmetry adjustment module. The upper left-hand figure shows curves 601 and 602 of the gate voltages VPB and VNB obtained when the symmetry adjustment module is not present. The upper right-hand figure shows curves 603 and 604 of the voltages CAN_H and CAN_L at the two bus terminals CANH and CANL obtained when the symmetry adjustment module is not present. As indicated by the dashed lines 605 and 606 in the figure, the outputs at the two bus terminals CANH and CANL exhibit significant dips, with the common-mode voltage significantly deviating from VCC / 2, exhibiting significant asymmetry. The lower figure shows the voltage response of a transmitter under the same conditions as the upper figure, except that it has a symmetry adjustment module. The lower left-hand figure shows curves 611 and 612 of the gate voltages VPB and VNB obtained. The lower right-hand figure shows curves 613 and 614 of the voltages CAN_H and CAN_L obtained at the two bus terminals CANH and CANL. Compared with the upper right figure, it can be clearly seen that in the case of a symmetric adjustment module, even in the presence of a large mismatch, the curves 613 and 614 of the voltages CAN_H and CAN_L at the two bus terminals still achieve good symmetry without any depression.

[0057] It is clear that when the symmetry adjustment module according to the present invention is applied, the bus output can still exhibit good symmetry even in the presence of larger mismatches. Optimizing symmetry can also improve the electromagnetic compatibility (EMC) of transceivers used in bus systems, ensuring impedance symmetry at both ends of the bus system and preventing output glitches even in the presence of interference. At the same time, various bus systems are developing towards high-speed applications, and higher-speed communications require higher symmetry. The optimization of symmetry by the present invention greatly improves the application rate of bus systems, such as the application rate of CAN. Moreover, with the help of the symmetry adjustment module according to the present invention, bus symmetry is optimized, and the bus output has good symmetry even in applications without common-mode capacitors. Therefore, the present invention allows for improved symmetry at a very low cost.

[0058] The above description of the exemplary embodiments of the disclosed subject matter, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, various modifications are contemplated within the scope of such embodiments and examples, as those skilled in the relevant art will recognize.

[0059] In this regard, although the subject matter disclosed herein has been described in conjunction with various embodiments and corresponding drawings, it should be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiments to perform the same, similar, alternative, or alternative functions of the disclosed subject matter without departing from the described embodiments. Accordingly, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in accordance with the breadth and scope of the claims appended hereto.

[0060] In particular, with respect to the various functions performed by the aforementioned components (assemblies, devices, circuits, systems, etc.), unless otherwise specified, the terms used to describe such components (including references to "modules" or "devices") are intended to correspond to any component or structure that performs the designated functions of the components (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present disclosure shown herein. In addition, while particular features have been disclosed with respect to only one of several embodiments, for any given or particular application, such features may be combined with one or more other features of other embodiments, which may be desirable and advantageous.

Claims

1. A symmetry adjustment module for adjusting the symmetry between a first output driving stage and a second output driving stage, the symmetry adjustment module comprising: A sampling circuit coupled to the first output driving stage and the second output driving stage and configured to output a sampling voltage (VOC_SENSE) related to a first equivalent impedance of the first output driving stage and a second equivalent impedance of the second output driving stage; A reference voltage generation circuit configured to generate a reference voltage; A comparison circuit coupled to the sampling circuit and the reference voltage generation circuit and configured to compare the sampling voltage (VOC_SENSE) with the reference voltage to output a control signal; The symmetry adjustment module generates an adjustment signal based on the control signal, and the adjustment signal is used to adjust the first equivalent impedance and / or the second equivalent impedance until symmetry between the first output driving stage and the second output driving stage is achieved.

2. The symmetry adjustment module according to claim 1, characterized in that: The symmetry adjustment module is used for a CAN transmitter, the CAN transmitter includes a first bus terminal (CANH) and a second bus terminal (CANL), a first end of the first output driving stage is coupled to a power supply voltage VCC, a second end of the first output driving stage is coupled to the first bus terminal (CANH) and the second bus terminal (CANL), a first end of the second output driving stage is coupled to a reference potential, and a second end of the second output driving stage is coupled to the first bus terminal and the second bus terminal.

3. The symmetry adjustment module according to claim 1 or 2, wherein, The first output driving stage includes a first driving transistor (P0), the sampling circuit includes a first sampling transistor (P1) coupled to the gate of the first driving transistor, and the size of the first sampling transistor (P1) is reduced by a first ratio based on the size of the first driving transistor (P0); And The second output driving stage includes a second driving transistor (N0), the sampling circuit includes a second sampling transistor (N1) coupled to the gate of the second driving transistor, wherein the size of the second sampling transistor (N1) is reduced by a second ratio based on the size of the second driving transistor (N0), and the first ratio is equal to the second ratio.

4. The symmetry adjustment module according to claim 3, wherein, A second end of the first sampling transistor (P1) and a second end of the second sampling transistor (N1) are coupled to a sampling node, and the sampling node is used to output the sampling voltage (VOC_SENSE).

5. The symmetry adjustment module according to claim 4, wherein, A first end of the first sampling transistor (P1) is coupled to the power supply voltage VCC, and a control end of the first sampling transistor (P1) is coupled to a control end of the first driving transistor (P0) and receives the adjustment signal; A first end of the second sampling transistor (N1) is coupled to the reference potential, and a control end of the second sampling transistor (N1) is coupled to a control end of the second driving transistor and receives the adjustment signal.

6. The symmetry adjustment module according to claim 1 or 2, wherein, The reference voltage includes a first reference voltage VREF1 and a second reference voltage VREF2. The reference voltage generating circuit includes a first reference voltage generating circuit for generating the first reference voltage VREF1 and a second reference voltage generating circuit for generating the second reference voltage VREF2; The symmetry adjustment module has a power supply voltage VCC coupled to the sampling circuit and the first output driver stage; The first reference voltage VREF1, the second reference voltage VREF2, and the power supply voltage VCC satisfy: VREF1 > VCC / 2 > VREF2.

7. The symmetry adjustment module according to claim 6, wherein, The comparison circuit includes a first operational amplifier and a second operational amplifier. The input terminal of the first operational amplifier is coupled to the first reference voltage generating circuit and the sampling circuit to compare the sampling voltage (VOC_SENSE) with the first reference voltage VREF1 to output a first control signal. And the input terminal of the second operational amplifier is coupled to the second reference voltage generating circuit to compare the sampling voltage (VOC_SENSE) with the second reference voltage VREF2 to output a second control signal. The symmetry adjustment module generates an adjustment signal based on the first control signal and / or the second control signal.

8. The symmetry adjustment module according to claim 1, wherein The symmetry adjustment module further includes a switch, and the switch is configured to turn on or off the symmetry adjustment module.

9. The symmetry adjustment module according to claim 8, wherein: The symmetry adjustment module is for a CAN transmitter and controls the switch to turn on or off based on a switch control signal; The switch control signal is generated based on the pulse signal received by the CAN transmitter: when the rising edge of the pulse signal arrives, the switch control signal jumps from a first state to a second state, and after a delay time, the switch control signal is inverted.

10. A method for adjusting symmetry, the method includes: Collecting a sampling voltage (VOC_SENSE) related to a first equivalent impedance of a first output driver stage and a second equivalent impedance of a second output driver stage; Comparing the sampling voltage (VOC_SENSE) with a reference voltage to generate a control signal; Generating an adjustment signal based on the control signal to adjust the first equivalent impedance and / or the second equivalent impedance until symmetry between the first output driver stage and the second output driver stage is achieved.

11. The method for adjusting symmetry according to claim 10, wherein: The method for adjusting symmetry is used to adjust the symmetry between a first output driver stage and a second output driver stage of a CAN transmitter.

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