Semiconductor device, electronic device, and preparation method for semiconductor device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device, an electronic device, and a preparation method for a semiconductor device. Provided is a semiconductor device capable of over-voltage protection for a gate electrode of a transistor. The semiconductor device comprises a substrate, a transistor arranged on the substrate, and a protective device, wherein the protective device comprises a channel layer, barrier layers, a first electrode and a second electrode; the channel layer is formed on the substrate; the barrier layers are formed on the channel layer; the first electrode and the second electrode are each arranged on a barrier layer, the first electrode is electrically separated from the second electrode, and the barrier layer corresponding to the position of the first electrode is electrically separated from the barrier layer corresponding to the position of the second electrode; and a gate electrode of the transistor is electrically connected to the first electrode, and a source electrode or a drain electrode of the transistor is electrically connected to the second electrode. A Schottky diode is formed by means of the barrier heights of electrodes, a channel layer and barrier layers, and a diode is formed by the channel layer and the barrier layers, so as to form a channel for current leakage, thus protecting transistors.

Description

Semiconductor device, electronic device, and method for manufacturing semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 29, 2023, with application number 202311871834.5 and invention name “Semiconductor device, electronic device, method for preparing semiconductor device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, an electronic device including the semiconductor device, and a method for preparing the semiconductor device. Background Art

[0003] With the development of communication technology, the field of radio frequency communication has put forward demands for higher frequency, higher voltage, higher output power and efficiency for semiconductor devices.

[0004] Semiconductor devices made of compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs), are increasingly being adopted in high-power radio frequency devices, high-voltage switching devices and other fields due to their excellent physical properties such as wide bandgap, high electron drift rate, radiation resistance, and high temperature resistance. For example, they are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment and other systems.

[0005] GaN HEMT semiconductor devices have low reliability. Their gates are susceptible to damage from overvoltages, such as electrostatic discharge (ESD). This high potential (up to tens of thousands to hundreds of thousands of volts) and short duration of action can be extremely destructive to semiconductor devices. Therefore, it is essential to develop a protective structure for GaN HEMT semiconductor devices.

[0006] Summary of the Invention

[0007] The present application provides a semiconductor device, an electronic device including the semiconductor device, and a method for manufacturing the semiconductor device, with the purpose of providing a semiconductor device capable of protecting a transistor gate from overvoltage.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In one aspect, the present application provides a semiconductor device including a transistor, which may be a high electron mobility transistor (HEMT).

[0010] The semiconductor device includes a substrate, a transistor and a protective device arranged on the substrate, the protective device is used to protect the transistor gate from overvoltage; the protective device includes: a first channel layer, a first barrier layer, a first electrode and a second electrode, the first channel layer is formed on the substrate, the first barrier layer is formed on the first channel layer, the first electrode and the second electrode are both arranged on the first barrier layer, and the first electrode and the second electrode are electrically isolated, the first barrier layer corresponding to the position of the first electrode is electrically isolated from the first barrier layer corresponding to the position of the second electrode; and the gate of the transistor is electrically connected to the first electrode, and the source or drain of the transistor is electrically connected to the second electrode.

[0011] In the protective device for transistor gate overvoltage protection provided in the present application, the first electrode and the first barrier layer can form a Schottky diode SBD1, and the barrier between the first barrier layer and the first channel layer corresponding to the position of the first electrode can be considered as a diode D1. The second electrode and the first barrier layer can form a Schottky diode SBD2, and the barrier between the first barrier layer and the first channel layer corresponding to the position of the second electrode can be considered as a diode D2.

[0012] For example, when the first electrode is connected to a high potential and the second electrode is connected to a low potential, the Schottky diode SBD1 and the diode D1 are both forward-conducting and in the on state, and the Schottky diode SBD2 and the diode D2 are in the reverse-blocking state; when the voltage exceeds a certain threshold, the kinetic energy of the electrons in the channel of the diode D2 and the Schottky diode SBD2 increases, so that the kinetic energy of some electrons is large enough to overcome the potential barriers of the diode D2 and the Schottky diode SBD2, so that the electrons escape to the second electrode, forming a current channel to protect the transistor.

[0013] In one possible implementation, a second channel layer is further formed on the substrate, and the second channel layer is electrically isolated from the first channel layer; a second barrier layer is formed on the second channel layer, and the second barrier layer is electrically isolated from the first barrier layer; and the source and drain of the transistor are both in ohmic contact with the second channel layer.

[0014] In some examples, the transistor may be a high electron mobility transistor (HEMT). In this example, the HEMT and the protection device are integrated on the same substrate. The resulting device can be referred to as device-level on-chip protection, which effectively reduces component damage caused by electrostatic discharge during device packaging.

[0015] In a possible implementation, the first channel layer and the second channel layer are located in the same channel layer, and the first barrier layer and the second barrier layer are located in the same barrier layer.

[0016] In a possible implementation, the gate of the transistor is located on a side of the second barrier layer away from the second channel layer; the gate, the first electrode, and the second electrode of the transistor are located in the same metal layer.

[0017] Since the channel layer of the protection device and the channel layer of the transistor are located on the same layer, and the barrier layer of the protection device and the barrier layer of the transistor are located on the same layer, when preparing the semiconductor device, the transistor and the protection device can be prepared simultaneously using the front-end process. The manufacturing process of the protection device is fully compatible with the GaN HEMT device.

[0018] In a possible implementation, there are a plurality of first electrodes and a plurality of second electrodes; the plurality of first electrodes and the plurality of second electrodes are alternately arranged in the first direction.

[0019] By using a plurality of first electrodes and a plurality of second electrodes arranged alternately, the lengths of the first electrodes and the second electrodes can be increased, thereby improving the current carrying capacity of the protection device and improving the protection performance of the transistor.

[0020] In a possible implementation, the distance S between the first electrode and the second electrode is 0.5 μm≤S≤20 μm.

[0021] The size of the distance S between the first electrode and the second electrode can determine the turn-on voltage V of the protection device. ON .

[0022] In a possible implementation, the width d of the first electrode and / or the second electrode is 2 μm≤d≤20 μm.

[0023] In one possible implementation, the length of the first electrode is not equal to the length of the second electrode.

[0024] For example, the length dimension of the first electrode is greater than the length dimension of the second electrode.

[0025] In this way, different turn-on voltages of the protection device in the forward and reverse directions can be achieved to adapt to protection devices with different turn-on voltage levels.

[0026] In one possible implementation, a dielectric layer is provided between the first electrode and the second electrode; and a dielectric layer is provided between the first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode.

[0027] In some process methods, a groove can be etched between the first electrode and the second electrode, and the groove can be made to pass through the channel layer, and then filled with dielectric material to electrically isolate the two electrodes, and the barrier layer under the two electrodes can be switched to form two electrically isolated parts.

[0028] In one possible implementation, the material of the first barrier layer includes Al x Ga 1-x N, 0.2≤x≤0.4.

[0029] In a possible implementation, the thickness h of the first barrier layer is 10 nm ≤ h ≤ 30 nm.

[0030] In the example of this application, the turn-on voltage of the protection device can be controlled by limiting the composition and thickness of the barrier layer.

[0031] In one possible implementation, the protection device's turn-on voltage V ON , 5V≤V ON ≤100V.

[0032] Since the protection device provided in this application has a turn-on voltage of 5V≤V ON ≤100V, then when the normal operating voltage range of the gate of the transistor to be protected is higher, the gate of the transistor can still be protected from overvoltage.

[0033] In one possible implementation, the off-state leakage current I of the protection device is I≤10 -2 mA / mm.

[0034] The protection device provided in the present application has low off-state leakage current, low static power consumption, and low parasitic capacitance, and is suitable for high-frequency circuit applications.

[0035] In one possible implementation, the side of the transistor and the protective device facing away from the substrate has an interconnection wiring layer; the gate of the transistor is electrically connected to the first electrode through the interconnection wiring layer; the source or drain of the transistor is electrically connected to the second electrode through the interconnection wiring layer.

[0036] That is, the transistor and the protection device can be manufactured by the front-end process, and the metal wiring of the interconnection wiring layer manufactured by the back-end process is used to electrically connect the transistor and the protection device.

[0037] In another aspect, the present application provides a method for preparing a semiconductor device, the method comprising:

[0038] fabricating transistors and protective devices on a substrate;

[0039] electrically connecting the gate of the transistor to the first electrode of the protection device, and electrically connecting the source or drain of the transistor to the second electrode of the protection device;

[0040] The protective device is made on the substrate and includes:

[0041] forming a first channel layer on a substrate;

[0042] forming a first barrier layer on the first channel layer;

[0043] A first electrode and a second electrode are formed on the first barrier layer. The first electrode and the second electrode are electrically isolated from each other. The first barrier layer corresponding to the first electrode position is electrically isolated from the first barrier layer corresponding to the second electrode position.

[0044] In the protective device manufactured using the preparation method provided in the present application, the first electrode and the first barrier layer can form a Schottky diode SBD1, the barrier between the first barrier layer and the first channel layer corresponding to the position of the first electrode can be considered as a diode D1, the second electrode and the first barrier layer can form a Schottky diode SBD2, and the barrier between the first barrier layer and the first channel layer corresponding to the position of the second electrode can be considered as a diode D2. For example, when the first electrode is connected to a high potential and the second electrode is connected to a low potential, the Schottky diode SBD1 and the diode D1 are both forward-conducting and in the on state, and the Schottky diode SBD2 and the diode D2 are in the reverse cutoff state; when the voltage exceeds a certain threshold, the kinetic energy of the electrons in the channel of diode D2 and Schottky diode SBD2 increases, so that the kinetic energy of some electrons is large enough to overcome the barrier of diode D2 and the barrier of Schottky diode SBD2, so that the electrons escape to the second electrode, forming a current channel, and protecting the transistor gate from overvoltage.

[0045] In one possible implementation, manufacturing a transistor and a protection device on a substrate includes:

[0046] forming a channel layer on a substrate;

[0047] forming a barrier layer on the channel layer;

[0048] The active area for making the transistor and the area for making the protective device are electrically isolated to form a stacked first channel layer and a first barrier layer in the area of ​​the protective device, and a stacked second channel layer and a second barrier layer in the active area, the first channel layer is electrically isolated from the second channel layer, and the first barrier layer is electrically isolated from the second barrier layer.

[0049] That is, transistors and protective devices can be manufactured simultaneously using the front-end process. The process for manufacturing protective devices can be compatible with the process for manufacturing transistors and will not pose any challenges to the process for manufacturing protective devices.

[0050] In one possible implementation, after forming the barrier layer on the channel layer, the preparation method further includes:

[0051] Etching a groove in a region for making a protective device, wherein the groove penetrates the barrier layer;

[0052] A first electrode and a second electrode are formed on the barrier layer separated by the groove.

[0053] After the first channel layer and the second barrier layer are formed, a groove can be etched to switch the two-dimensional electron gas channel of the protection device.

[0054] In a possible implementation, when the first electrode and the second electrode are formed on the first barrier layer, the method further includes:

[0055] A gate of a transistor is produced.

[0056] The gate of the transistor, the first electrode and the second electrode of the protective device can be manufactured using the same process, and the manufacturing process has strong compatibility.

[0057] In one possible implementation, forming the first electrode and the second electrode on the first barrier layer includes:

[0058] A plurality of first electrodes and a plurality of second electrodes are manufactured along a first direction parallel to the surface of the substrate, and the plurality of first electrodes and the plurality of second electrodes are alternately arranged in the first direction.

[0059] In this way, the first electrode and the second electrode with a larger length can be arranged per unit area to improve the current carrying capacity of the protection device.

[0060] In one possible implementation, after the transistor and the protective device are fabricated on the substrate, the fabrication method further includes:

[0061] An interconnection wiring layer is formed on the side of the transistor and the protection device away from the substrate. The gate of the transistor is electrically connected to the first electrode through the interconnection wiring layer, and the source or drain of the transistor is electrically connected to the second electrode through the interconnection wiring layer.

[0062] On the other hand, the present application also provides an electronic device, which includes the semiconductor device in any of the above implementations, and the electronic device also includes a substrate, and the transistor is arranged on the substrate.

[0063] In the electronic device provided by the present application, since it includes the semiconductor device in any of the above-mentioned implementation methods, the protection device and the protected transistor in the semiconductor device are integrated on the same substrate, that is, the protection device is integrated on the chip. In addition, the present application uses a Schottky diode connected in series and a diode formed by a channel layer and a barrier layer to form a current leakage path to protect the transistor gate from overvoltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 is a schematic diagram of a partial structure of a base station provided in an embodiment of the present application;

[0065] FIG2 is an exploded schematic diagram of a partial structure of a mobile phone provided in an embodiment of the present application;

[0066] FIG3 is a schematic diagram of a packaging structure of a semiconductor device provided in an embodiment of the present application;

[0067] FIG4 is a partial circuit diagram of an electronic device provided in an embodiment of the present application;

[0068] FIG5 is a partial circuit diagram of an electronic device provided in an embodiment of the present application;

[0069] FIG6 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0070] FIG7 is a semiconductor energy level diagram of each film layer structure in a protection device provided by an embodiment of the present application;

[0071] FIG8 is an equivalent circuit diagram of a protective device according to an example of the present application;

[0072] FIG9 is a circuit connection diagram of a transistor and a protection device according to an example of the present application;

[0073] FIG10 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0074] FIG11 is a schematic structural diagram of a first electrode and a second electrode provided in an embodiment of the present application;

[0075] FIG12 is a schematic structural diagram of a first electrode and a second electrode provided in an embodiment of the present application;

[0076] FIG13 is a schematic structural diagram of a first electrode and a second electrode provided in an embodiment of the present application;

[0077] FIG14 is a schematic structural diagram of a first electrode and a second electrode provided in an embodiment of the present application;

[0078] FIG15 is a schematic structural diagram of a first electrode and a second electrode provided in an embodiment of the present application;

[0079] FIG16 is a graph showing an IV characteristic curve of a protection device provided in an embodiment of the present application;

[0080] FIG17 is a schematic diagram showing the connection relationship between an electrode of a transistor and an electrode of a protection device provided in an embodiment of the present application;

[0081] FIG18 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0082] 19A to 19F are schematic structural diagrams corresponding to each step in the manufacturing process of a semiconductor device provided by an embodiment of the present application;

[0083] 20A to 20F are schematic structural diagrams corresponding to each step in the manufacturing process of a semiconductor device provided by an embodiment of the present application;

[0084] FIG21 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] Before introducing the embodiments of the present application, some technical terms related to the embodiments of the present application are introduced as follows:

[0086] Heterojunction: A junction formed by the contact of two different semiconductor materials. The lattice constants of these two materials are different, resulting in lattice mismatch.

[0087] Semiconductor heterojunction energy band diagram: shows the changes in the energy of the conduction band minimum and the valence band maximum on both sides of the heterojunction interface.

[0088] The following describes the solutions involved in the embodiments of the present application in conjunction with the accompanying drawings.

[0089] The present invention provides an electronic device, which may include a communication device (e.g., a base station, a mobile phone, a tablet, a wearable device, a smart screen, a wireless headset), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF induction device, and a microwave heating device. The present invention does not impose any particular restrictions on the specific form of the electronic device.

[0090] The aforementioned electronic devices generally include radio frequency semiconductor devices, such as power amplifiers (PAs). The PA's primary function is to amplify radio frequency signals. Taking a base station as an example, Figure 1 shows a simplified schematic diagram of the structure of a base station. The base station includes a control unit, which includes a wireless transceiver, an antenna, and related signal processing circuits. The control unit primarily comprises four components: a cell controller, a voice channel controller, a signaling channel controller, and a multi-port interface for expansion. The base station's control unit typically controls several base transceiver stations. Through remote commands from the transceiver stations and mobile stations, the base station's control unit manages all mobile communication interfaces, primarily the allocation, release, and management of wireless channels.

[0091] Continuing with Figure 1, the base station also includes a transmission unit, which is connected to the core network. The control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and these services are processed by the control unit.

[0092] Referring to Figure 1, the base station also includes a baseband unit (BBU) and a radio frequency (RF) unit. The BBU primarily performs baseband modulation and demodulation, wireless resource allocation, call processing, power control, and soft handoff. The RF unit primarily converts between over-the-air radio frequency channels and baseband digital channels. The signal is then amplified by a power amplifier (PA) and sent to the antenna via an RF feeder for transmission. Terminal devices, such as mobile phones and tablets, receive the radio waves transmitted by the antenna over wireless channels and demodulate their own signals.

[0093] Continuing with FIG1 , the base station further includes a power supply unit, which can be used to supply power to structures such as the transmission unit, the baseband unit, and the control unit.

[0094] Figure 2 shows the structure of another electronic device, taking a mobile phone as an example. The mobile phone can include a middle frame 11, a rear cover 12, and a display screen 13. The middle frame 11 includes a carrier board 111 for supporting the display screen 13, and a frame 110 surrounding the carrier board 111. As shown in Figure 3, the RF power amplifier (PA) is located in the transmit chain of the RF front-end system of the smart terminal and can be installed on the carrier board 111. The RF power amplifier (PA) mainly functions to amplify the modulated RF signal and then transmit it externally through the filter, switch, and antenna.

[0095] With the development of mobile communication technology, the functional requirements for the above-mentioned radio frequency semiconductor devices are becoming increasingly higher, such as higher frequency, higher voltage, higher output power and efficiency.

[0096] Among the semiconductor materials that can be selected, gallium nitride (GaN) has become a key material for the manufacture of radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, high saturation electron mobility rate and other characteristics. For example, a high electron mobility transistor (HEMT) based on gallium nitride (GaN) is made of a GaN epitaxial single crystal thin film grown on a single crystal substrate. The single crystal substrate generally uses materials such as sapphire (Sapphire), silicon carbide (SiC) or silicon (Si) single crystal. For example, when the substrate uses silicon single crystal material, the HEMT obtained can be called a gallium nitride on silicon (GaN-on-Si) HEMT device. In other examples, the substrate can be a composite substrate formed based on the above different materials.

[0097] As shown in FIG. 3 , the semiconductor device 300 including the HEMT in the above-mentioned apparatus is disposed on a substrate 400 , and the semiconductor device 300 is disposed on the substrate 400 via a first electrical connection structure (e.g., a metal layer) 500 , so that the semiconductor device 300 can be signal-interconnected with other electronic devices on the substrate 400 .

[0098] The substrate 400 is then disposed on the circuit board 100 via the second electrical connection structure 200. For example, the circuit board 100 may be a printed circuit board (PCB), and the second electrical connection structure 200 may be a ball grid array (BGA) or other electrical connection structures.

[0099] Gallium nitride high electron mobility transistors (GaN HEMTs) have great potential for application in high-power and high-speed radio frequency applications due to their wide bandgap and high carrier concentration. However, their electrostatic discharge (ESD) protection is relatively weak, requiring additional protection devices.

[0100] As shown in Figures 4 and 5, protection devices can be set at the input, output or power supply pins of the device; for example, protection devices must be configured at the pin ports of RF signal input, RF signal output, bias circuit input power supply, and Vdd power supply input to prevent external ESD pulse current from damaging the protected device.

[0101] When the protected device is working normally, the protection device is in the off state. When the protected device encounters ESD shock, the protection device turns on to release ESD current, so that the protected device is protected from ESD shock.

[0102] An embodiment of the present application provides a semiconductor device that integrates not only a transistor but also a protection device for overvoltage protection of the transistor gate.

[0103] As shown in FIG6 , FIG6 is a structural diagram of a semiconductor device according to an example of the present application, wherein the semiconductor device includes a substrate 10 , a transistor 20 and a protection device 30 disposed on the substrate 10 .

[0104] The protection device 30 includes: a first channel layer 301 disposed on the substrate 10 , a first barrier layer 302 disposed on the first channel layer 301 , and a first electrode 303 and a second electrode 304 disposed on the first barrier layer 302 .

[0105] The first electrode 303 and the second electrode 304 are electrically isolated from each other.

[0106] The first barrier layer 302 corresponding to the position of the first electrode 303 is electrically isolated from the first barrier layer 302 corresponding to the position of the second electrode 304 .

[0107] The gate G of the transistor is electrically connected to the first electrode 303, and the source S or drain G of the transistor is electrically connected to the second electrode 304; that is, it can be understood that: in one embodiment, as shown in Figure 6, the gate G of the transistor is electrically connected to the first electrode 303, and the source S of the transistor is electrically connected to the second electrode 304; in another embodiment, the gate G of the transistor is electrically connected to the first electrode 303, and the drain G of the transistor is electrically connected to the second electrode 304.

[0108] The protective device in this application exhibits a high-resistance state at low bias voltages and a low-resistance state when the bias voltage exceeds a certain threshold. When the protected transistor is operating normally, the protective device is in a high-resistance state, and the current flowing through the protective device is very small. When the external input voltage exceeds the protective device's turn-on voltage, the protective device acts as a voltage clamp, releasing a large current while maintaining a nearly constant voltage, thereby exhibiting a low-resistance state and protecting the transistor from damage caused by high-voltage static electricity.

[0109] Figure 7 is a semiconductor energy level diagram of each film layer structure in the protection device of the example of this application, Figure 8 is an equivalent circuit diagram of the protection device of the example of this application, and Figure 9 is a circuit connection relationship diagram of the transistor and the protection device of the example of this application.

[0110] FIG. 7 shows an energy band diagram of the first electrode 303 and the second electrode 304 comprising a metal material, an energy band diagram of the first barrier layer 302 comprising an AlGaN material, and an energy band diagram of the first channel layer 301 comprising a GaN material.

[0111] In Figure 7, the physical meanings of the various quantities in the energy band diagram are as follows:

[0112] E F Fermi level: For a microscopic system composed of fermions (electrons, protons, and neutrons), each fermion is in its own quantum energy state. In band theory, the Fermi level can be considered a hypothetical energy level that an electron has a 50% chance of occupying in thermodynamic equilibrium.

[0113] E C : The bottom of the conduction band is shown as the bandgap width.

[0114] E V : The valence band top is shown as the bandgap width.

[0115] qφ b : Shown as Schottky barrier.

[0116] qV bi: Shown as a semiconductor barrier.

[0117] As shown in FIG7 , in the protective device 30 shown in FIG6 , the first electrode 303 and the first barrier layer 302 form a Schottky diode SBD1. The first barrier layer 302 and the first channel layer 301 below the first electrode 303 form a diode D1. As shown in FIG8 , Schottky diode SBD1 and diode D1 are connected in series. The second electrode 304 and the first barrier layer 302 form a Schottky diode SBD2. The first barrier layer 302 and the first channel layer 301 below the second electrode 304 form a diode D2. As shown in FIG8 , Schottky diode SBD2 and diode D2 are connected in series. The first channel layer 301 forms a resistor R. Resistor R is connected in series between the cathode of diode D1 and the cathode of diode D2.

[0118] In the example of FIG. 9 , in the protection device 30 , a first electrode of the Schottky diode SBD1 is electrically connected to the gate G of the transistor, and a second electrode of the Schottky diode SBD2 is electrically connected to the source S of the transistor.

[0119] The working principles of the protection device illustrated in Figures 8 and 9 include: for example, when the first electrode 303 is connected to a high potential and the second electrode 304 is connected to a low potential (for example, grounded), the Schottky diode SBD1 and the diode D1 are both forward-conducting and in the on state, and the Schottky diode SBD2 and the diode D2 are both in the reverse-cutoff state. When the voltage exceeds a certain threshold, the kinetic energy of the electrons in the first channel layer 301 increases, so that the kinetic energy of some of the electrons can overcome the potential barriers of the diode D2 and the Schottky diode SBD2, thereby escaping to the second electrode 304, so that the protection device forms a current channel, which protects the transistor and prevents overvoltage on the transistor gate.

[0120] On the contrary, when the second electrode 304 is connected to a high potential and the first electrode 303 is connected to a low potential, the Schottky diode SBD2 and the diode D2 are both forward-conducting and in the on state, and the Schottky diode SBD1 and the diode D1 are both in the reverse-cutoff state. When the voltage exceeds a certain threshold, the kinetic energy of the electrons in the first channel layer 301 increases, so that the kinetic energy of some of the electrons can overcome the potential barriers of the diode D1 and the Schottky diode SBD1, thereby escaping to the first electrode 303, so that the protective device forms a current channel, which protects the transistor and prevents overvoltage on the transistor gate.

[0121] Returning to Figure 6 , transistor 20 includes a second channel layer 201 with a second barrier layer 202 formed thereon. The second barrier layer 202 forms a heterojunction with the second channel layer 201, forming a two-dimensional electron gas (2DEG) channel under polarization. Both the source S and drain D of transistor 20 form ohmic contacts with the second channel layer 201.

[0122] In some examples, as shown in FIG. 6 , the first channel layer 301 of the protection device 30 and the second channel layer 201 of the transistor 20 are in the same channel layer, and the first channel layer 301 is electrically isolated from the second channel layer 201 .

[0123] 6 , the first barrier layer 302 of the protection device 30 and the second barrier layer 202 of the transistor 20 are in the same barrier layer, and the first barrier layer 302 is electrically isolated from the second barrier layer 202 .

[0124] In some embodiments, the first channel layer 301 and the second channel layer 201 located in the same channel layer are made of the same material, or have the same thickness.

[0125] In some implementation structures, the first barrier layer 302 and the second barrier layer 202 located in the same barrier layer are made of the same material, or have the same thickness.

[0126] In a feasible process, a stacked channel layer and a barrier layer can be formed on the substrate 10 , and then the channel layer and the barrier layer are patterned to form an electrically isolated second channel layer 201 and a first channel layer 301 , as well as an electrically isolated second barrier layer 202 and a first barrier layer 302 .

[0127] In some examples, the gate G of the transistor may be located in the same metal layer as the first electrode 303 and the second electrode 304 of the protection device.

[0128] For example, the gate G, the first electrode 303 and the second electrode 304 located in the same metal layer can be made of the same material, for example, at least one of Ni, Au, Pt and Ti.

[0129] The transistor 20 and protection device 30 of the present application are integrated on the same substrate 10 to form an on-chip protection semiconductor device. This effectively reduces damage to components caused by electrostatic discharge during the semiconductor device packaging process, reduces the ESD sensitivity and failure risk of the protected GaN HEMT device during the packaging process, and improves the yield and reliability of the semiconductor device.

[0130] In addition, when manufacturing the on-chip protective semiconductor device, the protected transistor and protective device can be manufactured using a front-end process. That is, the preparation process of the protective device is fully compatible with the process of the GaN HEMT device and does not pose any challenges to the process.

[0131] In addition, the protection device of the example of this application has a simple structure and occupies a small area, which can improve the integration density of the transistor.

[0132] In the semiconductor device of the present application example, the protected transistor can be not only an enhancement-mode GaN HEMT device, but also a depletion-mode GaN HEMT device.

[0133] In some other examples, such as Figure 10, Figure 10 is a structural diagram of another semiconductor device provided in the present application including a transistor 20 and a protective device 30. In this example, a buffer layer 40 may also be included, and the buffer layer 40 is stacked on the substrate 10, and the first channel layer 301 and the second channel layer 201 are stacked on the buffer layer 40.

[0134] In some other examples, a first cap layer 305 stacked on the first barrier layer 302 and a second cap layer 205 stacked on the second barrier layer 202 may be further included, and the first cap layer 305 and the second cap layer 205 are electrically isolated from each other.

[0135] In a feasible process, a buffer layer 40, a channel layer, a barrier layer and a cap layer can be sequentially formed on a substrate, and then the channel layer, the barrier layer and the cap layer are patterned to obtain the electrically isolated first channel layer 301 and the second channel layer 201, the electrically isolated first barrier layer 302 and the second barrier layer 202, and the electrically isolated first cap layer 305 and the second cap layer 205 as shown in FIG. 10 .

[0136] The buffer layer 40 includes but is not limited to a single layer or multiple layers of group IIIA nitrides and group IIIA nitrides, or a superlattice structure composed thereof. The buffer layer is used to buffer the stress between the substrate and the channel layer and improve the quality of epitaxial growth of the channel layer.

[0137] The first channel layer 301 and the second channel layer 201 may include gallium nitride (GaN) material. Either the first channel layer 301 or the second channel layer 201 may include one channel layer, or may include at least two stacked channel layers.

[0138] The first barrier layer 302 and the second barrier layer 202 may include, but are not limited to, Group IIIA nitrides and multi-component Group IIIA nitrides.

[0139] The first capping layer 305 and the second capping layer 205 may include, but are not limited to, grown nitride or oxide layers. For example, in some embodiments, a grown GaN single crystal layer may be selected, and in some embodiments, a grown polycrystalline SiNx layer may be selected.

[0140] In some examples, an isolation layer may be stacked between the first channel layer 301 and the first barrier layer 302 , and an isolation layer may be stacked between the second channel layer 201 and the second barrier layer 202 , and the two isolation layers may also be electrically isolated.

[0141] In some other examples, the gate G of the transistor may be stacked on the gate dielectric layer, and the gate dielectric layer may be stacked on the cap layer.

[0142] As shown in FIG11 , FIG11 shows the structure of the first electrode 303 and the second electrode 304. In this example, the first electrode 303 and the second electrode 304 are in a strip-shaped structure, and the interval S between the first electrode 303 and the second electrode 304 is shown.

[0143] The distance S between the first electrode 303 and the second electrode 304 can affect the turn-on voltage V of the protection device. ON .

[0144] For example, 0.5 μm ≤ S ≤ 20 μm. For example, 1 μm ≤ S ≤ 20 μm; or, 10 μm ≤ S ≤ 20 μm; or, 15 μm ≤ S ≤ 20 μm.

[0145] The first electrode 303 and the second electrode 304 have various shapes.

[0146] As shown in FIG11 , the first electrode 303 and the second electrode 304 may both be long strip structures.

[0147] As shown in FIG12 , the first electrode 303 and the second electrode 304 may be in a bent structure. In some examples, the bending angle of the first electrode 303 and the second electrode 304 may be close to 90°.

[0148] As shown in FIG. 13 , the first electrode 303 may be in a circular structure, and the second electrode 304 may be in a ring structure, where the second electrode 304 surrounds the periphery of the first electrode 303 .

[0149] As shown in FIG. 14 , the first electrode 303 may be in a ring structure, and the second electrode 304 may be in a ring structure, where the second electrode 304 surrounds the periphery of the first electrode 303 .

[0150] As shown in Figure 15 , there are multiple first electrodes 303 and multiple second electrodes 304. The multiple first electrodes 303 and the multiple second electrodes 304 are arranged alternately in a first direction parallel to the surface of the substrate. As shown in Figure 15 , the multiple first electrodes 303 and the multiple second electrodes 304 are arranged at intervals along a P direction parallel to the substrate.

[0151] When the electrode arrangement shown in FIG. 15 is adopted, the length of the first electrode 303 and the second electrode 304 can be increased, thereby increasing the current carrying capacity of the protective device.

[0152] In some examples, the length L of at least one of the first electrode 303 and the second electrode 304 is 100 μm ≤ L ≤ 1000 μm, for example, 500 μm ≤ L ≤ 1000 μm; or 500 μm ≤ L ≤ 800 μm; or 800 μm ≤ L ≤ 1000 μm.

[0153] As shown in FIG13 , the length dimensions of the first electrode 303 and the second electrode 304 in FIG13 can be understood as follows: the length dimension of the first electrode 303 is the circumference of the first electrode 303 , and the length dimension of the second electrode 304 is the circumference of the outer ring of the second electrode 304 .

[0154] As shown in FIG14 , the length dimensions of the first electrode 303 and the second electrode 304 in FIG14 can be understood as follows: the length dimension of the first electrode 303 is the circumference of the outer ring of the first electrode 303 , and the length dimension of the second electrode 304 is the circumference of the outer ring of the second electrode 304 .

[0155] In some examples, the width of the first electrode 303 and the second electrode 304 may affect the current flow capacity of the protection device.

[0156] The width d of the first electrode 303 and / or the second electrode 304 is 2 μm≤d≤20 μm, for example, 10 μm≤d≤20 μm, for another example, 10 μm≤d≤15 μm, and for another example, 10 μm≤d≤18 μm.

[0157] As shown in Figures 11, 12, and 15, the width dimension of the first electrode 303 is the dimension perpendicular to the extension direction. In Figure 13, the width dimension of the first electrode 303 is the diameter of the first electrode 303, and the width dimension of the second electrode 304 is the difference between the outer and inner diameters. In Figure 14, the width dimension of the first electrode 303 is the difference between the outer and inner diameters, and the width dimension of the second electrode 304 is the difference between the outer and inner diameters.

[0158] In this example, returning to FIG. 10 , the thickness of the first barrier layer 302 can affect the turn-on voltage V of the protection device.ON In some examples, the larger the thickness of the first barrier layer 302 is, the higher the threshold voltage V ON The thickness h of the first barrier layer 302 given in this application is 10nm≤h≤30nm. For example, 20nm≤h≤30nm; or 15nm≤h≤30nm; 18nm≤h≤30nm.

[0159] The composition of the first barrier layer 302 can also affect the turn-on voltage V ON In some examples, the material of the first barrier layer 302 includes Al x Ga 1-x N, 0.2≤x≤0.4. Al x Ga 1-x The Al content in N can affect the turn-on voltage V of the protection device. ON , for example, 0.3≤x≤0.4, or, 0.2≤x≤0.3, or, 0.3≤x≤0.35.

[0160] The protection device provided in this application has a turn-on voltage V ON Relatively large, for example, 5V≤V ON ≤100V, or 50V≤V ON ≤100V, 80V≤V ON ≤100V; 50V≤V ON ≤90V; 20V≤V ON ≤90V. This allows for overvoltage protection of the transistor gate even when the operating voltage of the protected transistor is high. Furthermore, the protection device has a simple structure and does not occupy a large area, thereby increasing the integration density of the protected transistor.

[0161] The protection device of the present application example not only turns on the voltage V ON The off-state leakage current is also small. For example, the off-state leakage current of the protection device is I, and I≤10 -2 mA / mm.

[0162] As shown in Figure 16, Figure 16 shows the IV characteristic curve, i.e., the current-voltage characteristic curve, of the protective device of the present application. In the graph, the horizontal axis of Curve 1 represents voltage (voltage) and the vertical axis represents current density (current density). The horizontal axis of Curve 2 represents voltage (voltage) and the vertical axis represents current (current). As shown in Figure 16, the turn-on voltage of the protective device is 34V, and the off-state leakage current is on the order of 0.1mA, which is very low.

[0163] In the semiconductor device of the present application example, multiple protected transistors are integrated, each of which can be arranged in an array on a substrate, and each transistor has a gate G, a source S, and a drain D. As shown in Figure 17, Figure 17 exemplarily shows six protected transistors, as well as the arrangement of the multiple gates G, multiple sources S, and multiple drains D included in the six transistors, wherein the multiple gates G, multiple sources S, and multiple drains D can be arranged in a direction parallel to the substrate, with the multiple gates G interconnected, the multiple sources S interconnected, and the multiple drains D interconnected.

[0164] The first electrode 303 in the protection device can be electrically connected to the interconnected gate G through a metal trace 1, and the second electrode 304 can be electrically connected to the interconnected source S through a metal trace 2. The transistor and the protection device for overvoltage protection of the transistor gate in the example of the present application can be manufactured through a front-end process, and the metal traces 1 and 2 shown in FIG17 can be manufactured in the interconnect trace layer through a back-end process.

[0165] That is, the production of protective devices can be completed in the front-end process, providing ESD protection functions for GaN HEMT devices during the back-end process to module packaging, reducing the ESD sensitivity and failure risk of the protected GaN HEMT devices in the above process, and improving the reliability of the devices.

[0166] The present application also provides a method for manufacturing a semiconductor device, as shown in FIG18 . FIG18 is a flowchart of the manufacturing method, and the manufacturing method includes:

[0167] S1: manufacturing transistors and protective devices on a substrate;

[0168] The protective device is made on the substrate and includes:

[0169] A first channel layer is formed on the substrate; a first barrier layer is formed on the first channel layer; a first electrode and a second electrode are formed on the first barrier layer, the first electrode is electrically isolated from the second electrode, and the first barrier layer corresponding to the position of the first electrode is electrically isolated from the first barrier layer corresponding to the position of the second electrode.

[0170] S2: electrically connecting the gate of the transistor to the first electrode of the protection device, and electrically connecting the source or drain of the transistor to the second electrode of the protection device.

[0171] The protective device manufactured using the method of the example of the present application includes a Schottky diode SBD1 formed by a first electrode and a first barrier layer, a diode D1 formed between the first barrier layer and the first channel layer corresponding to the position of the first electrode, and also includes a Schottky diode SBD2 formed by a second electrode and the first barrier layer, and a diode D2 formed between the first barrier layer and the first channel layer corresponding to the position of the second electrode.

[0172] Schottky diode SBD1 and diode D1 are connected in series, and Schottky diode SBD2 and diode D2 are connected in series, and are coupled between the gate and source (or drain) of the transistor.

[0173] For example, when the protected transistor is at a normal operating voltage, Schottky diode SBD1 and diode D1 are both forward-conducting and in the on state, while Schottky diode SBD2 and diode D2 are in the reverse-blocking state. However, when the gate of the transistor is overvoltage and the voltage exceeds a certain threshold, the kinetic energy of electrons in the channel of diode D2 and Schottky diode SBD2 increases, and the kinetic energy of some electrons overcomes the potential barrier of diode D2 and Schottky diode SBD2 and escapes to the second electrode, forming an electron leakage channel to protect the transistor from high-voltage shock.

[0174] In addition, the protection device provided in this application and the protected transistor are integrated on the same substrate to form an on-chip integrated protection device. In this way, the semiconductor device can provide ESD protection during the subsequent packaging process, for example, to reduce the ESD sensitivity of the protected transistor and even the risk of failure.

[0175] In some feasible processes, the protection device and the protected transistor can be manufactured using the front-end process. For example, the channel layer in the protection device and the channel layer in the transistor can be manufactured simultaneously using the same process; the barrier layer in the protection device and the barrier layer in the transistor can be manufactured simultaneously using the same process; the first and second electrodes of the protection device can be manufactured simultaneously with the gate of the transistor using the same process. This makes the protection device compatible with the transistor manufacturing process, facilitating process implementation.

[0176] The specific process flow involved in the above-mentioned method for preparing the semiconductor device is introduced below with reference to the accompanying drawings.

[0177] 19A to 19F illustrate the process structure after each step is completed in the process of manufacturing a semiconductor device according to an embodiment of the present application.

[0178] As shown in FIG19A , a buffer layer, a channel layer, a barrier layer and a cap layer are sequentially formed on a substrate.

[0179] In some other examples, an isolation layer may be further formed between the channel layer and the barrier layer.

[0180] The substrate may be silicon, silicon carbide, aluminum oxide, or a composite substrate formed based on the above substrates.

[0181] The buffer layer may be a Group IIIA nitride, such as AlN or AlGaN, and is used to buffer the stress between the substrate and the channel layer and improve the quality of epitaxial growth of the channel layer.

[0182] The barrier layer comprises aluminum gallium nitride (AlGaN) material. For example, a Group IIIA nitride barrier layer is disposed on top of a Group IIIA nitride channel layer. The Group IIIA nitride barrier layer is used to cooperate with the Group IIIA nitride channel layer to generate a 2DEG through polarization in the region where the Group IIIA nitride channel layer and the Group IIIA nitride barrier layer meet, thereby providing a channel for conducting current.

[0183] As shown in Figure 19B, the active area and the protection area of ​​the semiconductor device are isolated. The active area in the example of the present application can be understood as the area where the transistor is set, and the protection area is the area where the protection device is set.

[0184] In one feasible solution, the channel layer in the active area and the channel layer in the protection area can be cut off by forming a physical etching groove. The etching method can be at least one of reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), wet potassium hydroxide (KOH) solution, thermal oxidation followed by wet etching, and light-assisted electrochemical etching.

[0185] In another feasible solution, a shallow trench isolation (STI) process may be used to isolate the channel layer of the active area from the channel layer of the protection area.

[0186] In the example of FIG19B , the active area and the protection area are isolated by etching a groove, and the groove passes through the cap layer to the buffer layer.

[0187] As shown in FIG19C , the grooves are etched. The grooves in this step can be etched using at least one of reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), wet potassium hydroxide (KOH) solution, thermal oxidation followed by wet etching, and light-assisted electrochemical etching.

[0188] The bottom end position of the groove may be the surface of the channel layer, or the end position may be ±0.5 nm from the surface of the channel layer.

[0189] In some feasible processes, after etching the grooves, the surface roughness RMS of the trench layer is less than or equal to 0.3 nm, or is close to the surface roughness of the epitaxially grown cap layer.

[0190] As shown in FIG19D , a source electrode S and a drain electrode D are formed in the grooves etched in the active region of FIG19C , and are in ohmic contact with the channel layer.

[0191] In one achievable method, the ohmic contact source S and drain D are formed by sputtering or evaporative deposition followed by etching or stripping. Optional implementation schemes for the source S and drain D include high temperature annealing, ion implantation or secondary epitaxy.

[0192] For example, when high-temperature annealing is used to make the ohmic contact source S and drain D, at least one material among Ti, Al, Ni, and Au can be selected, and the ohmic metal is subjected to high-temperature annealing treatment at 800°C-900°C in a nitrogen atmosphere to obtain the ohmic contact of the source S and drain D.

[0193] For another example, in the case of an ion implantation ohmic contact scheme, the ohmic contact area is first implanted with ions, where the implanted ions may be elements such as Si or Ge, and then an annealing activation treatment is performed at a high temperature above 1000°C.

[0194] For example, to produce ohmic contacts using secondary epitaxial growth technology, epitaxial growth must be performed at a high temperature of over 1000°C.

[0195] The source electrode S or the drain electrode D may be a single-layer structure or a stacked multi-layer structure, for example, a stacked Ti layer, an Al layer, a Ni layer, and an Au layer.

[0196] As shown in FIG19E , the gate G of the transistor, the first electrode and the second electrode of the protective device are obtained.

[0197] In a feasible solution, the gate G of the transistor, the first electrode and the second electrode of the protection device may be deposited and grown simultaneously, or may be deposited and grown separately.

[0198] The options for depositing metal include but are not limited to at least one of Ni and Au, or at least one of Pt, Ti, and Au, or at least one of W, Ti, and Au, or at least one of TiN and Cu.

[0199] The gate G, first electrode, or second electrode of the transistor may be a single-layer structure or a stacked multi-layer structure. For example, it may be a stacked Ni layer and Au layer; another example, it may be a stacked Pt layer, Ti layer, and Au layer; another example, it may be a stacked W layer, Ti layer, and Au layer; another example, it may be a stacked TiN layer and Cu layer.

[0200] In another process step, before the gate G is formed, a gate dielectric layer may be formed, and then the gate G may be formed on the gate dielectric layer.

[0201] As shown in FIG19F , an interconnection wiring layer is fabricated using a back-end process. For example, metal wiring is deposited and then electrically connected to the transistor and the protection device. The gate G of the transistor is electrically connected to the first electrode, and the source S of the transistor is electrically connected to the second electrode.

[0202] In an implementable solution, the metal traces may be formed by electroplating, sputtering, or evaporation, and the metal types include but are not limited to one or more of Ni, Au, Cu, Pt, Ti, and W.

[0203] In other achievable process steps, the method shown in Figures 20A to 20F can also be used. Figures 20A to 20F illustrate the process structure after each step is completed in another process of manufacturing a semiconductor device according to an embodiment of the present application.

[0204] As shown in FIG20A , a buffer layer, a channel layer, a barrier layer and a cap layer are sequentially formed on a substrate.

[0205] As shown in FIG20B , the structure shown in FIG20A is patterned using photolithography mask technology to expose the source S and drain D to be prepared for ohmic contact, as well as the groove area of ​​the protective device. Then, dry etching is used to sequentially etch away the cap layer and barrier layer in these areas, and the photolithography mask layer is removed to complete wafer cleaning, thereby obtaining the structure shown in FIG20B .

[0206] In some examples, the bottom surface roughness of the etched grooves is less than 0.3 nm.

[0207] The stop position of the etched groove is ±0.5 nm from the surface of the trench layer.

[0208] The width of the etched groove of the protection device may be 3 μm, and the length of the etched groove may be 600 μm.

[0209] As shown in FIG20C , the source S and drain D of the transistor are formed in the groove formed in FIG20B for forming the ohmic contact layer, and the etched groove of the protection device is retained.

[0210] As shown in FIG20D , ion implantation is used to isolate the active region of the transistor from the region outside the protective device. For example, high-energy N ions can be used. The purpose of the ion implantation is to destroy the 2DEG channel in the non-functional region. After isolation, the leakage current between the functional regions can be less than or equal to 1 nA / mm.

[0211] After isolation, the leakage current between functional areas can be less than or equal to 1nA / mm. This can be understood as: the leakage current between protected transistors can be less than or equal to 1nA / mm, or the leakage current between the protected transistor and the protection device can be less than or equal to 1nA / mm.

[0212] The functional area in the example of this application can be understood as the area where the transistor is set (the area where the two-dimensional electron gas channel needs to be retained), and the non-functional area can be understood as the area where the two-dimensional electron gas channel does not need to be retained.

[0213] As shown in FIG20E , the gate G of the transistor may be formed by electron beam evaporation to form the first electrode and the second electrode of the protective device.

[0214] As shown in FIG20F , an interconnection wiring layer is fabricated using a back-end process. For example, metal wiring is deposited and then electrically connected to the transistor and the protection device using the metal wiring. The gate G of the transistor is electrically connected to the first electrode, and the source S of the transistor is electrically connected to the second electrode.

[0215] As shown in FIG21 , in the manufactured semiconductor device, a dielectric layer is filled in the groove between the first electrode and the second electrode and in the groove extending through the channel layer. The dielectric layer is used to electrically isolate the first electrode from the second electrode and to switch the two-dimensional electron gas channel of the protection device.

[0216] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0217] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A transistor and a protection device disposed on the substrate; The protection device includes: A first channel layer formed on the substrate; A first barrier layer formed on the first channel layer; A first electrode and a second electrode, both the first electrode and the second electrode are disposed on the first barrier layer, and the first electrode and the second electrode are electrically isolated; The first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode are electrically isolated; The gate of the transistor is electrically connected to the first electrode, and the source or drain of the transistor is electrically connected to the second electrode.

2. The semiconductor device according to claim 1, wherein A second channel layer is further formed on the substrate, and the second channel layer is electrically isolated from the first channel layer; A second barrier layer is formed on the second channel layer, and the second barrier layer is electrically isolated from the first barrier layer; The source and drain of the transistor are both in ohmic contact with the second channel layer.

3. The semiconductor device according to claim 2, characterized in that, The first channel layer and the second channel layer are located in the same channel layer, and the first barrier layer and the second barrier layer are located in the same barrier layer.

4. The semiconductor device according to claim 2 or 3, wherein The gate of the transistor is located on the side of the second barrier layer away from the second channel layer; the gate of the transistor, the first electrode and the second electrode are located in the same metal layer.

5. The semiconductor device according to any one of claims 1-4, wherein There is a dielectric layer between the first electrode and the second electrode; There is the dielectric layer between the first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode.

6. The semiconductor device according to any one of claims 1-5, characterized in that, There are multiple first electrodes and multiple second electrodes; The multiple first electrodes and the multiple second electrodes are arranged alternately in a first direction, and the first direction is parallel to the surface of the substrate.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The distance S between the first electrode and the second electrode satisfies 0.5μm ≤ S ≤ 20μm.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The width d of the first electrode and / or the second electrode satisfies 2μm ≤ d ≤ 20μm.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The material of the first barrier layer includes Al x Ga 1-x N, where 0.2 ≤ x ≤ 0.

4.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The thickness h of the first barrier layer satisfies 10nm ≤ h ≤ 30nm.

11. The semiconductor device according to any one of claims 1-10, characterized in that, The turn-on voltage V of the protection device ON , 5V ≤ V ON ≤ 100V.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The off-state leakage current I of the protection device, I ≤ 10 -2 mA / mm.

13. The semiconductor device according to any one of claims 1-12, characterized in that, There is an interconnect wiring layer on the side of the transistor and the protection device away from the substrate; The gate of the transistor is electrically connected to the first electrode through the interconnect wiring layer; The source or drain of the transistor is electrically connected to the second electrode through the interconnect wiring layer.

14. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Fabricating a transistor and a protection device on a substrate; Electrically connecting the gate of the transistor to the first electrode of the protection device, and the source or drain of the transistor to the second electrode of the protection device; Fabricating the protection device on the substrate includes: Fabricating a first channel layer on the substrate; Fabricating a first barrier layer on the first channel layer; Fabricating the first electrode and the second electrode on the first barrier layer, the first electrode and the second electrode are electrically isolated, and the first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode are electrically isolated.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, Fabricating the transistor and the protection device on the substrate includes: Fabricating a channel layer on the substrate; Fabricating a barrier layer on the channel layer; Electrically isolating the active region for fabricating the transistor and the region for fabricating the protection device, so as to fabricate the stacked first channel layer and the first barrier layer in the region of the protection device, and fabricate the stacked second channel layer and the second barrier layer in the active region, where the first channel layer is electrically isolated from the second channel layer, and the first barrier layer is electrically isolated from the second barrier layer.

16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, After fabricating the barrier layer on the channel layer, the fabrication method further includes: Etching a groove in the region for fabricating the protection device, where the groove penetrates the barrier layer; Fabricating the first electrode and the second electrode on the barrier layer separated by the groove.

17. The method for manufacturing a semiconductor device according to any one of claims 14-16, characterized in that, When fabricating the first electrode and the second electrode on the first barrier layer, it further includes: Fabricating the gate of the transistor.

18. The method for manufacturing a semiconductor device according to any one of claims 14-17, characterized in that, When fabricating the first electrode and the second electrode on the first barrier layer, it includes: Fabricating a plurality of the first electrodes and a plurality of the second electrodes along a first direction parallel to the surface of the substrate, where the plurality of the first electrodes and the plurality of the second electrodes are arranged alternately in the first direction.

19. The method for manufacturing a semiconductor device according to any one of claims 14-18, characterized in that, After fabricating the transistor and the protection device on the substrate, the fabrication method further includes: Fabricating an interconnection trace layer on a side of the transistor and the protection device facing away from the substrate, where the gate of the transistor is electrically connected to the first electrode through the interconnection trace layer, and the source or drain of the transistor is electrically connected to the second electrode through the interconnection trace layer.

20. An electronic device, characterized in that, Including: A substrate; The semiconductor device according to any one of claims 1-13, where the semiconductor device is disposed on the substrate.

Images