Memory array and manufacturing method therefor, and memory and electronic device

Abstract

The present application relates to the technical field of electronics. Provided are a memory array and a manufacturing method therefor, and a memory and an electronic device, which are used for solving the problem of a capacitor structure in a memory having a low density of integration. The memory array comprises: a substrate, and a capacitor unit arranged on the substrate. The capacitor unit comprises a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode and the third electrode all extend in the thickness direction of the substrate, the first electrode is arranged around the second electrode, and the second electrode is arranged around the third electrode. The capacitor unit further comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged between the first electrode and the second electrode, and the second dielectric layer is arranged between the second electrode and the third electrode. The memory array is used for improving the density of integration of a capacitor structure.

Description

Storage array and preparation method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 26, 2023, with application number 202311816759.2 and application name “Memory Array and Preparation Method thereof, Memory, Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a storage array and a preparation method thereof, a memory, and an electronic device. Background Art

[0003] With the rapid development of artificial intelligence, big data, and big models, people are paying more and more attention to the data generated by various activities. By analyzing this data, we can obtain the desired information. For example, by analyzing the user's search data, browsing data, and purchase data on shopping websites, we can create a profile of a specific user, thereby achieving precise advertising, improving the user experience and increasing the conversion rate of advertising transactions. For example, by obtaining passenger information on a city's subway, bus, shared bicycles, etc., we can optimize subway and bus route planning, departure time intervals on the same route, and the deployment of shared bicycles. Obviously, after obtaining this data, it is necessary to store it, or when analyzing this data, it is necessary to store this data in memory or cache. The device that stores data is a memory.

[0004] Based on volatility, memory can be categorized as volatile memory and non-volatile memory. Volatile memory is typically used as internal memory or cache, while non-volatile memory is typically used as external storage. Volatile memory is a type of memory whose stored information disappears when the current or voltage is interrupted, whereas non-volatile memory does not.

[0005] In some technologies, the storage cells of memory typically utilize capacitor structures, which store data by charging and discharging the capacitor structures. To ensure efficient data storage, the capacitor structures must meet certain requirements. In existing technologies, to meet these requirements, the capacitor structures must be relatively large, making further reduction difficult. Therefore, increasing the integration density of capacitor structures in memory is an urgent issue.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a memory array and a method for manufacturing the same, a memory, and an electronic device to solve the problem of low integration density of capacitor structures in the memory.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, an embodiment of the present application provides a storage array comprising a substrate and a capacitor unit, wherein the capacitor unit is arranged on the substrate, the capacitor unit comprising a first electrode, a second electrode, and a third electrode, the first electrode, the second electrode, and the third electrode all extending along the thickness direction of the substrate, the first electrode being arranged around the second electrode, and the second electrode being arranged around the third electrode; the capacitor unit also comprises a first dielectric layer and a second dielectric layer, the first dielectric layer being arranged between the first electrode and the second electrode, and the second dielectric layer being arranged between the second electrode and the third electrode.

[0010] The capacitor cell in the memory array includes a first electrode, a second electrode, and a third electrode. A first dielectric layer is disposed between the first electrode and the second electrode, and a second dielectric layer is disposed between the second electrode and the third electrode. Thus, the first electrode, the second electrode, and the first dielectric layer form one capacitor, and the second electrode, the third electrode, and the second dielectric layer form another capacitor. In other words, the capacitor cell forms two capacitors using three electrodes, and the two capacitors share the second electrode. Thus, forming two capacitors eliminates one electrode, thereby reducing the size of the capacitor. Furthermore, because the first, second, and third electrodes extend along the thickness of the substrate, the formed capacitor cell also extends in the thickness direction. This reduces the area occupied by the capacitor cell on the substrate surface, increasing the process window. Finally, the first electrode surrounds the second electrode, and the second electrode surrounds the third electrode. The capacitor formed by the second electrode, the third electrode, and the second dielectric layer is nested within the capacitor formed by the first electrode, the second electrode, and the first dielectric layer. Furthermore, to meet read window requirements, the capacitor of the memory cell needs to have a certain capacitance value. This can be achieved by having the capacitor electrodes be larger than a certain area. By having the first electrode surround the second electrode and the second electrode surround the third electrode, the electrode area can be increased, thereby increasing the capacitance value of the capacitor. Therefore, when the capacitance of the capacitors is equal, the volume of the capacitors can be further reduced. Reducing the volume of the capacitors can improve the integration density of the capacitors and increase the storage density of the memory cells.

[0011] In one possible implementation of the first aspect, at least a portion of the second electrode is cylindrical, and at least a portion of the first electrode is cylindrical. In this manner, the cylindrical portion of the second electrode can be formed by depositing a conductive material on the inner surface of the deep hole. The cylindrical portion of the first electrode can also be formed by forming a second dielectric layer outside the second electrode and then depositing a conductive material. In this manner, the second electrode and the first electrode can be formed using mature semiconductor processes.

[0012] In one possible implementation of the first aspect, the first dielectric layer and the second dielectric layer are connected on a side away from the substrate. In this manner, after forming the second electrode, a dielectric material can be deposited on the surface of the second electrode to simultaneously form the first and second dielectric layers, thereby reducing process steps.

[0013] In one possible implementation of the first aspect, the memory array includes a plurality of capacitor units arranged in an array, wherein the third electrodes of any two adjacent capacitor units in a row are connected, or the first electrodes are connected. In this way, the capacitors included in all capacitor units in a row can be connected in series, thereby forming a memory.

[0014] In one possible implementation of the first aspect, the memory array further includes a first connection structure disposed on a side of two adjacent capacitor cells that is remote from the substrate, and the third electrodes of the two adjacent capacitor cells are connected via the first connection structure. Thus, by disposing the first connection structure on a side remote from the capacitor cells, the first connection structure can be formed after the capacitor cells are formed, facilitating the provision of the first connection structure in the memory array.

[0015] In one possible implementation of the first aspect, the memory array further includes: a plurality of transistors disposed between the substrate and the plurality of capacitor cells; and a contact structure, one end of the contact structure being connected to the first connection structure and the other end being connected to at least one transistor. Thus, the first connection structure connected to the third electrodes of two adjacent capacitor cells can be connected to the transistor via the contact structure, allowing the transistor to control the storage state of the capacitor where the third electrode is located.

[0016] In one possible implementation of the first aspect, the third electrodes, first connection structures, and contact structures of two adjacent capacitor cells are made of the same material and are integrally configured. This ensures good contact at the interface between the third electrodes, first connection structures, and contact structures, preventing interdiffusion due to different materials that could affect resistance at the connection.

[0017] In one possible implementation of the first aspect, the memory array further includes a second connection structure disposed between two adjacent capacitor units and close to the substrate, wherein the first electrodes of the two adjacent capacitor units are connected via the second connection structure. Thus, the first electrodes of the two adjacent capacitor units are connected via the second connection structure. Because the second connection structure is disposed close to the substrate, it facilitates formation of the second connection structure on the substrate surface.

[0018] In one possible implementation of the first aspect, the memory array further includes a plurality of transistors disposed between the substrate and the plurality of capacitor units; the second connection structure is in contact with at least one of the transistors. Thus, the second connection structure can be directly disposed on the transistor formed on the substrate and in contact with the transistor.

[0019] In a possible implementation of the first aspect, the first electrodes and the second connection structures of two adjacent capacitor units are made of the same material and are integrally provided, so that the second connection structure can be prepared while the first electrodes are deposited.

[0020] In one possible implementation of the first aspect, the memory array further includes a first connection structure and a second connection structure, and the first connection structure and the second connection structure are alternately arranged in a row of capacitor cells. Thus, a first electrode of a capacitor cell in a row can be connected to a first electrode of a preceding capacitor via the second connection structure, and a third electrode of the capacitor cell can be connected to a third electrode of a succeeding capacitor via the first connection structure, thereby achieving a series connection of the capacitors in a row.

[0021] In one possible implementation of the first aspect, the multiple transistors of the memory array include a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to the first electrode, a second electrode of the first transistor and a first electrode of the second transistor are both connected to the second electrode, and a second electrode of the second transistor is connected to the third electrode. In this way, each capacitor in a capacitor unit is connected in parallel with a transistor.

[0022] In one possible implementation of the first aspect, the second electrode of the first transistor is the same electrode as the first electrode of the second transistor; the second electrode includes a cylindrical first portion and a second portion located at an end of the first portion proximal to the substrate, with an edge of the second portion connected to the end of the first portion proximal to the substrate, and the second portion contacting the same electrode. In this manner, the first and second portions of the second electrode can be simultaneously formed by deposition on the inner surface of a deep hole formed in the same gate electrode, saving process steps.

[0023] In one possible implementation of the first aspect, a memory array includes multiple transistors arranged in an array configuration, with a row of transistors connected in series and correspondingly connected to a row of capacitor cells. The memory array also includes multiple word lines embedded in a substrate, with each word line connected to the gates of a column of transistors. Because the multiple word lines are embedded in the substrate, transistors can be formed on only one side of the substrate surface, while capacitor cells can be formed on the other side of the substrate surface, facilitating corresponding connections between a row of transistors and a row of capacitor cells.

[0024] In one possible implementation of the first aspect, the memory array further includes a first bit line and a second bit line; the multiple transistors in the memory array include a first transistor and a second transistor, wherein the first electrode of the first transistor is connected to the first bit line, the second electrode of the first transistor is connected to the first electrode, the first electrode of the second transistor is connected to the third electrode, and the second electrode of the second transistor is connected to the second bit line; and the second electrode is connected to a power signal terminal. In this way, one transistor is connected to one electrode of a capacitor in a capacitor cell, and an electrode shared by two capacitors in the capacitor cell, namely the second electrode, is connected to the power signal terminal, thereby enabling one transistor to control the storage state of one capacitor.

[0025] In a possible implementation of the first aspect, the first dielectric layer and the second dielectric layer are both made of ferroelectric materials. In this way, the capacitor formed is a ferroelectric capacitor, which is beneficial for improving the read and write speed and durability of the memory array.

[0026] In a second aspect, the present application provides a method for preparing a storage array, comprising: forming a second electrode on a substrate, the second electrode extending along the thickness direction of the substrate; forming a first dielectric layer on one side of the second electrode, and forming a second dielectric layer on the other side of the second electrode; forming a first electrode on a side of the first dielectric layer away from the second electrode, and forming a third electrode on a side of the second dielectric layer away from the second electrode, wherein the first electrode and the second electrode extend along the thickness direction of the substrate, the second electrode surrounds the first electrode, and the third electrode surrounds the second electrode.

[0027] In one possible implementation of the second aspect, the first dielectric layer and the second dielectric layer are formed simultaneously. In this way, after forming the second electrode, a dielectric material can be deposited on the surface of the second electrode to form the first dielectric layer and the second dielectric layer, thereby saving process steps.

[0028] In a third aspect, the present application provides a memory comprising a peripheral circuit and a memory array as described in any one of the first aspects, wherein the peripheral circuit is electrically connected to the memory array. Since the memory adopts the memory array described in the first aspect, the memory also has a high storage density.

[0029] In a fourth aspect, the present application provides an electronic device comprising a printed circuit board and the memory according to the third aspect, wherein the memory is disposed on the printed circuit board. Since the electronic device employs the memory according to the third aspect, the electronic device also has good storage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0031] FIG2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0032] FIG3 is a schematic diagram of a top view and a schematic diagram of a front cross-sectional structure of a storage array provided in an embodiment of the present application;

[0033] FIG4 is a schematic diagram of the cross-sectional structure of the storage array taken along line AA in FIG3 ;

[0034] FIG5 is a schematic diagram of the structure of a capacitor unit in a storage array provided by an embodiment of the present application;

[0035] FIG6 is a circuit diagram of the memory array in FIG3 ;

[0036] FIG7 is a schematic diagram of a front cross-sectional structure of another storage array provided in an embodiment of the present application;

[0037] FIG8 is a schematic diagram of a top view of the storage array in FIG7 ;

[0038] FIG9 is a flow chart of manufacturing a memory array according to an embodiment of the present application;

[0039] FIG10 is a schematic diagram of the three-dimensional structure of a substrate provided for preparing a memory array in an embodiment of the present application;

[0040] FIG11 is a schematic diagram of the cross-sectional structure along the BB direction in FIG10;

[0041] FIG12 is a schematic diagram of the structure of the memory array after forming the second electrode in an embodiment of the present application;

[0042] FIG13 is a schematic diagram of the cross-sectional structure along the CC direction in FIG12;

[0043] FIG14 is a schematic diagram of the structure of a memory array after removing the sacrificial layer in an embodiment of the present application;

[0044] FIG15 is a schematic diagram of the cross-sectional structure along the EE direction in FIG14;

[0045] FIG16 is a schematic structural diagram of a memory array after forming a first dielectric layer and a second dielectric layer in an embodiment of the present application;

[0046] FIG17 is a schematic diagram of the cross-sectional structure along the FF direction in FIG16;

[0047] FIG18 is a schematic diagram of the structure of a memory array after removing part of the dielectric layer in an embodiment of the present application;

[0048] FIG19 is a schematic diagram of the cross-sectional structure along the GG direction in FIG18;

[0049] FIG20 is a schematic structural diagram of a second connection structure formed after removing excess conductive material from a memory array in an embodiment of the present application;

[0050] FIG21 is a schematic diagram of the cross-sectional structure along the HH direction in FIG20;

[0051] FIG22 is a schematic structural diagram of a first connection structure formed after removing excess conductive material from a memory array in an embodiment of the present application;

[0052] FIG23 is a schematic diagram of the cross-sectional structure along the II direction in FIG22 . DETAILED DESCRIPTION

[0053] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0054] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0055] FIG1 is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 can be a terminal device such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 includes a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0056] The system-on-chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system-on-chip 210 may include one or more processors, such as an application processor (AP) 211 for processing applications and a graphics processing unit (GPU) 212 for processing image data. The system-on-chip 210 may also include a first random access memory (RAM) 213 for caching high-speed data. The first random access memory 213 may be electrically connected to the processor of the system-on-chip 210. The first random access memory 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash).

[0057] The application processor 211 , the image processing unit 212 and the first random access memory 213 may be integrated into one die, or may be separately provided in multiple die.

[0058] The electronic device 200 may further include a second random access memory 220 electrically connected to the system-on-chip 210 via the bus 205. The second random access memory 220 may be a dynamic random access memory (DRAM). The second random access memory 220 may be used to store volatile data, such as temporary data generated by the system-on-chip 210. The storage capacity of the second random access memory 220 is generally greater than that of the first random access memory 213, but the read speed is generally slower than that of the first random access memory 213.

[0059] In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the system-on-chip 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the system-on-chip 210 and the second random access memory 220 may be packaged in a package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster data transmission rate between chips.

[0060] Figure 2 is a schematic diagram of the structure of a memory 300 provided in an embodiment of the present application. In one embodiment, the memory 300 may be the first random access memory 213 shown in Figure 1 or the second random access memory 220. This application does not limit the application scenario of the memory 300.

[0061] The memory 300 includes the memory array 100 and a controller. The controller may include one or more peripheral circuits such as a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 , or an input / output driver 360 .

[0062] In one embodiment, the memory array 100 includes a plurality of memory cells 400 arranged in an array. The memory cell 400 may include a capacitor. For example, 1 bit or multiple bits of data may be stored by charging and discharging the capacitor. The memory array 100 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to a corresponding signal line. One or more of the above signal lines can be used to select a memory cell 400 to be read or written in the memory array by receiving a control level output by a controller, so as to change the charge and discharge state of the capacitor in the memory cell 400, thereby realizing data reading and writing operations.

[0063] Decoder 320 is used to decode the address of storage cell 400. Decoder 320 decodes the received address to determine the storage cell 400 to be accessed. Driver 330 controls the signal line level based on the decoding result generated by decoder 320, thereby enabling access to the specified storage cell 400. Buffer 350 caches read data, for example, using a FIFO (first-in, first-out) buffering mechanism. Timing controller 340 controls the timing of buffer 350 and controls driver 330 to drive signal lines in storage array 100. Input / output driver 360 drives transmission signals, such as received data signals and transmitted data signals, allowing data signals to be transmitted over long distances. The storage array 100, decoder 320, driver 330, timing controller 340, buffer 350, and input / output driver 360 can be integrated into a single chip or integrated into multiple chips.

[0064] To improve the storage density of a memory 300, the present application proposes a memory array 100, as shown in Figures 3 and 4, wherein Figure 3 is a schematic top view of the memory array 100, and Figure 4 is a schematic cross-sectional view of the memory array 100 along the AA direction in Figure 3. The memory array 100 includes a substrate 110 and a capacitor unit 120 disposed on the substrate 110.

[0065] The substrate 110 may be made of silicon or other semiconductor materials, which may include, for example, doped and / or undoped semiconductor materials. The substrate 110 may include other elemental semiconductor materials such as germanium (Ge). In some embodiments, the substrate 110 may be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate 110 may be made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). In some embodiments, the substrate 110 includes an epitaxial layer. For example, the substrate 110 has an epitaxial layer located above a semiconductor body. In some embodiments, the substrate 110 may also be a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) substrate.

[0066] Capacitor unit 120 is disposed on substrate 110. FIG5 is a schematic diagram of the structure of capacitor unit 120. Referring to FIG4 and FIG5 , capacitor unit 120 includes a first electrode 121, a second electrode 123, and a third electrode 125. Each of first electrode 121, second electrode 123, and third electrode 125 extends along a thickness direction D of substrate 110. For example, first electrode 121, second electrode 123, and third electrode 125 may be disposed perpendicular to the surface of substrate 110. First electrode 121 surrounds second electrode 123, and second electrode 123 surrounds third electrode 125. That is, first electrode 121 at least partially surrounds second electrode 123, and second electrode 123 at least partially surrounds third electrode 125. First electrode 121, second electrode 123, and third electrode 125 may comprise a conductive material, which may be one or more of doped polysilicon, a metal, or a metal compound material, as well as various other suitable electrode materials, such as titanium nitride (TiN), tungsten (W), or molybdenum (Mo).

[0067] Capacitor unit 120 further includes a first dielectric layer 127 and a second dielectric layer 129. First dielectric layer 127 is disposed between first electrode 121 and second electrode 123, separating first electrode 121 from second electrode 123. Second dielectric layer 129 is disposed between second electrode 123 and third electrode 125, separating second electrode 123 from third electrode 125. Thus, first electrode 121, second electrode 123, and first dielectric layer 127 form one capacitor 1201b, while second electrode 123, third electrode 125, and second dielectric layer 129 form another capacitor 1201a. In other words, one capacitor unit 120 includes two capacitors, and these two capacitors share one electrode, namely, second electrode 123. Forming two capacitors eliminates one electrode, reducing the size of the capacitors and facilitating increased integration density of memory array 100. In addition, the capacitor of the capacitor unit 120 needs to have a certain capacitance value. Increasing the capacitance value can be achieved by making the capacitor electrode larger than a certain area. By having the first electrode 121 surround the second electrode 123 and the second electrode 123 surround the third electrode 125, the area of ​​the electrode can be increased, thereby increasing the capacitance value of the capacitor to meet the requirements of the reading window.

[0068] In some embodiments, at least a portion of the first electrode 121 may be cylindrical, and at least a portion of the second electrode 123 may also be cylindrical. The cylindrical shape may have a thin wall, and the cross-section perpendicular to the thin wall is a hollow closed figure. The space surrounded by the thin wall is connected to the outside at both ends of the thin wall. For example, the cylindrical shape may be a tube, and its cross-section may be a circular ring. In this way, the second electrode 123 can be inserted into the first electrode 121, that is, the first electrode 121 is arranged around the second electrode 123. The third electrode 125 may be at least partially cylindrical or cylindrical. In this case, the first electrode 121 and the second electrode 123 extending along the thickness direction D of the substrate 110 may be a thin wall extending along the thickness direction D of the substrate 110. The thickness of the first electrode 121 and the second electrode 123 may be the same or different. The thickness of the first electrode 121 and the second electrode 123 may range from 5 nm to 15 nm, for example, 5 nm, 8 nm, 15 nm, etc.

[0069] In some embodiments, the first dielectric layer 127 and the second dielectric layer 129 may be made of dielectric materials, which may be ceramics such as aluminum oxide (Al2O3) or barium titanate (BaTiO3), or organic polymers such as polyacrylate (PPS) or polyimide (PI), or other appropriate dielectric materials.

[0070] In some possible embodiments, the first dielectric layer 127 and the second dielectric layer 129 may be made of ferroelectric materials, such as lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), hafnium oxide-based materials, perovskite materials (e.g., calcium titanate), and lanthanum bismuth titanate, or other ferroelectric materials. In some possible embodiments, the ferroelectric material may include a hafnium oxide-based material and / or a zirconium oxide-based material. In addition, the hafnium oxide-based material or the zirconium oxide-based material may be doped with at least one of the following: silicon (Si), aluminum (Al), germanium (Ge), magnesium (Mg), calcium (Ca), strontium (Sr), niobium (Nb), yttrium (Y), barium (Ba), and titanium (Ti). In this case, a memory formed by using a ferroelectric material as the dielectric layer of a capacitor unit may be called a ferroelectric memory, which has advantages such as high speed, good durability, and non-volatility.

[0071] In some embodiments, the thicknesses of the first dielectric layer 127 and the second dielectric layer 129 can be the same or different. For example, the thickness of the first dielectric layer 127 is less than the thickness of the second dielectric layer 129. In this way, by adjusting the thicknesses of the first dielectric layer 127 and the second dielectric layer 129, the capacitance values ​​of the two capacitors in the capacitor unit 120 can be as equal as possible. The thickness of the first dielectric layer 127 or the second dielectric layer 129 can range from 5 nm to 15 nm, for example, 5 nm, 8 nm, 15 nm, etc.

[0072] In some embodiments, the first dielectric layer 127 and the second dielectric layer 129 can be formed on both sides of the second electrode 123 through a deposition process. It is easy to understand that in order to space adjacent electrodes apart, the first dielectric layer 127 and the second dielectric layer 129 can also extend along the thickness direction D of the substrate 110. In addition, the first dielectric layer 127 and the second dielectric layer 129 can be connected on the side away from the substrate 110, thereby, the first dielectric layer 127 and the second dielectric layer 129 can be provided integrally. Therefore, the first dielectric layer 127 and the second dielectric layer 129 can also be formed simultaneously through the same process. The first dielectric layer 127 and the second dielectric layer 129 can be formed using a suitable process such as a sputtering process or an ALD process.

[0073] In some embodiments, the memory array 100 may adopt a 1T1C (1 transistor 1 capacity) memory architecture. It is readily understood that although this application only uses the 1T1C memory architecture as an example, the inventive concept of this application may also be applied to 1TnC and nTmC memory architectures.

[0074] Please refer to FIG6 , which is a circuit schematic diagram of the memory array 100 in FIG3 and FIG4 . The memory array 100 may include a plurality of word lines WL arranged along a first direction, such as word line WL(1) and word line WL(2), and a plurality of bit lines BL arranged along a second direction, such as bit line BL(1) and bit line BL(2), wherein the first direction and the second direction intersect. The bit lines BL may include a plurality of capacitors 1201 and a plurality of transistors 140, wherein the plurality of capacitors 1201 are arranged in series, and each capacitor 1201 is arranged in parallel with a transistor 140. That is, the bit lines BL may include a plurality of capacitors 1201 arranged in series, and each capacitor 1201 is arranged in parallel with a transistor 140. The capacitor 1201 and the transistor 140 being connected in parallel means that the first electrode and the second electrode of the transistor 140 are respectively connected to the two electrodes of the capacitor 1201. Since the plurality of capacitors 1201 are arranged in series, the plurality of transistors 140 are also arranged in series.

[0075] In addition, the gate of each transistor 140 is connected to a word line WL. The same word line WL can be connected to the gates of multiple transistors 140 located in different bit lines BL.

[0076] Thus, in the initial state of writing or erasing data to a capacitor in the memory array 100, the bit line BL corresponding to the capacitor is set to a high level. The multiple transistors 140 included in the bit line BL are arranged in series, and all of the multiple transistors 140 are turned on, that is, the word lines WL connected to the gates of the multiple transistors 140 are all set to a high level. In this way, when writing or erasing data stored in the capacitor, the transistor 140 corresponding to the capacitor can be disconnected, that is, the word line corresponding to the transistor 140 is set to a low level, resulting in a large voltage drop across the capacitor, thereby enabling data writing or erasing. When reading the storage state of the capacitor, the storage state of the selected capacitor can be determined by controlling the voltage of the word line WL and the bit line BL and integrating the read current between the word line WL and the bit line BL.

[0077] Based on the above circuit structure, please continue to refer to Figures 3 and 4. The storage array 100 may include a plurality of capacitor units 120 as described above. A plurality of capacitor units 120 may be arranged in an array, that is, a plurality of capacitor units 120 may be arranged in multiple rows and columns, wherein the rows may extend in the horizontal direction of Figure 3 and the columns may extend in the vertical direction of Figure 3. The number of capacitor units 120 in any two rows or columns may be equal or different. It is easy to understand that the rows and columns here do not strictly limit the arrangement of the capacitor units 120, but are only used to distinguish the arrangement of the capacitor units 120 in two different directions, wherein the rows and columns respectively represent the different arrangement directions of the capacitor units 120. The rows and columns do not require that the capacitor units 120 in each row or column are completely aligned.

[0078] The plurality of capacitor units 120 in each row may be arranged in series. For example, the plurality of capacitor units 120 include a first capacitor unit 120a, a second capacitor unit 120b, and a third capacitor unit 120c, wherein the first capacitor unit 120a, the second capacitor unit 120b, and the third capacitor unit 120c are arranged in series. Since the capacitors 1201a and 1201b included in each capacitor unit 120 share the second electrode 123, the capacitors 1201a and 1201b are arranged in series.

[0079] In order to arrange the multiple capacitor units 120 in each row in series, the first electrode 121 of one capacitor unit 120 in a row can be connected to the first electrode 121 of an adjacent capacitor unit 120, and the third electrode 125 can be connected to the third electrode 125 of another adjacent capacitor unit 120, that is, the first electrodes 121 or the third electrodes 125 of two adjacent capacitor units 120 in a row are connected. For example, the first electrode 121 of the first capacitor unit 120a is connected to the first electrode 121 of the second capacitor unit 120b, and the third electrode 125 of the second capacitor unit 120b is connected to the third electrode 125 of the third capacitor unit 120c.

[0080] By connecting multiple capacitor units 120 in each row in series, the multiple capacitor units 120 connected in series can form a bit line BL. The voltage level applied to the bit line BL can be changed to select the multiple capacitor units 120 in the row. In combination with the word line WL, a capacitor in a specific capacitor unit 120 can be selected.

[0081] It will be appreciated that the memory array 100 may further include a first connection structure 131 and a second connection structure 132. The third electrode 125 of one capacitor unit 120 in a row may be connected to the third electrode 125 of an adjacent capacitor unit 120 via the first connection structure 131. In other words, the third electrodes 125 of two adjacent capacitor units 120 may be connected via the first connection structure 131. Since the third electrode 125 extends along the thickness direction D of the substrate 110 and is surrounded by the second electrode 123, to facilitate connection between two adjacent third electrodes 125, the first connection structure 131 may be disposed on a side of the third electrode 125 away from the substrate. In other words, the first connection structure 131 may be disposed on a side of the two adjacent capacitor units 120 away from the substrate. The first electrode 121 of one capacitor unit 120 in a row may be connected to the first electrode 121 of the adjacent capacitor unit 120 via the second connection structure 132. In other words, the first electrodes 121 of two adjacent capacitor units 120 may be connected via the second connection structure 132. Since the first electrode 121 is disposed at the outermost periphery of the capacitor unit 120 , two adjacent capacitor units 120 can be directly connected via the second connection structure 132 . For ease of arrangement, the second connection structure 132 can be disposed close to the substrate 110 .

[0082] Continuing with FIG4 , the first connection structures 131 and the second connection structures 132 may be alternately arranged in a row of capacitor units 120. For example, a row of capacitor units 120 may include a first capacitor unit 120a, a second capacitor unit 120b, and a third capacitor unit 120c arranged in sequence. The first electrode 121 of the first capacitor unit 120a may be connected to the first electrode 121 of the second capacitor unit 120b via the second connection structure 132. The second capacitor unit 120b is disposed between the third capacitor unit 120c and the first capacitor unit 120a. The third electrode 125 of the third capacitor unit 120c is connected to the third electrode 125 of the second capacitor unit 120b via the first connection structure 131. This process is repeated to achieve connection of a row of capacitor units 120. In this way, in a row of capacitor units 120, except for the two capacitor units 120 at the beginning and the end of a row, the first electrodes 121 in other capacitor units 120 are connected to the first electrode 121 of an adjacent capacitor unit 120, and the third electrodes 125 are connected to the third electrode 125 of another adjacent capacitor unit 120.

[0083] Based on the above circuit structure, the memory array 100 further includes a plurality of transistors 140, each of which includes a first electrode 141 and a second electrode 142. Continuing with FIG. 4 , the plurality of transistors 140 may be disposed between the substrate 110 and the plurality of capacitor units 120. For example, when the transistor 140 is a field-effect transistor (MOSFET), the transistor 140 includes a first electrode 141, a second electrode 142, and a gate 143. The first electrode 141 and the second electrode 142 may be formed within or on the surface of the substrate 110. The gate 143 may be formed between the first electrode 141 and the second electrode 142 of the corresponding transistor 140, and the gate 143 may be buried in the substrate 110. After the transistors 140 are formed on the substrate 110, the transistors 140 may not be considered part of the substrate 110. The substrate 110 only includes the portion where the transistors 140 are not formed. Therefore, the plurality of transistors 140 may be considered disposed between the substrate 110 and the plurality of capacitor units 120.

[0084] It can be understood that the memory array 100 can control the capacitor of the corresponding capacitor unit 120 through the transistor 140 to read and write. Therefore, the multiple transistors 140 included in the memory array 100 can be set corresponding to the multiple capacitor units 120. At this time, the multiple transistors 140 can also be arranged in an array, and a row of transistors 140 can be connected to a row of capacitor units 120, that is, every two transistors 140 in a row of transistors 140 are set corresponding to the capacitor 1201a and the capacitor 1201b of one capacitor unit 120 in the corresponding row of capacitor units 120. For example, the multiple transistors 140 in a row of transistors 140 include a first transistor 140a and a second transistor 140b, and the first transistor 140a and the second transistor 140b are correspondingly connected to the capacitor 1201a and the capacitor 1201b of the corresponding capacitor unit 120, wherein the first transistor 140a and the second transistor 140b are set adjacent to each other or not.

[0085] The first transistor 140a and the second transistor 140b are arranged adjacent to each other. In some possible embodiments, in each row, of the two adjacent transistors 140, the first pole 141 of one transistor 140 can be the second pole 142 of the other transistor 140, or the second pole 142 of one transistor 140 can be the first pole 141 of the other transistor 140. In other words, the second pole 142 of the first transistor 140a and the first pole 141 of the second transistor 140b are the same pole. For example, as shown in Figure 4, the second pole 142 of the transistor 140a and the first pole 141 of the transistor 140b are the same pole. At this time, the first pole 141 of the first transistor 140a can be connected to the first electrode 121 of the corresponding capacitor unit 120, the second pole 142 of the first transistor 140a (also the first pole 141 of the second transistor 140b) can be connected to the second electrode 123 of the corresponding capacitor unit 120, and the second pole 142 of the second transistor 140b can be connected to the third electrode 125.

[0086] The second electrode 123 of the capacitor unit 120 can be directly connected to the same electrode of the adjacent first transistor 140a and the second transistor 140b. For example, as described above, the second electrode 123 is at least partially cylindrical. That is, a portion of the second electrode 123 is cylindrical, which can be referred to as the first portion 1231 of the second electrode 123. In addition to the cylindrical first portion 1231, the second electrode 123 also includes a second portion 1232. The second portion 1232 is located at an end of the first portion 1231 close to the substrate 110, and the edge of the second portion 1232 is connected to the end of the first portion 1231 close to the substrate 110. The second portion 1232 can close the end of the cylindrical first portion 1231 close to the substrate 110. The second portion 1232 directly contacts the same electrode of the first transistor 140a and the second transistor 140b, thereby achieving simultaneous connection of the second electrode 123 to the first transistor 140a and the second transistor 140b.

[0087] In other possible embodiments, the first transistor 140a and the second transistor 140b do not share the same electrode, the first electrode 141 of the first transistor 140a can be connected to the first electrode 121 of the corresponding capacitor unit 120, and the second electrode 142 of the first transistor 140a can be connected to the second electrode 123 of the corresponding capacitor unit 120; the first electrode 141 of the second transistor 140b can be connected to the second electrode 123, and the second electrode 142 of the second transistor 140b can be connected to the third electrode 125.

[0088] To arrange multiple transistors 140 corresponding to multiple capacitor units 120, multiple capacitor units 120 in a row can be connected in series via a first connection structure 131 or a second connection structure 132. Therefore, the first connection structure 131 or the second connection structure 132 can be connected to at least one transistor 140 to achieve a parallel connection between the transistor 140 and the corresponding capacitor 1201a or capacitor 1201b. The first electrode 141 and / or the second electrode 142 of the transistor 140 are provided with a contact region 134. The contact region 134 enables the first electrode 141 and the second electrode 142 of the transistor to achieve ohmic contact when connected to the first connection structure 131 or the second connection structure 132.

[0089] In some embodiments, since the first connection structure 131 connects the third electrodes 125 of two adjacent capacitor units 120 on a side of the capacitor unit 120 away from the substrate 110, the memory array 100 may further include a contact structure 133 to connect the third electrodes 125 of the two adjacent capacitor units 120 to the transistor 140. One end of the contact structure 133 is connected to the first connection structure 131, and the other end is connected to at least one transistor 140. As previously described, when a row of transistors 140 are arranged in series, two adjacent transistors 140 in the row 140 may share a common electrode. In this case, the other end of the contact structure 133 may be connected to the same electrode of the two adjacent transistors 140. Furthermore, when a row of transistors 140 are arranged in series, the first electrode 141 of one of the two adjacent transistors 140 in the row 140 may be the second electrode 142 of the other transistor 140. In this case, the other end of the contact structure 133 may be connected to both the first electrode 141 of one of the two adjacent transistors 140 and the second electrode 142 of the other transistor 140. If the transistor 140 is the last transistor 140 in a row of transistors 140 , the other end of the contact structure 133 is only connected to the transistor 140 .

[0090] In some possible embodiments, the contact structure 133 may be made of the same material as the first connection structure 131, and the contact structure 133 may be formed by the same process as the first connection structure 131. For example, the contact structure 133 and the first connection structure 131 are formed simultaneously by the same sputtering or chemical vapor deposition process. In some specific embodiments, the contact structure 133, the first connection structure 131, and the third electrodes 125 of the two adjacent capacitor units 120 connected to the first connection structure 131 are all made of the same material and can be formed simultaneously by the same process. In addition, since there is a connection relationship between the contact structure 133, the first connection structure 131, and the third electrodes 125 of the two adjacent capacitor units 120 connected to the first connection structure 131, the contact structure 133, the first connection structure 131, and the third electrodes 125 of the two adjacent capacitor units 120 connected to the first connection structure 131 can also be provided as one piece.

[0091] In some embodiments, since the second connection structure 132 is disposed close to the substrate 110, that is, the second connection structure 132 can be disposed between two adjacent capacitor units 120 and on the side of the transistor 140 away from the substrate 110. Therefore, in order to connect one transistor 140 in parallel with one capacitor 1201a or one capacitor 1201b, the second connection structure 132 can be directly in contact with the transistor 140, that is, the second connection structure 132 can be directly connected to the first electrode 141 or the second electrode 142 of one transistor 140. Similarly, the first electrodes 121 of the two adjacent capacitor units 120 connected to the second connection structure 132 can be made of the same material and can be formed simultaneously by the same process. In this case, the first electrodes 121 of the two adjacent capacitor units 120 connected to the second connection structure 132 can be integrally disposed.

[0092] In this way, the two capacitors 1201 a and 1201 b in one capacitor unit 120 are connected in parallel with the two transistors 140 a and 140 b respectively.

[0093] Continuing with FIG4 , the memory array 100 includes multiple transistors 140 arranged in an array. Since a row of transistors 140 is connected in series, a row of transistors 140 can also be considered a bit line BL of the memory array 100. Each row of transistors 140 is connected to a corresponding row of capacitor cells 120. Specifically, the two capacitors 1201a and 1201b in a capacitor cell 120 are connected in parallel to the two transistors 140a and 140b, respectively. The memory array 100 also includes multiple word lines WL, which can be embedded in the substrate 110. The transistors 140 can also include gates 143, which are connected to the gates 143 of a column of transistors 140. In this way, a capacitor can be selected via a word line WL and a bit line BL, allowing read and write operations to be performed on the capacitor.

[0094] Please refer to Figures 7 and 8. Figure 7 is a schematic front cross-sectional view of another memory array 100, and Figure 8 is a circuit schematic diagram of the memory array 100. The memory array 100 in Figure 7 may also include a capacitor unit 120. The memory array 100 in Figure 7 differs from the memory array 100 in Figure 4 in that the transistor 140 of the memory array 100 in Figure 7 and the capacitor of the capacitor unit 120 are arranged in series, while the transistor 140 and the capacitor of the capacitor unit 120 in the memory array 100 in Figure 4 are arranged in parallel.

[0095] Continuing with FIG8 , memory array 100 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of source lines SL. The plurality of word lines WL may be arranged along a first direction, and the plurality of bit lines BL may be arranged along a second direction. The first and second directions may intersect. A memory cell may be disposed between any word line WL and any bit line BL. A memory cell may include a transistor and a capacitor. The transistor may include a first electrode, a second electrode, and a gate. The gate may be connected to the word line WL, the first electrode may be connected to the bit line BL, the second electrode may be connected to one electrode of the capacitor, and the other electrode of the capacitor may be connected to the source line SL.

[0096] This capacitor can be one of the two capacitors in capacitor unit 120. That is, the capacitor can be capacitor 1201b in capacitor unit 120, which is composed of at least first electrode 121, first dielectric layer 127, and second electrode 123, or capacitor 1201a in capacitor unit 120, which is composed of at least second electrode 123, second dielectric layer 129, and third electrode 125. As shown in FIG7 , capacitor unit 120 can also be disposed on substrate 110.

[0097] In some embodiments, since one capacitor unit 120 includes two capacitors, the two capacitors in one capacitor unit 120 may be connected to two transistors 140, respectively. For example, the two transistors may be a first transistor 140a and a second transistor 140b, respectively. The first electrode 121 of the capacitor unit 120 is connected to the first electrode 141 or the second electrode 142 of the first transistor 140a, the third electrode 125 of the capacitor unit 120 is connected to the first electrode 141 or the second electrode 142 of the second transistor 140b, and the second electrode 123 of the capacitor unit 120 is connected to a power signal terminal, which may be a source line SL. Meanwhile, the gate of the first transistor 140a and the gate of the second transistor 140b may be connected to a first word line WL(1) and a second word line WL(2), respectively. The first electrode 141 or the second electrode 142 of the first transistor 140a may be connected to the same bit line BL as the first electrode 141 or the second electrode 142 of the second transistor 140b.

[0098] In this way, by setting the word line WL to a high level, the gate 143 connected to the word line WL is set to a high level, the transistor 140 corresponding to the gate 143 is turned on, and the charge stored in the capacitor connected to the transistor 140 can be obtained or changed through the bit line BL of the transistor 140, thereby performing read and write operations on the storage unit composed of the transistor 140 and the capacitor.

[0099] In some embodiments, to facilitate connection to the capacitor unit 120, the first portion 1231 of the second electrode 123 may be cylindrical. In addition to the cylindrical first portion 1231, the second electrode 123 may also include a second portion 1232. The second portion 1232 may be located at an end of the first portion 1231 away from the substrate 110, and the edge of the second portion 1232 is connected to the end of the first portion 1231 away from the substrate 110. The second portion 1232 may enclose the end of the cylindrical first portion 1231 away from the substrate 110. The second portion 1232 may be connected to the source line SL, thereby simultaneously connecting the two capacitors of the capacitor unit 120 to the source line SL.

[0100] In some embodiments, the memory array 100 may include a plurality of capacitor units 120 and a plurality of transistors 140, and the plurality of capacitor units 120 may be arranged in an array on the substrate 110. Since every two transistors 140 correspond to one capacitor unit 120, the plurality of transistors 140 may also be arranged in an array on the substrate 110. To facilitate electrical connection, the gates of each row or column of transistors 140 may be connected to the same word line WL. In addition, the gates 143 of the plurality of transistors 140 may be buried in the substrate 110, and accordingly, the word lines WL connecting the gates of each row or column of transistors 140 may also be buried in the substrate 110. The gates 143 of the plurality of transistors 140 may also be integrally provided with the corresponding word lines WL.

[0101] Although this application only illustrates a memory array formed by one layer of memory cells, it is easy to understand that the disclosure of this application is also applicable to a memory array having multiple layers stacked.

[0102] In addition, an embodiment of the present application further provides a method for preparing a memory array, as shown in FIG9 , which is a flow chart of preparing a memory array. The method may include the following steps:

[0103] S100 , forming a second electrode 123 on the substrate 110 , wherein the second electrode 123 extends along a thickness direction D of the substrate 110 .

[0104] First, a substrate 110 is provided, as shown in Figures 10 and 11. Figure 10 is a schematic diagram of the three-dimensional structure of the substrate 110, and Figure 11 is a schematic diagram of the cross-sectional structure along the BB direction in Figure 10. Transistors 140 are formed on the substrate 110. The transistors 140 can be distributed in an array on the substrate 110. The transistors 140 may include a first electrode 141, a second electrode 142, and a gate 143. The transistors 140 may be buried in the substrate 110. For example, the first electrode 141 and the second electrode 142 of the transistor 140 may be formed by doping the substrate 110, forming a groove between the first electrode 141 and the second electrode 142, and forming a gate dielectric layer in the groove to form the gate 143. The gate 143 may be made of a metal, such as tungsten (W). The gate dielectric layer may be made of a high-K dielectric material, such as aluminum oxide (Al2O3).

[0105] The transistors 140 may be arranged in an array, that is, the transistors 140 may be arranged in multiple rows and columns, wherein the direction of each row may be along the BB direction, and the direction of each column may be perpendicular to the BB direction. Each row of transistors 140 may be arranged in series, and the first electrode 141 of one transistor 140 of adjacent transistors 140 in each row of transistors 140 is connected to the second electrode 142 of another transistor 140. In some embodiments, the first electrode 141 of one transistor 140 of adjacent transistors 140 and the second electrode 142 of another transistor 140 may be the same electrode. For ease of explanation, the following example will be exemplified by taking the first electrode 141 of one transistor 140 of adjacent transistors 140 and the second electrode 142 of another transistor 140 as the same electrode.

[0106] The gate 143 of each column of transistors 140 may be connected to the same word line WL. In some embodiments, the gate 143 of each column of transistors 140 may be integrally formed, that is, the gate 143 of each column of transistors 140 extends in the arrangement direction of each column of transistors 140 and extends from at least the first transistor 140 to the last transistor 140 in the column of transistors 140.

[0107] In some embodiments, the second electrode 123 may be formed on the first electrode 141 or the second electrode 142 of each row of transistors 140. For example, when two adjacent transistors 140 in each row of transistors 140 share the same electrode, the second electrode 123 may be arranged at intervals of one electrode (the first electrode 141 or the second electrode 142).

[0108] Please refer to Figures 12 and 13. Figure 12 is a schematic diagram of the structure after the second electrode 123 is formed, and Figure 13 is a schematic diagram of the cross-sectional structure along the CC direction in Figure 12. Before forming the second electrode 123, a sacrificial layer 151 is formed on the substrate 110. The sacrificial layer 151 can be made of an insulating material. For example, the material of the sacrificial layer 151 is silicon oxide (SiO2). The sacrificial layer 151 can be formed using a CVD (Chemical Vapor Deposition) process. The sacrificial layer 151 not only fills the groove formed between the first pole 141 and the second pole 142 on the substrate 110 that is not filled by the gate 143, but also extends a certain dimension away from the substrate 110 in the thickness direction D of the substrate 110. In some embodiments, this dimension is the same as the dimension of the second electrode 123 extending in the thickness direction D of the substrate 110.

[0109] After forming the sacrificial layer 151, a mask layer can be formed on the surface of the sacrificial layer 151. A pattern can be formed on the mask layer through a photolithography process. This pattern exposes the sacrificial layer 151 at the locations where the second electrodes 123 are to be formed. For example, an array of holes can be formed on the mask layer. The locations of the holes correspond to the locations where the second electrodes 123 are to be formed, and the shape of the holes is the same as the shape formed by the outer edge of the cross section of the second electrode 123. The sacrificial layer 151 is etched through the holes formed in the mask layer to form deep holes in the sacrificial layer 151. The etching process can use a plasma etching process to achieve anisotropic etching.

[0110] Then, a second electrode 123 is formed in the formed deep hole. The second electrode 123 can be formed by a deposition process, for example, a PVD (Physical Vapor Deposition) process or an ALD (Atomic Layer Deposition) process, etc. That is, the second electrode 123 can be formed by attaching a layer of electrode material on the inner surface of the deep hole, and the inner surface of the deep hole includes the bottom surface of the deep hole. The second electrode 123 thus formed extends along the thickness direction of the substrate 110. The thickness of the attached electrode material is the thickness of the second electrode 123. The thickness range of the second electrode 123 can be 5nm to 15nm, for example, 5nm, 8nm, 15nm, etc. It is easy to understand that the shape of the inner surface of the deep hole is the shape of the surface of one side of the second electrode 123. The material of the second electrode 123 can be a conductive material, such as titanium nitride (TiN).

[0111] S200 , forming a first dielectric layer 127 on one side of the second electrode 123 , and forming a second dielectric layer 129 on the other side of the second electrode 123 .

[0112] After forming the second electrode 123, the sacrificial layer 151 is removed, as shown in Figures 14 and 15. Figure 14 is a schematic diagram of the structure after removing the sacrificial layer 151, and Figure 15 is a schematic diagram of the cross-sectional structure along the EE direction in Figure 14. A wet etching process can be used to remove the sacrificial layer 151. After removing the sacrificial layer 151, both sides of the second electrode 123 are unobstructed, and at this point, only the second electrode 123 is provided on the surface of the substrate 110.

[0113] Thereafter, a first dielectric layer 127 can be formed on one side of the second electrode 123, and a second dielectric layer 129 can be formed on the other side of the second electrode 123, as shown in Figures 16 and 17, Figure 16 is a schematic diagram of the structure after the first dielectric layer 127 and the second dielectric layer 129 are formed, and Figure 17 is a schematic diagram of the cross-sectional structure along the FF direction in Figure 16. The first dielectric layer 127 and the second dielectric layer 129 can be formed by a deposition process, such as an ALD (Atomic Layer Deposition) process. In some embodiments, the portion of the second electrode 123 extending along the thickness direction of the substrate 110 is cylindrical, and therefore, the first dielectric layer 127 can be formed on the outer surface of the second electrode 123, and the second dielectric layer 129 can be formed on the inner surface of the second electrode 123.

[0114] It is easy to understand that the first dielectric layer 127 and the second dielectric layer 129 can be deposited simultaneously by the same process. In addition, because the dielectric layer formed by the deposition process is also formed on the upper edge of the second electrode 123, the first dielectric layer 127 and the second dielectric layer 129 are connected on the side of the second electrode 123 away from the substrate 110, forming an integrated structure.

[0115] S300, forming a first electrode 121 on a side of the first dielectric layer 127 away from the second electrode 123, and forming a third electrode 125 on a side of the second dielectric layer 129 away from the second electrode 123, wherein the first electrode 121 and the second electrode 123 extend along the thickness direction of the substrate 110, the second electrode 123 surrounds the first electrode 121, and the third electrode 125 surrounds the second electrode 123.

[0116] After forming the first dielectric layer 127 on one side of the second electrode 123 and the second dielectric layer 129 on the other side, the first electrode 121 and the third electrode 125 can be formed. The first electrode 121 and the third electrode 125 can be made of the same material as the second electrode 123, and the process for forming the first electrode 121 and the third electrode 125 can also be the same as the process for forming the second electrode 123. It is easy to understand that the first electrode 121 and the third electrode 125 can be formed simultaneously using the same process.

[0117] In some embodiments, because the capacitor unit 120 is connected to the transistor 140 embedded in the substrate 110, the connection between the first electrode 121 and the transistor 140 can be achieved simultaneously with the formation of the first electrode 121. Before forming the first electrode 121, a portion of the dielectric layer covering the surface of the substrate 110 due to the formation of the first dielectric layer 127 and the second dielectric layer 129 can be removed through photolithography and etching processes, thereby exposing a portion of the surface of the substrate 110, as shown in Figures 18 and 19. Figure 18 is a schematic diagram of the structure after the removal of a portion of the dielectric layer, and Figure 19 is a schematic diagram of the cross-sectional structure along the GG direction in Figure 18.

[0118] Therefore, referring to Figures 20 and 21, when the first electrode 121 and the third electrode 125 are formed by a deposition process, a conductive material (the same material as the first electrode 121 and the second electrode 123) can be simultaneously formed on the exposed portion of the substrate surface. This conductive material can form a second connecting structure 132. The second connecting structure 132 connects the first electrodes 121 of two adjacent capacitor cells 120 in each row of capacitor cells 120, and also connects the first electrode 121 to the first electrode 141 or the second electrode 142 of the transistor 140. The second connecting structure 132 only connects some of the adjacent two capacitor cells 120 in a row of capacitor cells 120. For example, if the capacitor cells 120 in a row are arranged sequentially, the some of the adjacent two capacitor cells 120 can be the adjacent two capacitor cells in a row consisting only of the capacitor cells at odd positions and the capacitor cell arranged thereafter, or the adjacent two capacitor cells in a row consisting only of the capacitor cells at even positions and the capacitor cell arranged thereafter.

[0119] The portion of the dielectric layer that is removed may correspond to at least the portion between two adjacent capacitor units 120. The portion of the dielectric layer that is removed may connect the first electrodes 121 of the adjacent capacitor units 120 and the transistors 140. In other words, within a row of capacitor units 120, the dielectric layer between the first and second capacitor units may be removed, the dielectric layer between the second and third capacitor units may be retained, and the dielectric layer between the third and fourth capacitor units may be removed, and this process may be repeated.

[0120] It is easy to understand, referring to Figures 20 and 21, when the first electrode 121, the second electrode 123 and the second connection structure 132 are formed at the same time, the conductive material will also cover the upper surface of the substrate 110. Therefore, after forming the first electrode 121, the second electrode 123 and the second connection structure 132, it is necessary to remove part of the conductive material. This part of the conductive material does not correspond to the removed dielectric layer. That is, after removing part of the conductive material, the remaining conductive material covers the position exposed after removing the dielectric layer. As shown in Figures 20 and 21, Figure 20 is a schematic diagram of the structure after removing excess conductive material, and Figure 21 is a schematic diagram of the cross-sectional structure along the HH direction in Figure 20. For example, unnecessary conductive material can be removed by photolithography and etching processes.

[0121] Finally, the third electrode 125 needs to be connected to the transistor 140. After forming the first electrode 121 and the third electrode 125, an insulating material, such as SiO2, can be deposited on the substrate 110. The insulating material can completely cover the first electrode 121 and the third electrode 125, that is, the first electrode 121 and the third electrode 125 do not expose the upper surface formed by the insulating material.

[0122] 22 and 23 , in order to connect the third electrode 125 to the transistor 140, a contact hole can be formed on the upper surface of the insulating material by a photolithography process and an etching process, and a conductive material is deposited in the contact hole to form a first connection structure 131 and a contact structure 133. Since the deposited conductive material will cover the entire upper surface of the insulating material, in order to form only the first connection structure 131 and the contact structure 133, it is also necessary to remove the conductive material other than the first connection structure 131 and the contact structure 133. As shown in FIG22 and FIG23 , FIG22 is a schematic diagram of the structure after removing excess conductive material, and FIG23 is a schematic diagram of the cross-sectional structure along the II direction in FIG22 . The third electrodes 125 of two adjacent capacitor units 120 are connected through the first connection structure 131, and the first connection structure 131 is connected to the transistor 140 through the contact structure 133, thereby achieving the connection of the third electrodes 125 of the two adjacent capacitor units 120 to the transistor 140.

[0123] The specific process steps of the above preparation method are described based on the structure corresponding to the circuit architecture of Figure 6 as an example. The structures corresponding to other circuit architectures (such as Figure 8) can refer to the above method steps without departing from the inventive concept of this application, and the process steps can be adjusted according to the different adaptability of the structure.

[0124] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; A capacitor unit is arranged on the substrate, the capacitor unit includes a first electrode, a second electrode and a third electrode, the first electrode, the second electrode and the third electrode all extend along the thickness direction of the substrate, the first electrode is arranged around the second electrode, and the second electrode is arranged around the third electrode; the capacitor unit also includes a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged between the first electrode and the second electrode, and the second dielectric layer is arranged between the second electrode and the third electrode.

2. The storage array according to claim 1, wherein: At least a portion of the second electrode is cylindrical, and at least a portion of the first electrode is cylindrical.

3. The storage array according to claim 1 or 2, characterized in that: The first dielectric layer is connected to the second dielectric layer at a side away from the substrate.

4. The storage array according to any one of claims 1 to 3, characterized in that: The storage array includes a plurality of capacitor units arranged in an array, and the third electrodes of any two adjacent capacitor units in a row of the capacitor units are connected, or the first electrodes are connected.

5. The storage array according to claim 4, wherein: It also includes a first connection structure, which is arranged on a side of the two adjacent capacitor units away from the substrate, and the third electrodes of the two adjacent capacitor units are connected through the first connection structure.

6. The storage array according to claim 5, characterized in that: Also includes: A plurality of transistors are disposed between the substrate and the plurality of capacitor units; A contact structure, one end of which is connected to the first connection structure, and the other end of which is connected to at least one of the transistors.

7. The storage array according to claim 6, wherein: The third electrodes of the two adjacent capacitor units, the first connection structure and the contact structure are made of the same material and are integrally arranged.

8. The storage array according to claim 4, wherein: It also includes a second connection structure, which is arranged between the two adjacent capacitor units and close to the substrate. The first electrodes of the two adjacent capacitor units are connected through the second connection structure.

9. The storage array according to claim 8, wherein: It also includes a plurality of transistors disposed between the substrate and the plurality of capacitor units; the second connection structure is in contact with at least one of the transistors.

10. The storage array according to claim 8, wherein: The first electrodes and the second connection structure of the two adjacent capacitor units are made of the same material and are integrally provided.

11. The storage array according to any one of claims 4 to 10, characterized in that: It also includes a first connection structure and a second connection structure. In a row of the capacitor units, the first connection structure and the second connection structure are alternately arranged.

12. The storage array according to any one of claims 1 to 10, wherein: The multiple transistors of the storage array include a first transistor and a second transistor, the first electrode of the first transistor is connected to the first electrode, the second electrode of the first transistor and the first electrode of the second transistor are both connected to the second electrode, and the second electrode of the second transistor is connected to the third electrode.

13. The storage array according to claim 12, wherein: The second electrode of the first transistor is the same as the first electrode of the second transistor; The second electrode includes a cylindrical first portion and a second portion located at one end of the first portion close to the substrate, an edge of the second portion is connected to the end of the first portion close to the substrate, and the second portion contacts the same electrode.

14. The storage array according to any one of claims 1 to 13, wherein: The plurality of transistors in the storage array are arranged in an array, and a row of the transistors is arranged in series and connected to a row of the capacitor units correspondingly; The memory array further comprises a plurality of word lines buried in the substrate, wherein one word line is connected to the gates of a column of the transistors.

15. The storage array according to claim 1 or 2, characterized in that: Also including a first bit line and a second bit line; The multiple transistors of the storage array include a first transistor and a second transistor, the first electrode of the first transistor is connected to the first bit line, the second electrode of the first transistor is connected to the first electrode, the first electrode of the second transistor is connected to the third electrode, the second electrode of the second transistor is connected to the second bit line; the second electrode is connected to the power signal terminal.

16. The storage array according to any one of claims 1 to 15, wherein: The first dielectric layer and the second dielectric layer are both ferroelectric materials.

17. A method for preparing a storage array, characterized in that: include: forming a second electrode on the substrate, wherein the second electrode extends along a thickness direction of the substrate; forming a first dielectric layer on one side of the second electrode and forming a second dielectric layer on the other side of the second electrode; A first electrode is formed on a side of the first dielectric layer away from the second electrode, and a third electrode is formed on a side of the second dielectric layer away from the second electrode, wherein the first electrode and the second electrode extend along the thickness direction of the substrate, the second electrode surrounds the first electrode, and the third electrode surrounds the second electrode.

18. The method for preparing a memory array according to claim 17, wherein: The first dielectric layer and the second dielectric layer are formed simultaneously.

19. A memory, characterized in that: The invention comprises a peripheral circuit and a memory array according to any one of claims 1 to 16, wherein the peripheral circuit is electrically connected to the memory array.

20. An electronic device, characterized in that: The invention comprises a printed circuit board and the memory as claimed in claim 19, wherein the memory is arranged on the printed circuit board.

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