Mode switching circuit and method, external expansion connector, and pcie board card

Abstract

The present application relates to the technical field of mode switching, and discloses a mode switching circuit and method, an external expansion connector, and a PCIe board card. The mode switching circuit comprises a first switching circuit, a second switching circuit, a clock switching circuit and a first bidirectional level converter. An input end of the first switching circuit is configured to be connected to a first back surface differential pin of a connector, a first output end is connected to a first reset presence end of a PCIe device, and a second output end is connected to the clock switching circuit. A first input end of the second switching circuit is configured to be connected to a second reset presence end of the PCIe device, a second input end is connected to the clock switching circuit, and an output end is connected to a first front surface differential pin of the connector. Two groups of level conversion channels of the first bidirectional level converter respectively perform data transmission. According to the present application, the connector can be switched between an RC interface and an ED interface, and no device or cable needs to be replaced during interface mode switching, so that the flexibility and universality of an external expansion interface are greatly improved, and the switching is simple.

Description

Mode switching circuit, method, expansion connector and PCIe board

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 27, 2023, with application number 202311813726.2, and application name “Mode switching circuit, method, external expansion connector and PCIe board card”, all contents of which are incorporated by reference in this application. Technical Field

[0003] The present application relates to the field of mode switching technology, and in particular to a mode switching circuit, method, external expansion connector and PCIe board. Background Art

[0004] PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) is the mainstream bus standard for servers, and more and more PCIe devices are gradually being used in various scenarios.

[0005] The PCIe bus interface of a PCIe device can function as either an RC (Root Complex) interface or an Endpoint (ED) interface, requiring the interface to switch between RC and ED modes. However, the functional definitions of some low-speed signals in the PCIe bus interface differ between RC and ED modes, making switching difficult.

[0006] Current switching solutions typically define two modes, which cannot be changed. Changes require rework or the use of non-standard custom cables for external expansion. This inflexible switching approach increases labor and component costs.

[0007] Summary of the Invention

[0008] The present application provides a mode switching circuit, method, external expansion connector and PCIe board.

[0009] In one aspect, the present application provides a mode switching circuit, comprising: a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level converter;

[0010] An input end of the first switching circuit is configured to be connected to a first reverse differential pin of the connector, a first output end of the first switching circuit is configured to be connected to a first reset in-position terminal of the PCIe device, and a second output end of the first switching circuit is connected to the clock switching circuit; the first switching circuit is configured to transmit an RC reset signal and / or an RC in-position signal between the first reverse differential pin and the first reset in-position terminal, or to send an ED differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;

[0011] The first input end of the second switching circuit is configured to be connected to the second reset in-position end of the PCIe device, the second input end is connected to the clock switching circuit, and the output end is configured to be connected to the first front differential pin of the connector; the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or to transmit an ED reset signal and / or an ED in-position signal between the first front differential pin and the second reset in-position end;

[0012] The clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and an RC differential clock signal sent to the second switching circuit, or to generate a reference clock signal sent to the PCIe device based on the ED differential clock signal; and

[0013] The first group of level conversion channels of the first bidirectional level converter is configured to transmit data between the second reverse differential pin of the connector and the first data end of the PCIe device, and the second group of level conversion channels is configured to transmit data between the second front differential pin of the connector and the second data end of the PCIe device; both groups of level conversion channels of the first bidirectional level converter can be configured to transmit I2C bus signals, or to transmit wake-up signals and / or identification signals.

[0014] In some embodiments, the mode switching circuit further includes: a first tri-state level conversion circuit;

[0015] A first side port of the first tri-state level conversion circuit is connected to the first output terminal of the first switching circuit, and a second side port of the first tri-state level conversion circuit is configured to be connected to a first reset position terminal of the PCIe device;

[0016] The first tri-state level conversion circuit is configured to: transmit an RC reset signal and / or an RC in-position signal in an RC interface mode; or

[0017] The port of the first tri-state level conversion circuit is in a high-impedance state in the ED interface mode.

[0018] In some embodiments, the first tri-state level conversion circuit includes a first tri-state level converter; the first tri-state level converter is configured to connect a first output terminal of the first switching circuit to a first reset-in-position terminal of the PCIe device; and

[0019] The enable terminal of the first tri-state level converter is configured to receive an RC enable signal, and the RC enable signal is valid in the RC interface mode.

[0020] In some embodiments, the first tri-state level conversion circuit further includes: a first level circuit; the first level circuit is connected to the power supply terminal of the first tri-state level converter;

[0021] The first level circuit is configured to: provide a reference level to the first three-state level converter in the RC interface mode; or

[0022] The first level circuit is configured to stop supplying power in the ED interface mode.

[0023] In some embodiments, the first level circuit includes: a first switch tube;

[0024] The input end of the first switch tube is connected to the power supply, and the output end is connected to the power supply end of the first tri-state level converter; and

[0025] The control terminal of the first switch tube is connected to the RC enable signal; in response to determining that the RC enable signal is valid, the first switch tube is turned on.

[0026] In some embodiments, in the first switching circuit, the input terminal of the first switching circuit is directly connected to the second output terminal via a first conductive line; and

[0027] A first via hole is provided on a pin of a port on one side of the first tri-state level conversion circuit. The first wire passes through the first via hole and is electrically connected to the first via hole.

[0028] In some embodiments, the mode switching circuit further includes: a second three-state level conversion circuit;

[0029] A first side port of the second tri-state level conversion circuit is connected to the first input terminal of the second switching circuit, and a second side port of the second tri-state level conversion circuit is configured to be connected to the second reset position terminal of the PCIe device;

[0030] In the RC interface mode, the port of the second tri-state level conversion circuit is in a high impedance state; and

[0031] In the ED interface mode, the second tri-state level conversion circuit is configured to transmit an ED reset signal and / or an ED presence signal.

[0032] In some embodiments, the second tri-state level conversion circuit includes a second tri-state level converter; the second tri-state level converter is configured to connect the first input terminal of the second switching circuit to the second reset position terminal of the PCIe device; and

[0033] The enable terminal of the second tri-state level converter is configured to receive an ED enable signal, and the ED enable signal is valid in the ED interface mode.

[0034] In some embodiments, the second tri-state level conversion circuit further includes: a second level circuit; the second level circuit is connected to the power supply terminal of the second tri-state level converter;

[0035] The second level circuit is configured to: stop power supply in RC interface mode; or

[0036] The second level circuit is configured to provide a reference level to the second tri-state level converter in the ED interface mode.

[0037] In some embodiments, the second level circuit includes: a second switch tube;

[0038] The input end of the second switch tube is connected to the power supply, and the output end is connected to the power supply end of the second tri-state level converter; and

[0039] The control terminal of the second switch tube is connected to the ED enable signal; in response to determining that the ED enable signal is valid, the second switch tube is turned on.

[0040] In some embodiments, in the second switching circuit, the second input terminal and the output terminal of the second switching circuit are directly connected via a second wire; and

[0041] A second via hole is provided on the pin of a port on one side of the second tri-state level conversion circuit, and the second wire passes through the second via hole and is electrically connected to the second via hole.

[0042] In some embodiments, the mode switching circuit further includes: a second bidirectional level converter and a third tri-state level conversion circuit;

[0043] A first side port of the third three-state level conversion circuit is connected to the third reverse differential pin of the connector, and a second side port of the third three-state level conversion circuit is configured to be connected to a third reset-in-position terminal of the PCIe device;

[0044] The first set of level shifting channels of the second bidirectional level shifter is configured to transmit data between the fourth reverse differential pin of the connector and the third data terminal of the PCIe device, and the second set of level shifting channels is configured to transmit data between the fourth front differential pin of the connector and the fourth data terminal of the PCIe device;

[0045] In the RC interface mode, the third tri-state level shifting circuit is configured to transmit an RC reset signal and / or an RC in-position signal; the first group of level shifting channels of the second bidirectional level shifter is configured to transmit an I2C bus signal, and the second group of level shifting channels is configured to transmit a wake-up signal and / or an identification signal; and

[0046] In ED interface mode, the port of the third three-state level conversion circuit is in high-impedance state; the first group of level conversion channels of the second bidirectional level converter is configured to transmit wake-up signals and / or identification signals, and the second group of level conversion channels is configured to transmit I2C bus signals.

[0047] In some embodiments, a clock switching circuit includes: a clock generator and a clock buffer;

[0048] The first output terminal of the clock generator is connected to the first input terminal of the clock buffer and is configured to output a local differential clock signal in an RC interface mode;

[0049] The second output terminal of the clock generator is connected to the second input terminal of the second switching circuit and is configured to output an RC differential clock signal in an RC interface mode;

[0050] The second input terminal of the clock buffer is connected to the second output terminal of the first switching circuit and is configured to receive the ED differential clock signal in the ED interface mode; and

[0051] The clock buffer is configured to generate a reference clock signal sent to the PCIe device based on the local differential clock signal or the ED differential clock signal.

[0052] In some embodiments, the enable terminal of the clock generator is configured to receive an RC enable signal; and

[0053] In response to determining that the RC enable signal is valid in the RC interface mode and the RC enable signal is valid, the clock generator outputs a local differential clock signal and an RC differential clock signal.

[0054] In some embodiments, the selection terminal of the clock buffer is configured to receive a clock selection signal;

[0055] In response to determining that the clock select signal indicates the RC interface mode, the first input terminal of the clock buffer is active; or

[0056] In response to determining that the clock select signal indicates the ED interface mode, the second input terminal of the clock buffer is active.

[0057] In some embodiments, the mode switching circuit further includes: a mode selection circuit; and

[0058] The mode selection circuit is configured to provide a mode selection signal indicating that the RC interface mode or the ED interface mode is currently selected to the PCIe device.

[0059] In some embodiments, the mode selection circuit includes: a selection switch, a first resistor, and a second resistor;

[0060] The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to the ground through the selection switch and the second resistor in sequence; or the first end of the selection switch is connected to the power supply, and the second end of the selection switch is connected to the ground through the first resistor and the second resistor in sequence; and

[0061] One end of the second resistor close to the first resistor is configured to be connected to the PCIe device to provide a mode selection signal.

[0062] On the other hand, the present application provides a mode switching method, which is implemented based on the mode switching circuit as described above, and the method includes:

[0063] In RC interface mode, perform the following steps:

[0064] Controlling the first switching circuit to transmit an RC reset signal and / or an RC in-position signal between the first reverse differential pin of the connector and the first reset in-position terminal of the PCIe device;

[0065] Controlling the clock switching circuit to generate a reference clock signal sent to the PCIe device and an RC differential clock signal sent to the second switching circuit;

[0066] controlling the second switching circuit to send an RC differential clock signal to the first front differential pin of the connector; and

[0067] Controlling a first group of level conversion channels of the first bidirectional level converter to transmit I2C bus signals, and a second group of level conversion channels to transmit wake-up signals and / or identification signals; or

[0068] In ED interface mode, perform the following steps:

[0069] Controlling the first switching circuit to send the ED differential clock signal transmitted by the first reverse differential pin of the connector to the clock switching circuit;

[0070] Controlling the clock switching circuit to generate a reference clock signal sent to the PCIe device based on the ED differential clock signal;

[0071] Controlling the second switching circuit to transmit an ED reset signal and / or an ED presence signal between the first front differential pin of the connector and the second reset presence terminal of the PCIe device; and

[0072] A first group of level conversion channels of the first bidirectional level converter is controlled to transmit a wake-up signal and / or an identification signal, and a second group of level conversion channels is controlled to transmit an I2C bus signal.

[0073] On the other hand, the present application provides an external expansion connector, including: a connector and the mode switching circuit as described above.

[0074] In another aspect, the present application provides a PCIe board, comprising: a PCIe device and at least one external expansion connector as described above; and

[0075] The PCIe device is provided with RC firmware and ED firmware; the PCIe device is in RC interface mode, and the RC firmware is loaded; or the PCIe device is in ED interface mode, and the ED firmware is loaded.

[0076] In some embodiments, the expansion connector includes a mode selection circuit, and the PCIe device is configured to: load the RC firmware in response to an RC mode instruction triggered by the mode selection circuit; and

[0077] In response to an ED mode instruction triggered by the mode selection circuit, ED firmware is loaded. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0079] FIG1 is a first structural diagram of a mode switching circuit according to an embodiment of the present application;

[0080] FIG2 is a schematic structural diagram of a mode switching circuit in an RC interface mode according to an embodiment of the present application;

[0081] 3 is a schematic structural diagram of a mode switching circuit in ED interface mode according to an embodiment of the present application;

[0082] FIG4 is a second structural diagram of a mode switching circuit according to an embodiment of the present application;

[0083] FIG5 is a schematic structural diagram of a first tri-state level conversion circuit according to an embodiment of the present application;

[0084] FIG6 is a schematic structural diagram of a second tri-state level conversion circuit according to an embodiment of the present application;

[0085] FIG7 is a schematic structural diagram of a clock switching circuit according to an embodiment of the present application;

[0086] FIG8 is a schematic structural diagram of a mode selection circuit according to an embodiment of the present application;

[0087] FIG9 is a third structural diagram of a mode switching circuit according to an embodiment of the present application;

[0088] FIG10 is a schematic structural diagram of a PCIe board according to an embodiment of the present application;

[0089] FIG11 is a schematic diagram of an architecture of a PCIe board and a server in RC interface mode according to an embodiment of the present application;

[0090] Figure 12 is a schematic diagram of the architecture of a PCIe board and a server in ED interface mode according to an embodiment of the present application.

[0091] Explanation of the reference numerals: 101, first switching circuit; 102, second switching circuit; 103, clock switching circuit; 1031, clock generator; 1032, clock buffer; 104, first bidirectional level converter; 105, first three-state level converter; 1051, first three-state level converter; 1052, first level circuit; M1, first switch tube; 106, second three-state level converter; 1061, second three-state level converter; 1062, second level circuit; M2, second switch tube; 107, second bidirectional level converter; 108, Third three-state level conversion circuit; 109, mode selection circuit; SW1, selection switch; R1, first resistor; R2, second resistor; 1011, first wire; 1021, second wire; 200, connector; 201, first reverse differential pin; 202, first front differential pin; 203, second reverse differential pin; 204, second front differential pin; 205, third reverse differential pin; 206, third front differential pin; 207, fourth reverse differential pin; 208, fourth front differential pin; 300, PCIe device. DETAILED DESCRIPTION

[0092] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0093] With the rapid development of 5G (5th Generation Mobile Communication Technology) networks, cloud computing, and big data, PCIe (PCIe), as the mainstream bus standard for servers, is gradually being upgraded and gradually adopted in the high-end market. With the implementation of PCIe application interfaces, the high-speed interconnect cables for the PCIe bus within servers can now support SlimSAS (thin SAS) cable assemblies and the higher-speed MCIO (Mini Cool Edge I / O) cable assemblies. Both SlimSAS and MCIO connectors are cable assembly connector interfaces designed for PCIe, and are board-to-cable connector interfaces.

[0094] To support the high-speed PCIe interface, the majority of the latest servers utilize MCIO high-speed connectors for internal PCIe interconnects. MCIO connectors are high-speed, high-density board-to-cable connectors that support PCIe. They are compact, offer reliable and stable connections, and are available in a variety of interface specifications, including support for high-speed differential pairs (x4, x8, and x16). External cable connections are available in a variety of configurations, including left-side, right-side, vertical, and 90-degree options, ensuring flexible use within the chassis.

[0095] In order to achieve a more compact interface design and flexible use of PCIe bus interfaces of different specifications, most new-generation servers will design the PCIe bus interface into multiple MCIO X8-specification PCIe bus interfaces. These can be used as a single PCIe X8 bus, split into two PCIe X4 buses, or combined to form a PCIe X16-specification bus interface.

[0096] Among them, the MCIO connector has defined the position of the high-speed differential bus according to the protocol, and also defined the position of the low-speed auxiliary signal line. However, the function definition and position of the low-speed auxiliary signal are not yet unified, and the signal definitions are different. As a result, when the PCIe bus interface expanded through the connector works in RC interface mode or ED interface mode, the function definitions of some low-speed signals are different. It is difficult for the PCIe bus interface to achieve the same interface definition in different modes.

[0097] Most cable assemblies are connected using a crossover cable. Figure 1 shows a schematic diagram of a crossover cable connection. As shown in Figure 1, the connector is divided into side A (front) and side B (back). Side A of connector P1 is sequentially connected to side B of connector P2, and side B of connector P1 is sequentially connected to side A of connector P2, thus forming a crossover connection between the AB sides. This connection method is called a crossover cable connection.

[0098] In this connection mode, one side of the connector is a PCIe bus interface operating in RC interface mode, which is used to connect to an RC master device (also called an RC host), such as a server host; the other side is a PCIe bus interface operating in ED interface mode, which is used to connect to an ED slave device (also called an ED slave), such as an NVMe hard drive or an external network card. Therefore, RC interface mode can also be called master mode, and ED interface mode can also be called slave mode.

[0099] Taking the MCIO X8 connector as an example, when it functions as an RC interface, the pin definitions for its A and B sides are shown in Table 1 below. When it functions as an ED interface, the pin definitions for its A and B sides are shown in Table 2 below. For example, if connector P1 shown in Figure 1 is an RC interface and connector P2 is an ED interface, the pin definitions for connector P1 are shown in Table 1, and the pin definitions for connector P2 are shown in Table 2.

[0100] Table 1

[0101] Table 2

[0102] As shown in Tables 1 and 2 above, the MCIO X8 connector defines eight pairs of high-speed differential signals according to the protocol, including receive signals (PCIe_RX_DP / DN[0:7]) and transmit signals (PCIe_TX_DP / DN[0:7]). For the input and output high-speed differential data lines on both sides of the cable, the use of differential lines allows for consistent input and output definitions of the high-speed differential data lines on both connectors (or devices with connectors on both sides). This allows both connectors P1 and P2 to have their A-side defined as RX data reception and their B-side defined as TX data transmission.

[0103] In addition, the low-speed signal area of ​​the MCIO connector defines a variety of low-speed auxiliary signals, including:

[0104] (1) PCIe_RESET*: Reset signal. The RC master device can output a reset signal for resetting the enabled ED slave device. There are two sets of this signal on each X8 connector, which can support two external X4 mode ED slave devices. When used in X8 mode, PCIe_RESET0 is valid and PCIe_RESET1 is invalid.

[0105] (2) PCIe_PRSNT*: The ED slave device’s presence signal. The RC master device reads this signal to confirm whether the ED slave device is in place. If this signal is pulled low, it indicates that the ED slave device is in place.

[0106] (3) PCIe_CLK_DN / DP*: The differential clock signal of the PCIe bus, typically 100 MHz. In some embodiments, this signal is output by the RC master device to the ED slave device, providing the ED slave device with a homologous clock signal. Therefore, the signal definitions and input and output directions on the RC master device and the ED slave device are different.

[0107] (4) MCIO_SDA / SCL*: I2C (Inter-Integrated Circuit, two-wire serial bus) bus signals. SDA (Serial Data Line) is the serial data line, and SCL (Serial Clock Line) is the serial clock line. The I2C bus is a bidirectional, two-wire synchronous serial bus with a master-slave mode mechanism. Only one master device is allowed at a time. Therefore, the pin definitions for master and slave modes are different in RC mode and ED mode. Generally, the RC interface is the master device, and the ED interface is the slave device.

[0108] (5) PCIe_WAKE*: Wake-up signal. When a PCIe device enters sleep mode and the main power supply has stopped, the PCIe device uses this signal to submit a wake-up request to the processor system, causing the processor system to resume supplying the main power supply Vcc to the PCIe device.

[0109] (6) MCIO_ID*: The RC master device reads the identification (ID) signal of the ED slave device to determine whether the peer device is an X8 mode device or an X4 mode device. MCIO_IO[1:0] = 00 indicates that the ED slave device is in two X4 mode devices, and MCIO_IO[1:0] = 10 indicates that there is one X4 mode device or one X8 mode device. It is necessary to use the in-position signal (PCIe_PRSNT) to determine the port application status of the ED slave device and configure the PCIe bus port mode.

[0110] As shown in Tables 1 and 2 above, the definitions of low-speed auxiliary signals for the PCIe bus interface, such as the reference clock signal (PCIe_CLK_DP / DN), reset signal (PCIe_RESET), presence signal (PCIe_PRSNT), and I2C bus signals (MCIO_SDA / SCL), vary in different master-slave modes, making it impossible to achieve a unified interface definition. In some embodiments, the MCIO connector of the RC master device provides the reference clock signal, reset signal, I2C bus signals, etc., while the ED slave device is the receiver, receiving these low-speed auxiliary signals.

[0111] An embodiment of the present application provides a mode switching circuit that can switch the connector between the RC interface and the ED interface through simple electronic components. There is no need to replace components or cables when changing the interface mode, which greatly increases the interface flexibility and versatility of the connector when used as an external expansion interface for PCIe devices, and switching is simple.

[0112] In some embodiments, a mode switching circuit is provided, as shown in FIG1 . This mode switching circuit can expand the functionality of a connector 200 . When a PCIe device 300 is expanded based on the connector 200 , the mode switching circuit acts as a peripheral circuit of the PCIe device 300 , allowing the connector 200 to flexibly switch between an RC interface mode and an ED interface mode. The connector 200 may be a SlimSAS connector or an MCIO connector.

[0113] The mode switching circuit primarily expands the functionality of the pins corresponding to the low-speed auxiliary signals in connector 200. These pins may include: a first reverse differential pin 201, a first front differential pin 202, a second reverse differential pin 203, a second front differential pin 204, etc. It will be appreciated that the differential pins have two pins, i.e., the first reverse differential pin 201 and the like each include two pins.

[0114] One of the first reverse differential pin 201 and the first front differential pin 202 is used to transmit a differential clock signal (e.g., PCIe_CLK_DN / DP), and the other is used to transmit a reset signal (e.g., PCIe_RESET) and / or a position signal (e.g., PCIe_PRSNT). For example, the first reverse differential pin 201 may be pins B11 and B12 in Table 1 or Table 2, and the first front differential pin 202 may be pins A11 and A12 in Table 1 or Table 2. One of the second reverse differential pin 203 and the second front differential pin 204 is used to transmit an I2C bus signal (e.g., MCIO_SDA / SCL), and the other is used to transmit a wake-up signal (e.g., PCIe_WAKE) and / or an identification signal (e.g., MCIO_ID). For example, the second reverse differential pin 203 may be pins B8 and B9 in Table 1 or Table 2, and the second front differential pin 204 may be pins A8 and A9 in Table 1 or Table 2.

[0115] 1 , the mode switching circuit includes a first switching circuit 101 , a second switching circuit 102 , a clock switching circuit 103 and a first bidirectional level converter 104 .

[0116] The input end of the first switching circuit 101 is configured to be connected to the first reverse differential pin 201 of the connector 200, the first output end is configured to be connected to the first reset active pin of the PCIe device 300, and the second output end is connected to the clock switching circuit 103 to provide a corresponding differential clock signal, namely, an ED differential clock signal, to the clock switching circuit 103. In some embodiments, the first switching circuit 101 is configured to transmit an RC reset signal and / or an RC active signal between the first reverse differential pin 201 and the first reset active pin, or to send the ED differential clock signal transmitted by the first reverse differential pin 201 to the clock switching circuit 103. The first reset active pin of the PCIe device 300 is used to transmit an RC reset signal and an RC active signal. It will be understood that the first reset active pin includes two ports: a first reset port and a first active port. The first reset port is used to transmit the RC reset signal, and the first active port is used to receive the RC active signal.

[0117] The first input of the second switching circuit 102 is configured to be connected to the second reset active terminal of the PCIe device 300, and the second input is connected to the clock switching circuit 103 to obtain the RC differential clock signal generated by the clock switching circuit 103. The output of the second switching circuit 102 is configured to be connected to the first front differential pin 202 of the connector 200. In some embodiments, the second switching circuit 102 is configured to send an RC differential clock signal to the first front differential pin 202, or to transmit an ED reset signal and / or an ED active signal between the first front differential pin 202 and the second reset active terminal. The second reset active terminal of the PCIe device 300 is used to transmit the ED reset signal and the ED active signal. It will be understood that the second reset active terminal includes two ports, namely, a second reset terminal and a second active terminal. The second reset terminal is used to receive the ED reset signal, and the second active terminal is used to send the ED active signal.

[0118] The first group of level conversion channels of the first bidirectional level converter 104 is configured to transmit data between the second reverse differential pins 203 of the connector 200 and the first data port of the PCIe device 300, and the second group of level conversion channels is configured to transmit data between the second front differential pins 204 of the connector 200 and the second data port of the PCIe device 300. Since the second reverse differential pins 203 and the second front differential pins 204 each include two pins, each group of level conversion channels of the first bidirectional level converter 104 includes at least two level conversion channels. Therefore, the first bidirectional level converter 104 includes at least four level conversion channels. As shown in FIG1 , the first and second level conversion channels (corresponding to A1-B1 and A2-B2) of the first bidirectional level converter 104 are connected to the second reverse differential pins 203, and the third and fourth level conversion channels (corresponding to A3-B3 and A4-B4) are connected to the second front differential pins 204.

[0119] The first data port and the second data port of the PCIe device 300 are used for data transmission with the connector 200. One of the ports is used for transmitting I2C bus signals, and the other is used for transmitting a wake-up signal and / or an identification signal. Furthermore, both sets of level conversion channels of the first bidirectional level converter 104 can be configured to transmit I2C bus signals, or to transmit a wake-up signal and / or an identification signal.

[0120] The first bidirectional level converter 104 can implement bidirectional level conversion, that is, it can implement level conversion when side A is the input end and side B is the output end, or when side B is the input end and side A is the output end. In other words, the first bidirectional level converter 104 can implement bidirectional data transmission between the connector 200 and the PCIe device 300, and its level conversion channel can transmit both I2C bus signals and wake-up signals and / or identification signals.

[0121] The clock switching circuit 103 can determine whether to actively generate a differential clock signal in different modes. The clock switching circuit 103 is configured to generate a reference clock signal sent to the PCIe device 300 and an RC differential clock signal sent to the second switching circuit 102, or to generate a reference clock signal sent to the PCIe device 300 based on the ED differential clock signal. In different modes, the clock switching circuit 103 performs different functions. In RC interface mode, as an RC master device, it needs to provide a differential clock signal to the outside world. Therefore, it needs to actively generate a differential clock signal, namely an RC differential clock signal.

[0122] The working principle of the mode switching circuit is as follows:

[0123] FIG2 shows the pin function definition of the connector 200 in RC interface mode, which is consistent with Table 1 above. As shown in FIG2 , in RC interface mode, the first reset in-position terminal of the PCIe device 300 can transmit corresponding reset signals and in-position signals, namely, the RC reset signal and the RC in-position signal. The first switching circuit 101 is configured to transmit the RC reset signal and / or the RC in-position signal between the first reverse differential pin 201 and the first reset in-position terminal, thereby being able to send the RC reset signal to the opposite end or receive the RC in-position signal sent by the opposite end based on the first reverse differential pin 201. In this case, the local device is the RC master device, and the opposite end is generally an ED slave device.

[0124] Furthermore, the mode switching circuit needs to provide a differential clock signal, i.e., an RC differential clock signal, to the opposite end. In some embodiments, the clock switching circuit 103 is configured to generate a reference clock signal sent to the PCIe device 300 and an RC differential clock signal sent to the second switching circuit 102. The second switching circuit 102 is configured to send the RC differential clock signal to the first front differential pin 202, thereby providing the RC differential clock signal to the opposite end connected to the connector 200. The reference clock signal is the clock signal required for the PCIe device 300 to operate. For example, in response to determining that the PCIe device 300 is an FPGA (Field Programmable Gate Array), two homologous reference clock signals can be provided to it.

[0125] In the RC interface mode, the first group of level conversion channels of the first bidirectional level converter 104 is configured to transmit I2C bus signals, and the second group of level conversion channels is configured to transmit wake-up signals and / or identification signals.

[0126] As shown in Figure 2, in the RC interface mode, the first reverse differential pin 201 is used to transmit the RC reset signal (PCIe_RESET) and the RC in-position signal (PCIe_PRSNT), the first front differential pin 202 is used to transmit the RC differential clock signal (PCIe_CLK_DP / DN), the second reverse differential pin 203 is used to transmit the I2C bus signal (MCIO_SDA / SCL), and the second front differential pin 204 is used to transmit the wake-up signal (MCIO_WAKE) and the identification signal (MCIO_ID).

[0127] Figure 3 shows the pin function definitions of connector 200 in ED interface mode, which are consistent with Table 2 above. As shown in Figure 3, in ED interface mode, a differential clock signal, namely an ED differential clock signal, must be provided by the peer end. In some embodiments, first switching circuit 101 is configured to transmit the ED differential clock signal transmitted by first reverse differential pin 201 to clock switching circuit 103. Clock switching circuit 103 is configured to generate a reference clock signal based on the ED differential clock signal, which is then transmitted to PCIe device 300.

[0128] The second reset and presence terminal of the PCIe device 300 can transmit corresponding reset signals and presence signals, namely, an ED reset signal and an ED presence signal. The second switching circuit 102 is configured to transmit the ED reset signal and / or the ED presence signal between the first front differential pin 202 and the second reset and presence terminal, thereby being able to send the ED presence signal to the peer end or receive the ED reset signal sent by the peer end based on the first front differential pin 202. In this case, the local device is an ED slave device, and the peer end is generally an RC master device.

[0129] In ED interface mode, the first set of level-shifting channels of the first bidirectional level translator 104 is configured to transmit a wake-up signal and / or an identification signal, and the second set of level-shifting channels is configured to transmit I2C bus signals. That is, in RC interface mode or ED interface mode, the two sets of level-shifting channels of the first bidirectional level translator 104 have opposite functions.

[0130] As shown in Figure 3, in the ED interface mode, the first reverse differential pin 201 is used to transmit the ED differential clock signal (PCIe_CLK_DP / DN), the first front differential pin 202 is used to transmit the ED reset signal (PCIe_RESET) and the ED presence signal (PCIe_PRSNT), the second reverse differential pin 203 is used to transmit the wake-up signal (MCIO_WAKE) and the identification signal (MCIO_ID), and the second front differential pin 204 is used to transmit the I2C bus signal (MCIO_SDA / SCL).

[0131] In some embodiments, since each level conversion channel in the first bidirectional level converter 104 can implement bidirectional data transmission, any group of level conversion channels therein can transmit I2C bus signals, or transmit wake-up signals and / or identification signals. The PCIe device 300 can independently determine the functions of its first data terminal and second data terminal. In some embodiments, in RC interface mode, the PCIe device 300 sets its first data terminal to transmit I2C bus signals, and its second data terminal to transmit wake-up signals and / or identification signals. In ED interface mode, the PCIe device 300 sets its first data terminal to transmit wake-up signals and / or identification signals, and its second data terminal to transmit I2C bus signals.

[0132] Some embodiments provide a mode switching circuit that uses simple electronic components to switch connector 200 between an RC interface and an ED interface. This eliminates the need to replace components or cables when changing interface modes, significantly increasing the flexibility and versatility of connector 200 as an external expansion interface for PCIe devices and simplifying switching. Furthermore, a PCIe device can function as both a master device connecting to external devices and a slave device connecting to a server host, enabling flexible switching in different application scenarios. This reduces labor costs and the cost of external accessories, significantly increasing product competitiveness.

[0133] In some embodiments, the first switching circuit 101 is used to implement switching between the differential clock signal and the reset in-position signal. For example, the first switching circuit 101 can be a multiplexer (MUX) or the like to select the input end and the first output end of the first switching circuit 101, or select the input end and the second output end to implement signal switching. However, this switching method is relatively complex to implement. In some embodiments, the mode switching circuit is further provided with a three-state level conversion circuit, namely, a first three-state level conversion circuit 105. In addition to outputting a high level and a low level, the three-state level conversion circuit also has a high impedance state. The characteristic that the high impedance state does not affect the signal is utilized to implement signal switching.

[0134] In some embodiments, as shown in FIG4 , the mode switching circuit further includes: a first tri-state level conversion circuit 105. A port on one side of the first tri-state level conversion circuit 105 (such as the port on the right side of FIG4 ) is connected to the first output terminal of the first switching circuit 101, and a port on the other side (such as the port on the left side of FIG4 ) is configured to be connected to the first reset in-position terminal of the PCIe device 300. In the RC interface mode, the first tri-state level conversion circuit 105 is configured to transmit an RC reset signal and / or an RC in-position signal. In the ED interface mode, the port of the first tri-state level conversion circuit 105 is in a high-impedance state. At this time, the input and output terminals of the first switching circuit 101 can be directly connected, that is, the input terminal of the first switching circuit 101 is connected to the first output terminal, and the input terminal of the first switching circuit 101 is also connected to the second output terminal.

[0135] In some embodiments, a side port of the first tri-state level conversion circuit 105 is connected to the first output terminal of the first switching circuit 101, which can be directly connected to the first reverse differential pin 201 of the connector 200. Furthermore, the first reverse differential pin 201 can also be directly connected to the clock switching circuit 103 to provide the ED differential clock signal thereto in the ED interface mode.

[0136] In the RC interface mode, the first tri-state level shifter 105 can operate normally, that is, it can perform level shifting between the connector 200 and the PCIe device 300 to transmit an RC reset signal and / or an RC in-position signal between the two. In this case, although the RC reset signal and / or the RC in-position signal may affect the ED differential clock signal, since the reset signal and the in-position signal have very low signal rates, their impact on the differential clock signal can be ignored. That is, the first tri-state level shifter 105 transmits the RC reset signal and / or the RC in-position signal, and substantially does not affect the operation of the clock switching circuit 103.

[0137] In ED interface mode, first tri-state level shifter 105 is inactive, and its port is in a high-impedance state. Specifically, the first output of first switching circuit 101 is in a high-impedance state. At this time, the ED differential clock signal is transmitted between the input and second output of first switching circuit 101. The high-impedance state of first tri-state level shifter 105 has minimal impact on the ED differential clock signal, essentially preventing it from affecting the normal generation of the ED differential clock signal. Therefore, first reverse differential pin 201 of connector 200 can normally provide the ED differential clock signal.

[0138] In some embodiments, the first tri-state level shifter 105, whose port output is in a high-impedance state when not in operation, not only performs level shifting between the connector 200 and the PCIe device 300 to isolate signals, but also maintains the ED differential clock signal in the high-impedance state. This simplifies the circuit structure of the first switching circuit 101, allowing it to transmit different signals in different modes, thus achieving signal switching.

[0139] In some embodiments, as shown in FIG5 , the first tri-state level conversion circuit 105 includes a first tri-state level converter 1051. The first tri-state level converter 1051 is configured to connect the first output terminal of the first switching circuit 101 to the first reset-in-position terminal of the PCIe device 300. The enable terminal of the first tri-state level converter 1051 is configured to receive an RC enable signal, which is valid in the RC interface mode.

[0140] In some embodiments, data transmission between the connector 200 and the PCIe device 300 is implemented by a first tri-state level converter 1051. For example, the first tri-state level converter 1051 can be a directional level converter, such as TXU0202, etc., one of which (A1-B1Y shown in FIG5 ) is used to send an RC reset signal to the first reverse differential pin 201 of the connector 200, and the other (B2-A2Y shown in FIG5 ) is used to send an RC presence signal to the PCIe device 300.

[0141] The enable terminal (OE) of the first tri-state level converter 1051 is connected to an RC enable signal, which is an enable signal generated by the PCIe device 300. In the RC interface mode, the PCIe device 300 outputs a valid RC enable signal, allowing the first tri-state level converter 1051 to operate normally. Conversely, in the ED interface mode, the PCIe device 300 outputs an invalid RC enable signal, causing the port of the first tri-state level converter 1051 to be in a high-impedance state.

[0142] Generally, when the enable terminal (OE) of the first tri-state level converter 1051 is at a high level, it can operate normally, that is, when the RC enable signal is at a high level, it is valid. In response to determining that the enable terminal (OE) of the first tri-state level converter 1051 is at a low level, all output pins of the first tri-state level converter 1051 are in a high impedance state.

[0143] In some embodiments, the first tri-state level converter 1051 is further provided with a power supply terminal, which is generally connected to a high level. If the power supply terminal is connected to a low level, all ports will also be in a high impedance state. For example, as shown in FIG5 , the power supply terminal can be V CCA or V CCB , when VCCA or V CCB When any voltage in the ED interface is less than 100mV, all ports will be in a high-impedance state, which is equivalent to a disconnected state with no impact on the circuit. To ensure that it can be in a high-impedance state in ED interface mode, the voltage of the power supply terminal is also controlled based on a level circuit.

[0144] In some embodiments, as shown in FIG5 , the first tri-state level conversion circuit 105 further includes a first level circuit 1052. The first level circuit 1052 is connected to the power supply terminal of the first tri-state level converter 1051. In the RC interface mode, the first level circuit 1052 is configured to provide a reference voltage to the first tri-state level converter 1051. For example, the reference voltage is 3.3V. In the ED interface mode, the first level circuit 1052 is configured to stop supplying power, causing the power supply terminal of the first tri-state level converter 1051 to be at a low voltage level, and all its ports to be in a high-impedance state.

[0145] In some embodiments, as shown in FIG5 , the first level circuit 1052 includes: a first switch tube M1. The input end of the first switch tube M1 is connected to the power supply V CC The output end is connected to the power supply end of the first tri-state level converter 1051. The control end of the first switch tube M1 is connected to the RC enable signal. When the RC enable signal is valid, the first switch tube M1 is turned on.

[0146] For example, when the RC enable signal is at a high level, the first switch tube M1 may be an NMOS (N-Metal-Oxide-Semiconductor) tube, whose drain and source are connected to the power supply V CC , the power supply end of the first tri-state level converter 1051, whose gate is connected to the RC enable signal. When the RC enable signal is high, the first switch tube M1 is turned on, and the power supply V CC Conversely, when the RC enable signal is at a low level, the first switch tube M1 is turned off, the power supply terminal of the first tri-state level converter 1051 is at a low level, and all its ports are in a high impedance state.

[0147] Furthermore, to ensure the signal quality of the clock signal, bifurcation of the clock signal line is generally not permitted. Therefore, in some embodiments, in the first switching circuit 101, the input terminal and the second output terminal of the first switching circuit 101 are directly connected via a first wire 1011. A first via is provided on the pin of a port on one side of the first tri-state level conversion circuit 105, and the first wire 1011 passes through the first via and is electrically connected to the first via.

[0148] In some embodiments, as shown in FIG5 , the input and second output terminals of the first switching circuit 101 are directly connected via a first conductor 1011. Specifically, the first reverse differential pin 201 and the clock switching circuit 103 are directly connected via the first conductor 1011. It will be appreciated that the first conductor 1011 needs to transmit an ED differential clock signal and comprises two conductors. To prevent bifurcation of the clock signal line (i.e., the first conductor 1011), vias, i.e., first vias, are provided at the pins on one side of the first tri-state level shifter circuit 105. For example, first vias are provided at ports B1Y and B2 of the first tri-state level shifter 1051. Passing the first conductor 1011 through the first vias, connecting the first conductor 1011 in a via-in-disk layout, effectively prevents the impact of bifurcated lines on the clock signal.

[0149] In some embodiments, the second switching circuit 102 is also used to implement switching between the differential clock signal and the reset in-position signal. For example, the second switching circuit 102 can be a multiplexer (MUX) to select the first input terminal and output terminal of the second switching circuit 102, or select the second input terminal and output terminal to implement signal switching. In some embodiments, as shown in Figure 4, the mode switching circuit further includes: a second three-state level conversion circuit 106. Similar to the first three-state level conversion circuit 105 described above, the second three-state level conversion circuit 106 implements signal switching by outputting a high-impedance state.

[0150] As shown in FIG4 , one port of the second tri-state level shifter circuit 106 is connected to the first input terminal of the second switching circuit 102, and the other port is configured to be connected to the second reset and active terminal of the PCIe device 300. In RC interface mode, the port of the second tri-state level shifter circuit 106 is in a high-impedance state. In ED interface mode, the second tri-state level shifter circuit 106 is configured to transmit an ED reset signal and / or an ED active signal. In this case, the input and output terminals of the second switching circuit 102 can be directly connected, that is, the first input terminal of the second switching circuit 102 is connected to the output terminal, and the second input terminal of the second switching circuit 102 is also connected to the output terminal.

[0151] In some embodiments, a side port of the second tri-state level conversion circuit 106 is connected to the first input terminal of the second switching circuit 102, which can be directly connected to the first front differential pin 202 of the connector 200. Furthermore, the first front differential pin 202 can also be directly connected to the clock switching circuit 103 to obtain the RC differential clock signal provided by the clock switching circuit 103 in the RC interface mode.

[0152] In some embodiments, in RC interface mode, the second tri-state level shifter circuit 106 is inoperative, and its port is in a high-impedance state. Specifically, the first input terminal of the second switching circuit 102 is in a high-impedance state. At this time, the RC differential clock signal is transmitted between the second input terminal and the output terminal of the second switching circuit 102. The high-impedance state of the second tri-state level shifter circuit 106 has a minimal impact on the RC differential clock signal, essentially not affecting the normal generation function of the RC differential clock signal. Therefore, the clock switching circuit 103 can normally provide the RC differential clock signal to the first front differential pin 202 of the connector 200.

[0153] In ED interface mode, the second tri-state level shifter 106 can operate normally, i.e., it can perform level shifting between the connector 200 and the PCIe device 300 to transmit the ED reset signal and / or the ED in-position signal between the two. In this case, although the ED reset signal and / or the ED in-position signal may affect the RC differential clock signal, the signal rates of the reset and in-position signals are very low, and their impact on the differential clock signal can be ignored. In other words, the second tri-state level shifter 106 transmits the ED reset signal and / or the ED in-position signal, and substantially does not affect the operation of the clock switching circuit 103.

[0154] In some embodiments, the second tri-state level shifter 106, whose port output is in a high-impedance state when not in operation, can not only achieve level shifting between the connector 200 and the PCIe device 300 to isolate signals, but also maintain the RC differential clock signal in the high-impedance state. This simplifies the circuit structure of the second switching circuit 102, allowing the second switching circuit 102 to transmit different signals in different modes, thereby achieving signal switching.

[0155] In some embodiments, as shown in FIG6 , the second tri-state level conversion circuit 106 includes a second tri-state level converter 1061. The second tri-state level converter 1061 is configured to connect the first input terminal of the second switching circuit 102 to the second reset-in-position terminal of the PCIe device 300. The enable terminal of the second tri-state level converter 1061 is configured to receive an ED enable signal, which is valid in the ED interface mode.

[0156] In some embodiments, data transmission between the connector 200 and the PCIe device 300 is implemented by a second tri-state level converter 1061. For example, the second tri-state level converter 1061 can be a directional level converter, such as TXU0202, etc., one of which (A1-B1Y shown in FIG6 ) is used to send an ED in-position signal to the first front differential pin 202 of the connector 200, and the other (B2-A2Y shown in FIG6 ) is used to send an ED reset signal to the PCIe device 300.

[0157] The enable terminal (OE) of the second tri-state level converter 1061 is connected to an ED enable signal, which is an enable signal generated by the PCIe device 300. In the ED interface mode, the PCIe device 300 outputs a valid ED enable signal, allowing the second tri-state level converter 1061 to operate normally. Conversely, in the RC interface mode, the PCIe device 300 outputs an invalid ED enable signal, causing the port of the second tri-state level converter 1061 to be in a high-impedance state.

[0158] Generally, when the enable terminal (OE) of the second tri-state level converter 1061 is at a high level, it can operate normally, that is, when the ED enable signal is at a high level, it is valid. In response to determining that the enable terminal (OE) of the second tri-state level converter 1061 is at a low level, all output pins of the second tri-state level converter 1061 are in a high impedance state.

[0159] In some embodiments, as shown in FIG6 , the second tri-state level conversion circuit 106 further includes a second level circuit 1062. The second level circuit 1062 is connected to the power supply terminal of the second tri-state level converter 1061. In the RC interface mode, the second level circuit 1062 is configured to stop supplying power, causing the power supply terminal of the second tri-state level converter 1061 to be at a low level and all its ports to be in a high-impedance state. In the ED interface mode, the second level circuit 1062 is configured to provide a reference voltage to the second tri-state level converter 1061, for example, 3.3V.

[0160] In some embodiments, as shown in FIG6 , the second level circuit 1062 includes: a second switch tube M2. The input end of the second switch tube M2 is connected to the power supply V CC The output end is connected to the power supply end of the second tri-state level converter 1061. The control end of the second switch tube M2 is connected to the ED enable signal. When the ED enable signal is valid, the second switch tube M2 is turned on.

[0161] For example, when the RC enable signal is at a high level, the second switch tube M2 may be an NMOS tube, the drain and source of which are connected to the power supply V CC , the power supply end of the second tri-state level converter 1061, whose gate is connected to the ED enable signal. When the ED enable signal is high, the second switch tube M2 is turned on, and the power supply V CC Conversely, when the ED enable signal is at a low level, the second switch tube M2 is turned off, the power supply terminal of the second tri-state level converter 1061 is at a low level, and all its ports are in a high impedance state.

[0162] Furthermore, to ensure the signal quality of the clock signal, bifurcation of the clock signal line is generally not permitted. In some embodiments, in the second switching circuit 102, the second input terminal and the output terminal of the second switching circuit 102 are directly connected via a second wire 1021. A second via is provided on the pin of a port on one side of the second tri-state level conversion circuit 106, and the second wire 1021 passes through the second via and is electrically connected to the second via.

[0163] In some embodiments, as shown in FIG6 , the second input terminal and the output terminal of the second switching circuit 102 are directly connected via a second wire 1021 , i.e., the first positive differential pin 202 and the clock switching circuit 103 are directly connected via the second wire 1021 . It can be understood that the second wire 1021 needs to transmit an RC differential clock signal, which includes two wires. In order to prevent the clock signal line (i.e., the second wire 1021) from bifurcation, a via, i.e., a second via, is provided on the pin of the port on one side of the second three-state level converter 106 . For example, a first via is provided on the ports B1Y and B2 of the second three-state level converter 1061 . Passing the second wire 1021 through the second via and connecting the second wire 1021 in a hole-in-disk layout can effectively avoid the impact on the clock signal caused by line bifurcation.

[0164] In some implementations, as shown in FIG. 7 , the clock switching circuit 103 includes a clock generator 1031 and a clock buffer 1032 .

[0165] The first output terminal (Out1) of the clock generator 1031 is connected to the first input terminal (IN1) of the clock buffer 1032 and is configured to output a local differential clock signal in RC interface mode. The second output terminal (Out2) of the clock generator 1031 is connected to the second input terminal of the second switching circuit 102, for example, to the first positive differential pin 202, and is configured to output an RC differential clock signal in RC interface mode.

[0166] The second input terminal (IN2) of the clock buffer 1032 is connected to the second output terminal of the first switching circuit 101, for example, to the first reverse differential pin 201, and is configured to receive an ED differential clock signal in ED interface mode. Furthermore, the clock buffer 1032 is configured to generate a reference clock signal for transmission to the PCIe device 300 based on the local differential clock signal or the ED differential clock signal.

[0167] In some embodiments, in RC interface mode, the clock generator 1031 operates normally, allowing the clock switching circuit 103 to output an RC differential clock signal and generate a local differential clock signal to provide a reference clock signal to the PCIe device 300. In ED interface mode, the clock generator 1031 stops operating, and the second input terminal (IN2) of the clock buffer 1032 receives the differential clock signal sent by the other end, i.e., the ED differential clock signal, to generate a reference clock signal that can be provided to the PCIe device 300.

[0168] In some embodiments, as shown in FIG7 , the enable terminal (EN) of the clock generator 1031 is configured to receive an RC enable signal. The RC enable signal is valid in RC interface mode, and when the RC enable signal is valid, the clock generator 1031 outputs a local differential clock signal and an RC differential clock signal. When the RC enable signal is invalid, that is, in ED interface mode, the clock generator 1031 is disabled and does not operate, that is, does not output an RC differential clock signal.

[0169] In addition, as shown in FIG7 , the select terminal (SEL) of the clock buffer 1032 is configured to receive a clock select signal. When the clock select signal indicates the RC interface mode, the first input terminal (IN1) of the clock buffer 1032 is valid. When the clock select signal indicates the ED interface mode, the second input terminal (IN2) of the clock buffer 1032 is valid. For example, when the clock select signal is low, the first input terminal (IN1) is selected for use, i.e., the first input terminal (IN1) is valid. When the clock select signal is high, the second input terminal (IN2) is selected for use, i.e., the second input terminal (IN2) is valid, thereby switching the input clock.

[0170] In some embodiments, the clock selection signal can be a signal generated by the PCIe device 300, or the clock selection signal can also be an RC enable signal or an ED enable signal. In some embodiments, in the RC interface mode, the PCIe device 300 generates a valid RC enable signal and a clock selection signal, and the enable terminal of the clock generator 1031 is valid, for example, connected to a high level (i.e., the RC enable signal is a high level at this time). At this time, the first output terminal (Out1) of the clock generator 1031 outputs a local differential clock signal, and the second output terminal (Out2) outputs an RC differential clock signal. Moreover, under the action of the clock selection signal, the clock buffer 1032 selects the first input terminal (IN1) as valid and its second input terminal (IN2) as invalid, that is, it does not pay attention to the signal obtained by the second input terminal (IN2).

[0171] In ED interface mode, the PCIe device 300 generates an invalid RC enable signal and clock select signal, and the enable terminal of the clock generator 1031 is invalid, so it does not operate. For example, all output ports are in a high-impedance state. In addition, under the action of the clock select signal, the clock buffer 1032 selects the first input terminal (IN1) to be invalid and the second input terminal (IN2) to be valid. In other words, it does not pay attention to the signal obtained by the first input terminal (IN1), but instead obtains the ED differential clock signal based on the second input terminal (IN2), thereby providing the corresponding reference clock signal to the PCIe device 300, allowing the PCIe device 300 to operate based on the ED differential clock signal provided by the other end.

[0172] Since the connector 200 can operate in a larger modulus mode, such as X8 mode or X16 mode, and there can be multiple connectors 200, it may be necessary to provide multiple sets of differential clock signals to the outside. In some embodiments, the clock generator 1031 can output multiple sets of differential clock signals. As shown in Figure 7, the clock generator 1031 can output five clock signals, one of which (Out1) is a local differential clock signal, another (Out2) is an RC differential clock signal, and the remaining output terminals (Out3, Out4, and Out5) can also provide corresponding differential clock signals to the outside.

[0173] In some embodiments, the clock generator 1031 and the clock buffer 1032 can be used to switch the clock signal in different modes. When acting as an RC master device, it can provide an RC differential clock signal to the other end. When acting as an ED slave device, it can operate based on the ED differential clock signal provided by the other end.

[0174] In some embodiments, the mode switching circuit further includes a mode selection circuit 109. The mode selection circuit 109 is configured to provide a mode selection signal to the PCIe device 300 indicating that the RC interface mode or the ED interface mode is currently selected.

[0175] In some embodiments, a user can actively select a desired mode based on the hardware structure provided by the mode selection circuit 109. In some embodiments, the mode selection circuit 109 is connected to the PCIe device 300, and the mode selection circuit 109 can send a mode selection signal to the PCIe device 300 to actively select whether the RC interface mode or the ED interface mode is currently required.

[0176] In some embodiments, as shown in FIG8 , the mode selection circuit 109 includes: a selection switch SW1 , a first resistor R1 and a second resistor R2 . As shown in FIG8 , one end of the first resistor R1 is connected to a power supply V CC, and the other end is connected to the ground through the selection switch SW1 and the second resistor R2. Alternatively, one end of the selection switch SW1 is connected to the power supply V CC The other end is grounded through the first resistor R1 and the second resistor R2 in sequence.

[0177] The first resistor R1 and the second resistor R2 form a voltage divider circuit, and the selection switch SW1 is used to control whether the circuit where the first resistor R1 and the second resistor R2 are located is conductive. For example, as shown in FIG8 , the selection switch SW1 is a dip switch. When the dip switch is set to ON, the dip switch is conductive, and the power supply V CC When the dip switch is set to OFF, the dip switch is turned off and the power supply V CC No power supply.

[0178] Furthermore, as shown in FIG8 , one end of the second resistor R2 close to the first resistor R1 is configured to be connected to the PCIe device 300 to provide a mode selection signal. When the selection switch SW1 is turned on, for example, when the dip switch is set to ON, the power supply V CC Power can be supplied, at this time the connection node between the first resistor R1 and the second resistor R2 has a level, and the mode selection circuit 109 outputs a high-level mode selection signal. When the selection switch SW1 is turned off, for example, when the dip switch is set to OFF, the power supply V CC When no power is supplied, the voltage at the connection node between the first resistor R1 and the second resistor R2 is 0, so the mode selection circuit 109 outputs a low-level mode selection signal.

[0179] In some embodiments, by turning the selector switch SW1 on and off, a high or low level mode selection signal can be output to the PCIe device 300, thereby informing the PCIe device 300 of the current operating mode and enabling mode switching. Furthermore, by operating the selector switch SW1, the connector 200 can be selected to function as a PCIe RC master device or a PCIe ED slave device, providing flexible switching.

[0180] In some embodiments, if the connector 200 is an X8 mode connector, such as an MCIO X8 connector, in addition to the low-speed auxiliary signal pins such as the first reverse differential pin 201, the first front differential pin 202, the second reverse differential pin 203, and the second front differential pin 204, it also includes a third reverse differential pin 205, a third front differential pin 206, a fourth reverse differential pin 207, a fourth front differential pin 208, etc.

[0181] Similar to the first reverse differential pin 201, the first front differential pin 202, the second reverse differential pin 203, and the second front differential pin 204, one of the third reverse differential pin 205 and the third front differential pin 206 is used to transmit a differential clock signal (e.g., PCIe_CLK_DN / DP), and the other is used to transmit a reset signal (e.g., PCIe_RESET) and / or a position signal (e.g., PCIe_PRSNT). For example, the third reverse differential pin 205 may be pins B29 and B30 in Table 1 or Table 2, and the third front differential pin 206 may be pins A29 and A30 in Table 1 or Table 2. One of the fourth reverse differential pin 207 and the fourth front differential pin 208 is used to transmit an I2C bus signal (e.g., MCIO_SDA / SCL), and the other is used to transmit a wake-up signal (e.g., PCIe_WAKE) and / or an identification signal (e.g., MCIO_ID). For example, the fourth reverse differential pin 207 may be pins B26 and B27 in Table 1 or Table 2, and the fourth forward differential pin 208 may be pins A26 and A27 in Table 1 or Table 2.

[0182] For a connector supporting the X8 mode, as shown in FIG. 9 , the mode switching circuit further includes: a second bidirectional level converter 107 and a third tri-state level conversion circuit 108 .

[0183] One side port of the third three-state level conversion circuit 108 is connected to the third reverse differential pin 205 of the connector 200, and the other side port is configured to be connected to the third reset and active terminal of the PCIe device 300. The third reset and active terminal of the PCIe device 300 is also used to transmit an RC reset signal and an RC active signal. It will be understood that the third reset and active terminal includes two ports: a third reset terminal and a third active terminal, which are used to transmit the RC reset signal and receive the RC active signal, respectively.

[0184] The first group of level conversion channels of the second bidirectional level converter 107 is configured to transmit data between the fourth reverse differential pin 207 of the connector 200 and the third data terminal of the PCIe device 300, and the second group of level conversion channels is configured to transmit data between the fourth front differential pin 208 of the connector 200 and the fourth data terminal of the PCIe device 300.

[0185] In some embodiments, the operating principle of the third tri-state level shifter circuit 108 is similar to that of the first tri-state level shifter circuit 105. For example, the third tri-state level shifter circuit 108 has the same structure as the first tri-state level shifter circuit 105. Furthermore, the operating principle of the second bidirectional level shifter 107 is similar to that of the first bidirectional level shifter 104. For example, the second bidirectional level shifter 107 has the same structure as the first bidirectional level shifter 104. The first bidirectional level shifter 104 and the second bidirectional level shifter 107 can be level shifter modules that support I2C bus and GPIO (General Purpose Input / Output) signals, such as LSF0204. Thus, after level shifting, they can be connected to GPIO pins of the PCIe device 300 to transmit I2C bus signals, wake-up signals, etc. to the PCIe device 300.

[0186] In some embodiments, in RC interface mode, the third tri-state level shifter circuit 108 is configured to transmit an RC reset signal and / or an RC in-position signal. The first group of level shifter channels of the second bidirectional level shifter 107 is configured to transmit I2C bus signals, and the second group of level shifter channels is configured to transmit a wake-up signal and / or an identification signal. Furthermore, the third front differential pin 206 provides a differential clock signal to the opposite end. For example, as shown in FIG7 , other outputs of the clock generator 1031, such as output Out3, can provide a corresponding differential clock signal to the third front differential pin 206 so as to provide the differential clock signal to the opposite end device.

[0187] In ED interface mode, the ports of the third tri-state level shifter circuit 108 are in high impedance state. The first group of level shifter channels of the second bidirectional level shifter 107 is configured to transmit wake-up signals and / or identification signals, and the second group of level shifter channels is configured to transmit I2C bus signals.

[0188] In some embodiments, when the connector 200 connected to the mode switching circuit operates in X8 mode, its third reverse differential pin 205, third front differential pin 206, fourth reverse differential pin 207, and fourth front differential pin 208 are all inactive, and therefore the second bidirectional level shifter 107 and the third three-state level shifter circuit 108 may not operate. When the connector 200 operates in X4 mode, it can be divided into two X4 mode connectors, that is, it can support two X4 external devices. In this case, the third three-state level shifter circuit 108 and the first three-state level shifter circuit 105 correspond to different external devices and correspond to different RC reset signals and RC in-position signals. Similarly, the second bidirectional level shifter 107 and the first bidirectional level shifter 104 also correspond to different external devices.

[0189] The mode switching circuit provided in some embodiments is applicable to both X4 mode connectors and X8 mode connectors, and is still applicable when two X8 mode connectors are combined to form an X16 specification connector, thus having wide applicability.

[0190] In some embodiments, a mode switching method is provided. This method is implemented based on any of the mode switching circuits provided in the above embodiments, for example, the mode switching circuit shown in FIG1 . The method performs different steps in different modes. In some embodiments, in RC interface mode, the method includes steps a1 through a4. In ED interface mode, the method includes steps b1 through b4.

[0191] Step a1: Control the first switching circuit 101 to transmit an RC reset signal and / or an RC presence signal between the first reverse differential pin 201 of the connector 200 and the first reset presence terminal of the PCIe device 300 .

[0192] Step a2: Control the clock switching circuit 103 to generate a reference clock signal sent to the PCIe device 300 and an RC differential clock signal sent to the second switching circuit 102 .

[0193] Step a3: Control the second switching circuit 102 to send an RC differential clock signal to the first front differential pin 202 of the connector 200 .

[0194] Step a4: Control the first group of level conversion channels of the first bidirectional level converter 104 to transmit I2C bus signals, and the second group of level conversion channels to transmit wake-up signals and / or identification signals.

[0195] Step b1: Control the first switching circuit 101 to send the ED differential clock signal transmitted by the first reverse differential pin 201 of the connector 200 to the clock switching circuit 103 .

[0196] Step b2: Control the clock switching circuit 103 to generate a reference clock signal sent to the PCIe device 300 according to the ED differential clock signal.

[0197] Step b3: Control the second switching circuit 102 to transmit the ED reset signal and / or the ED presence signal between the first front differential pin 202 of the connector 200 and the second reset presence terminal of the PCIe device 300 .

[0198] Step b4: Control the first group of level conversion channels of the first bidirectional level converter 104 to transmit the wake-up signal and / or the identification signal, and the second group of level conversion channels to transmit the I2C bus signal.

[0199] In some embodiments, the principles of steps a1 to a4, and steps b1 to b4, are the same as the operating principles of the mode switching circuit shown in FIG1 , and are not described in detail herein. The mode switching method can be executed by the PCIe device 300 , i.e., the PCIe device 300 can control the operation of the first switching circuit 101 , the second switching circuit 102 , the control clock switching circuit 103 , and the first bidirectional level converter 104 in different modes, thereby enabling the PCIe device 300 to function as a corresponding master or slave device in either the RC interface mode or the ED interface mode, achieving master-slave mode compatibility.

[0200] In some embodiments, an expansion connector is provided for expanding a PCIe device 300. In some embodiments, the expansion connector includes: a connector 200 and any one of the mode switching circuits provided in the above embodiments.

[0201] In some embodiments, the mode switching circuit can be used to unify the RC interface and the ED interface on the same connector 200, so that the external expansion connector has universality and can support arbitrary switching of master-slave modes, thereby enabling the device to seamlessly connect to various application scenarios.

[0202] In some embodiments, a PCIe board is provided, comprising: a PCIe device 300 and at least one expansion connector as described above. The PCIe device 300 is provided with RC firmware and ED firmware. In RC interface mode, the PCIe device 300 loads the RC firmware; in ED interface mode, the PCIe device 300 loads the ED firmware.

[0203] In some embodiments, RC firmware and ED firmware are pre-installed in the PCIe device 300. In RC interface mode, for example, based on a mode selection signal output by the mode selection circuit 109, the PCIe device 300 determines that the current interface mode is RC. The RC firmware is then loaded, thereby configuring its first reset active terminal to transmit an RC reset signal and receive an RC active signal, configuring its first data terminal to transmit an I2C bus signal, configuring its second data terminal to transmit a wake-up signal and / or an identification signal, and configuring the function of the port connected to the first bidirectional level shifter 104. In ED interface mode, the PCIe device 300 loads the ED firmware, disables its first reset active terminal, configures its first data terminal to transmit a wake-up signal and / or an identification signal, configures its second data terminal to transmit an I2C bus signal, and configures the function of the port connected to the first bidirectional level shifter 104.

[0204] The PCIe bus interface of the PCIe device 300 is connected to the expansion connector. It can be connected to the high-speed differential signal interface of the expansion connector via an R-tile hardware interface, for example, to the connector's differential pairs such as PCIe_RX_DP / DN[0:7] and PCIe_TX_DP / DN[0:7]. Furthermore, the PCIe device 300 can access low-speed auxiliary signals via GPIO pins. The aforementioned first reset pin and first data pin are both GPIO pins.

[0205] In some embodiments, when the expansion connector includes the mode selection circuit 109 , the PCIe device 300 is configured to: load RC firmware in response to an RC mode instruction triggered by the mode selection circuit 109 ; and load ED firmware in response to an ED mode instruction triggered by the mode selection circuit 109 .

[0206] In some embodiments, taking the mode selection circuit 109 shown in FIG8 as an example, in response to determining that the selection switch SW1 is set to ON, a high-level mode selection signal can be provided to the PCIe device 300. This is equivalent to inputting an RC mode instruction. Therefore, the PCIe device 300 can load RC firmware to control the mode switching circuit to operate in RC interface mode, such as outputting a high-level RC enable signal. Conversely, in response to determining that the selection switch SW1 is set to OFF, a low-level mode selection signal can be provided to the PCIe device 300. This is equivalent to inputting an ED mode instruction. Therefore, the PCIe device 300 can load ED firmware to control the mode switching circuit to operate in ED interface mode, such as outputting a high-level ED enable signal.

[0207] In some embodiments, the PCIe device 300 includes an Ethernet optical port configured to connect to a remote server to achieve storage data sharing and migration.

[0208] For example, taking the PCIe device 300 using an FPGA as the main processing core, a structural schematic diagram of the PCIe board can be seen in Figure 10. As shown in Figure 10, in the PCIe board, the FPGA is peripherally equipped with a DDR SODIMM (Double Data Rate Synchronous Dynamic Random Access Memory, such as DDR4 SODIMM) for data temporary storage, two Ethernet optical ports, and some basic components. Figure 10 uses a 100G QSFP28 Ethernet optical port as an example. In addition, the FPGA is equipped with two PCIe Gen5 x16 interfaces, one of which is a gold finger mode ED end slave mode device interface (PCIe Gen5.0 x16 Endpoint), and the other is implemented through an external expansion connector provided in some embodiments to achieve interface expansion. Figure 10 uses two x8 external expansion connectors (MCIO PCIe x8) to expand the PCIe Gen5 x16 interface.

[0209] As mentioned above, the external expansion connector supports both RC master device port and ED slave device port. The two interfaces realize compatibility design on the same interface, and the external support is synchronized with the server interface definition method. The same cable can be inserted into the server to connect to the server PCIe bus, or directly connected to the normal MCIO external expansion slave device inside the server, such as NVMe (Non-Volatile Memory Express, non-volatile memory host controller interface specification) hard disk, etc., so that the PCIe board can be used as an RC host port.

[0210] For example, the PCIe board shown in Figure 10 can be used in the server expansion scenario. As shown in Figure 11, one end of the PCIe board working in the golden finger mode (PCIe Gen5.0 x16 Endpoint) can be connected to the PCIe slot of the server. The interface of the PCIe board is defined as the RC interface mode, which can be connected to the backplane interface of the NVMe expansion hard disk. Since the definition of the PCIe board interface in some embodiments is consistent with the interface definition of the server, the cable in the server (the cable corresponding to the dotted line in Figure 11) can be directly replaced with the PCIe board, thereby realizing the architectural design of storage acceleration. In addition, the PCIe board can also be connected to a remote server through an Ethernet network, thereby realizing storage data sharing and migration.

[0211] As shown in Figure 12, if the PCIe card's interface is defined as ED interface mode, it can be directly connected to the server's MCIO interface (MCIO PCIe x8) via a cable, thereby enabling PCIe device expansion. Because the interfaces are compatible, simply relocating the cable connector and flipping the selector switch SW1 on the PCIe card mode selection circuit 109 before re-powering the system can achieve a new architecture mode.

[0212] In some embodiments, a mode switching circuit can be used to implement different interface definitions on the same connector, thereby implementing RC interface mode and ED interface mode on the same connector, and being compatible with both modes. This allows the PCIe device 300 to flexibly switch between PCIe master-slave modes, is reusable, and has strong compatibility. The PCIe board can be used as a slave device to connect to a server host, or as a master device to connect to external devices, such as external NVME hard drives and external network cards. This can greatly save board replacement and hardware costs, and provide more application possibilities for the PCIe bus architecture, such as computing acceleration, network acceleration, storage acceleration, etc., ultimately achieving a better price-performance ratio and an ideal network and storage device deployment solution. Furthermore, when the PCIe device 300 is an FPGA device, the flexible and reconfigurable characteristics of the FPGA can be fully utilized to achieve flexible switching in different application scenarios, greatly increasing the application flexibility of the FPGA accelerator and reducing the hardware architecture deployment cost. Furthermore, this flexible master-slave mode switching method facilitates the simplification of the server's internal architecture and can also reduce costs.

[0213] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A mode switching circuit, characterized in that, Including: A first switching circuit (101), a second switching circuit (102), a clock switching circuit (103), and a first bidirectional level converter (104); The input end of the first switching circuit (101) is configured to be connected to the first reverse differential pin (201) of the connector (200). The first output end of the first switching circuit (101) is configured to be connected to the first reset present end of the Peripheral Component Interconnect Express (PCIe) device (300). The second output end of the first switching circuit (101) is connected to the clock switching circuit (103). The first switching circuit (101) is configured to transmit a Root Complex (RC) reset signal and / or an RC present signal between the first reverse differential pin (201) and the first reset present end, or to send the ED differential clock signal transmitted by the first reverse differential pin (201) to the clock switching circuit (103); The first input end of the second switching circuit (102) is configured to be connected to the second reset present end of the PCIe device (300). The second input end is connected to the clock switching circuit (103). The output end is configured to be connected to the first front differential pin (202) of the connector (200). The second switching circuit (102) is configured to send an RC differential clock signal to the first front differential pin (202), or to transmit an Endpoint (ED) reset signal and / or an ED present signal between the first front differential pin (202) and the second reset present end; The clock switching circuit (103) is configured to generate a reference clock signal sent to the PCIe device (300) and an RC differential clock signal sent to the second switching circuit (102), or to generate a reference clock signal sent to the PCIe device (300) according to the ED differential clock signal; and The first group of level conversion channels of the first bidirectional level converter (104) are configured to perform data transmission between the second reverse differential pin (203) of the connector (200) and the first data end of the PCIe device (300). The second group of level conversion channels are configured to perform data transmission between the second front differential pin (204) of the connector (200) and the second data end of the PCIe device (300). Both groups of level conversion channels of the first bidirectional level converter (104) can be configured to transmit I2C bus signals, or to be configured to transmit wake-up signals and / or identification signals.

2. The mode switching circuit according to claim 1, wherein Also including: A first three-state level conversion circuit (105); The first side port of the first three-state level conversion circuit (105) is connected to the first output end of the first switching circuit (101). The second side port of the first three-state level conversion circuit (105) is configured to be connected to the first reset present end of the PCIe device (300); The first tri-state level conversion circuit (105) is configured to: transmit an RC reset signal and / or an RC presence signal in the RC interface mode; or The port of the first tri-state level conversion circuit (105) is in a high impedance state in the ED interface mode.

3. The mode switching circuit according to claim 2, wherein The first tri-state level conversion circuit (105) includes a first tri-state level converter (1051); the first tri-state level converter (1051) is configured to connect the first output terminal of the first switching circuit (101) to the first reset presence terminal of the PCIe device (300); And The enable terminal of the first tri-state level converter (1051) is configured to receive an RC enable signal, and the RC enable signal is valid in the RC interface mode.

4. The mode switching circuit according to claim 3, wherein The first tri-state level conversion circuit (105) further includes: a first level circuit (1052); the first level circuit (1052) is connected to the power supply terminal of the first tri-state level converter (1051); The first level circuit (1052) is configured to: provide a reference level to the first tri-state level converter (1051) in the RC interface mode; or The first level circuit (1052) is configured to: stop power supply in the ED interface mode.

5. The mode switching circuit according to claim 4, wherein The first level circuit (1052) includes: a first switching transistor (M1); The input terminal of the first switching transistor (M1) is connected to a power supply, and the output terminal is connected to the power supply terminal of the first tri-state level converter (1051); and The control terminal of the first switching transistor (M1) receives the RC enable signal; in response to determining that the RC enable signal is valid, the first switching transistor (M1) conducts.

6. The mode switching circuit according to claim 2, wherein In the first switching circuit (101), the input terminal and the second output terminal of the first switching circuit (101) are directly connected through a first wire (1011); and A first via is provided on the pin of the port on one side of the first tri-state level conversion circuit (105), and the first wire (1011) passes through the first via and is electrically connected to the first via.

7. The mode switching circuit according to claim 1, wherein Further included is: A second tri-state level conversion circuit (106); The first side port of the second tri-state level conversion circuit (106) is connected to the first input terminal of the second switching circuit (102), and the second side port of the second tri-state level conversion circuit (106) is configured to be connected to the second reset presence terminal of the PCIe device (300); The port of the second tri-state level conversion circuit (106) is in a high impedance state in the RC interface mode; or The second tri-state level conversion circuit (106) is configured to: transmit an ED reset signal and / or an ED presence signal in the ED interface mode.

8. The mode switching circuit according to claim 7, characterized in that The second tri-state level conversion circuit (106) includes a second tri-state level converter (1061); the second tri-state level converter (1061) is configured to connect the first input terminal of the second switching circuit (102) to the second reset presence terminal of the PCIe device (300); And The enable terminal of the second three-state level converter (1061) is configured to receive an ED enable signal, and the ED enable signal is valid in the ED interface mode.

9. The mode switching circuit according to claim 8, wherein The second three-state level conversion circuit (106) further includes: a second level circuit (1062); the second level circuit (1062) is connected to the power supply terminal of the second three-state level converter (1061); The second level circuit (1062) is configured to: stop power supply in the RC interface mode; or The second level circuit (1062) is configured to: provide a reference level to the second three-state level converter (1061) in the ED interface mode.

10. The mode switching circuit according to claim 9, characterized in that, The second level circuit (1062) includes: a second switching transistor (M2); The input terminal of the second switching transistor (M2) is connected to a power supply, the output terminal is connected to the power supply terminal of the second three-state level converter (1061); and The control terminal of the second switching transistor (M2) receives the ED enable signal; in response to determining that the ED enable signal is valid, the second switching transistor (M2) conducts.

11. The mode switching circuit according to claim 7, wherein In the second switching circuit (102), the second input terminal and the output terminal of the second switching circuit (102) are directly connected through a second wire (1021); And A second via is provided on the pin of one side port of the second three-state level conversion circuit (106), and the second wire (1021) passes through the second via and is electrically connected to the second via.

12. The mode switching circuit according to claim 1, wherein Further included: A second bidirectional level converter (107) and a third three-state level conversion circuit (108); The first side port of the third three-state level conversion circuit (108) is connected to the third reverse differential pin (205) of the connector (200), and the second side port of the third three-state level conversion circuit (108) is configured to be connected to the third reset present terminal of the PCIe device (300); The first group of level conversion channels of the second bidirectional level converter (107) is configured to perform data transmission between the fourth reverse differential pin (207) of the connector (200) and the third data terminal of the PCIe device (300), and the second group of level conversion channels is configured to perform data transmission between the fourth front differential pin (208) of the connector (200) and the fourth data terminal of the PCIe device (300); In the RC interface mode, the third three-state level conversion circuit (108) is configured to transmit an RC reset signal and / or an RC present signal; The first group of level conversion channels of the second bidirectional level converter (107) is configured to transmit I2C bus signals, and the second group of level conversion channels is configured to transmit wake-up signals and / or identification signals; or In the ED interface mode, the port of the third three-state level conversion circuit (108) is in a high impedance state; the first group of level conversion channels of the second bidirectional level converter (107) is configured to transmit wake-up signals and / or identification signals, and the second group of level conversion channels is configured to transmit I2C bus signals.

13. The mode switching circuit according to claim 1, wherein The clock switching circuit (103) includes: a clock generator (1031) and a clock buffer (1032); A first output terminal of the clock generator (1031) is connected to a first input terminal of the clock buffer (1032), and is configured to output a local differential clock signal in the RC interface mode; A second output terminal of the clock generator (1031) is connected to a second input terminal of the second switching circuit (102), and is configured to output the RC differential clock signal in the RC interface mode; A second input terminal of the clock buffer (1032) is connected to a second output terminal of the first switching circuit (101), and is configured to receive the ED differential clock signal in the ED interface mode; and The clock buffer (1032) is configured to generate a reference clock signal sent to the PCIe device (300) according to the local differential clock signal or the ED differential clock signal.

14. The mode switching circuit according to claim 13, wherein An enable terminal of the clock generator (1031) is configured to access an RC enable signal; and In response to determining that the RC enable signal is valid in the RC interface mode and the RC enable signal is valid, the clock generator (1031) outputs the local differential clock signal and the RC differential clock signal.

15. The mode switching circuit according to claim 13, wherein A selection terminal of the clock buffer (1032) is configured to access a clock selection signal; In response to determining that the clock selection signal indicates the RC interface mode, a first input terminal of the clock buffer (1032) is valid; Or In response to determining that the clock selection signal indicates the ED interface mode, a second input terminal of the clock buffer (1032) is valid.

16. The mode switching circuit according to claim 1, wherein It further includes: A mode selection circuit (109); and The mode selection circuit (109) is configured to provide a mode selection signal indicating the currently selected RC interface mode or the currently selected ED interface mode to the PCIe device (300).

17. The mode switching circuit according to claim 16, wherein The mode selection circuit (109) includes: a selection switch (SW1), a first resistor (R1), and a second resistor (R2); A first end of the first resistor (R1) is connected to a power supply, and a second end of the first resistor (R1) is grounded sequentially through the selection switch (SW1) and the second resistor (R2); alternatively, a first end of the selection switch (SW1) is connected to the power supply, and a second end of the selection switch (SW1) is grounded sequentially through the first resistor (R1) and the second resistor (R2); and An end of the second resistor (R2) close to the first resistor (R1) is configured to be connected to the PCIe device (300) to provide the mode selection signal.

18. A mode switching method, characterized in that, Implemented based on the mode switching circuit according to any one of claims 1 to 17, the method includes: In the RC interface mode, perform the following steps: Control the first switching circuit (101) to transmit an RC reset signal and / or an RC presence signal between a first reverse differential pin (201) of the connector (200) and a first reset presence end of the PCIe device (300); The control clock switching circuit (103) generates a reference clock signal sent to the PCIe device (300) and an RC differential clock signal sent to the second switching circuit (102); controls the second switching circuit (102) to send the RC differential clock signal to the first positive differential pin (202) of the connector (200); and, controls the first group of level conversion channels of the first bidirectional level converter (104) to transmit I2C bus signals, and the second group of level conversion channels to transmit wake-up signals and / or identification signals; or In the ED interface mode, the following steps are performed: controls the first switching circuit (101) to send the ED differential clock signal transmitted by the first negative differential pin (201) of the connector (200) to the clock switching circuit (103); controls the clock switching circuit (103) to generate a reference clock signal sent to the PCIe device (300) according to the ED differential clock signal; controls the second switching circuit (102) to transmit an ED reset signal and / or an ED presence signal between the first positive differential pin (202) of the connector (200) and the second reset presence terminal of the PCIe device (300); and, controls the first group of level conversion channels of the first bidirectional level converter (104) to transmit wake-up signals and / or identification signals, and the second group of level conversion channels to transmit I2C bus signals.

19. An external expansion connector, characterized in that, Comprises: a connector (200) and a mode switching circuit according to any one of claims 1 to 17.

20. A PCIe board, characterized in that, Comprises: a PCIe device (300) and at least one external expansion connector according to claim 19; the PCIe device (300) is provided with RC firmware and ED firmware; when the PCIe device (300) is in the RC interface mode, the RC firmware is loaded; or when the PCIe device (300) is in the ED interface mode, the ED firmware is loaded.

21. The PCIe board according to claim 20, wherein, The external expansion connector includes a mode selection circuit (109), and the PCIe device (300) is configured to: in response to an RC mode instruction triggered based on the mode selection circuit (109), load the RC firmware; or in response to an ED mode instruction triggered based on the mode selection circuit (109), load the ED firmware.

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