Tuner circuit and radio-frequency chip

Abstract

The present invention relates to the technical field of wireless communications. Disclosed in the present invention are a tuner circuit and a radio-frequency chip. The tuner circuit comprises a tuner unit and a tuning device unit, wherein the tuner unit comprises a first resistor, a first transistor, a second resistor and a second transistor; a first end of the first resistor and a first end of the second resistor are connected to each other and jointly serve as an input end of the tuner unit, a second end of the first resistor is connected to a gate electrode of the first transistor, a drain electrode of the first transistor is connected to an input end of the tuning device unit, a source electrode of the first transistor is connected to a drain electrode of the second transistor, a second end of the second resistor is connected to a gate electrode of the second transistor, and a source electrode of the second transistor is grounded; the resistance value of the first resistor is greater than the resistance value of the second resistor; the gate width of the first transistor is greater than the gate width of the second transistor; and the gate length of the first transistor is greater than the gate length of the second transistor. The tuner circuit of the present invention can achieve a higher withstand voltage value and a lower Fom value can be achieved with a smaller area.

Description

Tuning switch circuit and RF chip Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a tuning switch circuit and a radio frequency chip. Background Art

[0002] With the rapid development of integrated circuits and wireless communication technologies, mobile phones have become a necessity in people's lives. With the advent of the 5G era, users' demands for faster and more stable data transmission and reception have continuously increased, leading to an increase in the number of frequency bands, functions, and modes required for smartphone operation.

[0003] To meet these demands, wireless communications generally use carrier aggregation (CA), multiple-input multiple-output (MIMO), and new wideband 5G frequency bands to provide higher data rates. This requires more antennas in mobile phones. At the same time, more antennas reduce the space available for a single antenna, ultimately leading to reduced antenna efficiency. Currently, to overcome the issues caused by reduced antenna area and efficiency, the mainstream approach is to tune the antenna using antenna tuning devices. Antenna tuning switches are an essential component of antenna tuning devices. Because tuning switches often operate in non-50Ω systems and have voltage standing wave ratios (VSWR) as high as 5:1, they have high voltage withstand requirements, often reaching 48dBm (80V). However, the source-drain breakdown voltage of field-effect transistors (FETs) in silicon-on-insulator (SOI) processes is typically around 3V, necessitating the connection of multiple FETs in series to meet these requirements.

[0004] In traditional switch designs, a series stack of field-effect transistors (FETs) is typically used to evenly distribute the voltage swing at the antenna end, thereby improving the switch's power-carrying capacity. In this structure, n FETs of the same size and type, from transistors M1 to Mn, are connected in series. However, without adding an additional voltage divider circuit, the voltage difference between the transistor stacks is not completely equal, resulting in a voltage withstand value that is lower than the theoretical design value during actual use. During the design process, more series stacks are required to meet actual usage requirements. Furthermore, the additional series stacks increase the area of ​​the entire tuning chip, increase the on-resistance (Ron), and worsen the insertion loss (IL).

[0005] Summary of the Invention

[0006] The purpose of an embodiment of the present invention is to provide a tuning switch circuit, which can simultaneously increase the gate width of the field effect transistor close to the antenna end while increasing the gate length for the sake of on-resistance consideration; so as to solve the problem that the existing tuning chip area is too large, the on-resistance is increased, and the insertion loss is deteriorated.

[0007] To solve the above technical problems, an embodiment of the present invention provides a tuning switch circuit, comprising a tuning switch unit and a tuning device unit, wherein the input end of the tuning switch unit is used to connect to a first bias voltage, the output end of the tuning switch unit is connected to the input end of the tuning device unit, and the output end of the tuning device unit is used to connect to an antenna;

[0008] The tuning switch unit includes a first resistor, a first transistor, a second resistor, and a second transistor; a first end of the first resistor and a first end of the second resistor are connected and serve together as an input end of the tuning switch unit, a second end of the first resistor is connected to the gate of the first transistor, a drain of the first transistor is connected to the input end of the tuning device unit, a source of the first transistor is connected to the drain of the second transistor, a second end of the second resistor is connected to the gate of the second transistor, and a source of the second transistor is grounded; substrates of the first transistor and the second transistor are respectively used to connect to a second bias voltage, and the second bias voltage is used to control the threshold voltages of the first transistor and the second transistor respectively;

[0009] The resistance of the first resistor is greater than the resistance of the second resistor; the gate width of the first transistor is greater than the gate width of the second transistor; and the gate length of the first transistor is greater than the gate length of the second transistor.

[0010] Preferably, the tuning switch unit includes n resistors and n transistors, the first end of the nth resistor is connected to the first end of the first resistor, the second end of the nth resistor is connected to the gate of the nth transistor, the drain of the nth transistor is connected to the source of the (n-1)th transistor, and the source of the nth transistor is grounded; the substrate of the nth transistor is used to connect to the second bias voltage; wherein n≥3;

[0011] The resistance of the nth resistor is smaller than the resistance of the n-1th resistor, the gate width of the nth transistor is smaller than the gate width of the n-1th transistor, and the gate length of the nth transistor is smaller than the gate length of the n-1th transistor.

[0012] Preferably, the first transistor to the nth transistor are connected to form a transistor by non-uniformly stacking transistors, the transistor closest to the input end of the antenna has the largest gate length, and the on-resistance value of the transistor is expressed by the following formula:

[0013] Wherein, Ron is the on-resistance value after n resistors are connected, gm is the transconductance of the transistor, u nis the carrier mobility of the transistor, Cox is the gate oxide capacitance per unit area of ​​the transistor, Vgs is the gate-source voltage of the transistor, Vth is the threshold voltage of the transistor, W is the gate width of the transistor, and L is the gate length of the transistor.

[0014] Preferably, the tuning device unit is a capacitor, a first end of the capacitor serves as an input end of the tuning device unit, and a second end of the capacitor serves as an output end of the tuning device unit.

[0015] Preferably, the tuning device unit is an inductor, a first end of the inductor serves as an input end of the tuning device unit, and a second end of the inductor serves as an output end of the tuning device unit.

[0016] In a second aspect, an embodiment of the present invention provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned tuning switch circuit.

[0017] Compared with the prior art, the tuning switch circuit of the present invention connects the first end of a first resistor and the first end of a second resistor and both serve as the input end of the tuning switch unit, the second end of the first resistor is connected to the gate of a first transistor, the drain of the first transistor is connected to the input end of the tuning device unit, the source of the first transistor is connected to the drain of the second transistor, the second end of the second resistor is connected to the gate of the second transistor, and the source of the second transistor is grounded; the substrate of the first transistor and the substrate of the second transistor are respectively connected to a second bias voltage, and the second bias voltage is used to control the threshold voltage of the first transistor and the second transistor respectively; the resistance of the first resistor is greater than the resistance of the second resistor; the gate width of the first transistor is greater than the gate width of the second transistor; and the gate length of the first transistor is greater than the gate length of the second transistor. In this way, while increasing the gate length, the gate width of the field effect transistor near the antenna end can be simultaneously increased for on-resistance considerations, and a smaller field effect transistor is used at the port near the ground. While reducing the gate width, the gate width of the field effect transistor near the ground end can be simultaneously reduced for area considerations, thereby achieving an antenna tuning switch with a higher withstand voltage and lower on-resistance value in a smaller area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0019] FIG1 is a schematic diagram of the overall structure of a tuning switch circuit provided in an embodiment of the present invention.

[0020] In the figure, 100, tuning switch circuit, 1, tuning switch unit, 2, tuning device unit, 3, antenna. DETAILED DESCRIPTION

[0021] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] As shown in FIG1 , an embodiment of the present invention provides a tuning switch circuit 100, which includes a tuning switch unit 1 and a tuning device unit 2. The input end of the tuning switch unit 1 is used to connect to a first bias voltage Vgate, the output end of the tuning switch unit 1 is connected to the input end of the tuning device unit 2, and the output end of the tuning device unit 2 is used to connect to an antenna 3.

[0023] The tuning switch unit 1 includes a first resistor R1, a first transistor M1, a second resistor R2, and a second transistor M2; the first end of the first resistor R1 and the first end of the second resistor R2 are connected and serve together as the input end of the tuning switch unit 1, the second end of the first resistor R1 is connected to the gate of the first transistor M1, the drain of the first transistor M1 is connected to the input end of the tuning device unit 2, the source of the first transistor M1 is connected to the drain of the second transistor M2, the second end of the second resistor R2 is connected to the gate of the second transistor M2, and the source of the second transistor M2 is grounded; the substrate Stack 1 of the first transistor M1 and the substrate Stack 2 of the second transistor M2 are respectively used to connect to a second bias voltage Vbody, and the second bias voltage Vbody is used to control the threshold voltages of the first transistor M1 and the second transistor M2, respectively.

[0024] The resistance of the first resistor R1 is greater than the resistance of the second resistor R2; the gate width of the first transistor M1 is greater than the gate width of the second transistor M2; and the gate length of the first transistor M1 is greater than the gate length of the second transistor M2. By increasing the gate length while simultaneously increasing the gate width of the field-effect transistor near the antenna 3 for on-resistance considerations, a smaller field-effect transistor is used at the port near the ground. While reducing the gate width, the gate width of the field-effect transistor near the ground end can be simultaneously reduced for area considerations. This allows for a higher withstand voltage and lower on-resistance antenna tuning switch to be implemented with a smaller area.

[0025] Among them, the gate width of the transistor refers to the width of the gate in the transistor, and the gate length of the transistor refers to the length of the gate electrode of the transistor. The gate width and gate length of the transistor provide different gates of the transistor and provide options for different processes.

[0026] In this embodiment, the tuning switch unit 1 includes n resistors and n transistors. The first end of the nth resistor Rn is connected to the first end of the first resistor R1, the second end of the nth resistor Rn is connected to the gate of the nth transistor Mn, the drain of the nth transistor Mn is connected to the source of the n-1th transistor Mn-1, and the source of the nth transistor Mn is grounded. The substrate Stack n of the nth transistor Mn is used to connect to the second bias voltage Vbody. Wherein, n ≥ 3.

[0027] The resistance of the nth resistor Rn is smaller than the resistance of the n-1th resistor Rn-1, the gate width of the nth transistor Mn is smaller than the gate width of the n-1th transistor Mn-1, and the gate length of the nth transistor Mn is smaller than the gate length of the n-1th transistor Mn-1.

[0028] Specifically, the drain of the first transistor M1 is connected to the tuning device unit 2, the drain of the second transistor M2 is connected to the source of the first transistor M1, and so on, the drain of the nth transistor Mn is connected to the source of the n-1th transistor Mn-1. The first transistor M1 is close to the input end of the antenna 3. When the antenna 3 resonates, a standing wave voltage is formed. During resonance, the maximum value of the standing wave voltage is much greater than the amplitude of the input signal. At this time, since the drain of the first transistor M1 is connected to the tuning device unit 2, the first transistor M1 is very likely to break down. The gate width of the field-effect transistor near the ground end can be simultaneously reduced; thus, an antenna tuning switch with a higher withstand voltage and lower on-resistance can be achieved with a smaller area.

[0029] In this embodiment, the first transistor M1 to the nth transistor Mn are transistors formed by connecting in a non-uniform stacking manner. The transistor closest to the input end of the antenna 3 has the largest gate length. The on-resistance value of the transistor is expressed as follows:

[0030] Wherein, Ron is the on-resistance value after the resistor Rn is connected, gm is the transconductance of the transistor, u n is the carrier mobility of the transistor, Cox is the gate oxide capacitance per unit area of ​​the transistor, Vgs is the gate-source voltage of the transistor, Vth is the threshold voltage of the transistor, W is the gate width of the transistor, and L is the gate length of the transistor.

[0031] Preferably, L1>L2>···>Ln-1>Ln; W1>W2>···>Wn-1>Wn; R1>R2···>Rn-1>Rn, which facilitates the design of an antenna tuning switch with a larger withstand voltage and a lower Fom value (radio frequency index) in a smaller area.

[0032] In this embodiment, the tuning device unit 2 is a capacitor, a first end of the capacitor serves as an input end of the tuning device unit 2, and a second end of the capacitor serves as an output end of the tuning device unit 2. The drain of the first transistor M1 is connected to the first end of the capacitor, and the second end of the capacitor is connected to the input end of the antenna 3.

[0033] In this embodiment, the tuning device unit 2 is an inductor, a first end of the inductor serves as an input end of the tuning device unit 2, and a second end of the inductor serves as an output end of the tuning device unit 2. The drain of the first transistor M1 is connected to the first end of the inductor, and the second end of the inductor is connected to the input end of the antenna 3.

[0034] The tuning device unit 2 is a capacitor or an inductor. Preferably, the tuning device unit 2 is a capacitor, which has a good charge storage effect and a stable circuit voltage.

[0035] Example 2

[0036] An embodiment of the present invention provides a radio frequency chip, which includes the tuning switch circuit 100 described above.

[0037] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0038] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A tuning switch circuit, characterized in that, The tuning switch circuit includes a tuning switch unit and a tuning device unit. The input end of the tuning switch unit is used to connect to a first bias voltage. The output end of the tuning switch unit is connected to the input end of the tuning device unit. The output end of the tuning device unit is used to connect to an antenna. The tuning switch unit includes a first resistor, a first transistor, a second resistor, and a second transistor. The first ends of the first resistor and the second resistor are connected together and serve as the input end of the tuning switch unit. The second end of the first resistor is connected to the gate of the first transistor. The drain of the first transistor is connected to the input end of the tuning device unit. The source of the first transistor is connected to the drain of the second transistor. The second end of the second resistor is connected to the gate of the second transistor. The source of the second transistor is grounded. The substrates of the first transistor and the second transistor are respectively used to connect to a second bias voltage, and the second bias voltage is used to control the threshold voltages of the first transistor and the second transistor respectively. Wherein, the resistance value of the first resistor is greater than that of the second resistor; the gate width of the first transistor is greater than that of the second transistor; the gate length of the first transistor is greater than that of the second transistor.

2. The tuning switch circuit according to claim 1, characterized in that, The tuning switch unit includes n resistors and n transistors. The first end of the nth resistor is connected to the first end of the first resistor. The second end of the nth resistor is connected to the gate of the nth transistor. The drain of the nth transistor is connected to the source of the (n - 1)th transistor. The source of the nth transistor is grounded. The substrate of the nth transistor is used to connect to the second bias voltage. Wherein, n ≥ 3. The resistance value of the nth resistor is less than that of the (n - 1)th resistor. The gate width of the nth transistor is less than that of the (n - 1)th transistor. The gate length of the nth transistor is less than that of the (n - 1)th transistor.

3. The tuning switch circuit according to claim 2, wherein The first transistor to the nth transistor are connected to form a transistor in a non-uniform stacked transistor manner. The transistor closest to the input end of the antenna has the largest gate length. The on-resistance value of the transistor is as follows: Among them, Ron is the on-resistance value after connecting n of the resistors, gm is the transconductance of the transistor, u n is the carrier mobility of the transistor, Cox is the gate oxide capacitance per unit area of the transistor, Vgs is the gate-source voltage of the transistor, Vth is the threshold voltage of the transistor, W is the gate width of the transistor, and L is the gate length of the transistor.

4. The tuning switch circuit according to claim 1, characterized in that The tuning device unit is a capacitor. The first end of the capacitor serves as the input end of the tuning device unit. The second end of the capacitor serves as the output end of the tuning device unit.

5. The tuning switch circuit according to claim 1, wherein The tuning device unit is an inductor. The first end of the inductor serves as the input end of the tuning device unit. The second end of the inductor serves as the output end of the tuning device unit.

6. A radio frequency chip, characterized in that, The radio frequency chip includes the tuning switch circuit according to any one of claims 1 - 5.

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