Ferroelectric capacitor and preparation method therefor, storage array, memory, and electronic device

Abstract

Provided are a ferroelectric capacitor and a preparation method therefor, a storage array, a memory, and an electronic device, which relate to the technical field of semiconductors, and are used to reduce the M phase in a ferroelectric layer in a ferroelectric capacitor and improve the reliability of the ferroelectric capacitor. The ferroelectric capacitor comprises a first electrode (10), a second electrode (20), and a ferroelectric layer (30), the ferroelectric layer (30) being located between the first electrode (10) and the second electrode (20). The first electrode (10) is polycrystalline and comprises first columnar crystal grains, and a first included angle is present between the direction of extension of the first columnar crystal grains and a first reference plane, the first included angle being greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of the first columnar crystal grains to the number of all crystal grains in the first electrode (10) is greater than or equal to fifty percent. The first reference plane is parallel to the portion of the surface of the ferroelectric layer (30) opposite to the first columnar crystal grains. The ferroelectric capacitor is applied to the electronic device to improve performance of the electronic device.

Description

Ferroelectric capacitor and preparation method thereof, storage array, memory and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 29, 2023, with application number 202311872523.0 and application name “Ferroelectric capacitor and its preparation method, storage array, memory and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a ferroelectric capacitor and a preparation method thereof, a storage array, a memory and an electronic device. Background Art

[0003] Currently, Ferroelectric Random Access Memory (FeRAM) has been widely used due to its characteristics of non-volatility of stored data and fast access rate.

[0004] Typically, a ferroelectric memory device includes multiple ferroelectric capacitors, each of which includes two electrodes arranged opposite to each other, and a ferroelectric layer located between the two electrodes. Under the support of the two electrodes, the ferroelectric layer undergoes a high-temperature crystallization process to form a polycrystalline thin film with a mixture of orthorhombic (O phase), tetragonal (T phase), and monoclinic (M phase). The O phase and T phase give the ferroelectric layer ferroelectric properties, while the M phase gives the ferroelectric layer dielectric properties. The oxygen ions in the O phase can deviate from the equilibrium point under voltage drive, producing two polarization states in opposite directions, which are used to store 0 / 1 information. The ferroelectric layer has a large amount of M phase, and the ferroelectric layer is prone to fatigue and breakdown, which seriously affects the reliability of the ferroelectric memory device.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a ferroelectric capacitor and a preparation method thereof, a memory array, a memory and an electronic device, which are used to reduce the M phase in the ferroelectric layer of the ferroelectric capacitor and improve the reliability of the ferroelectric capacitor.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a ferroelectric capacitor is provided, comprising a first electrode, a second electrode, and a ferroelectric layer. The ferroelectric layer is located between the first electrode and the second electrode. The first electrode is polycrystalline, comprises first columnar grains, and a first angle exists between the extension direction of the first columnar grains and a first reference plane. The first angle is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to 50 percent. The first reference plane is parallel to a portion of the surface of the ferroelectric layer that is opposite the first columnar grains.

[0009] Such an arrangement can make the first electrode have a preferred orientation that hardly presents the (200) crystal orientation, so that the M phase generated in the ferroelectric layer can be less and the O phase generated can be more. The less M phase and more O phase in the ferroelectric layer can, on the one hand, reduce the coercive electric field of the ferroelectric capacitor and lower the operating voltage of the ferroelectric capacitor, so that the storage unit using the ferroelectric capacitor provided by the embodiment of the present application can have a smaller operating voltage and lower power consumption when performing read and write operations. On the other hand, it can delay the fatigue period of the ferroelectric capacitor and reduce the leakage current of the ferroelectric capacitor, thereby increasing the number of storage times of the ferroelectric capacitor, ensuring the storage window of the ferroelectric capacitor after multiple storages, improving the reliability of the ferroelectric capacitor, and further ensuring the accuracy of the read and write operations of the storage unit using the ferroelectric capacitor provided by the embodiment of the present application, and improving the performance of the memory.

[0010] At the same time, the ferroelectric layer has fewer M phases and more O phases, which can also make the film layer of the ferroelectric layer have better bearing capacity and the structure of the ferroelectric capacitor more stable, thereby ensuring the storage capacity of the ferroelectric capacitor, improving the reliability of the ferroelectric capacitor, reducing the storage window loss rate of the storage array (memory) using the ferroelectric capacitor, ensuring the accuracy of the storage array read and write operations, and reducing the misread rate.

[0011] In some embodiments, the ferroelectric capacitor further includes a third electrode, which is located on a side of the first electrode away from the ferroelectric layer; the third electrode is amorphous or a polycrystalline material with randomly distributed crystal orientations.

[0012] In this way, the first electrode and the third electrode are located on the same side of the ferroelectric layer, and the first electrode and the third electrode can jointly provide clamping stress for the ferroelectric layer, and the thickness of the first electrode can be relatively small. In the process of preparing a ferroelectric capacitor, in order to make the first electrode polycrystalline, the first electrode includes first columnar grains, and there is a first angle between the extension direction of the first columnar grains and the first reference plane, and the ratio of the number of first columnar grains to the number of all grains in the first electrode is greater than or equal to 50%, when preparing the first electrode, it is necessary to adjust the process conditions, such as the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the first electrode can shorten the preparation time of the first electrode, thereby reducing the difficulty and process complexity of the preparation of the ferroelectric capacitor and improving the preparation efficiency of the ferroelectric capacitor.

[0013] In some embodiments, the ferroelectric capacitor further includes a first buffer layer, the first buffer layer being located between the first electrode and the ferroelectric layer and in contact with the ferroelectric layer.

[0014] By configuring the first buffer layer between the first electrode and the ferroelectric layer, the stress between the first electrode and the ferroelectric layer can be adjusted, thereby improving the structural stability of the ferroelectric capacitor. Furthermore, the first buffer layer can inhibit the diffusion of metal particles in the first electrode into the ferroelectric layer, inhibit the diffusion of oxygen atoms in the ferroelectric layer into the first electrode, reduce oxygen vacancies formed in the ferroelectric layer due to the migration of oxygen ions, weaken the oxidation reaction between the electrode and the oxygen ions, and prevent the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor, preventing the ferroelectric capacitor from being broken down, and increasing the service life of the ferroelectric capacitor. Furthermore, the reduction of oxygen vacancies in the ferroelectric layer can also improve polarization fatigue and imprinting effects caused by oxygen vacancies, thereby improving the accuracy of reading and writing data in a storage unit using the ferroelectric capacitor.

[0015] In some embodiments, the second electrode is a polycrystalline material, includes second columnar grains, and a second angle exists between the extension direction of the second columnar grains and a second reference plane, wherein the second angle is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of the second columnar grains to the number of all grains in the second electrode is greater than or equal to 50 percent, and the second reference plane is parallel to the portion of the surface of the ferroelectric layer opposite the second columnar grains. In this way, the second electrode also has a preferred orientation that hardly exhibits a (200) crystal orientation, thereby reducing the amount of M phase and increasing the amount of O phase generated in the ferroelectric layer.

[0016] In some embodiments, the ferroelectric capacitor further includes a fourth electrode, which is located on a side of the second electrode away from the ferroelectric layer; the fourth electrode is amorphous or a polycrystalline material with randomly distributed crystal orientations.

[0017] In this way, the second electrode and the fourth electrode are located on the same side of the ferroelectric layer, and the second electrode and the fourth electrode can jointly provide clamping stress for the ferroelectric layer, and the thickness of the second electrode can be relatively small. In the process of preparing the ferroelectric capacitor, in order to make the second electrode include second columnar grains, and the second angle between the extension direction of the second columnar grains and the second reference plane, the ratio of the number of second columnar grains to the number of all grains in the second electrode is greater than or equal to 50%, when preparing the second electrode, it is necessary to adjust the process conditions, such as the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the second electrode can shorten the preparation time of the second electrode, thereby reducing the difficulty and process complexity of the preparation of the ferroelectric capacitor and improving the preparation efficiency of the ferroelectric capacitor.

[0018] In some embodiments, the ferroelectric capacitor further includes a second buffer layer, which is located between the second electrode and the ferroelectric layer and contacts the ferroelectric layer. Similar to the working principle of the first buffer layer in the above-described embodiment, the provision of the second buffer layer can extend the service life of the ferroelectric capacitor, improve the accuracy of reading and writing data in a memory cell using the ferroelectric capacitor, and enhance the structural stability of the ferroelectric capacitor.

[0019] In some embodiments, the material of the ferroelectric layer includes a hafnium oxide-based material and a doping element; the doping element includes at least one of zirconium, lanthanum, aluminum, titanium, and niobium.

[0020] In some embodiments, the material of the first electrode includes at least one of metal, conductive oxide, and conductive nitride; and / or the material of the second electrode includes at least one of metal, conductive oxide, and conductive nitride.

[0021] In some embodiments, the first electrode and the second electrode are both planar electrodes, and the first electrode and the second electrode are stacked. In this way, the structure of the ferroelectric capacitor can be relatively simple, thereby simplifying the preparation process of the ferroelectric capacitor and reducing the preparation cost.

[0022] In some embodiments, the surface of the first electrode close to the ferroelectric layer includes a connecting surface, a first side surface and a second side surface, the first side surface and the second side surface are located on opposite sides of the connecting surface and are both connected to the connecting surface, and the extension direction of the first side surface and the second side surface is different from the extension direction of the connecting surface; the ferroelectric layer is arranged opposite to the connecting surface, the first side surface and the second side surface; the second electrode is located on the side of the ferroelectric layer away from the first electrode, and is arranged opposite to the connecting surface, the first side surface and the second side surface.

[0023] In this way, the area facing each other between the first electrode and the second electrode of the ferroelectric capacitor can be larger, thereby making the capacitance value of the ferroelectric capacitor larger. When the ferroelectric capacitor provided by the embodiment of the present application is applied to a memory, even if the occupied area of ​​the ferroelectric capacitor is small, the capacitance value of the ferroelectric capacitor can meet the requirements of the memory, thereby helping to reduce the size of the memory and achieve miniaturization and high integration.

[0024] In a second aspect, a method for preparing a ferroelectric capacitor is provided, the method comprising forming a first electrode; forming a ferroelectric layer; and forming a second electrode. The ferroelectric layer is located between the first electrode and the second electrode. The first electrode includes first columnar grains, and a first angle exists between an extension direction of the first columnar grains and a first reference plane, the first angle being greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent. The first reference plane is parallel to a portion of the surface of the ferroelectric layer that is opposite the first columnar grains.

[0025] According to a third aspect, a memory array is provided. The memory array includes a plurality of memory cells. The plurality of memory cells include transistors and a ferroelectric capacitor as described in any one of the above embodiments. The transistors are connected to the ferroelectric capacitors.

[0026] In a fourth aspect, a memory is provided, comprising a controller and a memory array as described in any one of the above embodiments, wherein the controller is electrically connected to the memory array.

[0027] In a fifth aspect, an electronic device is provided, which includes a circuit board and a memory as described in any of the above embodiments, wherein the memory is located on the circuit board and electrically connected to the circuit board.

[0028] Among them, the technical effects brought about by any design method in the second to fifth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0030] FIG1 is a schematic structural diagram of an electronic device according to some embodiments;

[0031] FIG2 is a schematic diagram of the structure of a memory according to some embodiments;

[0032] FIG3 is a schematic diagram of the structure of another memory according to some embodiments;

[0033] FIG4 is a schematic diagram of the structure of a storage array according to some embodiments;

[0034] FIG5 is a schematic diagram of the structure of another storage array according to some embodiments;

[0035] FIG6 is a schematic structural diagram of a ferroelectric capacitor according to some embodiments;

[0036] FIG7 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0037] FIG8 is a diagram showing the XRD test results of the first electrode and the reference electrode;

[0038] FIG9 is a diagram showing TEM test results of the first electrode and the control electrode;

[0039] FIG10 is a schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0040] FIG11 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0041] FIG12 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0042] FIG13 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0043] FIG14 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0044] FIG15 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0045] FIG16 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0046] FIG17 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0047] FIG18 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0048] FIG19 is a schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0049] FIG20A is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0050] FIG20B is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0051] FIG21 is a schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0052] FIG. 22 is a flow chart of a method for fabricating a ferroelectric capacitor according to some embodiments. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0054] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0057] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] In the context of this application, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something with no intervening features or layers (i.e., directly on something).

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, game consoles, cameras, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), set-top boxes, etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), car automatic assisted driving systems, navigation and infotainment systems, powertrains, and battery management systems, etc. Financial terminal products include automated teller machines (ATMs), POS (Point of Sales) self-service terminals, etc. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device.

[0062] Figure 1 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. As shown in Figure 1, the electronic device 100 may include a bus 110 and a system on chip (SOC) 120 connected to the bus 110. The SOC 120 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 120 may include an application processor (AP) 121 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first random access memory (RAM) 123 for caching high-speed data. The first RAM 123 may be a static random access memory (SRAM), etc. The above-mentioned AP 121, GPU 122 and first RAM 123 may be integrated into a die, or may be separately provided in multiple dies.

[0063] As shown in FIG1 , the electronic device 100 may further include a second RAM 130 connected to the SOC 120 via the bus 110. The second RAM 130 may be a dynamic random access memory (DRAM). The second RAM 130 may be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is generally greater than that of the first RAM 123, but the read speed is generally slower than that of the first RAM 123.

[0064] In addition, the electronic device 100 may further include a communication chip 140 and a power management chip 150 connected to the SOC 120 via the bus 110. The communication chip 140 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 150 may be used to power other chips. In one embodiment, the SOC 120 and the second RAM 130 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve faster inter-chip data transmission rates.

[0065] FIG2 is a circuit block diagram of a memory 200 that can be used in an electronic device according to an embodiment of the present application. In one embodiment, the memory 200 can be the first RAM 123 shown in FIG1 , or the second RAM 130. The application scenario of the memory 200 of the present application is not limited. In one possible embodiment, the memory 200 can also be a RAM provided outside the SOC 120. The location of the memory 200 in the electronic device and its positional relationship with the SOC 120 are not limited in the present application.

[0066] As shown in FIG2 , the memory 200 includes a memory array 300 . In addition, the memory 200 may further include a controller 210 for accessing the memory array 300 , wherein the controller 210 is used to control read and write operations of the memory array 300 .

[0067] It can be understood that the memory 200 may include at least one memory array 300 , that is, the memory 200 may include one or more memory arrays.

[0068] The memory array 300 and the controller 210 have various possible packaging structures. For example, the memory array 300 and the controller 210 may be two independent chips, each integrated on a substrate. For example, the memory array 300 and the controller 210 may be electrically connected via metal traces arranged on the substrate. In this structure, since the memory array 300 and the controller 210 are two independent chips, the memory array 300 may be referred to as a stand-alone memory.

[0069] Alternatively, the memory array 300 and the controller 210 are stacked. For example, the memory array 300 and the controller 210 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0070] Alternatively, the memory array 300 and the controller 210 are integrated into the same chip, and the chip is integrated on a substrate. Therefore, the memory array 300 can be called an embedded memory.

[0071] In some examples, as shown in FIG3 , the memory array 300 may include a plurality of memory cells 310 , each of which may be used to store 1 bit (bit) or multiple bits of data. The memory array 300 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 310 is electrically connected to a corresponding word line and bit line. Different memory cells 310 may be electrically connected via word lines and bit lines. One or more of the above-mentioned word lines and bit lines are used to select a memory cell 310 to be read or written in the memory array by receiving a control level output by a control circuit, thereby implementing data read and write operations.

[0072] The controller 210 in the memory may include one or more circuit structures of the decoder 211 , the driver 212 , the timing controller 213 , the buffer 214 , or the input / output driver 215 shown in FIG. 3 .

[0073] In the structure of the memory 200 shown in FIG3 , the decoder 211 is used to decode the received address to determine the memory cell 310 to be accessed. The driver 212 is used to control the level of the signal line according to the decoding result generated by the decoder 211, thereby achieving access to the specified memory cell 310. The buffer 214 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO) method. The timing controller 213 is used to control the timing of the buffer 214 and control the driver 212 to drive the signal lines in the memory array 300. The input and output driver 215 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0074] The memory array 300 , decoder 211 , driver 212 , timing controller 213 , buffer 214 and input / output driver 215 may be integrated into one chip or may be integrated into multiple chips.

[0075] The memory involved in the present application can be a ferroelectric random access memory (FeRAM), a ferroelectric field-effect transistor (FeFET) memory, a ferroelectric tunnel junction (FTJ) memory, or a resistive random access memory (RRAM).

[0076] Figures 4 and 5 illustrate circuit structures of two possible memory arrays 300 provided in embodiments of the present application. As shown in Figures 4 and 5, the memory array 300 may include multiple memory cells 310, each of which includes a transistor T and a ferroelectric capacitor C. The memory array may also include word lines WL, bit lines BL, and source lines SL. Figure 4 shows four memory cells 310 in the memory array 300. In each memory cell 310, the first end of the ferroelectric capacitor C is connected to the first electrode of the transistor T, the second end of the ferroelectric capacitor C is connected to the source line SL, the second electrode of the transistor T is connected to the bit line BL, and the control end (e.g., gate) of the transistor T is connected to the word line WL.

[0077] Figure 5 also shows four memory cells 310 in the memory array 300. Different from the memory cell 310 shown in Figure 4, in the memory cell 310, the first end of the ferroelectric capacitor C is connected to the control end (e.g., the gate) of the transistor T, the second end of the ferroelectric capacitor C is connected to the word line WL, the first electrode of the transistor T is connected to the source line SL, and the second electrode of the transistor T is connected to the bit line BL.

[0078] It is understood that the number of memory cells 310 shown in Figures 4 and 5 does not limit the number of memory cells 310 in the memory array 300 provided in the embodiment of the present application. The number of memory cells 310 in the memory array 300 provided in the embodiment of the present application can be designed according to actual needs. The structure of the memory cell 310 in the embodiment of the present application is also not limited to the structure shown in Figures 4 and 5. A single memory cell 310 may also include multiple transistors T and multiple ferroelectric capacitors C.

[0079] Typically, a ferroelectric capacitor consists of two opposing electrodes and a ferroelectric layer located between them. Under the influence of the two electrodes, the ferroelectric layer undergoes a high-temperature crystallization process to form a polycrystalline thin film containing a mixture of orthorhombic (O-phase), tetragonal (T-phase), and monoclinic (M-phase). The presence of the O-phase and T-phase gives the ferroelectric layer its ferroelectric properties, while the M-phase imparts dielectric properties.

[0080] The ferroelectric layer contains crystals in the ferroelectric phase (i.e., the orthorhombic and tetragonal phases). When an electric field is applied to the ferroelectric layer, the central atoms of the crystal follow the electric field and remain in a low-energy state. When the electric field is reversed and applied to the ferroelectric layer, the central atoms move within the crystal in the direction of the electric field and remain in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains. Under the action of the electric field, the ferroelectric domains form polarized charges. The polarized charges formed before and after the ferroelectric domains are reversed under the electric field have different energies. This binary stable state causes the ferroelectric capacitor to charge and discharge, which can then be recognized by an external circuit, realizing a "0" or "1" storage state.

[0081] The electrodes of ferroelectric capacitors are crucial for generating ferroelectric properties in the ferroelectric layer. Existing ferroelectric capacitor electrodes are typically made of conductive materials such as titanium nitride (TiN), tungsten (W), and ruthenium (Ru), resulting in an amorphous or polycrystalline microstructure with randomly distributed crystal orientations. These electrodes are unable to effectively induce the ferroelectric layer, making it more susceptible to the formation of the M phase. This can lead to fatigue and breakdown issues in the ferroelectric layer, severely impacting the performance and competitiveness of the memory.

[0082] Based on this, as shown in FIG6 , an embodiment of the present application provides a ferroelectric capacitor C, comprising a first electrode 10, a second electrode 20, and a ferroelectric layer 30 located between the first electrode 10 and the second electrode 20. The first electrode 10 is polycrystalline and includes first columnar grains Q1. A first angle α is formed between an extension direction L1 of the first columnar grains Q1 and a first reference plane U1. The first angle α is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to 50 percent. The first reference plane U1 is parallel to a portion of the surface of the ferroelectric layer 30 that is opposite the first columnar grains Q1.

[0083] FIG6 illustrates an example in which the extension direction L1 of the first columnar grain Q1 is perpendicular to the first reference plane U1, i.e., the angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1 is 90 degrees. Of course, the first angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1 can also be 30 degrees, 45 degrees, 60 degrees, 70 degrees, 75 degrees, 80 degrees, etc.

[0084] It is understood that the polycrystalline body includes a plurality of first columnar grains Q1, and the angles between the extension directions L1 of different first columnar grains Q1 and the first reference plane U1 may be different. That is, among the plurality of first columnar grains Q1 in the polycrystalline body, the extension directions L1 of different first columnar grains Q1 may be different. For example, the extension directions L1 of some of the plurality of first columnar grains Q1 are different, while the extension directions L1 of other portions are the same. For another example, the extension direction L1 of at least one first columnar grain Q1 among the plurality of first columnar grains Q1 is different from the extension directions L1 of the plurality of first columnar grains Q1 surrounding the first columnar grain Q1.

[0085] In the embodiments of the present application, there are no restrictions on the height, cross-sectional shape, and cross-sectional size of the first columnar grains Q1. Among the multiple first columnar grains Q1 in a polycrystalline material, the heights of different first columnar grains Q1 can be the same or different. The cross-sectional shapes of different first columnar grains Q1 can be the same or different. The cross-sectional sizes of different first columnar grains Q1 can be the same or different.

[0086] 6 illustrates an example in which the ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is 100%. In other possible examples, the ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 may be 50%, 60%, 70%, 80%, 90%, etc.

[0087] In some examples, the material of the first electrode 10 and the material of the second electrode 20 may include at least one of a metal, a conductive oxide, and a conductive nitride. Examples of metals include W (tungsten), Pt (platinum), Sr (strontium), Ru (ruthenium), La (lanthanum), Mn (manganese), Ti (titanium), Au (gold), Ag (silver), and Al (aluminum). Examples of conductive oxides include TiO (titanium oxide), NbO (niobium oxide), RuO2 (ruthenium oxide), IrO (iridium oxide), ITO (indium tin oxide), AZO (aluminum-doped zinc oxide), and FTO (fluorine-doped tin oxide). Examples of conductive nitrides include TiN (titanium nitride), TiAlN (titanium aluminum nitride), WN (tungsten nitride), and TaN (tantalum nitride).

[0088] When the above-mentioned "metals, conductive oxides, and conductive nitrides" are prepared using different processes, the structures of the "metals, conductive oxides, and conductive nitrides" can be different, that is, the above-mentioned "metals, conductive oxides, and conductive nitrides" can be amorphous, polycrystalline with randomly distributed crystal orientations, or have columnar grains.

[0089] It can be understood that when the material of the first electrode 10 includes at least one of metal, conductive oxide, and conductive nitride, the above-mentioned "metal, conductive oxide, and conductive nitride" are all polycrystalline and include first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, and the ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent.

[0090] Exemplarily, the thickness of the first electrode 10 can be 10 nm to 300 nm. For example, the thickness of the first electrode 10 is 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 200 nm, 300 nm, etc. In this way, the thickness of the first electrode 10 will not be too small, and the structural stability of the first electrode 10 can be relatively high, thereby ensuring that the first electrode 10 clamps the ferroelectric layer 30 and ensures the generation of a ferroelectric phase in the ferroelectric layer 30. At the same time, the thickness of the first electrode 10 will not be too large, so that the preparation cost of the first electrode 10 will not be too high, and the preparation time will not be too long, which is conducive to controlling the cost and preparation efficiency of the ferroelectric capacitor C.

[0091] Exemplarily, the thickness of the second electrode 20 can be 10 nm to 300 nm. For example, the thickness of the second electrode 20 is 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 200 nm, 300 nm, etc. In this way, the thickness of the second electrode 20 is not too small, and the structural stability of the second electrode 20 can be relatively high, thereby ensuring that the second electrode 20 clamps the ferroelectric layer 30 and ensures the generation of a ferroelectric phase in the ferroelectric layer 30. At the same time, the thickness of the second electrode 20 is not too large, so that the preparation cost of the second electrode 20 is not too high and the preparation time is not too long, thereby helping to control the cost and preparation efficiency of the ferroelectric capacitor C.

[0092] It is understood that the thickness of the first electrode 10 and the thickness of the second electrode 20 in the embodiment of the present application are not limited to the above examples.

[0093] In some examples, the material of the ferroelectric layer 30 may include a hafnium oxide-based material and a doping element. The hafnium oxide-based material may include hafnium oxide or hafnium zirconium oxide, and the doping element may include at least one of zirconium (Zr), lanthanum (La), aluminum (Al), titanium (Ti), and niobium (Nb). It is understood that when the doping element is zirconium, the material of the ferroelectric layer 30 may also include zirconium oxide; when the doping element is lanthanum, the material of the ferroelectric layer 30 may also include lanthanum oxide; when the doping element is aluminum, the material of the ferroelectric layer 30 may also include aluminum oxide; when the doping element is Ti, the material of the ferroelectric layer 30 may also include titanium oxide; and when the doping element is niobium, the material of the ferroelectric layer 30 may also include niobium oxide. Of course, in order to provide the ferroelectric layer 30 with doping elements, the ferroelectric layer 30 may also include other materials containing lanthanum, aluminum, titanium, and niobium.

[0094] In some examples, as shown in Figure 6 , the ferroelectric layer 30 may have a single-layer structure. In other examples, as shown in Figure 7 , the ferroelectric layer 30 may have a multi-layer structure.

[0095] Taking the example of a ferroelectric layer 30 comprising hafnium oxide and doped with zirconium as an example, when the ferroelectric layer 30 is a single-layer structure, the ferroelectric layer 30 may be an alloy structure of interwoven hafnium oxide and zirconium oxide monolayers. When the ferroelectric layer 30 is a multi-layer structure, the ferroelectric layer 30 may include a plurality of alternating hafnium oxide layers 31 and a plurality of zirconium oxide layers 32. Alternatively, when the ferroelectric layer 30 is a multi-layer structure, the ferroelectric layer 30 may include a plurality of alternating hafnium-rich hafnium-zirconium oxide layers (having ferroelectric properties) and a plurality of zirconium-rich hafnium-zirconium oxide layers (having antiferroelectric properties). The term "hafnium-rich" herein means that the hafnium content in the hafnium-zirconium oxide layer is higher than the zirconium content, and "zirconium-rich" means that the zirconium content in the hafnium-zirconium oxide layer is higher than the hafnium content.

[0096] In the case where the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked, the film layer in the ferroelectric layer 30 closest to the first electrode 10 may be the hafnium oxide layer 31, and the film layer in the ferroelectric layer 30 closest to the second electrode 20 may be the zirconium oxide layer 32; alternatively, the film layer in the ferroelectric layer 30 closest to the first electrode 10 may be the zirconium oxide layer 32, and the film layer in the ferroelectric layer 30 closest to the first electrode 10 may be the hafnium oxide layer 31. Of course, in the case where the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked, the film layer in the ferroelectric layer 30 closest to the first electrode 10 and the film layer closest to the second electrode 20 may both be the hafnium oxide layer 31 or both be the zirconium oxide layer 32.

[0097] It is understood that because the strength of the chemical bond between hafnium and oxygen is different from the strength of the chemical bond between zirconium and oxygen, the hafnium oxide layer 31 and the zirconium oxide layer 32 have different binding effects on oxygen ions, resulting in different oxygen ion concentrations in the hafnium oxide layer and the zirconium oxide layer. Furthermore, the lattice fit between the hafnium oxide layer 31 and the first electrode 10 is different from the lattice fit between the zirconium oxide layer 32 and the first electrode 10. Therefore, the stress between the hafnium oxide layer 31 and the first electrode 10 is different from the stress between the zirconium oxide layer 32 and the first electrode 10. Of course, the lattice fit between the hafnium oxide layer 31 and the second electrode 20 is also different from the lattice fit between the zirconium oxide layer 32 and the second electrode 20. Therefore, the stress between the hafnium oxide layer 31 and the second electrode 20 is also different from the stress between the zirconium oxide layer 32 and the second electrode 20.

[0098] The stress applied by the first electrode 10 and the second electrode 20 to the ferroelectric layer 30, and the oxygen ion concentration in the ferroelectric layer 30, both affect the generation of the M phase and the O phase in the ferroelectric layer, thereby affecting the properties of the ferroelectric capacitor C. Therefore, when the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 alternately stacked, the performance of the ferroelectric capacitor C can be improved by adjusting the number and order of the hafnium oxide layers 31 and the zirconium oxide layers 32 in the ferroelectric layer 30.

[0099] For example, when the film layer closest to the first electrode 10 and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can both be the hafnium oxide layer 31, the memory window of the ferroelectric capacitor C can be larger. When the film layer closest to the first electrode 10 and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can both be the zirconium oxide layer 32, the ferroelectric capacitor C is less likely to have reliability issues such as fatigue or breakdown.

[0100] Of course, the performance of the ferroelectric capacitor C when the ferroelectric layer 30 is a single-layer structure differs from that when the ferroelectric layer 30 is a multi-layer structure. For example, when the ferroelectric layer 30 is an alloy structure composed of interwoven hafnium oxide and zirconium oxide monolayers, the storage time of the ferroelectric capacitor using this ferroelectric layer 30 can be longer. When the ferroelectric layer 30 is a multi-layer structure, the storage window of the ferroelectric capacitor using this ferroelectric layer 30 can be larger, the number of read and write operations can be greater, and the reliability of the ferroelectric capacitor C can be higher.

[0101] The present embodiment does not limit the thickness of the ferroelectric layer 30 and can be designed based on actual needs. In the case where the ferroelectric layer 30 has a multi-layer structure, the thickness of each sublayer in the ferroelectric layer 30 (for example, the hafnium oxide layer and the zirconium oxide layer) can also be designed based on actual needs. For example, in the case where the ferroelectric layer 30 includes multiple hafnium oxide layers and multiple zirconium oxide layers stacked alternately, the thickness of the hafnium oxide layer and the zirconium oxide layer can be in the nanometer range.

[0102] The first electrode 10 and the reference electrode (a polycrystalline electrode with random crystal orientation) were tested using X-ray diffraction (XRD) technology, and the test results shown in FIG8 were obtained. The first electrode 10 and the reference electrode were both made of tungsten (W).

[0103] In the test result diagram shown in FIG8 , the horizontal label is 2theta, which is the diffraction angle, and the unit is degree (°). The diffraction angle is the angle between the incident X-ray and the diffraction line, and theta is called the diffraction half-angle, which is the angle between the incident X-ray and the crystal plane that meets the diffraction conditions. The vertical axis is intensity, which is the intensity after the X-ray is diffracted. The unit of the vertical axis is au (arbitrary unit). In FIG8 , the diffraction curve of the first electrode 10 is represented by a “solid line”, and the diffraction curve of the control electrode is represented by a “dashed line”.

[0104] As shown in Figure 8, there are three higher peaks in the detection curve of the control electrode. From left to right, the three peaks respectively indicate the presence of the (110) crystal orientation, the (200) crystal orientation, and the (211) crystal orientation in the control electrode. However, there are only two higher peaks in the detection curve of the first electrode. From left to right, the two peaks respectively indicate the presence of the (110) crystal orientation and the (211) crystal orientation in the first electrode. The (200) crystal orientation is basically absent in the first electrode.

[0105] By observing the first electrode and the control electrode through a transmission electron microscope, the result diagram shown in Figure 9 can be obtained, wherein the observation result of the control electrode is shown in Figure 9 (a), and the observation result diagram of the first electrode is shown in Figure 9 (b). Referring to Figure 9 (a), due to the random distribution of the crystal orientation of the grains in the control electrode, the grains in the control electrode are easy to combine with each other to form a larger overall structure. At the same time, the growth rate of the individual grains in the control electrode in different directions is balanced, so that the size of the individual grains in different directions is larger and the volume of the individual grains is also larger. However, the first electrode 10 provided in the embodiment of the present application has a preferred orientation that is almost not (200) crystalline direction. The growth rate of the first columnar grains in the first electrode 10 in different directions is uneven, so that the first columnar grains Q1 in the first electrode can be columnar and extend along the thickness direction of the first electrode 10.

[0106] Research has found that the (200) crystal orientation in the electrode of a ferroelectric capacitor easily induces the generation of an M phase in the ferroelectric layer, while the (110) crystal orientation in the electrode easily induces the generation of an O phase in the ferroelectric layer. Therefore, when the (200) crystal orientation is substantially absent in the first electrode, the ferroelectric layer of the ferroelectric capacitor provided in the embodiment of the present application can contain less M phase and more O phase.

[0107] Based on this, in the ferroelectric capacitor C provided in the embodiment of the present application, the first electrode 10 is a polycrystalline, and the first electrode 10 includes a first columnar grain Q1. There is a first angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1. The first angle α is greater than 0 degrees and less than or equal to 90 degrees. When the ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent, the M phase generated in the ferroelectric layer 30 can be less and the O phase generated can be more.

[0108] The ferroelectric layer 30 has fewer M phases and more O phases. This can, on the one hand, reduce the coercive electric field of the ferroelectric capacitor C and lower the operating voltage of the ferroelectric capacitor C, thereby enabling the memory cell using the ferroelectric capacitor C provided by the embodiment of the present application to operate at a lower operating voltage and lower power consumption during read and write operations. Furthermore, the fatigue period of the ferroelectric capacitor C can be delayed, and the leakage current of the ferroelectric capacitor C can be reduced, thereby increasing the number of storage times of the ferroelectric capacitor C, ensuring the storage window of the ferroelectric capacitor C after multiple storages, and improving the reliability of the ferroelectric capacitor. This in turn ensures the accuracy of the read and write operations of the memory cell 310 using the ferroelectric capacitor C provided by the embodiment of the present application, thereby improving the performance of the memory.

[0109] At the same time, the ferroelectric layer 30 has fewer M phases and more O phases, which can also make the film layer of the ferroelectric layer 30 have better bearing capacity and the structure of the ferroelectric capacitor C more stable, thereby ensuring the storage capacity of the ferroelectric capacitor C, improving the reliability of the ferroelectric capacitor, reducing the storage window loss rate of the storage array (memory) using the ferroelectric capacitor C, ensuring the accuracy of the storage array read and write operations, and reducing the misread rate.

[0110] In some examples, the first angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1 can be greater than or equal to 30 degrees and less than or equal to 90 degrees. In this way, the (200) crystal orientation is less likely to be generated in the first electrode 10, thereby further reducing the M phase in the ferroelectric layer 30 and increasing the O phase in the ferroelectric layer 30.

[0111] 10 , the ferroelectric capacitor C may further include a third electrode 40, which is located on a side of the first electrode 10 away from the ferroelectric layer 30. The third electrode 40 is amorphous or a polycrystalline material with randomly distributed crystal orientations.

[0112] In this way, the first electrode 10 and the third electrode 40 are located on the same side of the ferroelectric layer 30. The first electrode 10 and the third electrode 40 can jointly provide clamping stress for the ferroelectric layer 30, and the thickness of the first electrode 10 can be relatively small. In the process of preparing the ferroelectric capacitor C, in order to make the first electrode 10 polycrystalline, the first electrode 10 includes first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, and the ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to 50%, when preparing the first electrode 10, it is necessary to adjust the process conditions, such as the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the first electrode 10 can shorten the preparation time of the first electrode 10, thereby reducing the difficulty and process complexity of the preparation of the ferroelectric capacitor and improving the preparation efficiency of the ferroelectric capacitor.

[0113] In some embodiments, referring to Figure 10, when the first electrode 10 is a polycrystalline, the first electrode 10 includes a first columnar grain Q1, and there is a first angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1, the second electrode 20 can be an amorphous material or a polycrystalline material with randomly distributed crystal orientations.

[0114] In other embodiments, as shown in Figure 11, when the first electrode 10 is a polycrystalline, the first electrode 10 includes a first columnar grain Q1, and there is a first angle α between the extension direction L1 of the first columnar grain Q1 and the first reference plane U1, the second electrode 20 can be a polycrystalline, the second electrode 20 includes a second columnar grain Q2, and there is a second angle β between the extension direction of the second columnar grain Q2 and the second reference plane U2, the second angle β is greater than 0 degrees and less than or equal to 90 degrees, the ratio of the number of the second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to fifty percent, and the second reference plane U2 is parallel to the portion of the surface of the ferroelectric layer 30 opposite to the second columnar grain Q2.

[0115] FIG11 illustrates an example in which the extension direction L2 of the second columnar grain Q2 is perpendicular to the second reference plane U2, i.e., the second angle β between the extension direction L2 of the second columnar grain Q2 and the second reference plane U2 is 90 degrees. Of course, the second angle β between the extension direction L2 of the second columnar grain Q2 and the second reference plane U2 can also be 30 degrees, 45 degrees, 60 degrees, 70 degrees, 75 degrees, 80 degrees, etc.

[0116] It is understood that the second electrode 20 includes a plurality of second columnar grains Q2, and the second angles between the extension directions L2 of different second columnar grains Q2 and the second reference plane U2 may be different. That is, the extension directions L2 of different second columnar grains Q2 in the polycrystalline body may be different. For example, the extension directions L2 of some of the plurality of second columnar grains Q2 are different, while the extension directions L2 of other portions are the same. For another example, the extension direction L2 of at least one second columnar grain Q2 among the plurality of second columnar grains Q2 is different from the extension directions L2 of the plurality of second columnar grains Q2 surrounding the second columnar grain Q2.

[0117] 11 illustrates an example in which the ratio of the number of second columnar grains Q2 to the number of all grains in the second electrode 20 is 100%. In other possible examples, the ratio of the number of second columnar grains Q2 to the number of all grains in the second electrode 20 may be 50%, 60%, 70%, 80%, 90%, etc.

[0118] In the ferroelectric capacitor C provided in the embodiment of the present application, the second electrode 20 is a polycrystalline material, and the second electrode 20 includes second columnar grains Q2. There is a second angle β between the extension direction of the second columnar grains Q2 and the second reference plane U2. The second angle β is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to fifty percent. The second electrode 20 also has a preferred orientation that hardly presents the (200) crystal direction, so that the M phase generated in the ferroelectric layer 30 can be less and the O phase generated is more.

[0119] In some examples, the second angle β between the extension direction L2 of the second columnar grain Q2 and the second reference plane U2 can be greater than or equal to 30 degrees and less than or equal to 90 degrees. In this way, the (200) crystal orientation is less likely to be generated in the second electrode 20, thereby further reducing the M phase in the ferroelectric layer 30 and increasing the O phase in the ferroelectric layer 30.

[0120] In some embodiments, as shown in FIG12 , when the second electrode 20 is polycrystalline, includes second columnar grains Q2, and a second angle β exists between the extension direction L2 of the second columnar grains Q2 and the second reference plane U2, the ferroelectric capacitor C may further include a fourth electrode 50, which is located on a side of the second electrode 20 away from the ferroelectric layer 30. The fourth electrode 50 is amorphous or polycrystalline with randomly distributed crystal orientations.

[0121] In this way, the second electrode 20 and the fourth electrode 50 are located on the same side of the ferroelectric layer 30. The second electrode 20 and the fourth electrode 50 can jointly provide clamping stress for the ferroelectric layer 30, and the thickness of the second electrode 20 can be relatively small. In the process of preparing the ferroelectric capacitor C, in order to ensure that the second electrode 20 includes second columnar grains Q2, and the extension direction of the second columnar grains Q2 has a second angle β with the second reference plane U2, and the ratio of the number of second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to 50%, when preparing the second electrode 20, it is necessary to adjust the process conditions, such as the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the second electrode 20 can shorten the preparation time of the second electrode 20, thereby reducing the difficulty and process complexity of the preparation of the ferroelectric capacitor C and improving the preparation efficiency of the ferroelectric capacitor C.

[0122] In some embodiments, as shown in Figure 13, when the first electrode 10 is polycrystalline, the first electrode 10 includes first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, the second electrode 20 is polycrystalline, the second electrode 20 includes second columnar grains Q2, and there is a second angle β between the extension direction L2 of the second columnar grains Q2 and the second reference plane U2, the ferroelectric capacitor C can include a third electrode 40 and a fourth electrode 50 at the same time.

[0123] In this way, the first electrode 10 and the third electrode 40 are located on the same side of the ferroelectric layer 30, and the first electrode 10 and the third electrode 40 can jointly provide clamping stress for the ferroelectric layer 30. The second electrode 20 and the fourth electrode 50 are located on the same side of the ferroelectric layer 30, and the second electrode 20 and the fourth electrode 50 can jointly provide clamping stress for the ferroelectric layer 30. The thickness of the first electrode 10 and the second electrode 20 can both be relatively small, which is beneficial to shortening the preparation time of the first electrode 10 and the second electrode 20 during the preparation process of the ferroelectric capacitor C and improving the preparation efficiency of the ferroelectric capacitor C.

[0124] Figures 14 and 15 are schematic structural diagrams of two ferroelectric capacitors C provided in embodiments of the present application. In some embodiments, as shown in Figures 14 and 15 , the ferroelectric capacitor C may further include a first buffer layer 60, which is located between the first electrode 10 and the ferroelectric layer 30 and contacts the ferroelectric layer 30. Compared to the ferroelectric capacitor C shown in Figure 14 , the ferroelectric capacitor C shown in Figure 15 further includes a third electrode 40.

[0125] For example, the material of the first buffer layer 60 may include titanium oxide, niobium oxide, cerium oxide, silicon nitride, etc. In the embodiment of the present application, there is no limitation on the thickness of the first buffer layer 60 and it can be designed according to actual needs.

[0126] The embodiment of the present application provides a first buffer layer 60 between the first electrode 10 and the ferroelectric layer 30. On the one hand, the first buffer layer 60 can be used to adjust the stress between the first electrode 10 and the ferroelectric layer 30, thereby improving the structural stability of the ferroelectric capacitor C. On the other hand, it can also inhibit the diffusion of metal particles in the first electrode 10 into the ferroelectric layer 30, inhibit the diffusion of oxygen atoms in the ferroelectric layer 30 into the first electrode 10, reduce the oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, weaken the oxidation effect between the electrode and the oxygen ions, and avoid the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor, preventing the ferroelectric capacitor from being broken down, and improving the service life of the ferroelectric capacitor. At the same time, the reduction of oxygen vacancies in the ferroelectric layer 30 can also improve the polarization fatigue and imprinting effect caused by oxygen vacancies, thereby improving the accuracy of reading and writing data in the storage unit 310 using the ferroelectric capacitor C.

[0127] Figures 16 and 17 respectively show schematic structural diagrams of two ferroelectric capacitors C provided in embodiments of the present application. In some embodiments, as shown in Figures 16 and 17, the ferroelectric capacitor C may further include a second buffer layer 70. The second buffer layer 70 is located between the second electrode 20 and the ferroelectric layer 30, and is in contact with the ferroelectric layer 30. Compared with the ferroelectric capacitor shown in Figure 16, the ferroelectric capacitor C shown in Figure 17 further includes a fourth electrode 50. In the case where the ferroelectric capacitor C includes the second buffer layer 70, the ferroelectric capacitor C may include the first buffer layer 60 (as shown in Figure 16), that is, the first buffer layer 60 may not be included (as shown in Figure 17).

[0128] For example, the material of the second buffer layer 70 may include titanium oxide, niobium oxide, cerium oxide, silicon nitride, etc. In the embodiment of the present application, there is no limitation on the thickness of the second buffer layer 70 and it can be designed according to actual needs.

[0129] The material of the second buffer layer 70 may be the same as or different from that of the first buffer layer 60 . The thickness of the second buffer layer 70 may be the same as or different from that of the first buffer layer 60 .

[0130] The embodiment of the present application, by providing a second buffer layer 70 between the second electrode 20 and the ferroelectric layer 30, can, on the one hand, inhibit the diffusion of metal particles in the second electrode 20 into the ferroelectric layer 30, inhibit the diffusion of oxygen atoms in the ferroelectric layer 30 into the second electrode 20, reduce the oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, weaken the oxidation effect between the electrode and the oxygen ions, and avoid the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor, preventing the ferroelectric capacitor from being broken down, and improving the service life of the ferroelectric capacitor. At the same time, the reduction of oxygen vacancies in the ferroelectric layer 30 can also improve the polarization fatigue and imprinting effect caused by oxygen vacancies, and improve the accuracy of reading and writing data in the storage unit 310 using the ferroelectric capacitor C. On the other hand, by providing the second buffer layer 70 between the second electrode 20 and the ferroelectric layer 30, the stress between the second electrode 20 and the ferroelectric layer 30 can also be adjusted, thereby improving the structural stability of the ferroelectric capacitor C.

[0131] FIG18 is a schematic structural diagram of a ferroelectric capacitor C provided in an embodiment of the present application. In yet other embodiments, as shown in FIG18 , in addition to the first electrode 10, the second electrode 20, and the ferroelectric layer 30, the ferroelectric capacitor C may further include a third electrode 40, a fourth electrode 50, a first buffer layer 60, and a second buffer layer 70. The functions of the third electrode 40, the fourth electrode 50, the first buffer layer 60, and the second buffer layer 70 can be referred to in the above examples and will not be further described here.

[0132] In some embodiments, the ferroelectric capacitor C can have a two-dimensional structure. In this case, as shown in FIG18 , the first electrode 10 and the second electrode 20 can both be planar electrodes, and the first electrode 10 and the second electrode 20 can be stacked. This can simplify the structure of the ferroelectric capacitor C, thereby simplifying the preparation process of the ferroelectric capacitor C and reducing the preparation cost.

[0133] In other embodiments, the ferroelectric capacitor C can be a three-dimensional structure. In this case, as shown in Figure 19, the surface of the first electrode 10 close to the ferroelectric layer 30 includes a connecting surface S1, a first side surface S2, and a second side surface S3. The first side surface S2 and the second side surface S3 are located on opposite sides of the connecting surface S1 and are both connected to the connecting surface S1. The extension direction of the first side surface S2 and the second side surface S3 is different from the extension direction of the connecting surface S1. The ferroelectric layer 30 is arranged relative to the connecting surface S1, the first side surface S2, and the second side surface S3. The second electrode 20 is located on the side of the ferroelectric layer 30 away from the first electrode 10, and is arranged relative to the connecting surface S1, the first side surface S2, and the second side surface S3.

[0134] In this way, the facing area between the first electrode 10 and the second electrode 20 of the ferroelectric capacitor C can be larger, thereby making it possible to increase the capacitance value of the ferroelectric capacitor C. When the ferroelectric capacitor C provided by the embodiment of the present application is applied to a memory, even if the occupied area of ​​the ferroelectric capacitor C is small, the capacitance value of the ferroelectric capacitor C can meet the requirements of the memory, thereby helping to reduce the size of the memory and achieve miniaturization and high integration.

[0135] In some examples, as shown in FIG. 20A , a ferroelectric capacitor C may be located on a substrate 101 having a recess H, and the ferroelectric capacitor C may be located in the recess H as a trench capacitor.

[0136] In some possible examples, the second electrode of the ferroelectric capacitor C covers the bottom wall and sidewalls of the groove, the ferroelectric layer is located inside the second electrode, and the first electrode is located inside the ferroelectric layer and fills the groove.

[0137] FIG20A illustrates a ferroelectric capacitor C including a first electrode 10, a second electrode 20, a ferroelectric layer 30, a third electrode 40, a fourth electrode 50, a first buffer layer 60, and a second buffer layer 70. In other possible examples, as shown in FIG20A , the fourth electrode 50 is located in a groove H of the substrate 101 and covers the bottom wall and inner wall of the groove H, the second electrode 20 is located inside the fourth electrode 50, the second buffer layer 70 is located inside the second electrode 20, the ferroelectric layer 30 is disposed inside the second buffer layer 70, the first buffer layer 60 is disposed inside the ferroelectric layer 30, the first electrode 10 is disposed inside the first buffer layer 60, and the third electrode 40 is disposed inside the first electrode 10 and fills the groove H. Of course, when the ferroelectric capacitor C is a trench capacitor, the structure of the ferroelectric capacitor C is not limited thereto.

[0138] In other examples, the ferroelectric capacitor C can be located on the substrate 101, and the ferroelectric capacitor C can be a fin capacitor. In this case, referring to FIG19 , the first electrode 10 can be a rectangular parallelepiped, and the first electrode 10 includes a connection surface S1, a first side surface S2, and a second side surface S3. The first side surface S2 and the second side surface S3 are respectively located on both sides of the connection surface and are connected to the connection surface. The extension direction of the first side surface S1 and the second side surface S2 are different from the extension direction of the connection surface S1. The ferroelectric layer 30 covers the first electrode 10 and is arranged opposite to the connection surface S1, the first side surface S2, and the second side surface S3. The second electrode 20 is located on the side of the ferroelectric layer 30 away from the first electrode 10 and is arranged opposite to the connection surface S1, the first side surface S2, and the second side surface S3.

[0139] FIG20B illustrates a ferroelectric capacitor C comprising a first electrode 10, a second electrode 20, a ferroelectric layer 30, a third electrode 40, a fourth electrode 50, a first buffer layer 60, and a second buffer layer 70. In other possible examples, referring to FIG20B , the fourth electrode 50 may be fin-shaped. The second electrode 20 covers the surface of the fourth electrode 50. The second buffer layer 70, the ferroelectric layer 30, the first buffer layer 60, the first electrode 10, and the third electrode 40 sequentially cover the surface of the second electrode 20.

[0140] In some other examples, as shown in Figure 21, the first electrode 10 of the ferroelectric capacitor C can be a planar electrode, the second electrode 20 can be a columnar electrode, the second electrode 20 runs through the first electrode 10 (that is, the first electrode 10 is arranged around the second electrode 20), and the ferroelectric layer 30 is located between the first electrode 10 and the second electrode 20.

[0141] 21 , in addition to the first electrode 10, the second electrode 20, and the ferroelectric layer 30, the ferroelectric capacitor C may further include a first buffer layer 60 and a second buffer layer 70. The first buffer layer 60 is located between the first electrode 10 and the ferroelectric layer 30, and the second buffer layer 70 is located between the second electrode 20 and the ferroelectric layer 30.

[0142] In some other examples, when the ferroelectric capacitor C includes a first electrode 10, a second electrode 20, a ferroelectric layer 30, a third electrode 40, a fourth electrode 50, a first buffer layer 60, and a second buffer layer 70, the third electrode 40 can be a planar electrode, the fourth electrode 50 can be a columnar electrode, the fourth electrode 50 runs through the third electrode 40, and between the fourth electrode 50 and the third electrode 40, along the direction of the fourth electrode 50 pointing to the third electrode 40, the second electrode 20, the second buffer layer 70, the ferroelectric layer 30, the first buffer layer 60 and the first electrode 10 are arranged in sequence.

[0143] The above embodiments of the present application illustrate three possible structures of the ferroelectric capacitor C when it is a three-dimensional structure, but it is understandable that the structure of the ferroelectric capacitor C is not limited thereto.

[0144] As shown in FIG22 , an embodiment of the present application provides a method for manufacturing a ferroelectric capacitor, the method comprising steps S100, S200, and S300. S100: Forming a first electrode 10. S200: Forming a ferroelectric layer 30. S300: Forming a first electrode 20.

[0145] The ferroelectric layer 30 is located between the first electrode 10 and the second electrode 20. The first electrode 10 is polycrystalline and includes first columnar grains Q1. An extension direction L1 of the first columnar grains Q1 forms a first angle α with a first reference plane U1. The first angle α is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to 50 percent. The first reference plane U1 is parallel to the portion of the surface of the ferroelectric layer 30 that is opposite the first columnar grains Q1.

[0146] In the above-mentioned preparation method, regarding the optional materials of the first electrode 10, the second electrode 20 and the ferroelectric layer 30, reference can be made to the above-mentioned description of the structure of the ferroelectric capacitor C of the present application, which will not be repeated here.

[0147] When forming the first electrode 10, the second electrode 20, or the ferroelectric layer 30, magnetron sputtering or thin film deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) can be used. This allows the first electrode 10, the second electrode 20, or the ferroelectric layer 30 to be relatively uniform, have high flatness, and high conformality, meaning that each layer has substantially consistent shape and surface flatness.

[0148] When the ferroelectric capacitor C is a three-dimensional structure, photolithography, etching (for example, dry etching, wet etching, etc.), chemical mechanical polishing (CMP), etc. may be used in the process of preparing the first electrode 10, the second electrode 20 or the ferroelectric layer 30.

[0149] For example, by controlling process conditions, the first electrode 10 can be polycrystalline, including first columnar grains Q1, and a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1. The first angle α is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of first columnar grains Q1 to the total number of grains in the first electrode 10 is greater than or equal to 50 percent. For example, process conditions such as temperature, reaction gas flow rate, and reaction equipment power can be adjusted to ensure that the first electrode 10 includes first columnar grains Q1, and a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1 is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of first columnar grains Q1 to the total number of grains in the first electrode 10 is greater than or equal to 50 percent. It will be appreciated that when different materials are selected for preparing the first electrode 10, the adjustment trend (increase or decrease) of the process conditions may also vary.

[0150] In the embodiment of the present application, the order of step S100, step S200, and step S300 is not limited and can be designed according to actual conditions. Figure 22 provides a flow chart of a possible method for preparing a ferroelectric capacitor. As shown in Figure 22, the second electrode 20 can be formed first (step S300), and then the ferroelectric layer 30 can be formed (step S200), and the ferroelectric layer 30 can be formed on one side of the second electrode 20. Finally, the first electrode 10 can be formed (step S100), and the first electrode 10 can be located on the side of the ferroelectric layer 30 away from the second electrode 20. In other words, the ferroelectric capacitor is prepared in the order of step S300, step S200, and step S100.

[0151] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any appropriate manner in any one or more embodiments or examples. The above description is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art who can easily think of changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application shall be based on the scope of protection of the claims.

Claims

1. A ferroelectric capacitor, characterized in that, Comprising: A first electrode and a second electrode, A ferroelectric layer located between the first electrode and the second electrode; Wherein, the first electrode is a polycrystal, the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane, the first included angle is greater than 0 degree and less than or equal to 90 degrees, and the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent; the first reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the first columnar grains.

2. The ferroelectric capacitor according to claim 1, characterized in that, Further comprising: A third electrode located on the side of the first electrode away from the ferroelectric layer; The third electrode is an amorphous or polycrystal with randomly distributed crystal orientations.

3. The ferroelectric capacitor according to claim 1 or 2, characterized in that, Further comprising: A first buffer layer located between the first electrode and the ferroelectric layer and in contact with the ferroelectric layer.

4. The ferroelectric capacitor according to any one of claims 1 to 3, characterized in that, The second electrode is a polycrystal, the second electrode includes second columnar grains, and there is a second included angle between the extending direction of the second columnar grains and a second reference plane, the second included angle is greater than 0 degree and less than or equal to 90 degrees; the ratio of the number of the second columnar grains to the number of all grains in the second electrode is greater than or equal to fifty percent, and the second reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the second columnar grains.

5. The ferroelectric capacitor according to claim 4, characterized in that, Further comprising: A fourth electrode located on the side of the second electrode away from the ferroelectric layer; The fourth electrode is an amorphous or polycrystal with randomly distributed crystal orientations.

6. The ferroelectric capacitor according to any one of claims 1 to 5, characterized in that, Further comprising: A second buffer layer located between the second electrode and the ferroelectric layer and in contact with the ferroelectric layer.

7. The ferroelectric capacitor according to any one of claims 1 to 6, wherein The material of the ferroelectric layer includes a hafnium oxide-based material and a doping element; the doping element includes at least one of zirconium, lanthanum, aluminum, titanium, and niobium.

8. The ferroelectric capacitor according to any one of claims 1 to 7, characterized in that The material of the first electrode includes at least one of a metal, a conductive oxide, and a conductive nitride; and / or, The material of the second electrode includes at least one of a metal, a conductive oxide, and a conductive nitride.

9. The ferroelectric capacitor according to any one of claims 1 to 8, characterized in that, The first electrode and the second electrode are both planar electrodes, and the first electrode and the second electrode are stacked.

10. The ferroelectric capacitor according to any one of claims 1 to 8, characterized in that, The surface of the first electrode close to the ferroelectric layer includes a connecting surface, a first side surface, and a second side surface. The first side surface and the second side surface are located on opposite sides of the connecting surface and are both connected to the connecting surface. The extending directions of the first side surface and the second side surface are both different from the extending direction of the connecting surface; the ferroelectric layer is disposed opposite to the connecting surface, the first side surface, and the second side surface; the second electrode is located on the side of the ferroelectric layer away from the first electrode and is disposed opposite to the connecting surface, the first side surface, and the second side surface.

11. A method for preparing a ferroelectric capacitor, characterized in that, Comprising: Forming a first electrode; Forming a ferroelectric layer; And, Forming a second electrode; Wherein, the ferroelectric layer is located between the first electrode and the second electrode; the first electrode is polycrystalline, the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane, the first included angle is greater than 0 degree and less than or equal to 90 degrees; the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent; the first reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the first columnar grains.

12. A storage array, characterized in that, Comprising: A plurality of memory cells, including a transistor and a ferroelectric capacitor as described in any one of claims 1 to 10, the transistor being connected to the ferroelectric capacitor.

13. A memory, characterized in that, Comprising: A memory array as described in claim 12; A controller, electrically connected to the memory array.

14. An electronic device, characterized in that, Comprising: A memory as described in claim 13; A circuit board, the memory being located on the circuit board and electrically connected to the circuit board.

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