Heat dissipating semiconductor package structure and preparation method therefor

Abstract

Provided are a heat dissipating semiconductor package structure and a preparation method therefor; in an embodiment, a third re-wiring layer is prepared while dummy metal wiring having good thermal conductivity is formed on a back face of a first chip, so as to construct a thermally conductive rail in contact with the first chip, and thus a heat dissipating semiconductor package structure having good thermal conductivity is prepared. The first chip is made thinner while removing a chip adhesive film having poor thermal conductivity, which can satisfy consumer demand for miniaturized lightweight products; further, the thermally conductive rail may also comprise a capacitor and / or an inductor formed during preparation of the third re-wiring layer, so as to implement a heat dissipation effect while implementing capacitor or inductor functionality, thereby reducing costs and reducing packaging size.

Description

Heat dissipation type semiconductor packaging structure and preparation method thereof Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a heat dissipation type semiconductor packaging structure and a preparation method thereof. Background Art

[0002] The rapid development of electronic products is the primary driving force behind the evolution of packaging technology. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development trends in advanced packaging. System-in-a-Package (SIP) is one of the most important and promising technologies for meeting this high-density system integration requirement.

[0003] SIP packaging refers to the integration of multiple functional chips, such as processors, memory and other functional chips, into a packaging structure based on application scenarios, the number of packaging substrate layers and other factors, thereby realizing complete functions through a packaging structure.

[0004] At present, the SIP packaging structure is highly centralized. The heat generated during the operation of the chip will cause irreversible damage to the chip itself, so the heat dissipation of the packaging structure needs to be considered.

[0005] As shown in Figure 1, in a traditional heat dissipation packaging structure, a heat sink 10 is typically mounted on the back of a chip 20 to dissipate heat through the heat sink 10, thereby effectively preventing damage to the chip 20 caused by high temperatures. Products with this structure can be used in large-sized terminal products. However, this heat dissipation method significantly increases the size of the packaging structure, which is not conducive to the miniaturization of IC (Integrated Circuit) chips. In other words, it is not conducive to the preparation of microelectronic devices and cannot be applied to miniaturized consumer terminals such as mobile phones.

[0006] Therefore, it is necessary to provide a heat dissipation type semiconductor packaging structure and a preparation method thereof. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a heat dissipation type semiconductor package structure and a preparation method thereof, so as to solve the problem in the prior art that it is difficult to prepare a miniaturized heat dissipation package structure.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a heat dissipation type semiconductor package structure, comprising the following steps:

[0009] providing a first supporting substrate;

[0010] forming a metal column on the first supporting substrate, wherein a first end of the metal column contacts the first supporting substrate;

[0011] forming a chip composite structure on the first supporting substrate, the chip composite structure comprising a first chip and a first redistribution layer, wherein a back surface of the first chip is in contact with the first supporting substrate by a chip adhesive film, and the first redistribution layer is located on a front surface of the first chip and electrically connected to a chip pad;

[0012] forming a first packaging layer, wherein the first packaging layer includes a first surface and a second surface opposite to each other, the first packaging layer encapsulating the metal pillar and the chip composite structure, and the second surface of the first packaging layer exposing the second end of the metal pillar and the first rewiring layer;

[0013] forming a second redistribution layer on the second surface of the first packaging layer, wherein the second redistribution layer is electrically connected to the metal pillar and the first redistribution layer;

[0014] Providing a second supporting substrate, and bonding the second supporting substrate to the second redistribution layer;

[0015] removing the first supporting substrate to expose the first end of the metal pillar and the chip bonding film;

[0016] performing grinding to remove the chip adhesive film;

[0017] forming a third redistribution layer on the first surface of the first packaging layer, the third redistribution layer being electrically connected to the metal pillars, and the third redistribution layer further comprising a dummy metal wiring located on and in contact with the back surface of the first chip, the dummy metal wiring constituting a thermal rail for the first chip;

[0018] forming a second chip on the third redistribution layer, wherein the second chip is electrically connected to the third redistribution layer;

[0019] forming a second packaging layer, wherein the second packaging layer covers the second chip and the third rewiring layer;

[0020] removing the second supporting substrate to expose the second redistribution layer;

[0021] A metal bump is formed on the second redistribution layer, wherein the metal bump is electrically connected to the second redistribution layer.

[0022] Optionally, after removing the chip adhesive film by grinding, the method further includes continuing to grind to thin the first chip.

[0023] Optionally, the thickness of the first chip after grinding is less than 80 μm.

[0024] Optionally, the dummy metal wiring is prepared synchronously with the metal wiring in the third rewiring layer.

[0025] Optionally, the vertical projection of the dummy metal wiring covers the heat source area of ​​the first chip.

[0026] Optionally, the virtual metal wiring includes one or a combination of capacitors and inductors.

[0027] The present invention further provides a heat dissipation type semiconductor packaging structure, the heat dissipation type semiconductor packaging structure comprising:

[0028] a metal post, the metal post comprising a first end and a second end opposite to each other;

[0029] A chip composite structure, the chip composite structure comprising a first chip and a first redistribution layer, the first redistribution layer being located on a front surface of the first chip and electrically connected to a chip pad;

[0030] a first packaging layer, the first packaging layer comprising a first surface and a second surface opposite to each other, the first packaging layer encapsulating the metal pillar and the chip composite structure, and the second surface of the first packaging layer exposing the second end of the metal pillar and the first redistribution layer;

[0031] a second redistribution layer, the second redistribution layer being located on the second surface of the first packaging layer, the second redistribution layer being electrically connected to the metal pillar and the first redistribution layer;

[0032] a third redistribution layer, the third redistribution layer being located on the first surface of the first packaging layer, the third redistribution layer being electrically connected to the first end of the metal pillar, and the third redistribution layer further comprising a dummy metal wiring located on and in contact with the back surface of the first chip, the thermal rail of the first chip being formed by the dummy metal wiring;

[0033] a second chip, the second chip being located on the third redistribution layer and electrically connected to the third redistribution layer;

[0034] a second packaging layer, the second packaging layer encapsulating the second chip and the third rewiring layer;

[0035] A metal bump is located on the second redistribution layer and is electrically connected to the second redistribution layer.

[0036] Optionally, the thickness of the first chip is less than 80 μm.

[0037] Optionally, the dummy metal wiring has the same material as the metal wiring in the third rewiring layer; the dummy metal wiring includes one or a combination of a capacitor and an inductor.

[0038] Optionally, the vertical projection of the dummy metal wiring covers the heat source area of ​​the first chip.

[0039] As described above, the heat-dissipating semiconductor packaging structure and preparation method thereof of the present invention form virtual metal wiring with good thermal conductivity on the back side of the first chip while preparing the third rewiring layer to constitute a thermal track in contact with the first chip, thereby preparing a heat-dissipating semiconductor packaging structure with good thermal conductivity; while removing the chip adhesive film with poor thermal conductivity, the first chip is thinned, thereby meeting consumers' demand for light, thin and short products; further, the thermal track may also include capacitors and / or inductors formed while preparing the third rewiring layer, so as to achieve heat dissipation while realizing the functions of capacitors and inductors, thereby reducing costs and reducing package size. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of a heat dissipation package in the prior art.

[0041] 2 to 8 are schematic structural diagrams showing the steps in preparing a semiconductor package structure in a comparative example of the present invention.

[0042] FIG. 9 is a flow chart showing a process for preparing a heat dissipation type semiconductor package structure according to an embodiment of the present invention.

[0043] 10 to 20 are schematic structural diagrams showing steps in preparing a heat dissipation type semiconductor package structure according to an embodiment of the present invention.

[0044] DESCRIPTION OF REFERENCE NUMERALS 10 heat sink 20 chip 110 first supporting substrate 111 first separation layer 120 second supporting substrate 121 second separation layer 122 substrate adhesive film 201 first metal seed layer 202 second metal seed layer 311 first metal wiring 312 first dielectric layer 321 second metal wiring 322 second dielectric layer 331 third metal wiring 332 third dielectric layer 333 dummy metal wiring 400 metal pillar 500 chip adhesive film 610 first chip 611 first chip bonding pad 620 second chip 621 second chip bonding pad 710 first encapsulation layer 720 second encapsulation layer 810 first metal bump 820 second metal bump A thermal rail S1 to S13 steps DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0047] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] Comparative Example

[0050] 2 to 8 , a heat dissipation type semiconductor package structure and a method for manufacturing the same are provided. The manufacturing steps may include:

[0051] First, as shown in FIG2 , a first support substrate 110 is provided. To facilitate separation, the surface of the first support substrate 110 preferably has a first separation layer 111 .

[0052] Next, as shown in FIG. 3 and FIG. 4 , a first redistribution layer is formed on the first supporting substrate 110 .

[0053] 3 , a metal seed layer, such as a Ti / Cu metal seed layer, may be first formed on the first supporting substrate 110, that is, the first metal seed layer 201 may be a Ti layer, and the second metal seed layer 202 may be a Cu layer. Then, as shown in FIG4 , the first rewiring layer including the first metal wiring 311 and the first dielectric layer 312 may be formed on the metal seed layer by electroplating.

[0054] Next, as shown in Figure 4, a metal pillar 400 and a chip composite structure are formed on the first redistribution layer, wherein the first end of the metal pillar 400 is electrically connected to the first metal wiring 311, and the chip composite structure includes a first chip 610 and a second redistribution layer, wherein the back side of the first chip 610 is bonded to a chip adhesive film 500 and contacts the first redistribution layer, and the second redistribution layer is located on the front side of the first chip 610 and includes a second metal wiring 321 and a second dielectric layer 322 electrically connected to the first chip pad 611.

[0055] Next, as shown in Figure 5, a first packaging layer 710 is formed, which includes a first surface and a second surface relative to each other. The first packaging layer 710 covers the metal pillar 400 and the chip composite structure, and the second surface of the first packaging layer 710 exposes the second end of the metal pillar 400 and the second metal wiring 321 in the second redistribution layer.

[0056] Next, as shown in FIG. 6 , a third redistribution layer is formed on the second surface of the first packaging layer 710 . The third redistribution layer includes a third metal wiring 331 electrically connected to the second end of the metal pillar 400 and a third dielectric layer 332 .

[0057] Next, as shown in FIG6 , a second supporting substrate 120 is provided, and the second supporting substrate 120 is bonded onto the third re-distribution layer.

[0058] To facilitate separation, the surface of the second support substrate 120 preferably has a second separation layer 121 , and to facilitate the combination of the second support substrate 120 and the third rewiring layer, a substrate adhesive film 122 is provided on the surface of the second separation layer 121 .

[0059] Then, as shown in Figure 7, the first supporting substrate 110 is removed to expose the first metal wiring 311 in the first redistribution layer, and a second chip 620 is formed on the first redistribution layer. The second chip 620 can be electrically connected to the first redistribution layer through a first metal bump 810 electrically connected to the second chip pad 621.

[0060] Then, as shown in FIG. 7 , a second packaging layer 720 is formed. The second packaging layer 720 covers the second chip 620 and the first re-distribution layer.

[0061] Next, as shown in FIG. 8 , the second supporting substrate 120 is removed to expose the third re-distribution layer.

[0062] Then, as shown in FIG8 , a second metal bump 820 is formed on the third redistribution layer. The second metal bump 820 is electrically connected to the third redistribution layer.

[0063] In the heat-dissipating semiconductor package structure formed in this comparative example, the presence of the die bonding film 500 on the backside of the first chip 610 results in poor heat dissipation performance. Furthermore, because the first chip 610 is bonded to the first redistribution layer via the die bonding film 500, the thickness of the first chip 610 must be greater than 10 μm during the die bonding process to avoid the risk of breakage. Furthermore, the first chip 610 cannot be thinned during the fabrication process. Consequently, the size of this heat-dissipating semiconductor package structure is difficult to meet the requirements of miniaturized products.

[0064] Example

[0065] Referring to FIG9 , this embodiment provides a method for fabricating a heat-dissipating semiconductor package structure. FIG10 through FIG20 illustrate schematic diagrams of the various steps involved in fabricating the heat-dissipating semiconductor package structure. The following describes the fabrication of the heat-dissipating semiconductor package structure in conjunction with the accompanying drawings.

[0066] First, referring to FIG. 9 and FIG. 10 , step S1 is performed to provide a first supporting substrate 110 .

[0067] Specifically, the first supporting substrate 110 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the first supporting substrate 110. The size of the first supporting substrate 110 is not limited here, and is preferably wafer-level.

[0068] Among them, in order to facilitate the subsequent removal of the first supporting substrate 110, in this embodiment, a first separation layer 111 is preferably formed on the surface of the first supporting substrate 110. The first separation layer 111 includes but is not limited to a tape and a polymer layer. For example, the first separation layer 111 can be a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the first supporting substrate 110, thereby improving the convenience of the separation operation.

[0069] Next, referring to FIG. 9 , FIG. 11 and FIG. 12 , step S2 is performed to form a metal pillar 400 on the first supporting substrate 110 , wherein a first end of the metal pillar 400 is in contact with the first supporting substrate 110 .

[0070] Specifically, referring to Figures 11 and 12, in this embodiment, the metal pillar 400 is formed by electroplating, thereby forming a metal seed layer on the surface of the first separation layer 111 using a method such as physical vapor deposition (PVD), wherein the metal seed layer may include a first metal seed layer 201 and a second metal seed layer 202 located above the first metal seed layer 201. In this embodiment, the first metal seed layer 201 is a Ti layer, and the second metal seed layer 202 is a Cu layer, but the type of the metal seed layer is not limited thereto. For example, the metal seed layer may also be a Ti / Ag layer, a Ni / Ti layer, etc., and no excessive restrictions are imposed here. After forming the metal seed layer, a photoresist may be used to form the metal pillar 400 after photolithography and electroplating, and then the photoresist may be removed.

[0071] Next, referring to Figures 9 and 12, step S3 is performed to form a chip composite structure on the first supporting substrate 110, wherein the chip composite structure includes a first chip 610 and a first redistribution layer, wherein the back side of the first chip 610 is bonded to the chip adhesive film 500 and contacts the first supporting substrate 110, and the first redistribution layer is located on the front side of the first chip 610 and is electrically connected to the chip pad.

[0072] Specifically, the chip composite structure is bonded to the chip adhesive film 500 to adhere to the metal seed layer. The first redistribution layer in the chip composite structure includes a first metal wiring 311 and a first dielectric layer 312. The first metal wiring 311 is electrically connected to a first chip pad 611 located on the front surface of the first chip 610. The first dielectric layer 312 can be formed from a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide. The first metal wiring 311 can include aluminum, copper, tungsten, or alloys thereof. The specific structure and material selection of the first redistribution layer are not overly limited herein.

[0073] In order to facilitate the subsequent removal and thinning of the first chip 610 by a grinding process, the chip adhesive film 500 is preferably made of a harder adhesive film material, and the specific type can be selected according to needs.

[0074] Next, referring to Figures 9 and 13, step S4 is performed to form a first packaging layer 710, wherein the first packaging layer 710 includes a first surface and a second surface relative to each other, the first packaging layer 710 covers the metal pillar 400 and the chip composite structure, and the second surface of the first packaging layer 710 exposes the second end of the metal pillar 400 and the first rewiring layer.

[0075] Specifically, the method of forming the first encapsulation layer 710 may include but is not limited to compression molding, transfer molding and spin coating, and the material of the first encapsulation layer 710 may include but is not limited to epoxy resin and polyamide. There is no excessive restriction on the material and preparation method of the first encapsulation layer 710.

[0076] The formation of the first packaging layer 710 may include a grinding step to expose the second end of the metal pillar 400 and the first metal wiring 311. The first rewiring layer may protect the first chip 610 to avoid damage to the first chip 610 due to grinding.

[0077] Next, referring to FIG. 9 and FIG. 14 , step S5 is performed to form a second redistribution layer on the second surface of the first packaging layer 710 . The second redistribution layer is electrically connected to the metal pillars 400 and the first redistribution layer.

[0078] Specifically, the second redistribution layer includes a second metal wiring 321 and a second dielectric layer 322. The second metal wiring 321 is electrically connected to the second end of the metal pillar 400 and is electrically connected to the first metal wiring 311. The second dielectric layer 322 can be formed of a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide. The second metal wiring 321 can include aluminum, copper, tungsten, or alloys thereof. The specific structure and material selection of the second redistribution layer are not excessively limited herein.

[0079] Next, referring to FIG. 9 and FIG. 14 , step S6 is performed to provide a second supporting substrate 120 , and bond the second supporting substrate 120 to the second redistribution layer.

[0080] Specifically, the second supporting substrate 120 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the second supporting substrate 120. The size of the second supporting substrate 120 is not limited here.

[0081] Among them, in order to facilitate the subsequent removal of the second supporting substrate 120, in this embodiment, a second separation layer 121 is preferably formed on the surface of the second supporting substrate 120. The second separation layer 121 includes but is not limited to a tape and a polymer layer. For example, the second separation layer 121 can be a light-to-heat conversion layer formed by a light-to-heat conversion (LTHC) coating material, so that light / radiation (such as laser) can be used later to enable the LTHC coating material to decompose under heat to release the second supporting substrate 120, thereby improving the convenience of the separation operation.

[0082] Furthermore, a substrate adhesive film 122 is preferably formed on the surface of the second separation layer 121 to achieve a good bond between the second separation layer 121 and the second redistribution layer through the substrate adhesive film 122. The substrate adhesive film 122 may include, for example, PBO, polyimide, benzocyclobutene (BCB), or other applicable polymers. After the second supporting substrate 120 is subsequently separated, the substrate adhesive film 122 may be removed using a cleaning solution.

[0083] Next, referring to FIG. 9 , FIG. 15 and FIG. 16 , step S7 is performed to remove the first support substrate 110 to expose the first ends of the metal pillars 400 and the chip bonding film 500 .

[0084] Specifically, as shown in FIG. 15 , after removing the first support substrate 110 , the metal seed layer is removed to expose the chip bonding film 500 .

[0085] Next, referring to FIG. 9 and FIG. 17 , step S8 is performed to perform grinding to remove the chip adhesive film 500 .

[0086] Specifically, during polishing, the chip adhesive film 500, which has poor thermal conductivity, can be removed to facilitate heat dissipation from the first chip 610. Polishing can then be continued to thin the metal pillars 400 and the first chip 610, thereby reducing the package size. The polishing method can be chemical mechanical polishing (CMP), for example, and is not particularly limited herein.

[0087] As an example, the thickness of the first chip 610 after grinding may be less than 80 μm, such as 80 μm, 60 μm, 50 μm, etc., to meet consumers' demand for thin, light and short products.

[0088] Next, referring to Figures 9 and 18, step S9 is executed to perform grinding to form a third redistribution layer on the first surface of the first packaging layer 710. The third redistribution layer is electrically connected to the metal pillar 400, and the third redistribution layer also includes a virtual metal wiring 333 located on the back side of the first chip 610 and in contact with the back side of the first chip 610. The thermal rail A of the first chip 610 is formed through the virtual metal wiring 333.

[0089] Specifically, the third rewiring layer includes a third dielectric layer 332, a third metal wiring 331 and the virtual metal wiring 333. The third dielectric layer 332 can be formed by a polymer such as polybenzoxazole (PBO) and polyimide, or by an inorganic dielectric material such as silicon nitride and silicon oxide; the third metal wiring 331 is electrically connected to the first end of the metal pillar 400, and the third metal wiring 331 may include aluminum, copper, tungsten or alloys thereof.

[0090] The dummy metal wiring 333 is preferably fabricated simultaneously with the third metal wiring 331 in the third rewiring layer. This allows the thermal track A to be formed on the back side of the first chip 610 in contact with the back side of the first chip 610 without increasing the number of process steps, thereby facilitating heat dissipation of the first chip 610. Of course, the dummy metal wiring 333 can also be fabricated separately, and this is not an undue limitation.

[0091] It is preferred that the vertical projection of the dummy metal wiring 333 covers the heat source area of ​​the first chip 610 , so as to achieve good heat dissipation for the heat source area of ​​the first chip 610 .

[0092] There is no excessive restriction on the selection of specific structures and materials of the third dielectric layer 332 , the third metal wiring 331 and the dummy metal wiring 333 in the third rewiring layer.

[0093] Next, referring to FIG. 9 and FIG. 19 , step S10 is performed to form a second chip 620 on the third redistribution layer. The second chip 620 is electrically connected to the third redistribution layer.

[0094] The second chip pad 621 of the second chip 620 may be electrically connected to the third metal wiring 331 through a first metal bump 810 such as a solder ball bump, but the present invention is not limited thereto.

[0095] Next, referring to FIG. 9 and FIG. 19 , step S11 is performed to form a second encapsulation layer 720. The second encapsulation layer 720 covers the second chip 620 and the third redistribution layer to protect the second chip 620 and the third redistribution layer. Methods for forming the second encapsulation layer 720 may include, but are not limited to, compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 720 may include, but is not limited to, epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 720 are not particularly limited herein.

[0096] Next, referring to FIG. 9 and FIG. 20 , step S12 is performed to remove the second supporting substrate 120 to expose the second redistribution layer.

[0097] Next, referring to FIG. 9 and FIG. 20 , step S13 is performed to form second metal bumps 820 on the second redistribution layer. The second metal bumps 820 are electrically connected to the second metal wirings 321 in the second redistribution layer.

[0098] The second metal bumps 820 may include solder ball bumps, C4 metal bumps, copper pillar bumps, etc. The specific type and material of the metal bumps are not excessively limited here.

[0099] Referring to FIG. 20 , the present invention further provides a heat dissipation type semiconductor package structure, the heat dissipation type semiconductor package structure comprising:

[0100] A metal pillar 400 , wherein the metal pillar 400 includes a first end and a second end opposite to each other;

[0101] A chip composite structure, the chip composite structure including a first chip 610 and a first redistribution layer, wherein the first redistribution layer is located on the front surface of the first chip 610 and is electrically connected to the chip pad;

[0102] a first packaging layer 710, wherein the first packaging layer 710 includes a first surface and a second surface opposite to each other, wherein the first packaging layer 710 covers the metal pillar 400 and the chip composite structure, and the second surface of the first packaging layer 710 exposes the second end of the metal pillar 400 and the first redistribution layer;

[0103] a second redistribution layer, the second redistribution layer being located on the second surface of the first packaging layer 710 , and the second redistribution layer being electrically connected to the metal pillar 400 and the first redistribution layer;

[0104] a third redistribution layer, the third redistribution layer being located on the first surface of the first packaging layer 710, the third redistribution layer being electrically connected to the first end of the metal pillar 400, and the third redistribution layer further comprising a dummy metal wiring 333 located on and in contact with the back surface of the first chip 610, the thermal rail A of the first chip 610 being formed by the dummy metal wiring 333;

[0105] a second chip 620, the second chip 620 being located on the third redistribution layer, and the second chip 620 being electrically connected to the third redistribution layer;

[0106] a second packaging layer 720 , wherein the second packaging layer 720 covers the second chip 620 and the third re-distribution layer;

[0107] A metal bump is located on the second redistribution layer and is electrically connected to the second redistribution layer.

[0108] Specifically, the preparation method of the heat dissipation type semiconductor packaging structure can be prepared using the above steps, but is not limited to this. This embodiment directly uses the above preparation process to prepare the heat dissipation type semiconductor packaging structure, so the preparation, material and specific structure of the heat dissipation type semiconductor packaging structure can refer to the above steps and will not be repeated here.

[0109] As an example, the thickness of the first chip 610 may be less than 80 μm, such as 80 μm, 60 μm, 50 μm, etc., to meet consumers' demand for thin, light and compact products.

[0110] As an example, the dummy metal wiring 333 and the metal wiring in the third redistribution layer have the same material, so that the dummy metal wiring 333 and the metal wiring in the third redistribution layer can be prepared simultaneously to reduce the complexity of process control.

[0111] As an example, the dummy metal wiring 333 may include one or a combination of a capacitor and an inductor, so as to realize the functions of the capacitor and the inductor while also achieving good heat dissipation.

[0112] As an example, the vertical projection of the dummy metal wiring 333 covers the heat source area of ​​the first chip 610 , so as to achieve good heat dissipation for the heat source area of ​​the first chip 610 .

[0113] In summary, the heat-dissipating semiconductor packaging structure and preparation method of the present invention form virtual metal wiring with good thermal conductivity on the back side of the first chip while preparing the third rewiring layer to form a thermal track in contact with the first chip, thereby preparing a heat-dissipating semiconductor packaging structure with good thermal conductivity; while removing the chip adhesive film with poor thermal conductivity, the first chip is thinned, which can meet consumers' demand for light, thin and short products; further, the thermal track may also include capacitors and / or inductors formed while preparing the third rewiring layer, so as to achieve heat dissipation while realizing the functions of capacitance and inductance, thereby reducing costs and reducing package size.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A preparation method of a heat dissipation type semiconductor packaging structure, characterized in that, It includes the following steps: Provide a first support substrate; Form metal pillars on the first support substrate, with the first ends of the metal pillars in contact with the first support substrate; Form a chip composite structure on the first support substrate, the chip composite structure including a first chip and a first redistribution layer. Wherein, the back surface of the first chip is bonded to the first support substrate through a chip adhesive film, and the first redistribution layer is located on the front surface of the first chip and is electrically connected to chip pads; Form a first encapsulation layer, the first encapsulation layer including an opposite first surface and a second surface, the first encapsulation layer covering the metal pillars and the chip composite structure, and the second surface of the first encapsulation layer exposing the second ends of the metal pillars and the first redistribution layer; Form a second redistribution layer on the second surface of the first encapsulation layer, the second redistribution layer being electrically connected to both the metal pillars and the first redistribution layer; Provide a second support substrate and bond the second support substrate to the second redistribution layer; Remove the first support substrate to expose the first ends of the metal pillars and the chip adhesive film; Perform grinding to remove the chip adhesive film; Form a third redistribution layer on the first surface of the first encapsulation layer, the third redistribution layer being electrically connected to the metal pillars, and the third redistribution layer further including virtual metal wirings located on the back surface of the first chip and in contact with the back surface of the first chip. The virtual metal wirings constitute a heat conduction track of the first chip; Form a second chip on the third redistribution layer, the second chip being electrically connected to the third redistribution layer; Form a second encapsulation layer, the second encapsulation layer covering the second chip and the third redistribution layer; Remove the second support substrate to expose the second redistribution layer; Form metal bumps on the second redistribution layer, the metal bumps being electrically connected to the second redistribution layer.

2. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: After performing grinding to remove the chip adhesive film, it further includes continuing to perform grinding to thin the first chip.

3. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 2, wherein: The thickness of the ground first chip is 80 μm or less.

4. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings are prepared synchronously with the metal wirings in the third redistribution layer.

5. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 1, characterized in that: The vertical projection of the virtual metal wirings covers the heat source area of the first chip.

6. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings include one or a combination of a capacitor and an inductor.

7. A heat-dissipating semiconductor package structure, characterized in that, The heat dissipation type semiconductor package structure includes: Metal pillars, the metal pillars including opposite first ends and second ends; A chip composite structure, the chip composite structure including a first chip and a first redistribution layer, the first redistribution layer being located on the front surface of the first chip and being electrically connected to chip pads; A first encapsulation layer, the first encapsulation layer including an opposite first surface and a second surface, the first encapsulation layer covering the metal pillars and the chip composite structure, and the second surface of the first encapsulation layer exposing the second ends of the metal pillars and the first redistribution layer; A second redistribution layer, the second redistribution layer being located on the second surface of the first encapsulation layer, the second redistribution layer being electrically connected to both the metal pillars and the first redistribution layer; A third redistribution layer, which is located on a first surface of the first encapsulation layer, is electrically connected to a first end of the metal post, and the third redistribution layer further includes a virtual metal wiring located on and in contact with a back surface of the first chip, and a heat conduction track of the first chip is formed by the virtual metal wiring; A second chip, which is located on the third redistribution layer, is electrically connected to the third redistribution layer; A second encapsulation layer, which encapsulates the second chip and the third redistribution layer; Metal bumps, which are located on the second redistribution layer and are electrically connected to the second redistribution layer.

8. The heat dissipation type semiconductor package structure according to claim 7, wherein: The thickness of the first chip is 80 μm or less.

9. The heat dissipating semiconductor package structure according to claim 7, wherein: The virtual metal wiring has the same material as the metal wiring in the third redistribution layer; the virtual metal wiring includes one or a combination of a capacitor and an inductor.

10. The heat dissipating semiconductor package structure according to claim 7, wherein: A projection of the virtual metal wiring in a vertical direction covers a heat source area of the first chip.

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