Semiconductor integrated circuit device

Abstract

The present invention provides a layout structure of a capacitance cell using a CFET and a back-surface wiring. The capacitance cell is provided with nanosheet FETs (P1, P2, P3) and nanosheet FETs (N1, N2, N3) formed thereon. A power supply wiring (11) for supplying VDD extends in the X-direction in a back surface-side wiring layer, and overlaps the nanosheet FETs (P1, P2, P3) in a plan view. The power supply wiring (11) is connected to the sources of the nanosheet FETs (P1, P2, P3) via a via (31) which is provided at a position that overlaps in a plan view. A power supply wiring (12) for supplying VSS is connected to gate wirings (51a, 51b, 51c).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device having standard cells including CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Document 1 discloses a capacitance cell using a CFET.

[0005] Patent Document 2 discloses a standard cell that uses a CFET, and further provides wiring on the back surface directly below the transistor, to which the source / drain of the transistor is connected.

[0006] International Publication No. 2020 / 110733 U.S. Patent Application Publication No. 2022 / 0123023

[0007] However, up to now, no study has been made on the layout structure of a capacitance cell when wiring is provided on the back surface immediately below the transistor in a CFET.

[0008] The present disclosure aims to provide a layout structure of a capacitance cell when wiring is provided on the back surface immediately below a transistor in a CFET.

[0009] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes a standard cell that is a capacitance cell, and the standard cell includes a first nanosheet FET (Field Effect Transistor) of a first conductivity type that includes a first nanosheet extending in a first direction. a second nanosheet FET of a second conductivity type, the second nanosheet FET being formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a planar view; a gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a planar view, and surrounding the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed in a first wiring layer on the back side of the first nanosheet FET, extending in the first direction, overlapping the first nanosheet FET in a planar view, and supplying a first power supply voltage; and a second power supply wiring connected to the gate wiring and supplying a second power supply voltage, the first power supply wiring being connected to the source of the first nanosheet FET via a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a planar view.

[0010] According to this aspect, a standard cell, which is a capacitance cell, includes a first nanosheet FET and a second nanosheet FET formed thereon. A first power supply wiring that supplies a first power supply voltage extends in a first direction in a first wiring layer on the back side and overlaps the first nanosheet FET in a planar view. A second power supply wiring that supplies a second power supply voltage is connected to gate wiring that serves as the gates of the first and second nanosheet FETs. The first power supply wiring is connected to the source of the first nanosheet FET through a first via provided at a position where the first and second nanosheet FETs overlap in a planar view. This forms a capacitance in the first nanosheet FET via the gate oxide film. Therefore, a layout structure of a capacitance cell using a CFET and backside wiring is realized.

[0011] A semiconductor integrated circuit device according to a second aspect of the present disclosure includes a first standard cell that is a capacitance cell, and second and third standard cells that are arranged in the same cell row as the first standard cell and have a logic function, and the first standard cell is a first nanosheet FET (Field Effect Transistor) of a first conductivity type that includes a first nanosheet extending in a first direction. a second nanosheet FET of a second conductivity type, the second nanosheet FET being formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a plan view; a gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a plan view, and surrounding the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed in a first wiring layer on the back side of the first nanosheet FET, extending in the first direction, overlapping the first nanosheet FET in a plan view, and supplying a first power supply voltage; and a second power supply wiring connected to the gate wiring and supplying a second power supply voltage, the first power supply wiring being connected to the first power supply wiring and the first nanosheet The second standard cell is connected to the source of the first nanosheet FET via a first via provided at a position overlapping the first nanosheet FET in a planar view, the second standard cell is formed at the same position in the depth direction as the first nanosheet FET and comprises a third nanosheet FET of the first conductivity type including a third nanosheet extending in the first direction, the third standard cell is formed at the same position in the depth direction as the first nanosheet FET and comprises a fourth nanosheet FET of the first conductivity type including a fourth nanosheet extending in the first direction, the third nanosheet has the same size in the second direction as the first nanosheet and has the same arrangement range in the second direction as the first nanosheet, and the size in the second direction of the fourth nanosheet is smaller than that of the first nanosheet.

[0012] According to this configuration, the third nanosheet FET included in the second standard cell and the fourth nanosheet FET included in the third standard cell are formed at the same position in the depth direction as the first nanosheet FET included in the first standard cell, which is a capacitive cell. The third nanosheet included in the third nanosheet FET has the same size and arrangement range in the second direction as the first nanosheet included in the first nanosheet FET. The fourth nanosheet included in the fourth nanosheet FET has a smaller size in the second direction than the first nanosheet. Therefore, the distance to the active region adjacent to the first direction of the active region of the first and second standard cells is determined. This allows for improved performance estimation accuracy.

[0013] According to the present disclosure, it is possible to provide a layout structure of a capacitance cell in a case where wiring is provided on the back surface immediately below a transistor in a CFET.

[0014] 1A and 1B are plan views showing an example of a layout structure of a capacitance cell according to the first embodiment; (a), (b), and (c) are cross-sectional views of the layout structure of FIG. 1; (a) and (b) are cross-sectional views of the layout structure of FIG. 1; (c) and (d) are cross-sectional views of the layout structure of FIG. 1; (a) and (b) are cross-sectional views of the layout structure of FIG. 1; (a) and (b) are cross-sectional views of the layout structure of FIG. 6 ... 10A and 10B are plan views showing an example of the layout structure of an inverter cell, where (a) and (b) are cell 1, and (c) and (d) are cell 2; (a) and (b) are plan views showing an example of the layout structure of a capacitance cell according to the second embodiment; (a) and (b) are plan views showing an example of the layout structure of an inverter cell, where (a) and (b) are cell 1, and (c) and (d) are cell 2; (a) and (b) are plan views showing an example of the layout structure of a capacitance cell according to a first modification of the second embodiment; (a) and (b) are plan views showing an example of the layout structure of a capacitance cell according to a second modification of the second embodiment;

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells), and at least some of the plurality of standard cells include CFETs, i.e., three-dimensional devices in which three-dimensional P-type FETs and N-type FETs are stacked vertically relative to a substrate. In this embodiment, the CFETs include nanosheet FETs.

[0016] In the plan views and cross-sectional views of the following embodiments, the description of each insulating film, etc. may be omitted. Furthermore, in this specification, expressions such as "same size" that mean that the size, etc., is the same are assumed to include the range of manufacturing variations.

[0017] In the following embodiments, "VDD" and "VSS" are used to indicate a power supply voltage or the power supply itself.

[0018] (First Embodiment) FIGS. 1 and 2 are diagrams showing an example of the layout structure of a capacitance cell according to the first embodiment, with FIGS. 1(a) and 1(b) being plan views, FIG. 2(a) being a cross-sectional view in a horizontal plane view, and FIGS. 2(b) and 2(c) being cross-sectional views in a vertical plane view. The capacitance cell shown in FIGS. 1 and 2 includes a CFET. FIG. 1(a) shows the lower portion, i.e., a P-type nanosheet FET formed on the side closer to the substrate, and a portion including the BM0 wiring layer, which is the wiring layer on the back side of the P-type nanosheet FET. FIG. 1(b) shows the upper portion, i.e., a N-type nanosheet FET formed on the side farther from the substrate, and a portion including the M0 wiring layer, which is the wiring layer on the front side of the N-type nanosheet FET. FIG. 2(a) is a cross-section along line X1-X1', FIG. 2(b) is a cross-section along line Y1-Y1', and FIG. 2(c) is a cross-section along line Y2-Y2'. Here, the surface side of the nanosheet FET refers to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are stacked. The back side of the nanosheet FET refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are laminated.

[0019] In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). The dotted lines running vertically and horizontally in plan views such as FIG. 1 and the dotted lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also differ for each layer. Furthermore, components do not necessarily need to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange components on a grid.

[0020] 3 is a circuit diagram of the capacitance cell shown in FIGS. 1 and 2. As shown in FIG. 3, the cell shown in FIGS. 1 and 2 has P-type transistors P1, P2, and P3 and N-type transistors N1, N2, and N3. The gates of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are commonly connected to VSS. The sources and drains of the P-type transistors P1, P2, and P3 are connected to VDD. The sources and drains of the N-type transistors N1, N2, and N3 are floating.

[0021] In the P-type transistors P1, P2, and P3, capacitance is formed via the gate oxide film between the gate connected to VSS and the source and drain connected to VDD. The N-type transistors N1, N2, and N3 are in the off state and serve as dummy transistors.

[0022] As shown in FIG. 1A, a power supply wiring 11 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 11 supplies VDD. The power supply wiring 11 is located in the center of the capacitance cell in the Y direction in a plan view. Furthermore, in the BM0 wiring layer, a wiring 15a extending in the X direction is formed above the power supply wiring 11 in the drawing, and a wiring 15b extending in the X direction is formed below the power supply wiring 11 in the drawing. The wirings 15a and 15b are dummy wirings in a floating state. It is not necessary to form the wirings 15a and 15b.

[0023] An active region 2P is formed above the power supply wiring 11, constituting the channel, source, and drain of the P-type nanosheet FET that becomes the P-type transistors P1, P2, and P3. The active region 2P overlaps with the power supply wiring 11 in a planar view. The active region 2P includes nanosheets 21a, 21b, and 21c that become the channel of the P-type nanosheet FET. In addition, portions 22a, 22b, 22c, and 22d of the active region 2P that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 11 via vias 31 formed on the back surface thereof. The vias 31 overlap with the power supply wiring 11 and the active region 2P in a planar view. Local wirings 41a, 41b, 41c, and 41d extending in the Y direction are formed. The local wirings 41a, 41b, 41c, and 41d are in contact with portions 22a, 22b, 22c, and 22d in the active region 2P, respectively.

[0024] As shown in FIG. 1B, a power supply wiring 12 extending in the X direction is formed in the M0 wiring layer. The power supply wiring 12 supplies VSS. The power supply wiring 12 is located in the center of the capacitance cell in the Y direction in a plan view, and overlaps the power supply wiring 11 in a plan view. Note that while FIG. 1 depicts the power supply wirings 11 and 12 as having the same wiring width, the power supply wirings 11 and 12 do not have to have the same wiring width. Also, in the M0 wiring layer, a wiring 16a extending in the X direction is formed above the power supply wiring 12 in the drawing, and a wiring 16b extending in the X direction is formed below the power supply wiring 12 in the drawing. The wirings 16a and 16b are dummy wirings in a floating state. Note that the wirings 16a and 16b do not necessarily have to be formed.

[0025] An active region 2N that constitutes the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistors N1, N2, and N3 is formed below the power supply wiring 12. The active region 2N overlaps with the power supply wiring 12 in a planar view. The active region 2N also overlaps with the active region 2P in a planar view. The active region 2N includes nanosheets 26a, 26b, and 26c that become the channel of the N-type nanosheet FET. The nanosheets 26a, 26b, and 26c of the N-type nanosheet FET overlap with the nanosheets 21a, 21b, and 21c of the P-type nanosheet FET, respectively, in a planar view.

[0026] The size of the active areas 2P and 2N in the Y direction is w1.

[0027] Local wirings 42a, 42b, 42c, and 42d are formed extending in the Y direction. The local wirings 42a, 42b, 42c, and 42d are in contact with portions 27a, 27b, 27c, and 27d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively.

[0028] The gate wirings 51a, 51b, and 51c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wiring 51a surrounds the outer peripheries of the nanosheets 21a and 26a in the Y and Z directions via a gate insulating film (not shown). The gate wiring 51a serves as the gates of the transistors P1 and N1. The gate wiring 51b surrounds the outer peripheries of the nanosheets 21b and 26b in the Y and Z directions via a gate insulating film (not shown). The gate wiring 51b serves as the gates of the transistors P2 and N2. The gate wiring 51c surrounds the outer peripheries of the nanosheets 21c and 26c in the Y and Z directions via a gate insulating film (not shown). The gate wiring 51c serves as the gates of the transistors P3 and N3.

[0029] The gate wirings 51 a, 51 b, and 51 c are connected to the power supply wiring 12 through vias 32 formed on their surfaces. The vias 32 overlap the power supply wiring 12 and the active region 2N in plan view, and are formed at the end in the Y direction of the region where the power supply wiring 12 and the nanosheets 26 a, 26 b, and 26 c overlap, i.e., at the position closest to the end.

[0030] In the capacitor cell according to this embodiment, VDD is supplied to the portions 22a, 22b, 22c, and 22d that serve as the source or drain of the P-type transistors P1, P2, and P3 from the power supply wiring 11 formed in the BM0 wiring layer through vias 31 that overlap the power supply wiring 11 and the active region 2P in a planar view. Therefore, the path length from the power supply wiring 11 to the portions 22a, 22b, 22c, and 22d is short. This reduces the resistance value from the power supply wiring 11 to the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitors that are configured.

[0031] Furthermore, in the capacitance cell according to this embodiment, gate wirings 51a, 51b, and 51c, which serve as the gates of P-type transistors P1, P2, and P3, are supplied with VSS from power supply wiring 12 formed in the M0 wiring layer through vias 32. The vias 32 are formed at the Y-direction ends of the regions where the power supply wiring 12 and the nanosheets 26a, 26b, and 26c overlap in plan view. This makes it possible to suppress the resistance value from the power supply wiring 12 to the gates surrounding the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitances that are formed.

[0032] 4 is a plan view showing an example of the layout structure of the inverter cell according to this embodiment, where (a) is the lower part of inverter cell 1, (b) is the upper part of inverter cell 1, (c) is the lower part of inverter cell 2, and (d) is the upper part of inverter cell 2. The inverter cell is an example of a logic cell.

[0033] Inverter cells 1 and 2 each include a P-type transistor P11 and an N-type transistor N11, and form an inverter circuit having an input A and an output Y. The P-type transistor P11 is formed in the lower part, and the N-type transistor N11 is formed in the upper part. Inverter cells 1 and 2 have almost the same layout structure. However, the active regions 2P1 and 2N1 of inverter cell 1 and the active regions 2P2 and 2N2 of inverter cell 2 differ in size and position in the Y direction.

[0034] 4A and 4C, a power supply wiring 11 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 11 supplies VDD. The power supply wiring 11 is located at the center of the inverter cells 1 and 2 in the Y direction in a plan view.

[0035] Active regions 2P1 and 2P2 that constitute the channel, source, and drain of a P-type nanosheet FET that becomes a P-type transistor P11 are formed above the power supply wiring 11. The active regions 2P1 and 2P2 overlap the power supply wiring 11 in a planar view. The active regions 2P1 and 2P2 include a nanosheet 121 that becomes the channel of the P-type nanosheet FET, and portions 122 and 123 that become the source or drain of the P-type nanosheet FET. The portion 122 is connected to the power supply wiring 11 through a via 161 formed on its back surface.

[0036] Local wirings 141 and 142 are formed extending in the Y direction. The local wirings 141 and 142 are in contact with portions 122 and 123 in the active regions 2P1 and 2P2, respectively.

[0037] 4B and 4D, a power supply wiring 12 extending in the X direction is formed in the M0 wiring layer. The power supply wiring 12 supplies VSS. The power supply wiring 12 is located in the center of the inverter cells 1 and 2 in the Y direction in a plan view. Also, in the M0 wiring layer, a wiring 113 extending in the X direction is formed above the power supply wiring 12 in the drawing, and a wiring 114 extending in the X direction is formed below the power supply wiring 12 in the drawing. The wiring 113 corresponds to the output Y, and the wiring 114 corresponds to the input A.

[0038] Active regions 2N1 and 2N2 that constitute the channel, source, and drain of an N-type nanosheet FET that becomes the N-type transistor N11 are formed below the power supply wiring 12. The active regions 2N1 and 2N2 overlap with the power supply wiring 12 in a planar view. The active regions 2N1 and 2N2 include a nanosheet 124 that becomes the channel of the N-type nanosheet FET, and portions 125 and 126 that become the source or drain of the N-type nanosheet FET.

[0039] Local wirings 143 and 144 are formed extending in the Y direction. The local wirings 143 and 144 are in contact with portions 125 and 126 in the active regions 2N1 and 2N2, respectively. The local wiring 143 is connected to the power supply wiring 12 through a via 162. The local wiring 144 is connected to the local wiring 142 through a via 163, and is also connected to the wiring 113 through a via 164.

[0040] The gate wiring 151 extends in the Y direction and also extends in the Z direction from top to bottom. The gate wiring 151 surrounds the outer peripheries of the nanosheets 121 and 124 in the Y and Z directions via a gate insulating film (not shown). The gate wiring 151 serves as the gates of the transistors P11 and N11. The gate wiring 151 is connected to the wiring 114 via a via 165.

[0041] In inverter cell 1, the size in the Y direction of active regions 2P1 and 2N1 is w1. In inverter cell 2, the size in the Y direction of active regions 2P1 and 2N1 is w2, which is smaller than w1 (w1 > w2). Therefore, the drive capability of inverter cell 1 is greater than the drive capability of inverter cell 2. Furthermore, in inverter cells 1 and 2, the positions of the top ends of active regions 2P1 and 2N1 in the Y direction on the drawing are aligned.

[0042] On the other hand, as described above, in the capacitance cell according to this embodiment, the size in the Y direction of the active regions 2P and 2N is w1, which is the same as the size in the Y direction of the active regions 2P1 and 2N1 of the inverter cell 1. Furthermore, in the capacitance cell according to this embodiment, the layout range in the Y direction of the active regions 2P and 2N is also the same as the layout range in the Y direction of the active regions 2P1 and 2N1 of the inverter cell 1.

[0043] That is, the nanosheets 121 and 124 of the inverter cell 1 have the same size in the Y direction as the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells, and also have the same arrangement range in the Y direction. The nanosheets 121 and 124 of the inverter cell 2 are smaller in size in the Y direction than the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells. The nanosheets 121 and 124 of the inverter cells 1 and 2 and the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells have the same top end in the Y direction in the drawing.

[0044] 5A and 5B are plan views showing an example layout of a circuit block, with (a) showing the lower part and (b) showing the upper part. In the layout of Fig. 5, a capacitance cell C1 according to this embodiment is placed in the center, with inverter cells C2 and C3 placed on either side. The inverter cell C2 on the left side of the capacitance cell in the drawing is the inverter cell 1 shown in Figs. 4A and 4B, and the inverter cell C3 on the right side of the capacitance cell in the drawing is the inverter cell 2 shown in Figs. 4C and 4D.

[0045] 5, the size in the Y direction of the active regions 2P and 2N of the capacitance cell C1 and the active regions 2P1 and 2N1 of the inverter cell C2 are the same (w1), and the size in the Y direction of the active regions 2P2 and 2N2 of the inverter cell C3 (w2) is smaller than the size in the Y direction of the active regions 2P and 2N of the capacitance cell C1. In the capacitance cell C1 and the inverter cells C2 and C3, the positions of the top ends of the active regions 2P, 2P1, 2P2, 2N, 2N1, and 2N2 in the Y direction are aligned.

[0046] Therefore, the active regions 2P1 and 2N1 of the inverter cell C2 are located across the entire Y-direction from the active regions 2P and 2N of the adjacent capacitor cell C1. Similarly, the active regions 2P2 and 2N2 of the inverter cell C3 are located across the entire Y-direction from the active regions 2P and 2N of the adjacent capacitor cell C1. That is, the distances to the adjacent active regions in the X-direction are determined for the active regions 2P1, 2N1, 2P2, and 2N2 of the inverter cells C2 and C3. This allows for improved accuracy in estimating the performance of the inverter cells 1 and 2.

[0047] 6A and 6B are plan views showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Fig. 7 is a cross-sectional view showing the cross section taken along line Y1-Y1' in Fig. 6.

[0048] Fig. 8 is a circuit diagram of the capacitance cell shown in Fig. 6 and Fig. 7. The circuit diagram of Fig. 8 is almost the same as Fig. 3, but the sources and drains of N-type transistors N1, N2, and N3 are not in a floating state but are connected to VSS.

[0049] The layout structure according to this modification has basically the same configuration as the layout structure according to the first embodiment, except that vias are added in the range A indicated by the dashed line in FIG.

[0050] That is, the local wirings 42a, 42b, 42c, and 42d are connected to the power supply wiring 12 through the vias 33. Furthermore, the wiring 16b is connected to the local wirings 42a, 42b, 42c, and 42d through the vias 34, and is also connected to the gate wirings 51a, 51b, and 51c through the vias 35.

[0051] According to this modification, capacitance is also formed between the local wirings 42a, 42b, 42c, and 42d at the upper portion and the portions 27a, 27b, 27c, and 27d in the active region 2N and the local wirings 41a, 41b, 41c, and 41d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0052] Furthermore, VSS is also supplied to the gate wirings 51a, 51b, and 51c from the wiring 16b, thereby suppressing the resistance value from the power supply wiring 12 to the gates surrounding the nanosheets 21a, 21b, and 21c.

[0053] (Modification 2) FIGS. 9A and 9B are plan views showing an example of a layout structure of a capacitor cell according to Modification 2 of this embodiment, where (a) shows the lower part and (b) shows the upper part.

[0054] 10 is a circuit diagram of the capacitance cell shown in FIG. 9. The circuit diagram in FIG. 10 is almost the same as that in FIG. 8, but the gates of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are connected to VDD instead of VSS. That is, in this modification, the N-type transistors N1, N2, and N3 form a capacitance. The P-type transistors P1, P2, and P3 are in the off state and serve as dummy transistors.

[0055] 9 , the local wirings 41a, 41b, 41c, and 41d at the bottom are connected to the M0 wiring 16b at the top via the via 36. The M0 wiring 16b is connected to the gate wirings 51a, 51b, and 51c via the via 37. As a result, VDD is supplied to the gate wirings 51a, 51b, and 51c from the power supply wiring 11 of the B-M0 layer via the via 31, the active region 2P, the local wirings 41a, 41b, 41c, and 41d, the via 36, ​​the M0 wiring 16b, and the via 37.

[0056] (Variant 3) Figure 11 is a plan view showing an example of the layout structure of an inverter cell according to this variant, where (a) is the lower part of inverter cell 1, (b) is the upper part of inverter cell 1, (c) is the lower part of inverter cell 2, and (d) is the upper part of inverter cell 2.

[0057] The layout structure shown in Fig. 11 is almost the same as the layout structure shown in Fig. 4. However, the centers of the active regions 2P2 and 2N2 of the inverter cell 2 in the Y direction are aligned with the active regions 2P1 and 2N1 of the inverter cell 1.

[0058] In this modification, when the capacitance cell according to this embodiment is arranged adjacent to the inverter cells 1 and 2, the active regions 2P and 2N of the adjacent capacitance cells are present over the entire range in the Y direction of the active regions 2P1, 2N1, 2P2, and 2N2 of the inverter cells 1 and 2. In other words, the distances to the adjacent active regions in the X direction are determined for the active regions 2P1, 2N1, 2P2, and 2N2 of the inverter cells 1 and 2. This improves the accuracy of estimating the performance of the inverter cells 1 and 2.

[0059] It should be noted that the same effect can be obtained not only in this modified example but also as long as the active regions 2P2 and 2N2 of the inverter cell 2 are present within the range of the active regions 2P1 and 2N1 of the inverter cell 1 in the Y direction.

[0060] Second Embodiment Figure 12 is a plan view showing an example of a layout structure of a capacitance cell according to a second embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit diagram of the capacitance cell shown in Figure 12 is the same as that shown in Figure 3. That is, P-type transistors P1, P2, and P3 form a capacitance.

[0061] 12A, power supply wirings 61 and 62 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 61 supplies VDD. The power supply wiring 62 supplies VSS. The power supply wiring 61 is arranged above the capacitance cell in the drawing, and the power supply wiring 62 is arranged below the capacitance cell in the drawing.

[0062] An active region 2P that constitutes the channel, source, and drain of the P-type nanosheet FET that becomes the P-type transistors P1, P2, and P3 is formed above the power supply wiring 61 and 62. The active region 2P overlaps the power supply wiring 61 and 62 in a planar view. The active region 2P includes nanosheets 21a, 21b, and 21c that become the channel of the P-type nanosheet FET. In addition, portions 22a, 22b, 22c, and 22d of the active region 2P that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 61 via vias 71 formed on the back surface thereof.

[0063] The size of the active areas 2P and 2N in the Y direction is w1.

[0064] Local wirings 81a, 81b, 81c, and 81d are formed extending in the Y direction. The local wirings 81a, 81b, 81c, and 81d are in contact with the portions 22a, 22b, 22c, and 22d in the active region 2P, respectively.

[0065] 12(b), an active region 2N is formed that constitutes the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistors N1, N2, and N3. The active region 2N overlaps with the active region 2P in plan view. The active region 2N includes nanosheets 26a, 26b, and 26c that become the channel of the N-type nanosheet FET.

[0066] In the M0 wiring layer, a wiring 65 extending in the X direction is formed. The wiring 65 is disposed below the active region 2N in the drawing. The wiring 65 is connected to the power supply wiring 62 through a via 72.

[0067] Local wirings 82a, 82b, 82c, and 82d are formed extending in the Y direction. The local wirings 82a, 82b, 82c, and 82d are in contact with portions 27a, 27b, 27c, and 27d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively.

[0068] The gate wirings 91a, 91b, and 91c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wiring 91a surrounds the outer peripheries of the nanosheets 21a and 26a in the Y and Z directions via a gate insulating film (not shown). The gate wiring 91a serves as the gates of the transistors P1 and N1. The gate wiring 91b surrounds the outer peripheries of the nanosheets 21b and 26b in the Y and Z directions via a gate insulating film (not shown). The gate wiring 91b serves as the gates of the transistors P2 and N2. The gate wiring 91c surrounds the outer peripheries of the nanosheets 21c and 26c in the Y and Z directions via a gate insulating film (not shown). The gate wiring 91c serves as the gates of the transistors P3 and N3.

[0069] The gate wirings 91a, 91b, and 91c are connected to the M0 wiring 65 through vias 73 formed on the surfaces thereof.

[0070] In the capacitance cell of this embodiment, the gate wirings 91a, 91b, and 91c that serve as the gates of the P-type transistors P1, P2, and P3 are supplied with VSS from the power supply wiring 62 formed in the BM0 wiring layer via via 72, M0 wiring 65, and via 73.

[0071] Furthermore, in the capacitance cell according to this embodiment, VDD is supplied to the portions 22a, 22b, 22c, and 22d that serve as the source and drain of the P-type transistors P1, P2, and P3 from a power supply wiring 61 formed in the BM0 wiring layer through a via 71 that overlaps the power supply wiring 61 and the active region 2P in a planar view. Therefore, the path length from the power supply wiring 61 to the portions 22a, 22b, 22c, and 22d is short. This reduces the resistance value from the power supply wiring 61 to the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is configured.

[0072] Figure 13 is a plan view showing an example of the layout structure of an inverter cell according to this embodiment, where (a) is the lower part of inverter cell 1, (b) is the upper part of inverter cell 1, (c) is the lower part of inverter cell 2, and (d) is the upper part of inverter cell 2.

[0073] Inverter cells 1 and 2 each include a P-type transistor P11 and an N-type transistor N11, and form an inverter circuit having an input A and an output Y. The P-type transistor P11 is formed in the lower part, and the N-type transistor N11 is formed in the upper part. Inverter cells 1 and 2 have almost the same layout structure. However, the active regions 2P4 and 2N4 of inverter cell 1 and the active regions 2P5 and 2N5 of inverter cell 2 differ in size and position in the Y direction.

[0074] 13A and 13C, power supply wiring 61 and 62 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 61 supplies VDD. The power supply wiring 62 supplies VSS. The power supply wiring 61 is arranged above the inverter cells 1 and 2 in the drawing, and the power supply wiring 62 is arranged below the inverter cells 1 and 2 in the drawing.

[0075] Active regions 2P4 and 2P5 that form the channel, source, and drain of a P-type nanosheet FET that becomes a P-type transistor P11 are formed above the power supply wiring 61 and 62. The active regions 2P4 and 2P5 overlap the power supply wiring 61 and 62 in plan view. The active regions 2P4 and 2P5 include a nanosheet 221 that becomes the channel of the P-type nanosheet FET, and portions 222 and 223 that become the source or drain of the P-type nanosheet FET. The portion 222 is connected to the power supply wiring 61 through a via 261 formed on its back surface.

[0076] Local wirings 241 and 242 are formed extending in the Y direction. The local wirings 241 and 242 are in contact with portions 222 and 223 in the active regions 2P4 and 2P5, respectively.

[0077] As shown in Figures 13(b) and 13(d), active regions 2N4 and 2N5 are formed, which constitute the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistor N11. The active regions 2N4 and 2N5 overlap with the power supply wiring 61 and 62 in a planar view. The active regions 2N4 and 2N5 include a nanosheet 224 that becomes the channel of the N-type nanosheet FET, and portions 225 and 226 that become the source or drain of the N-type nanosheet FET. In the M0 wiring layer, wirings 213 and 214 extending in the X direction are formed. The wiring 213 corresponds to the output Y, and the wiring 214 corresponds to the input A.

[0078] Local wirings 243 and 244 are formed extending in the Y direction. The local wirings 243 and 244 are in contact with portions 225 and 226 in the active regions 2N4 and 2N5, respectively. The local wiring 243 is connected to the power supply wiring 62 via a via 262. The local wiring 244 is connected to the local wiring 242 via a via 263, and is also connected to the wiring 213 via a via 264.

[0079] The gate wiring 251 extends in the Y direction and also extends in the Z direction from top to bottom. The gate wiring 251 surrounds the outer peripheries of the nanosheets 221 and 224 in the Y and Z directions via a gate insulating film (not shown). The gate wiring 251 serves as the gates of the transistors P11 and N11. The gate wiring 251 is connected to the wiring 214 via a via 265.

[0080] In inverter cell 1, the size in the Y direction of active regions 2P4 and 2N4 is w1. In inverter cell 2, the size in the Y direction of active regions 2P5 and 2N5 is w2, which is smaller than w1 (w1 > w2). Therefore, the drive capability of inverter cell 1 is greater than the drive capability of inverter cell 2. Furthermore, in inverter cells 1 and 2, the positions of the top ends of active regions 2P4, 2N4, 2P5, and 2N5 in the Y direction on the drawing are aligned.

[0081] On the other hand, as described above, in the capacitance cell according to this embodiment, the size in the Y direction of the active regions 2P, 2N is w1, which is the same as the size in the Y direction of the active regions 2P4, 2N4 of the inverter cell 1. Furthermore, in the capacitance cell according to this embodiment, the layout range in the Y direction of the active regions 2P, 2N is also the same as the layout range in the Y direction of the active regions 2P4, 2N4 of the inverter cell 1.

[0082] That is, the nanosheets 221 and 224 of the inverter cell 1 have the same size in the Y direction as the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells, and also have the same arrangement range in the Y direction. The nanosheets 221 and 224 of the inverter cell 2 are smaller in size in the Y direction than the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells. The nanosheets 221 and 224 of the inverter cells 1 and 2 and the nanosheets 21a, 21b, 21c, 26a, 26b, and 26c in the capacitor cells have the same top end in the Y direction in the drawing.

[0083] Therefore, when the capacitance cell according to this embodiment is placed adjacent to the inverter cells 1 and 2, the active regions 2P and 2N of the adjacent capacitance cells are present over the entire range in the Y direction of the active regions 2P4, 2N4, 2P5, and 2N5 of the inverter cells 1 and 2. In other words, the distances to the adjacent active regions in the X direction are determined for the active regions 2P4, 2N4, 2P5, and 2N5 of the inverter cells 1 and 2. This improves the accuracy of estimating the performance of the inverter cells 1 and 2.

[0084] Furthermore, the positions of the top ends of the active regions in the Y direction of the drawing are aligned for the capacitor cells and inverter cells 1 and 2. This configuration allows the active region constituting the P-type nanosheet FET to be positioned closer to the power supply wiring 61 that supplies VDD, which is located at the top of the drawing. This reduces the resistance in the power supply, thereby suppressing power supply voltage drops.

[0085] 14A and 14B are plan views showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit diagram of the capacitance cell shown in FIG. 14 is the same as that in FIG. 8.

[0086] The layout structure according to this modification has basically the same configuration as the layout structure according to the second embodiment. However, as shown in FIG. 14B , in the upper part, local wirings 82a, 82b, 82c, and 82d extend to positions where they overlap with the M0 wiring 65 in a plan view. The local wirings 82a, 82b, 82c, and 82d are connected to the power supply wiring 62 formed in the B-M0 wiring layer through vias 74. The local wirings 82a, 82b, 82c, and 82d are also connected to the M0 wiring 65 through vias 75.

[0087] That is, in this modified example, VSS is supplied from the power supply wiring 62 to the portions 27a, 27b, 27c, and 27d that become the source or drain of the N-type nanosheet FET in the active region 2N via the via 74 and the local wiring 82a, 82b, 82c, and 82d.

[0088] According to this modification, capacitance is also formed between the local wirings 82a, 82b, 82c, and 82d at the upper portion and the portions 27a, 27b, 27c, and 27d in the active region 2N and the local wirings 81a, 81b, 81c, and 81d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0089] 15A and 15B are plan views showing an example of a layout structure of a capacitance cell according to Modification 2 of this embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit diagram of the capacitance cell shown in Fig. 15 is the same as that shown in Fig. 10. That is, N-type transistors N1, N2, and N3 form a capacitance.

[0090] 15B, in the M0 wiring layer, a wiring 66 extending in the X direction is formed above the active region 2N in the drawing. The wiring 66 is connected to the power supply wiring 61 in the BM0 wiring layer through a via 76. The wiring 66 is also connected to the gate wirings 91a, 91b, and 91c through a via 77. As a result, VDD is supplied from the power supply wiring 61 to the gate wirings 91a, 91b, and 91c.

[0091] In addition, the local wirings 82a, 82b, 82c, and 82d at the top are connected to the power supply wiring 62 in the BM0 wiring layer through the vias 78. As a result, VSS is supplied from the power supply wiring 62 to the portions 27a, 27b, 27c, and 27d that become the source or drain of the N-type nanosheet FET in the active region 2N.

[0092] In the above-described embodiment, a P-type conductivity transistor is formed in the lower portion of the CFET, and an N-type conductivity transistor is formed in the upper portion thereof, but the conductivity types of the formed transistors may be reversed. That is, an N-type conductivity transistor may be formed in the lower portion, and a P-type conductivity transistor may be formed in the upper portion.

[0093] In the above-described embodiments, the lower and upper active regions of the capacitor cells and inverter cells have been described as being identical in size and position in the Y direction. However, this is not limiting, and the lower and upper active regions may be different in size and position in the Y direction. In this case, it is sufficient that the upper and lower active regions have the same size and position relationship as in the above-described embodiments.

[0094] Furthermore, in the above embodiment, an inverter cell has been used as an example of a logic cell, but other logic cells, such as a NAND cell, a NOR cell, or a flip-flop cell, may also be used.

[0095] In the above embodiment, the active areas of the logic cells have two sizes in the Y direction, w1 and w2, but three or more sizes may be used. In this case, the size and layout position of the active areas of the capacitance cells in the Y direction may be set to match the active area of ​​the largest size, for example.

[0096] In the above-described embodiment, the nanosheet FET has three overlapping sheets in a plan view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheets of the nanosheet FET are not limited to this. In addition, the number and cross-sectional shape of the nanosheets may be different between the lower and upper parts of the CFET.

[0097] The present disclosure can provide a layout structure for a capacitance cell using a CFET and backside wiring, which is useful for improving the performance of a semiconductor chip, for example.

[0098] 11, 12 Power supply wiring 16b Wiring 21a, 21b, 21c Nanosheets 26a, 26b, 26c Nanosheets 31, 32 Vias 42a, 42b, 42c, 42d Local wiring 51a, 51b, 51c Gate wiring 61, 62 Power supply wiring 65 Wiring 72, 74 Vias 91a, 91b, 91c Gate wiring 121, 124 Nanosheets 221, 224 Nanosheets P1, P2, P3, P11 Nanosheet FET N1, N2, N3, N11 Nanosheet FET 2P, 2N Active areas 2P1, 2P2, 2P4, 2P5, 2N1, 2N2, 2N4, 2N5 Active areas C1 Capacitor cell C2, C3 Inverter cell

Claims

1. A semiconductor integrated circuit device including a standard cell which is a capacitive cell, wherein the standard cell includes a first nanosheet FET (Field Effect Transistor) of a first conductivity type including a first nanosheet extending in a first direction, a second nanosheet FET of a second conductivity type formed above the first nanosheet FET in a depth direction, including a second nanosheet extending in the first direction and overlapping the first nanosheet in a plan view, a gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a plan view, and surrounding the peripheries of the first and second nanosheets in the second direction and the depth direction, a first power supply wiring formed in a first wiring layer on the back side of the first nanosheet FET, extending in the first direction, overlapping the first nanosheet FET in a plan view, and supplying a first power supply voltage, and a second power supply wiring connected to the gate wiring and supplying a second power supply voltage, and the first power supply wiring is connected to the source of the first nanosheet FET through a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a plan view.

2. The semiconductor integrated circuit device according to claim 1, wherein the second power supply wiring is formed in a second wiring layer on the front side of the second nanosheet FET, extends in the first direction, and overlaps the second nanosheet FET in a plan view.

3. The semiconductor integrated circuit device according to claim 2, wherein the second power supply wiring is connected to the gate wiring through a second via provided at a position overlapping the second power supply wiring and the second nanosheet FET in a plan view.

4. The semiconductor integrated circuit device according to claim 3, wherein the second via is arranged at an end in the second direction of a region where the second power supply wiring and the second nanosheet overlap in a plan view.

5. In the semiconductor integrated circuit device according to claim 3, the standard cell includes a first local wiring connected to the source of the second nanosheet FET and extending in the second direction, and the second power supply wiring is connected to the first local wiring via a third via provided at a position overlapping the second power supply wiring and the first local wiring in a plan view. Semiconductor integrated circuit device.

6. In the semiconductor integrated circuit device according to claim 5, the standard cell is formed in the second wiring layer, includes a first wiring extending in the first direction and connected to the gate wiring and the first local wiring. Semiconductor integrated circuit device.

7. In the semiconductor integrated circuit device according to claim 1, the second power supply wiring is formed in the first wiring layer, extends in the first direction, and overlaps the first nanosheet FET in a plan view. Semiconductor integrated circuit device.

8. In the semiconductor integrated circuit device according to claim 7, the standard cell is formed in a second wiring layer on the surface side of the second nanosheet FET, overlaps the second power supply wiring in a plan view, includes a first wiring connected to the gate wiring, and the second power supply wiring is connected to the first wiring via a second via provided at a position overlapping the second power supply wiring and the first wiring in a plan view. Semiconductor integrated circuit device.

9. In the semiconductor integrated circuit device according to claim 7, the standard cell includes a first local wiring connected to the source of the second nanosheet FET and extending in the second direction, and a first wiring formed in a second wiring layer on the surface side of the second nanosheet FET and connected to the first local wiring and the gate wiring, and the second power supply wiring is connected to the first local wiring via a third via provided at a position overlapping the second power supply wiring and the first local wiring in a plan view. Semiconductor integrated circuit device.

10. A semiconductor integrated circuit device, comprising: a first standard cell which is a capacitive cell; second and third standard cells which are arranged in the same cell column as the first standard cell and have logic functions, wherein the first standard cell includes: a first nanosheet FET (Field Effect Transistor) of a first conductivity type, including a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type, formed above the first nanosheet FET in a depth direction, including a second nanosheet extending in the first direction and overlapping the first nanosheet in a plan view; a gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a plan view, and surrounding the periphery of the first and second nanosheets in the second and depth directions; a first power supply wiring formed in a first wiring layer on the back side of the first nanosheet FET, extending in the first direction, overlapping the first nanosheet FET in a plan view, and supplying a first power supply voltage; and a second power supply wiring connected to the gate wiring and supplying a second power supply voltage, wherein the first power supply wiring is connected to the source of the first nanosheet FET through a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a plan view, the second standard cell includes a third nanosheet FET of the first conductivity type, formed at the same position as the first nanosheet FET in the depth direction and including a third nanosheet extending in the first direction, the third standard cell includes a fourth nanosheet FET of the first conductivity type, formed at the same position as the first nanosheet FET in the depth direction and including a fourth nanosheet extending in the first direction, the third nanosheet has the same size as the first nanosheet in the second direction and the same arrangement range in the second direction, and the fourth nanosheet has a size smaller than that of the first nanosheet in the second direction. A semiconductor integrated circuit device.

11. The semiconductor integrated circuit device according to claim 10, wherein the first nanosheet, the third nanosheet, and the fourth nanosheet have the same position at one end in the second direction. A semiconductor integrated circuit device.

12. In the semiconductor integrated circuit device according to claim 10, the second standard cell includes a fifth nanosheet FET of the second conductivity type, which is formed at the same position as the second nanosheet FET in the depth direction and includes a fifth nanosheet extending in the first direction; the third standard cell includes a sixth nanosheet FET of the second conductivity type, which is formed at the same position as the second nanosheet FET in the depth direction and includes a sixth nanosheet extending in the first direction; the fifth nanosheet has the same size and the same laying range as the second nanosheet in the second direction; and the sixth nanosheet has a size smaller than that of the second nanosheet in the second direction. A semiconductor integrated circuit device.

13. In the semiconductor integrated circuit device according to claim 12, the second nanosheet, the fifth nanosheet, and the sixth nanosheet have the same position at one end in the second direction. A semiconductor integrated circuit device.

14. In the semiconductor integrated circuit device according to claim 10, the second power supply wiring is formed in a second wiring layer on the surface side of the second nanosheet FET, extends in the first direction, and overlaps with the second nanosheet FET in a plan view. A semiconductor integrated circuit device.

15. In the semiconductor integrated circuit device according to claim 14, the second power supply wiring is connected to the gate wiring through a second via provided at a position overlapping with the second power supply wiring and the second nanosheet FET in a plan view. A semiconductor integrated circuit device.

16. In the semiconductor integrated circuit device according to claim 15, the second via is arranged at an end in the second direction of a region where the second power supply wiring and the second nanosheet overlap in a plan view. A semiconductor integrated circuit device.

17. In the semiconductor integrated circuit device according to claim 15, the first standard cell includes a first local wiring connected to the source of the second nanosheet FET and extending in the second direction; the second power supply wiring is connected to the first local wiring through a third via provided at a position overlapping with the second power supply wiring and the first local wiring in a plan view. A semiconductor integrated circuit device.

18. In the semiconductor integrated circuit device according to claim 10, the second power supply wiring is formed in the first wiring layer, extends in the first direction, and overlaps with the first nanosheet FET in a plan view. A semiconductor integrated circuit device.

19. In the semiconductor integrated circuit device according to claim 18, the first standard cell is formed in a second wiring layer on the surface side of the second nanosheet FET, overlaps with the second power supply wiring in a plan view, and includes a first wiring connected to the gate wiring. The second power supply wiring is connected to the first wiring via a second via provided at a position overlapping with the second power supply wiring and the first wiring in a plan view. A semiconductor integrated circuit device.

20. In the semiconductor integrated circuit device according to claim 18, the first standard cell includes a first local wiring connected to the source of the second nanosheet FET and extending in the second direction, and a first wiring formed in a second wiring layer on the surface side of the second nanosheet FET and connected to the first local wiring and the gate wiring. The second power supply wiring is connected to the first local wiring via a third via provided at a position overlapping with the second power supply wiring and the first local wiring in a plan view. A semiconductor integrated circuit device.

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