Semiconductor package

Abstract

A semiconductor package (10) comprises a substrate (11) having a first principal surface (11A), and a semiconductor device (100) mounted on the first principal surface (11A). The substrate (11) has: a first wiring layer (21) extending parallel to the first principal surface (11A); a first interlayer insulating layer (32) positioned at a location different from the first wiring layer (21) in a direction orthogonal to the first principal surface (11A); and a flat plate-shaped first functional layer (41) extending parallel to the first principal surface (11A) inside the first interlayer insulating layer (32). When viewed in a direction orthogonal to the first principal surface (11A), the first functional layer (41) overlaps the first wiring layer (21) without sandwiching another wiring therebetween. The volume of the first functional layer (41) is less than or equal to 0.5 times the volume of the substrate (11). The relative magnetic permeability of the first functional layer (41) is at least twice the relative magnetic permeability of the first interlayer insulating layer (32).

Description

Semiconductor Package

[0001] The present disclosure relates to semiconductor packages.

[0002] The electronic component described in Patent Document 1 has a core substrate. The core substrate has an opening penetrating the core substrate. The inside of the opening is filled with a magnetic resin. The magnetic resin further has a through hole. A through-hole conductor is located inside the through hole. The electronic component also has an insulating layer and a conductor layer. The insulating layer is located on a main surface of the core substrate. The conductor layer is located on the surface of the insulating layer. The conductor layer, together with the through-hole conductor, forms an inductor.

[0003] Japanese Patent Application Laid-Open No. 2020-178007

[0004] In electronic components such as those described in Patent Document 1, the volume of the magnetic resin determines the characteristics of the inductor formed by the conductor layer and the through-hole conductor. Therefore, if the core substrate is made thinner, the volume of the magnetic resin will be reduced, and the characteristics required of the inductor may not be satisfied. In other words, with electronic components such as those described in Patent Document 1, it is difficult to reduce the thickness while maintaining the characteristics required of the inductor. Note that while an example in which a portion of the core substrate functions as an inductor has been given here, it is also difficult to reduce the thickness while maintaining the required characteristics even when a portion of the core substrate functions as an element such as a capacitor.

[0005] In order to solve the above problems, the present disclosure provides a semiconductor package comprising a substrate having a first main surface and a semiconductor device mounted on the first main surface, wherein the substrate has a first wiring layer extending parallel to the first main surface, a first interlayer insulating layer located at a different location from the first wiring layer in a direction perpendicular to the first main surface, and a flat first functional layer extending parallel to the first main surface within the first interlayer insulating layer, wherein when viewed in a direction perpendicular to the first main surface, the first functional layer overlaps the first wiring layer without any other wiring sandwiched between them, the volume of the first functional layer is 0.5 times or less the volume of the substrate, and the relative permeability of the first functional layer is at least twice the relative permeability of the first interlayer insulating layer.

[0006] In addition, to solve the above-mentioned problems, the present disclosure provides a semiconductor package comprising a substrate having a first main surface and a semiconductor device mounted on the first main surface, wherein the substrate has a first wiring layer extending parallel to the first main surface, a second wiring layer located at a position different from the first wiring layer in a direction perpendicular to the first main surface and extending parallel to the first main surface, a first interlayer insulating layer located between the first wiring layer and the second wiring layer, and a flat first functional layer extending parallel to the first main surface within the first interlayer insulating layer, wherein when viewed in a direction perpendicular to the first main surface, the first functional layer overlaps the first wiring layer and the second wiring layer without any other wiring therebetween, and the volume of the first functional layer is 0.5 times or less the volume of the substrate, and the dielectric constant of the first functional layer is at least twice the dielectric constant of the first interlayer insulating layer.

[0007] According to the above configuration, it is possible to make the substrate thinner while allowing a portion of the substrate to function as an electronic component having desired characteristics.

[0008] FIG. 1 is a schematic configuration diagram of a semiconductor package according to a first embodiment. FIG. 2 is an enlarged transparent plan view of the vicinity of a first inductor wiring and a second inductor wiring in the semiconductor package according to the first embodiment. FIG. 3 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 4 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 5 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 6 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 7 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 8 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 9 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 10 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 11 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 12 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 13 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 14 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 15 is an explanatory diagram of a manufacturing method of a semiconductor package according to the first embodiment. FIG. 16 is a schematic configuration diagram of a semiconductor package according to a second embodiment. Fig. 17 is an enlarged transparent plan view of the vicinity of the first electrode and the second electrode in the semiconductor package of the second embodiment. Fig. 18 is a schematic configuration diagram of a semiconductor package of a modified example. Fig. 19 is a schematic configuration diagram of a semiconductor package of a modified example. Fig. 20 is a schematic configuration diagram of a semiconductor package of a modified example. Fig. 21 is an enlarged transparent plan view of the vicinity of the first inductor wiring and the second inductor wiring in the semiconductor package of the modified example. Fig. 22 is a schematic configuration diagram of a semiconductor package of the modified example. Fig. 23 is a schematic configuration diagram of a semiconductor package of the modified example.

[0009] An embodiment of a semiconductor package will be described below with reference to the drawings. The drawings may show components enlarged for ease of understanding. The dimensional ratios of the components may differ from those in the actual components or from those in other drawings. In the following description, some components are designated as first, second, etc. These are for convenience only and do not indicate the priority of the components. Furthermore, the first and second numbers may be interpreted interchangeably.

[0010] (First Embodiment) <Regarding Overall Configuration> As shown in Figure 1, a semiconductor package 10 includes a substrate 11 having a first main surface 11A and a second main surface 11B. The outer shape of the substrate 11 is generally rectangular. The first main surface 11A is one of the outer surfaces of the substrate 11 with the largest area. When viewed in a direction perpendicular to the first main surface 11A, the first main surface 11A is rectangular. The second main surface 11B is a surface of the outer surface of the substrate 11 that is parallel to the first main surface 11A. When viewed in a direction perpendicular to the second main surface 11B, the shape of the second main surface 11B is the same as the shape of the first main surface 11A.

[0011] In the following description, an axis perpendicular to the first main surface 11A is referred to as the first axis X. An axis parallel to one of the sides of the first main surface 11A is referred to as the second axis Y. An axis perpendicular to both the first axis X and the second axis Y is referred to as the third axis Z. A specific direction along the first axis X is referred to as the first positive direction X1, and a direction opposite to the first positive direction X1 is referred to as the first negative direction X2. In this embodiment, the first positive direction X1 coincides with the direction in which the first main surface 11A faces. A specific direction along the second axis Y is referred to as the second positive direction Y1, and a direction opposite to the second positive direction Y1 is referred to as the second negative direction Y2. A specific direction along the third axis Z is referred to as the third positive direction Z1, and a direction opposite to the third positive direction Z1 is referred to as the third negative direction Z2.

[0012] The substrate 11 includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, a fifth layer L5, and a sixth layer L6. When viewed in a direction along the first axis X, the outer shape of each of the first layer L1 to the sixth layer L6 is rectangular. The layers of the substrate 11 are arranged in the following order from the first positive direction X1 side to the first negative direction X2 side: the second layer L2, the first layer L1, the third layer L3, the fourth layer L4, the fifth layer L5, and the sixth layer L6.

[0013] The first layer L1 is the second layer from the side of the first positive direction X1 among the layers of the substrate 11. The first layer L1 includes a first wiring layer 21 and a first insulating layer 31. The material of the first wiring layer 21 is a conductive material. The material of the first wiring layer 21 includes, for example, at least one of Cu, Ag, Au, Ni, and Al. Alternatively, for example, the material of the first wiring layer 21 may be an alloy containing two or more of Cu, Ag, Au, Ni, and Al.

[0014] The first wiring layer 21 extends parallel to the first main surface 11A. In this embodiment, the first wiring layer 21 has a plurality of first inductor wirings 21A and a plurality of second inductor wirings 21B that are not connected to each other within the first layer L1 on which the first wiring layer 21 is located. The wiring shapes of the first inductor wirings 21A and the second inductor wirings 21B will be described later.

[0015] Furthermore, the first wiring layer 21 has other wiring 21C as wiring different from the first inductor wiring 21A and the second inductor wiring 21B in the layer in which the first wiring layer 21 is located. The other wiring 21C extends in an arbitrary wiring pattern in the first layer L1. The other wiring 21C may or may not be connected to the first inductor wiring 21A and the second inductor wiring 21B. Note that in FIG. 1, only some of the other wiring 21C are denoted by reference numerals.

[0016] The first insulating layer 31 is located in a portion of the first layer L1 excluding the first wiring layer 21. The material of the first insulating layer 31 is an organic resin containing an inorganic filler. In this embodiment, the inorganic filler is a silica filler. The inorganic filler is not limited to silica filler, and may be a glass filler or the like. In this embodiment, the organic resin is an epoxy resin. The organic resin is not limited to epoxy-based resins, and may be polyimide-based resins, liquid crystal polymer-based resins, acrylic-based resins, phenol-based resins, or combinations thereof.

[0017] The second layer L2 is stacked on the surface of the first layer L1 facing the first positive direction X1. That is, the second layer L2 is the layer closest to the first positive direction X1 in the substrate 11. The surface of the second layer L2 facing the first positive direction X1 is the first main surface 11A. The second layer L2 includes a first functional layer 41, a first interlayer insulating layer 32, and a plurality of first vias 51.

[0018] The first functional layer 41 extends parallel to the first main surface 11A. The first functional layer 41 is flat. The maximum dimension of the first functional layer 41 in the direction along the first axis X is smaller than the maximum dimension of the second layer L2 in the direction along the first axis X. The first functional layer 41 is not in contact with the first layer L1. The first functional layer 41 is not exposed at the first main surface 11A. In other words, the first functional layer 41 is buried in the second layer L2. In this embodiment, the first functional layer 41 has a first functional portion 41A and a second functional portion 41B that are not connected to each other in the second layer L2 in which the first functional layer 41 is located.

[0019] As shown in FIG. 2 , when viewed in a perspective view along the first axis X, the first functional unit 41A has a rectangular shape with its elongated length extending along the third axis Z. That is, the first functional unit 41A has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. The material of the first functional unit 41A is an organic resin containing magnetic powder. In this embodiment, the magnetic powder is FeSiCr-based metal powder. Note that the magnetic powder is not limited to FeSiCr-based metal powder, but may be, for example, FeSi-based, FeAl-based, or Fe-based metal powder, or a combination thereof. Note that the first functional unit 41A may be formed by sputtering a cobalt-based alloy such as a cobalt-zirconium-tantalum alloy. In this embodiment, the organic resin is an epoxy resin. Note that the organic resin is not limited to epoxy-based resins, but may also be polyimide-based, liquid crystal polymer-based, acrylic-based, or phenol-based resins, or a combination thereof. In addition, the organic resin may contain inorganic fillers in addition to the above materials. In this embodiment, the first functional unit 41A contains 60 vol% or more of magnetic powder. In this embodiment, the first functional unit 41A does not have magnetic anisotropy. The magnetic powder contained in the first functional unit 41A is FeSiCr-based metal powder and is spherical. The magnetic domains of the magnetic powder are randomly aligned, and because the magnetic powder is spherical, it does not have shape magnetic anisotropy. Therefore, if the magnetic powder is confirmed to be spherical when a cross section of the first functional unit 41A is observed with an electron microscope, and the magnetic domains are confirmed to be randomly aligned when the cross section is observed with a magnetic force microscope, etc., it can be said that the first functional unit 41A does not have magnetic anisotropy. In other words, the material of the first functional unit 41A does not clearly distinguish between the easy axis and the hard axis of magnetization. The relative permeability of the first functional unit 41A is 5 or more.

[0020] The second functional part 41B is located on the second negative direction Y2 side with respect to the first functional part 41A. When viewed in a direction along the first axis X, the second functional part 41B has a rectangular shape with its elongated sides in the direction along the second axis Y. That is, the second functional part 41B has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. The material of the second functional part 41B is the same as the material of the first functional part 41A. That is, the relative permeability of the second functional part 41B is 5 or more.

[0021] As shown in FIG. 1 , each first via 51 extends in a direction intersecting the first main surface 11A. In this embodiment, each first via 51 penetrates the second layer L2 in a direction perpendicular to the first main surface 11A. The material of each first via 51 is the same as the material of the first wiring layer 21. Each first via 51 is substantially truncated cone-shaped. The diameter of each first via 51 decreases toward the first negative direction X2. The end of each first via 51 on the first negative direction X2 side is connected to the first wiring layer 21. The end of each first via 51 on the first positive direction X1 side is exposed from the second layer L2. That is, the end of each first via 51 on the first positive direction X1 side is exposed from the first main surface 11A. Note that in FIG. 1 , only some of the first vias 51 are labeled with reference numerals.

[0022] The first interlayer insulating layer 32 is located in a portion of the second layer L2 excluding the first functional layer 41 and the first vias 51. That is, the first interlayer insulating layer 32 is located at a different location from the first wiring layer 21 in a direction perpendicular to the first main surface 11A. The first interlayer insulating layer 32 covers the entire first functional layer 41. That is, the first functional layer 41 is located inside the first interlayer insulating layer 32. The first interlayer insulating layer 32 also covers the entire circumferential surface of each first via 51. In other words, the first vias 51 penetrate the first interlayer insulating layer 32. The material of the first interlayer insulating layer 32 is the same as the material of the first insulating layer 31. The relative permeability of the first interlayer insulating layer 32 is less than half the relative permeability of the first functional layer 41. In other words, the relative magnetic permeability of the first functional layer 41 is at least twice the relative magnetic permeability of the first interlayer insulating layer 32 .

[0023] The second layer L2 does not have any parts with a higher conductivity than the first functional layer 41 other than the first vias 51. Therefore, when viewed in a direction along the first axis X, the first functional layer 41 overlaps the first wiring layer 21 of the first layer L1 without any other wiring therebetween. Note that the other wiring here is not limited to wiring that extends linearly, but refers to any part with a higher conductivity than the first functional layer 41, including wiring that functions as a terminal or pad.

[0024] The third layer L3 is stacked on the surface of the first layer L1 facing the first negative direction X2. The third layer L3 includes a second functional layer 42, a second interlayer insulating layer 33, and a plurality of second vias 52.

[0025] The second functional layer 42 extends parallel to the first main surface 11A. The second functional layer 42 is flat. The maximum dimension of the second functional layer 42 in the direction along the first axis X is smaller than the maximum dimension of the third layer L3 in the direction along the first axis X. The second functional layer 42 is not in contact with the first layer L1. Furthermore, the first functional layer 41 is not in contact with the fourth layer L4. In other words, the second functional layer 42 is buried in the third layer L3. In this embodiment, the second functional layer 42 has a third functional portion 42A and a fourth functional portion 42B that are not connected to each other within the third layer L3 in which the second functional layer 42 is located.

[0026] As shown in FIG. 2 , when viewed in a direction along the first axis X, the third functional unit 42A has a rectangular shape elongated in a direction along the third axis Z. That is, the third functional unit 42A has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. When viewed in a direction along the first axis X, the dimension of the third functional unit 42A in the direction along the second axis Y is larger than the dimension of the first functional unit 41A in the direction along the second axis Y. When viewed in a direction along the first axis X, the dimension of the third functional unit 42A in the direction along the third axis Z is slightly larger than the dimension of the first functional unit 41A in the direction along the third axis Z. When viewed in a direction along the first axis X, the third functional unit 42A overlaps the entire first functional unit 41A. The material of the third functional unit 42A is the same as the material of the first functional unit 41A. That is, the relative magnetic permeability of the third functional portion 42A is 5 or more.

[0027] The fourth functional unit 42B is located on the second negative direction Y2 side relative to the third functional unit 42A. When viewed in a direction along the first axis X, the fourth functional unit 42B has a rectangular shape with its elongated sides extending in a direction along the second axis Y. That is, the fourth functional unit 42B has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. The outer shape of the fourth functional unit 42B matches the outer shape of the second functional unit 41B. When viewed in a direction along the first axis X, the second functional unit 41B and the fourth functional unit 42B almost completely overlap. The material of the fourth functional unit 42B is the same as the material of the first functional unit 41A. That is, the relative permeability of the fourth functional unit 42B is 5 or greater.

[0028] In addition, in this embodiment, the combined volume of the second functional layer 42 and the first functional layer 41 is 0.5 times or less the volume of the substrate 11. That is, the volume of the first functional layer 41 is 0.5 times or less the volume of the substrate 11. In addition, the volume of the second functional layer 42 is 0.5 times or less the volume of the substrate 11.

[0029] Here, the volumes of the first functional layer 41 and the second functional layer 42 are measured, for example, by the following method. First, the substrate 11 is ground on a plane parallel to the first axis X. A ground cross-section of the substrate 11 is photographed, and the maximum dimension of the first functional layer 41 in the direction along the first axis X is measured on that cross-section. In this manner, the maximum dimension of the first functional layer 41 is measured on three cross-sections of the substrate 11, and the average value of the maximum dimensions at the three locations is defined as the thickness of the first functional layer 41. Furthermore, the substrate 11 is ground in a direction parallel to the first main surface 11A, i.e., on a plane parallel to the second axis Y and the third axis Z, so that the first functional layer 41 is exposed. A ground cross-section of the substrate 11 is photographed, and the total area of ​​the first functional layer 41 is measured on that cross-section. The volume of the first functional layer 41 is calculated by multiplying the total area by the calculated thickness. The volume of the second functional layer 42 is measured using a similar procedure.

[0030] In this embodiment, the maximum dimension of the second functional layer 42 in a direction perpendicular to the first main surface 11A is the same as the maximum dimension of the first functional layer 41 in a direction perpendicular to the first main surface 11A. Note that the "maximum dimension" here corresponds to the above-mentioned "thickness." Furthermore, "same maximum dimension" allows for manufacturing errors. Therefore, if the difference in the maximum dimension of each functional layer is within ±10%, it can be considered that the "same maximum dimension" is true.

[0031] As shown in FIG. 1 , each second via 52 extends in a direction intersecting the first main surface 11A. In this embodiment, each second via 52 penetrates the third layer L3 in a direction perpendicular to the first main surface 11A. The material of each second via 52 is the same as the material of the first via 51. Each second via 52 has a generally truncated cone shape. The diameter of each second via 52 decreases toward the first negative direction X2. The end of each second via 52 on the first positive direction X1 side is connected to the first wiring layer 21. The end of each second via 52 on the first negative direction X2 side is exposed from the third layer L3. Note that in FIG. 1 , only some of the second vias 52 are labeled with reference numerals.

[0032] The second interlayer insulating layer 33 is located in a portion of the third layer L3 excluding the second functional layer 42 and the second vias 52. The second interlayer insulating layer 33 covers the entire second functional layer 42. That is, the second functional layer 42 is located inside the second interlayer insulating layer 33. The second interlayer insulating layer 33 also covers the entire circumferential surface of each second via 52. In other words, the second vias 52 penetrate the second interlayer insulating layer 33. The material of the second interlayer insulating layer 33 is the same as the material of the first insulating layer 31. The relative magnetic permeability of the second interlayer insulating layer 33 is half or less of the relative magnetic permeability of the second functional layer 42. In other words, the relative magnetic permeability of the second functional layer 42 is at least twice the relative magnetic permeability of the second interlayer insulating layer 33.

[0033] The third layer L3 does not have any portion with a higher conductivity than the second functional layer 42, other than each second via 52. Therefore, when viewed in a direction along the first axis X, the second functional layer 42 overlaps the first wiring layer 21 of the first layer L1 without any other wiring therebetween.

[0034] The fourth layer L4 is stacked on the surface of the third layer L3 facing the first negative direction X2. The fourth layer L4 includes a second wiring layer 22 and a second insulating layer 34. The material of the second wiring layer 22 is the same as the material of the first wiring layer 21. The second wiring layer 22 extends parallel to the first main surface 11A. In this embodiment, the second wiring layer 22 extends in an arbitrary wiring pattern on the fourth layer L4. The second wiring layer 22 is connected to the end of the second via 52 facing the first negative direction X2. Note that in FIG. 1, only a portion of the second wiring layer 22 is denoted by a reference numeral. The second insulating layer 34 is located in a portion of the fourth layer L4 excluding the second wiring layer 22. The material of the second insulating layer 34 is the same as the material of the first insulating layer 31.

[0035] The fifth layer L5 is stacked on the surface of the fourth layer L4 on the first negative direction X2 side. The fifth layer L5 includes a plurality of third vias 53 and a third insulating layer 35. Each third via 53 extends in a direction intersecting the first main surface 11A. In this embodiment, each third via 53 penetrates the fifth layer L5 in a direction perpendicular to the first main surface 11A. The material of each third via 53 is the same as the material of the first via 51. Each third via 53 has a substantially truncated cone shape. The diameter of each third via 53 decreases toward the first negative direction X2 side. The end of each third via 53 on the first positive direction X1 side is connected to the second wiring layer 22. The end of each third via 53 on the first negative direction X2 side is exposed from the fifth layer L5. Note that in FIG. 1 , only some of the third vias 53 are labeled with reference numerals.

[0036] The third insulating layer 35 is located in a portion of the fifth layer L5 excluding the third vias 53. The third insulating layer 35 covers the entire circumferential surface of each third via 53. That is, the third vias 53 penetrate the third insulating layer 35. The material of the third insulating layer 35 is the same as the material of the first insulating layer 31.

[0037] The sixth layer L6 is stacked on the surface of the fifth layer L5 facing the first negative direction X2. That is, the sixth layer L6 is located closest to the first negative direction X2 on the substrate 11. The surface of the sixth layer L6 facing the first negative direction X2 is the second main surface 11B. The sixth layer L6 includes a plurality of built-in electrodes 61 and a fourth insulating layer 36.

[0038] Each built-in electrode 61 extends in a direction parallel to first main surface 11A. When viewed in a direction along first axis X, each built-in electrode 61 has a rectangular shape. Although not shown, each built-in electrode 61 has a two-layer structure consisting of a layer mainly composed of Ni and a layer mainly composed of Au, arranged in this order from the first positive direction X1 side. Each built-in electrode 61 is connected to the end of third via 53 on the first negative direction X2 side.

[0039] The fourth insulating layer 36 is located in a portion of the sixth layer L6 excluding the built-in electrodes 61. The fourth insulating layer 36 covers the peripheral surfaces of each built-in electrode 61. Therefore, the first negative direction X2 side of each built-in electrode 61 is exposed from the second main surface 11B. The material of the fourth insulating layer 36 is the same as the material of the first insulating layer 31. Note that in FIG. 1 , the boundaries between layers are indicated by imaginary dashed lines. However, there need not be a clear boundary between adjacent insulating layers.

[0040] Thus, the substrate 11 comprises a first wiring layer 21, a first interlayer insulating layer 32, a first functional layer 41, a second wiring layer 22, a second interlayer insulating layer 33, a second functional layer 42, a first via 51, a second via 52, and a third via 53.

[0041] The substrate 11 further includes a plurality of external electrodes 63. Each external electrode 63 is located on the first main surface 11A. Each external electrode 63 extends in a direction parallel to the first main surface 11A. Each external electrode 63 has a rectangular shape when viewed in a direction along the first axis X. Although not shown, each external electrode 63 has a two-layer structure consisting of a layer primarily composed of Cu and a layer primarily composed of an alloy containing Sn and Ag, arranged in order from the first negative direction X2. Each external electrode 63 is connected to a portion of the first via 51 exposed from the first main surface 11A. Note that in FIG. 1, only some of the external electrodes 63 are labeled with reference numerals.

[0042] The semiconductor package 10 includes a plurality of connection portions 62 and a plurality of semiconductor devices 100. Each connection portion 62 is made of a conductive material such as solder. The number of connection portions 62 corresponds to the number of external electrodes 63. Each connection portion 62 is applied to the corresponding external electrode 63. Each connection portion 62 covers the surface of each external electrode 63 facing the first positive direction X1. Note that in FIG. 1, only some of the connection portions 62 are denoted with reference numerals.

[0043] Each semiconductor device 100 is connected to a connecting portion 62. That is, each semiconductor device 100 is mounted on the first main surface 11A via the connecting portion 62 and the external electrodes 63. In this embodiment, two or more semiconductor devices 100 are mounted on the first main surface 11A. Note that one semiconductor device 100 is connected to multiple external electrodes 63 via the connecting portions 62. One example of a semiconductor device 100 is a semiconductor integrated device (CPU) including multiple load circuits. Another example of a semiconductor device 100 is a semiconductor switch such as a PMIC (power management IC). The maximum dimension of each semiconductor device 100 in a direction perpendicular to the first main surface 11A is smaller than the maximum dimension of the substrate 11 in a direction perpendicular to the first main surface 11A.

[0044] <Regarding the First Inductor Wiring and the Second Inductor Wiring> As shown in Fig. 2, the inductor portion P surrounded by the dashed line in Fig. 1 is viewed in a perspective direction along the first axis X. Note that Fig. 2 only illustrates the first functional layer 41, the second functional layer 42, the first inductor wiring 21A, the second inductor wiring 21B, and some of the first vias 51.

[0045] 2, the first wiring layer 21 has four first inductor wirings 21A. The four first inductor wirings 21A are aligned in a direction along the third axis Z. Each first inductor wiring 21A extends linearly parallel to the second axis Y. That is, the number of turns in the first inductor wiring 21A is 0. In other words, the number of turns in the first inductor wiring 21A is less than 0.5 turns.

[0046] A first line end of each first inductor wiring 21A on the second positive direction Y1 side is connected to a first via 51. Furthermore, a second line end of each first inductor wiring 21A on the second negative direction Y2 side is connected to a first via 51 different from the first line end connected to it. When viewed in a direction along the first axis X, the entire first inductor wiring 21A overlaps the third functional unit 42A of the second functional layer 42. When viewed in a direction along the first axis X, the first inductor wiring 21A, excluding its ends, overlaps the first functional unit 41A of the first functional layer 41. Therefore, most of the area of ​​each first inductor wiring 21A is sandwiched between the first functional unit 41A and the third functional unit 42A.

[0047] The first wiring layer 21 has four second inductor wirings 21B. The second inductor wirings 21B are aligned in a direction along the second axis Y. The second inductor wirings 21B extend as a whole in a direction along the third axis Z. A first line end of each second inductor wiring 21B on the third positive direction Z1 side is connected to a first via 51. Furthermore, a second line end of each second inductor wiring 21B on the third negative direction Z2 side is connected to a first via 51 different from the first line end. When viewed in a direction along the first axis X, a portion of the second inductor wiring 21B excluding the first and second line ends overlaps with the second functional portion 41B of the first functional layer 41 and the fourth functional portion 42B of the second functional layer 42.

[0048] In the following description, the four second inductor wirings 21B will be described as a first line 21B1, a second line 21B2, a third line 21B3, and a fourth line 21B4, in that order from the second positive direction Y1 side.

[0049] Suppose that the first line 21B1 is traced from the first line end, which is the end on the third positive direction Z1 side, to the second line end, which is the end in the opposite direction, and the first line 21B1 has a portion extending parallel to the third axis Z, a portion extending diagonally toward the second negative direction Y2 and the third negative direction Z2, a portion extending parallel to the third axis Z, and a portion extending diagonally toward the second positive direction Y1 and the third negative direction Z2.

[0050] The number of turns of the second inductor wiring 21B is determined based on a virtual vector. The starting point of the virtual vector is located on the center line of the second inductor wiring 21B. When viewed in a direction along the first axis X, the starting point of the virtual vector is moved from a state in which it is located at a first end of the center line to a second end of the center line, and the number of turns is determined to be 1.0 when the angle by which the direction of the virtual vector rotates is 360 degrees. However, when the direction of the virtual vector involves multiple windings, the number of turns increases when the windings are consecutive in the same direction.

[0051] Suppose a virtual vector is moved on the first line 21B1. At this time, the virtual vector, pointing in the third negative direction Z2, turns less than 90 degrees toward the second negative direction Y2, then turns less than 90 degrees toward the second positive direction Y1, and then turns again less than 90 degrees toward the second positive direction Y1. That is, the virtual vector turns in the range of several degrees to less than 90 degrees toward the second positive direction Y1 or the second negative direction Y2. That is, the number of turns on the first line 21B1 is 0.5 turns or less.

[0052] The second line 21B2 has a shape obtained by inverting the first line 21B1 with respect to a line of symmetry along the third axis Z. The third line 21B3 has the same shape as the first line 21B1. The fourth line 21B4 has the same shape as the second line 21B2. That is, the number of turns of each second inductor wiring 21B is less than 0.5 turns.

[0053] Here, for each first inductor wiring 21A, a first virtual line V1 is assumed to pass through the first line end and the second line end of the first inductor wiring 21A. Each first virtual line V1 extends parallel to the second axis Y. Furthermore, for each second inductor wiring 21B, a second virtual line V2 is assumed to pass through the first line end and the second line end of the second inductor wiring 21B. The second virtual line V2 extends along the third axis Z as a whole. In other words, the first virtual line V1 and the second virtual line V2 intersect with each other. Note that the first virtual line V1 and the second virtual line V2 may be perpendicular to each other.

[0054] <Method for Manufacturing a Semiconductor Package> As shown in FIG. 3 , a plate-shaped base substrate BL is prepared. The base substrate BL is made of silicon. In the following description, the main surface of the base substrate BL is assumed to be perpendicular to the first axis X. When viewed in the first negative direction X2, the base substrate BL has, for example, a rectangular shape. The dimensions of each side of the base substrate BL are such that multiple substrates 11 can be accommodated. Next, a release layer RL is applied to the first positive direction X1 side of the base substrate BL, i.e., the entire top surface. The release layer RL is a sheet-like member having adhesive properties, such as, for example, an infrared-curable resin tape, an acrylic resin adhesive, or a polyimide adhesive. Note that in FIG. 3 , the release layer RL is illustrated by a thick line.

[0055] 4, built-in electrode 61 is formed on release layer RL. Specifically, two layers, a layer mainly composed of Au and a layer mainly composed of Ni, are formed from the first negative direction X2 side by a method such as electroless plating or electrolytic plating. In this way, built-in electrode 61 is formed.

[0056] Next, as shown in FIG. 5 , the fourth insulating layer 36 and the third insulating layer 35 are formed. Specifically, an insulator is laminated from the first positive direction X1 side of the built-in electrode 61 and the release layer RL. The material of the insulator is epoxy resin containing silica filler. Next, a laser is irradiated onto the insulator from the first positive direction X1 side. Specifically, the laser is irradiated onto the insulator in a portion on the first positive direction X1 side of the built-in electrode 61 where the third via 53 will be formed. This processes the insulator, forming the fourth insulating layer 36 and the third insulating layer 35.

[0057] 6 , the third via 53 and the second wiring layer 22 are formed. The third via 53 and the second wiring layer 22 are formed by a known technique such as a semi-additive method. After the third via 53 and the second wiring layer 22 are formed, an insulator is laminated on the first positive direction X1 side of the second wiring layer 22 and the third insulating layer 35. This forms the second insulating layer 34 and a part of the second interlayer insulating layer 33.

[0058] Next, as shown in FIG. 7 , the functional sheet FS is formed. First, the functional sheet FS is laminated on the first positive direction X1 side of a portion of the formed second interlayer insulating layer 33. Then, the functional sheet FS is cured. The material of the functional sheet FS is an organic resin containing magnetic powder. In this embodiment, the functional sheet FS contains 60 vol % or more of magnetic powder.

[0059] 8, the second functional layer 42 is formed. That is, the functional sheet FS is processed into a desired shape to form the second functional layer 42. For example, the second functional layer 42 is formed by removing the functional sheet FS using a known technique such as dry etching or wet etching.

[0060] Next, as shown in FIG. 9 , the remaining second interlayer insulating layer 33 is formed. Specifically, an insulator similar to that described above is laminated from the first positive direction X1 side of the second functional layer 42 and the formed portion of the second interlayer insulating layer 33. Then, a laser is irradiated from the first positive direction X1 side onto the insulator and part of the formed first interlayer insulating layer 32. Specifically, the laser is irradiated onto the insulator and the portion of the second interlayer insulating layer 33 where the second via 52 is to be formed. In this way, the entire second interlayer insulating layer 33 is formed.

[0061] Next, as shown in Fig. 10, a second via 52 is formed. Specifically, the second via 52 is formed by copper electrolytic plating. Next, as shown in Fig. 11, a first insulating layer 31, a portion of the first interlayer insulating layer 32, and the first wiring layer 21 are formed. As described above, the first insulating layer 31 and a portion of the first interlayer insulating layer 32 are formed by laminating an insulator and irradiating it with a laser. The first wiring layer 21 is formed by a known technique such as a semi-additive method.

[0062] 12, the remaining first interlayer insulating layer 32, first functional layer 41, and first via 51 are formed. The first interlayer insulating layer 32, first functional layer 41, and first via 51 are formed in the same manner as described with reference to FIGS.

[0063] Next, as shown in Fig. 13, the external electrode 63 is formed. Specifically, the external electrode 63 is formed by a known technique such as a semi-additive method or a subtractive method. In this embodiment, two layers are formed from the first negative direction X2 side by the semi-additive method: a layer mainly composed of Cu and a layer mainly composed of an alloy containing Sn and Ag. In this way, the external electrode 63 is formed.

[0064] 14, the semiconductor device 100 is mounted. Specifically, first, the terminals of the semiconductor device 100 are connected by solder onto the external electrodes 63. The solder after connection becomes the connection portions 62.

[0065] Next, as shown in Figure 15, the base substrate BL and release layer RL are removed to separate the substrates 11. Specifically, first, the base substrate BL and release layer RL are removed by cutting. This forms a portion including a plurality of substrates 11. This portion is then separated by dicing along break lines DL to form the desired size of the substrate 11. This forms the semiconductor package 10. Note that in Figures 3 to 15, only some of the components may be labeled.

[0066] Effects of the First Embodiment (1-1) In the first embodiment, the relative permeability of the first functional layer 41 is at least twice that of the first interlayer insulating layer 32. With this configuration, the first functional layer 41 has a relatively high relative permeability, so that the first functional layer 41 functions like an inductor core. Furthermore, because the first functional layer 41 extends in a flat plate shape inside the first interlayer insulating layer 32, it is not necessary to excessively increase the dimension of the first functional layer 41 in a direction perpendicular to the first main surface 11A in order to ensure the volume of the first functional layer 41. Therefore, a thin design can be realized while allowing a portion of the substrate 11 to function as an inductor with desired characteristics.

[0067] (1-2) In the first embodiment, the number of turns in each first inductor wiring 21A is 0.5 turns or less. The relative permeability of the first functional layer 41 is 5 or more. With this configuration, the relative permeability of the first functional layer 41 is high, so a desired inductance can be obtained without increasing the number of turns in each first inductor wiring 21A. Furthermore, if the number of turns in each first inductor wiring 21A is 0.5 turns or less, the area required to provide the first inductor wiring 21A can be reduced. Therefore, the dimension in the direction parallel to the first main surface 11A of the substrate 11 can be prevented from increasing. The same applies to the second inductor wiring 21B.

[0068] (1-3) If the first functional layer 41 and the second functional layer 42 have magnetic anisotropy, it is preferable to arrange the inductor wiring along the easy axis of magnetization. In other words, if the first functional layer 41 has magnetic anisotropy, the shape and arrangement of the inductor wiring may be limited. In the first embodiment, the first functional layer 41 and the second functional layer 42 do not have magnetic anisotropy. In a configuration in which the first functional layer 41 and the second functional layer 42 do not have magnetic anisotropy, even if the first virtual line V1 in the first inductor wiring 21A and the second virtual line V2 in the second inductor wiring 21B intersect with each other, the magnetic anisotropy of the first functional layer 41 and the second functional layer 42 can be taken into consideration to prevent impairment of the inductor characteristics. In other words, this configuration improves the design freedom of the first inductor wiring 21A and the second inductor wiring 21B.

[0069] (1-4) In the first embodiment, the substrate 11 further includes a second functional layer 42. The material of the second functional layer 42 is the same as the material of the first functional layer 41. In this way, when the first functional layer 41 and the second functional layer 42 are made of the same material, the first functional layer 41 and the second functional layer 42 can be formed using a similar procedure during the manufacturing of the semiconductor package 10. This makes it possible to prevent the manufacturing process from becoming too complicated.

[0070] (1-5) In the first embodiment, the maximum dimension of the second functional layer 42 in the direction perpendicular to the first main surface 11A is the same as the maximum dimension of the first functional layer 41 in the direction perpendicular to the first main surface 11A. With this configuration, it is not necessary to individually manage the thickness of the insulating layer located in the same layer as each functional layer during the manufacturing process of the semiconductor package 10. That is, the thickness dimension for forming the second interlayer insulating layer 33 described in FIG. 9 and the thickness dimension for forming the first interlayer insulating layer 32 described in FIG. 12 can be formed to be the same thickness.

[0071] (1-6) In the first embodiment, the combined volume of the second functional layer 42 and the first functional layer 41 is 0.5 times or less the volume of the substrate 11. Thus, if the volume of each functional layer is small relative to the volume of the substrate 11, no special processing is required when arranging each functional layer within the substrate 11. In other words, a semiconductor package 10 having the first functional layer 41 and the second functional layer 42 can be manufactured using conventional substrate processing, resulting in inexpensive formation. Furthermore, because the volume of the entire substrate 11 other than the functional layers, particularly the insulating layer, is large, this configuration allows for a uniform thermal expansion coefficient throughout the entire semiconductor package 10. This prevents local thermal deformation in the semiconductor package 10.

[0072] (Regarding the Second Embodiment) A second embodiment of the semiconductor package will now be described. As shown in Fig. 16, the semiconductor package 10 of the second embodiment has a first main surface 11A and a second main surface 11B. The first main surface 11A and the second main surface 11B are the same as those of the first embodiment. The first axis X, the second axis Y, and the third axis Z are also treated in the same manner as those of the first embodiment.

[0073] The substrate 11 includes a first layer L1 to an eleventh layer L11. When viewed in a see-through manner in a direction along the first axis X, the outer shape of each of the first layer L1 to eleventh layer L11 is rectangular. The layers of the substrate 11 are arranged in the following order from the first positive direction X1 side to the first negative direction X2 side: second layer L2, first layer L1, third layer L3, fourth layer L4, fifth layer L5, sixth layer L6, seventh layer L7, eighth layer L8, ninth layer L9, tenth layer L10, and eleventh layer L11.

[0074] The first layer L1 is the second layer from the side of the first positive direction X1 among the layers of the substrate 11. The first layer L1 includes a first wiring layer 210 and a first insulating layer 301. The material of the first wiring layer 210 is the same as the material of the first wiring layer 21 in the first embodiment. The first wiring layer 210 extends parallel to the first main surface 11A. In this embodiment, the first wiring layer 210 includes a plurality of first electrodes 211 and other wirings 212. The first electrodes 211 will be described later.

[0075] The other wirings 212 extend in any wiring pattern on the second layer L2. The other wirings 212 may be connected to any of the first electrodes 211, or may not be connected to any of the first electrodes 211. Note that in FIG. 16, only some of the other wirings 212 are labeled with reference numerals.

[0076] The first insulating layer 301 is located in a portion of the first layer L1 excluding the first wiring layer 210. The material of the first insulating layer 301 is the same as the material of the first insulating layer 31 in the first embodiment. The second layer L2 is stacked on the surface of the first layer L1 on the first positive direction X1 side. That is, the second layer L2 is the layer on the substrate 11 closest to the first positive direction X1. The surface of the second layer L2 on the first positive direction X1 side is the first main surface 11A. The second layer L2 includes a plurality of first vias 510 and a second insulating layer 302.

[0077] Each first via 510 extends in a direction intersecting the first main surface 11A. In this embodiment, each first via 510 penetrates the second layer L2 in a direction perpendicular to the first main surface 11A. The material of each first via 510 is the same as the material of the first wiring layer 210. Each first via 510 is substantially truncated cone-shaped. The diameter of each first via 510 decreases toward the first negative direction X2. The end of each first via 510 on the first negative direction X2 side is connected to the first wiring layer 210. The end of each first via 510 on the first positive direction X1 side is exposed from the second layer L2. In other words, the end of each first via 510 on the first positive direction X1 side is exposed from the first main surface 11A. Note that in FIG. 16 , only some of the first vias 510 are labeled with reference numerals.

[0078] The second insulating layer 302 is located in a portion of the second layer L2 excluding the first vias 510. The material of the second insulating layer 302 is the same as the material of the first insulating layer 301. The third layer L3 is stacked on the surface of the first layer L1 on the first negative direction X2 side. The third layer L3 includes a first functional unit 411 that is part of the first functional layer 410, a first interlayer insulating layer 303, and a plurality of second vias 520.

[0079] In this embodiment, the first functional layer 410 has a flat plate shape as a whole. The first functional layer 410 is located across the third layer L3 and the fourth layer L4. The portion of the first functional layer 410 located on the third layer L3 is referred to as a first functional section 411, and the portion located on the fourth layer L4 is referred to as a second functional section 412.

[0080] The first functional portion 411 extends parallel to the first main surface 11A. The first functional portion 411 has a flat plate shape. The maximum dimension of the first functional portion 411 in the direction along the first axis X is the same as the maximum dimension of the third layer L3 in the direction along the first axis X.

[0081] 17 , when viewed in a direction along the first axis X, the first functional unit 411 has a rectangular shape with its elongated sides extending in the direction along the second axis Y. That is, the first functional unit 411 has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. The first functional unit 411 is in contact with a surface of the first wiring layer 210 facing the first negative direction X2. In other words, the first functional layer 410 is in contact with a surface of the first wiring layer 210 facing in a direction perpendicular to the first main surface 11A. That is, the first functional unit 411 is in contact with a surface of the first wiring layer 210 facing in a direction perpendicular to the first main surface 11A.

[0082] The material of the first functional portion 411 is an organic resin containing an inorganic filler. In this embodiment, the inorganic filler is barium titanate. In this embodiment, the organic resin is an epoxy resin. The organic resin is not limited to epoxy-based resins, but may be polyimide-based, liquid crystal polymer-based, acrylic-based, phenol-based resins, or combinations thereof. In addition, the first functional portion 411 may be made of SiO ２Alternatively, inorganic oxides such as SiN, TaO, and high-κ materials formed by sputtering may be used. In this embodiment, the first functional portion 41A contains 60 vol % or more of inorganic filler.

[0083] As shown in FIG. 16 , each second via 520 extends in a direction intersecting the first main surface 11A. In this embodiment, each second via 520 penetrates the third layer L3 in a direction perpendicular to the first main surface 11A. The material of each second via 520 is the same as the material of the first via 510. Each second via 520 has a substantially truncated cone shape. The diameter of each second via 520 decreases toward the first negative direction X2. The end of each second via 520 on the first positive direction X1 side is connected to the first wiring layer 210. The end of each second via 520 on the first negative direction X2 side is exposed from the third layer L3.

[0084] The first interlayer insulating layer 303 is located in a portion of the third layer L3 excluding the first functional portion 411 and the second vias 520. The first interlayer insulating layer 303 covers the entire peripheral surface of the first functional portion 411 and the entire peripheral surface of the second vias 520. In other words, the first functional portion 411 and each second via 520 penetrate the first interlayer insulating layer 303. The material of the first interlayer insulating layer 303 is the same as the material of the first insulating layer 301. The relative dielectric constant of the first interlayer insulating layer 303 is half or less of the relative dielectric constant of the first functional portion 411. In other words, the relative dielectric constant of the first functional layer 410 is at least twice the relative dielectric constant of the first interlayer insulating layer 303.

[0085] The fourth layer L4 is stacked on the surface of the third layer L3 facing the first negative direction X2. The fourth layer L4 includes a second wiring layer 220, a second functional unit 412, and a third insulating layer 304. The material of the second wiring layer 220 is the same as the material of the first wiring layer 210. The second wiring layer 220 extends parallel to the first main surface 11A. That is, the second wiring layer 220 is located at a different position from the first wiring layer 210 in the direction perpendicular to the first main surface 11A. The second wiring layer 220 is located on the first negative direction X2 side with respect to the first interlayer insulating layer 303. In other words, the first interlayer insulating layer 303 is located between the first wiring layer 210 and the second wiring layer 220.

[0086] In this embodiment, the second wiring layer 220 has second electrodes 221 and other wirings 222. The second electrodes 221 will be described later. The other wirings 222 extend in any wiring pattern on the second layer L2. The other wirings 222 may or may not be connected to the second electrodes 221. Note that in FIG. 16, only some of the other wirings 222 are labeled with reference numerals.

[0087] The material of the second functional portion 412 is the same as the material of the first functional portion 411. The second functional portion 412 extends parallel to the first main surface 11A. The maximum dimension of the second functional portion 412 in the direction along the first axis X is the same as the maximum dimension of the fourth layer L4 in the direction along the first axis X.

[0088] 17 , when viewed in a perspective view along the first axis X, the second functional unit 412 has a rectangular frame shape that follows the outer shape of the first functional unit 411. The surface of the second functional unit 412 on the first positive direction X1 side is connected to the first functional unit 411. As described above, the second functional unit 412 is part of the first functional layer 410. That is, there is no boundary between the second functional unit 412 and the first functional unit 411. When viewed in a perspective view along the first axis X, the first functional layer 410, which is made up of the second functional unit 412 and the first functional unit 411, overlaps the first wiring layer 210 and the second wiring layer 220 without any other wiring therebetween.

[0089] 16 , the second functional unit 412 covers a surface of the second electrode 221 facing a direction parallel to the first main surface 11A. The first functional unit 411 also covers a surface of the second electrode 221 facing the first positive direction X1. That is, the first functional layer 410 covers all of the second electrode 221 except for the surface on the first negative direction X2 side. In other words, the first functional layer 410 is in contact with a surface of the second wiring layer 220 facing a direction parallel to the first main surface 11A. The first functional layer 410 is in contact with a surface of the second wiring layer 220 facing a direction perpendicular to the first main surface 11A.

[0090] The third insulating layer 304 is located in a portion of the fourth layer L4 excluding the second wiring layer 220 and the second function section 412. The material of the third insulating layer 304 is the same as the material of the first insulating layer 301.

[0091] The fifth layer L5 is stacked on the surface of the fourth layer L4 on the first negative direction X2 side. The fifth layer L5 includes a plurality of third vias 530 and a fourth insulating layer 305. Each third via 530 extends in a direction intersecting the first main surface 11A. In this embodiment, each third via 530 penetrates the fifth layer L5 in a direction perpendicular to the first main surface 11A. The material of each third via 530 is the same as the material of the first via 510. Each third via 530 has a substantially truncated cone shape. The diameter of each third via 530 decreases toward the first negative direction X2 side. The end of each third via 530 on the first positive direction X1 side is connected to the second wiring layer 220. The end of each third via 530 on the first negative direction X2 side is exposed from the fifth layer L5. Note that in FIG. 16 , only some of the third vias 530 are labeled with reference numerals.

[0092] The fourth insulating layer 305 is located in a portion of the fifth layer L5 excluding the third vias 530. The fourth insulating layer 305 covers the entire circumferential surface of each third via 530. In other words, the third vias 530 penetrate the fourth insulating layer 305. The material of the fourth insulating layer 305 is the same as the material of the first insulating layer 301.

[0093] The sixth layer L6 is stacked on the surface of the fifth layer L5 on the first negative direction X2 side. The sixth layer L6 includes a plurality of through wires 710 and a core portion 700. Each through wire 710 extends in a direction intersecting the first main surface 11A. In this embodiment, each through wire 710 penetrates the sixth layer L6 in a direction perpendicular to the first main surface 11A. The material of each through wire 710 is the same as the material of the first via 510. Each through wire 710 has a substantially cylindrical shape. The end of each through wire 710 on the first positive direction X1 side is connected to the third via 530. That is, each through wire 710 is connected to the second wiring layer 220 via the third via 530. The end of each through wire 710 on the first negative direction X2 side is exposed from the sixth layer L6. Note that in FIG. 16 , only some of the through wires 710 are labeled with reference numerals.

[0094] The core portion 700 is located in a portion of the sixth layer L6 excluding the through wirings 710. The core portion 700 covers the entire circumferential surface of each through wiring 710. That is, the through wirings 710 penetrate the core portion 700 in a direction perpendicular to the first main surface 11A. In this embodiment, the maximum dimension of the core portion 700 in the direction along the first axis X is greater than the maximum dimension of the first interlayer insulating layer 303 in the direction along the first axis X.

[0095] The core portion 700 is made of a material such as glass cloth, glass filler-containing epoxy resin, glass, or ceramic. The bending strength of the core portion 700 is greater than that of the first interlayer insulating layer 303. The bending strength is measured by a bending strength test conforming to, for example, JIS K6911, ASTM C1161, or F2180. In this test, the core portion 700 to be measured is formed solely from the core portion 700, with the through wiring 710 of the sixth layer L6 removed. In addition, in this test, the first interlayer insulating layer 303 to be measured is formed solely from the first interlayer insulating layer 303, with the first functional portion 411 and the second via 520 of the third layer L3 removed.

[0096] The seventh layer L7 is stacked on the surface of the sixth layer L6 on the first negative direction X2 side. The seventh layer L7 includes a plurality of fourth vias 540 and a fifth insulating layer 306. Each fourth via 540 extends in a direction intersecting the first main surface 11A. In this embodiment, each fourth via 540 penetrates the seventh layer L7 in a direction perpendicular to the first main surface 11A. The material of each fourth via 540 is the same as the material of the first via 510. Each fourth via 540 has a substantially truncated cone shape. The diameter of each fourth via 540 decreases toward the first positive direction X1 side. The end of each fourth via 540 on the first positive direction X1 side is connected to the through wiring 710. The end of each fourth via 540 on the first negative direction X2 side is exposed from the seventh layer L7. Note that in FIG. 16 , only some of the fourth vias 540 are labeled with reference numerals.

[0097] The fifth insulating layer 306 is located in a portion of the seventh layer L7 excluding the fourth vias 540. The fifth insulating layer 306 covers the entire circumferential surface of each fourth via 540. In other words, the fourth vias 540 penetrate the fifth insulating layer 306. The material of the fifth insulating layer 306 is the same as the material of the first insulating layer 301.

[0098] The eighth layer L8 is stacked on the surface of the seventh layer L7 facing the first negative direction X2. The eighth layer L8 includes a third wiring layer 230 and a sixth insulating layer 307. The material of the third wiring layer 230 is the same as the material of the first wiring layer 210. The third wiring layer 230 extends parallel to the first main surface 11A. In this embodiment, the third wiring layer 230 extends in an arbitrary wiring pattern on the eighth layer L8. Note that in FIG. 16 , only some of the third wiring layers 230 are labeled with reference numerals. The third wiring layer 230 is connected to the end of the fourth via 540 facing the first negative direction X2. That is, each through-wire 710 is connected to the third wiring layer 230 via the fourth via 540. In this way, the through wiring 710 penetrates the core portion 700 in a direction perpendicular to the first main surface 11A, and connects the second wiring layer 220 and the third wiring layer 230.

[0099] The sixth insulating layer 307 is located in a portion of the eighth layer L8 excluding the third wiring layer 230. The material of the sixth insulating layer 307 is the same as the material of the first insulating layer 301. The ninth layer L9 is stacked on the surface of the eighth layer L8 facing the first negative direction X2. The ninth layer L9 includes a second functional layer 420, a second interlayer insulating layer 308, and a plurality of fifth vias 550.

[0100] The second functional layer 420 extends parallel to the first main surface 11A. The second functional layer 420 is flat. The maximum dimension of the second functional layer 420 in the direction along the first axis X is smaller than the maximum dimension of the ninth layer L9 in the direction along the first axis X. The second functional layer 420 is not in contact with the eighth layer L8. The second functional layer 420 is not in contact with the tenth layer L10. In other words, the second functional layer 420 is buried in the ninth layer L9.

[0101] Furthermore, in this embodiment, the combined volume of the second functional layer 420 and the first functional layer 410 is less than 0.5 times the volume of the substrate 11. That is, the volume of the first functional layer 410 is less than 0.5 times the volume of the substrate 11. Furthermore, the volume of the second functional layer 420 is less than 0.5 times the volume of the substrate 11. The volumes of the first functional layer 410 and the second functional layer 420 can be measured in the same manner as described in the first embodiment. Note that, in this embodiment, the maximum dimension of the second functional layer 420 in a direction perpendicular to the first main surface 11A is the same as the maximum dimension of the first functional layer 410 in a direction perpendicular to the first axis X.

[0102] Each fifth via 550 extends in a direction intersecting the first main surface 11A. In this embodiment, each fifth via 550 penetrates the ninth layer L9 in a direction perpendicular to the first main surface 11A. The material of each fifth via 550 is the same as the material of the first via 510. Each fifth via 550 is substantially truncated cone-shaped. The diameter of each fifth via 550 decreases toward the first positive direction X1. The end of each fifth via 550 on the first positive direction X1 side is connected to the third wiring layer 230. The end of each fifth via 550 on the first negative direction X2 side is exposed from the ninth layer L9. Note that in FIG. 16, only some of the fifth vias 550 are labeled with reference numerals.

[0103] The second interlayer insulating layer 308 is located in the ninth layer L9 except for the second functional layer 420 and the fifth vias 550. The second interlayer insulating layer 308 covers the entire second functional layer 420. That is, the second functional layer 420 is located inside the second interlayer insulating layer 308. The second interlayer insulating layer 308 is in direct contact with the surface of the eighth layer L8 on the first negative direction X2 side. That is, the second interlayer insulating layer 308 is adjacent to the third wiring layer 230 in the direction perpendicular to the first main surface 11A without any other wiring sandwiched therebetween. The second interlayer insulating layer 308 also covers the entire periphery of each fifth via 550. That is, the fifth via 550 penetrates the second interlayer insulating layer 308. The material of the second interlayer insulating layer 308 is the same as the material of the first insulating layer 301. The relative magnetic permeability of the second interlayer insulating layer 308 is half or less of the relative magnetic permeability of the second functional layer 420. In other words, the relative magnetic permeability of the second functional layer 420 is at least twice the relative magnetic permeability of the second interlayer insulating layer 308.

[0104] The ninth layer L9 does not have any portion with a higher conductivity than the second functional layer 420 other than each fifth via 550. Therefore, when viewed in a direction along the first axis X, the second functional layer 420 overlaps the third wiring layer 230 of the eighth layer L8 without any other wiring therebetween.

[0105] The tenth layer L10 is stacked on the surface of the ninth layer L9 on the first negative direction X2 side. The tenth layer L10 includes a fourth wiring layer 240 and a seventh insulating layer 309. The material of the fourth wiring layer 240 is the same as the material of the first wiring layer 210. The fourth wiring layer 240 extends parallel to the first main surface 11A. The fourth wiring layer 240 includes an inductor wiring 241 and another wiring 242 that is different from the inductor wiring 241. When viewed in a perspective view along the first axis X, a portion of the inductor wiring 241 overlaps the second functional layer 420. The other wiring 242 extends in an arbitrary wiring pattern in the tenth layer L10. Note that in FIG. 16, only some of the other wirings 242 are labeled.

[0106] The seventh insulating layer 309 is located in a portion of the tenth layer L10 excluding the fourth wiring layer 240. The material of the seventh insulating layer 309 is the same as the material of the first insulating layer 301. The eleventh layer L11 is stacked on the surface of the tenth layer L10 on the first negative direction X2 side. That is, the eleventh layer L11 is the layer on the substrate 11 closest to the first negative direction X2 side. The surface of the eleventh layer L11 on the first negative direction X2 side is the second main surface 11B. The eleventh layer L11 includes a plurality of sixth vias 560 and an eighth insulating layer 310.

[0107] Each sixth via 560 extends in a direction intersecting the first main surface 11A. In this embodiment, each sixth via 560 penetrates the eleventh layer L11 in a direction perpendicular to the first main surface 11A. The material of each sixth via 560 is the same as the material of the first via 510. Each sixth via 560 is substantially truncated cone-shaped. The diameter of each sixth via 560 decreases toward the first positive direction X1. The end of each sixth via 560 on the first positive direction X1 side is connected to the fourth wiring layer 240. The end of each sixth via 560 on the first negative direction X2 side is exposed from the eleventh layer L11. That is, the end of each sixth via 560 on the first negative direction X2 side is exposed from the second main surface 11B. Note that in FIG. 16 , only some of the sixth vias 560 are labeled with reference numerals.

[0108] The eighth insulating layer 310 is located in a portion of the eleventh layer L11 excluding the sixth vias 560. The eighth insulating layer 310 covers the entire circumferential surface of each sixth via 560. That is, the sixth vias 560 penetrate the eighth insulating layer 310. The material of the eighth insulating layer 310 is the same as the material of the first insulating layer 301.

[0109] As described above, the substrate 11 includes a first wiring layer 210, a second wiring layer 220, a third wiring layer 230, and a fourth wiring layer 240. The substrate 11 also includes a first interlayer insulating layer 303, a second interlayer insulating layer 308, a first functional layer 410, and a second functional layer 420. The substrate 11 also includes a first via 510 to a sixth via 560 and a through wiring 710. The substrate 11 also includes a core portion 700 inside the substrate 11.

[0110] As described above, the first functional layer 410 and the second functional layer 420 are located on both sides of the core unit 700 in a direction perpendicular to the first main surface 11A. The substrate 11 does not have a layer made of the same material as the second functional layer 420 on the side closer to the first main surface 11A with respect to the core unit 700. Similarly, the substrate 11 does not have a layer made of the same material as the first functional layer 410 on the side farther from the first main surface 11A with respect to the core unit 700. In other words, the first functional layer 410 is located on either the side closer to the first main surface 11A with respect to the core unit 700 or the side farther from the first main surface 11A with respect to the core unit 700. The substrate 11 does not have a layer made of the same material as the first functional layer 410 on the other side closer to the first main surface 11A with respect to the core unit 700 or the side farther from the first main surface 11A with respect to the core unit 700.

[0111] In the present embodiment, the second interlayer insulating layer 308 is located at a different position from the first interlayer insulating layer 303 in a direction perpendicular to the first main surface 11A. The second interlayer insulating layer 308 is located farther from the first main surface 11A than the first interlayer insulating layer 303. The relative dielectric constant of the first functional layer 410 is at least twice the relative dielectric constant of the first interlayer insulating layer 303, and the relative magnetic permeability of the second functional layer 420 is at least twice the relative magnetic permeability of the second interlayer insulating layer 308.

[0112] The substrate 11 further includes a plurality of first external electrodes 610 and a plurality of second external electrodes 620. Each first external electrode 610 is located on the first main surface 11A. Each first external electrode 610 extends parallel to the first main surface 11A. Each first external electrode 610 has a rectangular shape when viewed along the first axis X. Although not shown, each first external electrode 610 has a two-layer structure consisting of a layer primarily composed of Cu and a layer primarily composed of an alloy containing Sn and Ag, arranged in order from the first negative direction X2. Each first external electrode 610 is connected to a first via 510 exposed from the first main surface 11A. Note that in FIG. 16 , only some of the first external electrodes 610 are labeled with reference numerals.

[0113] Each second external electrode 620 is located on the second main surface 11B. Each second external electrode 620 extends in a direction parallel to the second main surface 11B. Each second external electrode 620 has a rectangular shape when viewed along the first axis X. Although not shown, each second external electrode 620 has a two-layer structure consisting of a layer primarily composed of Cu and a layer primarily composed of an alloy containing Sn and Ag, arranged in this order from the first positive direction X1. Each second external electrode 620 is connected to a sixth via 560 exposed from the second main surface 11B. Note that in FIG. 16 , only some of the second external electrodes 620 are labeled with reference numerals.

[0114] The semiconductor package 10 includes multiple connection portions 630, land portions 650, multiple semiconductor devices 100, and underfill 640. Each connection portion 630 is made of a conductive material such as solder. Each connection portion 630 is applied to a corresponding first external electrode 610 or second external electrode 620. In this embodiment, a portion of the second external electrode 620 is not covered by the connection portion 630. The connection portion 630 connected to the first external electrode 610 covers the surface of each first external electrode 610 facing the first positive direction X1. The connection portion 630 connected to the second external electrode 620 covers the surface of each second external electrode 620 facing the first negative direction X2. In FIG. 16 , only some of the connection portions 630 are labeled with reference numerals.

[0115] The land portion 650 is made of a conductive material such as solder. The land portion 650 is applied to the second external electrode 620 that is not covered by the connection portion 630. The land portion 650 covers the surface of the second external electrode 620 on the first negative direction X2 side. The land portion 650 is a member for connecting a motherboard mounted on the second main surface 11B. The volume of the land portion 650 is larger than the volume of the connection portion 630.

[0116] Each semiconductor device 100 is connected to the connection portion 630. That is, the semiconductor device 100 is mounted on the first main surface 11A via the connection portion 630 and the first external electrode 610. Furthermore, the semiconductor device 100 is mounted on the second main surface 11B via the connection portion 630 and the second external electrode 620. In this embodiment, two or more semiconductor devices 100 are mounted on the first main surface 11A. In this embodiment, two or more semiconductor devices 100 are mounted on the second main surface 11B. One or more selected from the semiconductor devices 100 mounted on the first main surface 11A are semiconductor integrated circuits including multiple load circuits. Furthermore, one or more selected from the semiconductor devices 100 mounted on the first main surface 11A are PMICs. Furthermore, one or more selected from the semiconductor devices 100 mounted on the second main surface 11B are PMICs. The maximum dimension of each semiconductor device 100 in a direction perpendicular to the first main surface 11A is smaller than the maximum dimension of the substrate 11 in a direction perpendicular to the first main surface 11A.

[0117] The underfill 640 is located on the first positive direction X1 side with respect to the first main surface 11A and on the first negative direction X2 side with respect to the semiconductor device 100. That is, the underfill 640 covers the periphery of the first external electrode 610 and the connecting portion 630 between the semiconductor device 100 and the first main surface 11A. The material of the underfill 640 is, for example, an epoxy resin. Note that the material of the underfill 640 is not limited to epoxy-based resin, but may also be polyimide-based resin, liquid crystal polymer-based resin, acrylic-based resin, phenol-based resin, or a combination thereof. The underfill 640 may also contain silica filler as an inorganic filler.

[0118] <First Electrode and Second Electrode> As shown in Fig. 17 , the capacitor section Q surrounded by the dashed line in Fig. 16 is viewed in a perspective direction along the first axis X. Note that Fig. 17 illustrates only the first functional layer 410, the first electrode 211, and the second electrode 221.

[0119] 17 , the first wiring layer 210 has four first electrodes 211. When viewed in a perspective view along the first axis X, each first electrode 211 has a rectangular shape with its longer sides aligned with the third axis Z. That is, the first electrode 211 has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. The four first electrodes 211 have the same shape. The four first electrodes 211 are lined up in the direction along the second axis Y at intervals.

[0120] When viewed in a perspective view along the first axis X, the second electrode 221 has a rectangular shape with its longer sides aligned with the second axis Y. That is, the second electrode 221 has a rectangular shape with two sides parallel to the second axis Y and two sides parallel to the third axis Z. When viewed in a perspective view along the first axis X, the second electrode 221 almost completely overlaps with all regions of the four first electrodes 211.

[0121] The first functional layer 410 overlaps the first electrode 211 and the second electrode 221 in the direction along the first axis X, without any other wiring therebetween. Furthermore, when viewed in a see-through manner in the direction along the first axis X, the first functional layer 410 covers the entire second electrode 221. In other words, the four first electrodes 211, second electrodes 221, and first functional layers 410 function as four capacitors.

[0122] As described above, the first functional layer 410 is located across the third layer L3 and the fourth layer L4. In other words, the maximum dimension of the first functional layer 410 in the direction perpendicular to the first main surface 11A is greater than the maximum dimension of the first interlayer insulating layer 303 in the direction perpendicular to the first main surface 11A. In this configuration, a portion of the first functional layer 410 is located in the same position as the first interlayer insulating layer 303 in the direction perpendicular to the first main surface 11A. In this way, even if a portion of the first functional layer 410 is located in another layer and protrudes from the first interlayer insulating layer 303, the first functional layer 410 can be said to be located within the first interlayer insulating layer 303 as long as at least a portion of the first functional layer 410 is located in the same position as the first interlayer insulating layer 303 in the direction perpendicular to the first main surface 11A.

[0123] Advantages of the Second Embodiment (2-1) In the second embodiment, the relative dielectric constant of the first functional layer 410 is at least twice the relative dielectric constant of the first interlayer insulating layer 303. With this configuration, the first functional layer 410 has a relatively high relative dielectric constant, and therefore functions like the core of a capacitor. Furthermore, because the first functional layer 410 extends in a flat plate shape inside the first interlayer insulating layer 303, it is not necessary to excessively increase the dimension of the first functional layer 410 in a direction perpendicular to the first main surface 11A in order to ensure the volume of the first functional layer 410. Therefore, a thin design can be realized while allowing a portion of the substrate 11 to function as a capacitor with desired characteristics.

[0124] (2-2) The first functional layer 410, which has a large relative dielectric constant, functions as an insulator against a DC power supply. Therefore, wiring can be arranged so as to be in contact with the first functional layer 410. In the second embodiment, the first functional layer 410 is in contact with a surface of the second wiring layer 220 that faces a direction parallel to the first main surface 11A. With this configuration, it is not necessary to arrange the first wiring layer 210 so as to avoid the first functional layer 410, and therefore it is possible to prevent the dimension of the substrate 11 in the direction parallel to the first main surface 11A from increasing.

[0125] (2-3) In the second embodiment, the first functional layer 410 is in contact with a surface of the first wiring layer 210 facing the first negative direction X2 and a surface of the second wiring layer 220 facing the first positive direction X1. With this configuration, similar to (2-2) above, it is not necessary to arrange the wiring layers so as to avoid the first functional layer 410, and therefore it is possible to prevent the dimension of the substrate 11 in the direction perpendicular to the first main surface 11A from increasing. Furthermore, it is possible to increase the proportion of the first functional layer 410 between the second electrode 221 and each first electrode 211, thereby improving the characteristics as a capacitor.

[0126] (2-4) In the second embodiment, one or more semiconductor devices 100 are mounted on the first main surface 11A, and one or more semiconductor devices 100, specifically, PMICs as semiconductor switches, are mounted on the second main surface 11B. From the viewpoint of mounting the semiconductor devices 100 on both the first positive direction X1 side and the first negative direction X2 side of the semiconductor package 10, according to the above configuration, the semiconductor devices 100 are mounted on both main surfaces of the substrate 11, so that the semiconductor package 10 can be made smaller than when different substrates are bonded together.

[0127] (2-5) In the second embodiment, a PMIC is mounted on the second main surface 11B as the semiconductor device 100. Also, a land portion 650 for mounting a motherboard is located on the second main surface 11B. In this configuration, the motherboard can be connected to the land portion 650. When power is supplied by the motherboard, this configuration is suitable for power control because the motherboard and the PMIC are located on the same side of the second main surface 11B.

[0128] (2-6) In the second embodiment, the relative dielectric constant of the first functional layer 410 is at least twice that of the first interlayer insulating layer 303. That is, the first functional layer 410, the first electrode 211, and the second electrode 221 function as a capacitor. Furthermore, the relative permeability of the second functional layer 420 is at least twice that of the second interlayer insulating layer 308. That is, the second functional layer 420 and the inductor wiring 241 function as an inductor. Furthermore, the second interlayer insulating layer 308 is located farther from the first main surface 11A than the first interlayer insulating layer 303. With this configuration, when a motherboard is connected to the land portion 650 and a current is passed through the semiconductor package 10, the current flows from the side closer to the second main surface 11B toward the first main surface 11A. That is, with the above configuration, the current is supplied in the following order: the inductor, the capacitor, and the semiconductor device 100 mounted on the first main surface 11A. This configuration can prevent the wiring resistance from increasing.

[0129] (2-7) In the second embodiment, a PMIC is mounted on the second main surface 11B as the semiconductor device 100. Furthermore, a semiconductor integrated circuit including a plurality of load circuits is mounted on the first main surface 11A as the semiconductor device 100. Furthermore, a PMIC is mounted on the first main surface 11A as the semiconductor device 100. With this configuration, the semiconductor package 10 has at least two PMICs, and thus can supply greater power to the semiconductor integrated circuit.

[0130] (2-8) In the second embodiment, the substrate 11 includes a core portion 700 inside the substrate 11, the core portion 700 having a bending strength greater than that of the first interlayer insulating layer 303. This configuration allows the substrate 11 to have an improved bending strength as a whole, compared to a configuration that does not include the core portion 700.

[0131] (2-9) In the second embodiment, the substrate 11 does not have a layer made of the same material as the first functional layer 410 on either the side closer to the first main surface 11A with respect to the core unit 700 or the side farther from the first main surface 11A with respect to the core unit 700. There is a risk that parasitic capacitance will be generated in unintended locations due to the first functional layer 410 and the wiring located around the first functional layer 410. According to the above configuration, by arranging a layer corresponding to the first functional layer 410 only on one side with respect to the core unit 700, it is possible to suppress the generation of parasitic capacitance in unintended locations.

[0132] <Modifications> The above-described first and second embodiments can be modified as follows. The above-described first and second embodiments and the following modifications can be combined and implemented to the extent that no technical contradiction occurs. Note that in the modifications shown in FIGS. 18 to 23 below, descriptions of parts having the same configuration as the first and second embodiments may be omitted or simplified. Note that in FIGS. 18 to 23, some of the reference numerals may be omitted for parts having the same configuration as the first and second embodiments.

[0133] 18 In the first and second embodiments, the first functional layers 41, 410 may be exposed from the substrate 11 in a direction parallel to the first main surface 11A. This also applies to the other functional layers.

[0134] 18 , the substrate 11 includes a first layer L1. The first layer L1 is located closest to the first positive direction X1 in the substrate 11. The first layer L1 includes a first interlayer insulating layer 81, a plurality of first vias 51, and a first functional layer 41. The first functional layer 41 is exposed from both end faces of the substrate 11 in a direction parallel to the first main surface 11A. Specifically, the first functional layer 41 extends across the entire area of ​​the substrate 11 in a direction perpendicular to the first positive direction X1.

[0135] 18 , the first via 51 penetrates the first layer L1 in a direction perpendicular to the first main surface 11A. The first interlayer insulating layer 81 is located in a portion of the first layer L1 excluding the first via 51 and the first functional layer 41. That is, in the example shown in FIG. 18 , the first via 51 penetrates the first interlayer insulating layer 81 in a direction perpendicular to the first main surface 11A. The first via 51 also penetrates the first functional layer 41 in a direction perpendicular to the first main surface 11A. The first functional layer 41 is sandwiched between the first interlayer insulating layers 81 on both sides in a direction perpendicular to the first main surface 11A. Therefore, the first functional layer 41 is located inside the first interlayer insulating layer 81.

[0136] According to this configuration, when forming the first functional layer 41, there is no need to perform complex processing on the shape of the first functional layer 41. Note that in the area shown as region A in FIG. 18 , wiring layers, vias, insulating layers, etc. are arranged in any pattern. Furthermore, the area shown as region A may also include functional layers, electrodes, core portions, and other components. Detailed illustration of this region A is omitted.

[0137] <Regarding the Modification Example Shown in FIG. 19> In the first and second embodiments, the circumferential surface of the via may be covered with another member.

[0138] In the first and second embodiments, a wiring layer may be provided in the same location as the first functional layer 41, 410 in the direction perpendicular to the first main surface 11A. This also applies to the other functional layers.

[0139] In the first and second embodiments, the semiconductor device 100, the connecting portions 62, 630, and the external electrodes may be entirely covered with a resin mold. In the first and second embodiments, the semiconductor package 10 may further include a heat dissipation sheet.

[0140] 19 , the substrate 11 includes a second layer L2, a first layer L1, a third layer L3, and a fourth layer L4, arranged in order from the first positive direction X1. The first layer L1 includes a first wiring layer 21 and a first insulating layer 91. The first wiring layer 21 includes an inductor wiring 21A and a first electrode 21B that are not connected to each other within the first layer L1 where the first wiring layer 21 is located. The first wiring layer 21 also includes another wiring 21C that is different from the inductor wiring 21A and the first electrode 21B. The other wiring 21C extends in an arbitrary pattern within the first layer L1. The first insulating layer 91 is located in a portion of the first layer L1 excluding the first wiring layer 21.

[0141] The second layer L2 includes a first interlayer insulating layer 81, a plurality of first vias 51, an insulating material NC, a first functional layer 41, and a third wiring layer 23. The first functional layer 41 is exposed from the end face of the substrate 11 on the second negative direction Y2 side in a direction parallel to the first main surface 11A. The relative permeability of the first functional layer 41 is at least twice that of the first interlayer insulating layer 81. When viewed through a perspective view in a direction perpendicular to the first main surface 11A, the first functional layer 41 overlaps the inductor wiring 21A without any other wiring sandwiched therebetween. In other words, the first functional layer 41 and the inductor wiring 21A function as an inductor.

[0142] The first vias 51 penetrate the second layer L2 in a direction perpendicular to the first main surface 11A. One or more selected from the plurality of first vias 51 penetrate the first functional layer 41 in a direction perpendicular to the first main surface 11A. The insulating material NC covers the circumferential surface of the first vias 51 penetrating the first functional layer 41. The insulating material NC has higher insulating properties than the first functional layer 41. In the example shown in FIG. 19 , the insulating material NC is an epoxy resin containing a glass filler. The material of the insulating material NC is not limited to this and may be the same as the material of the first insulating layer 31 in the first embodiment, for example. In the example shown in FIG. 19 , the presence of the insulating material NC improves the insulating properties of the first vias 51.

[0143] The third wiring layer 23 is located at the same location as the first functional layer 41 in a direction perpendicular to the first main surface 11A. In the example shown in FIG. 19 , the material of the third wiring layer 23 is the same as the material of the first wiring layer 21 in the first embodiment. However, the material of the third wiring layer 23 is not limited to this example. By arranging wiring in the same layer as the first functional layer 41 in this way, the wiring density within the substrate 11 can be improved. In other words, there is no need to arrange wiring in the same layer as the first functional layer 41, and an increase in the dimension of the substrate 11 in a direction perpendicular to the first main surface 11A can be suppressed.

[0144] The fourth layer L4 includes a second wiring layer 22 and a second insulating layer 92. The second wiring layer 22 includes a second electrode 22A and another wiring 22B that is different from the second electrode 22A. The second insulating layer 92 is located in a portion of the fourth layer L4 excluding the second wiring layer 22.

[0145] The third layer L3 includes a second interlayer insulating layer 82, a plurality of second vias 52, a second functional layer 42, and an insulating material NC. The second functional layer 42 includes a first functional portion 42A and a second functional portion 42B that are not connected to each other within the layer in which the second functional layer 42 is located. The first functional portion 42A is made of an organic resin containing magnetic powder. The relative permeability of the first functional portion 42A is at least twice that of the second interlayer insulating layer 82. When viewed in a direction perpendicular to the first main surface 11A, the first functional portion 42A overlaps the inductor wiring 21A without any other wiring sandwiched therebetween. In other words, the first functional portion 42A and the inductor wiring 21A function as an inductor.

[0146] The second functional unit 42B is made of an organic resin containing an inorganic filler. The dielectric constant of the second functional unit 42B is at least twice that of the second interlayer insulating layer 82. That is, the material of the first functional unit 42A is different from the material of the second functional unit 42B. When viewed through a perspective view in a direction perpendicular to the first main surface 11A, the second functional unit 42B overlaps the first electrode 21B and the second electrode 22A without any wiring therebetween. That is, the second functional unit 42B, the first electrode 21B, and the second electrode 22A function as a capacitor. This configuration allows both an inductor and a capacitor to be disposed within the substrate 11.

[0147] The second vias 52 also penetrate the third layer L3. One or more selected from the plurality of second vias 52 have their peripheral surfaces covered with an insulating material NC. The insulating material NC is the same as that described above. In the example shown in FIG. 19 , the first vias 51 and the insulating material NC covering the peripheral surfaces of the first vias 51 may penetrate the first layer L1 and directly contact the second vias 52.

[0148] A plurality of semiconductor devices 100 are mounted on the first main surface 11A via external electrodes 63 and connecting portions 62. In the example shown in FIG. 19 , the semiconductor package 10 includes a resin mold 660 and a heat dissipation sheet 670. The resin mold 660 covers the entire peripheral surfaces of the semiconductor devices 100, the external electrodes 63, and the connecting portions 62. The surface of the semiconductor device 100 facing the first positive direction X1 is not covered by the resin mold 660. The resin mold 660 is made of, for example, an epoxy-based resin. The resin mold 660 may also be made of a polyimide-based resin, a liquid crystal polymer-based resin, an acrylic-based resin, a phenol-based resin, or a combination thereof. The resin mold 660 may also contain an inorganic filler such as silica filler.

[0149] The heat dissipation sheet 670 covers the entire surfaces of the semiconductor devices 100 on the first positive direction X1 side. The heat dissipation sheet 670 is a resin sheet having thermal conductivity. The heat dissipation sheet 670 can efficiently absorb heat from the semiconductor devices 100 and dissipate the heat to the outside. In addition, in the area shown as region A in FIG. 19, wiring layers, vias, insulating layers, etc. are arranged in any pattern. In addition, the area shown as region A may also include functional layers, electrodes, core parts, and other components. Detailed illustration of this portion of region A is omitted.

[0150] 20 and 21 In the first embodiment, the shapes of the first inductor wiring 21A and the second inductor wiring 22A are not limited to those in the example of the first embodiment. Also, in the first embodiment, the number of turns of each inductor wiring is not limited to 0.5 turns or less.

[0151] In the first and second embodiments, the maximum dimension of the substrate 11 in a direction perpendicular to the first main surface 11A may be the same as or larger than the maximum dimension of the semiconductor device 100 in a direction perpendicular to the first main surface 11A.

[0152] In the second embodiment, the number of lands 650 is not limited to the example in the second embodiment. In the second embodiment, the semiconductor package 10 may further include a resin mold 660 in addition to the underfill 640.

[0153] 20 , the substrate 11 includes a first layer L1, a second layer L2, and a third layer L3, arranged in this order from the side of the first positive direction X1. The first layer L1 includes a first wiring layer 21 and a first insulating layer 91. The first wiring layer 21 includes a first inductor wiring 21A as a first wiring portion. The first wiring layer 21 also includes other wiring 21B. The other wiring 21B extends in an arbitrary pattern in the first layer L1. The first insulating layer 91 is located in a portion of the first layer L1 excluding the first wiring layer 21.

[0154] The second layer L2 includes a first functional layer 41, a first via 51, and a first interlayer insulating layer 81. When viewed in a direction perpendicular to the first main surface 11A, the first functional layer 41 overlaps the first inductor wiring 21A of the first wiring layer 21 without any other wiring therebetween. The relative permeability of the first functional layer 41 is at least twice the relative permeability of the first interlayer insulating layer 81. The first via 51 penetrates the second layer L2. The first interlayer insulating layer 81 is located in a portion of the second layer L2 excluding the first wiring layer 21.

[0155] The third layer L3 includes a second wiring layer 22 and a second insulating layer 92. The second wiring layer 22 extends parallel to the first main surface 11A. That is, the second wiring layer 22 is located on the opposite side of the first wiring layer 21 with the first interlayer insulating layer 81 sandwiched therebetween. The second wiring layer 22 includes a second inductor wiring 22A as a second wiring portion. When viewed through in a direction perpendicular to the first main surface 11A, the first functional layer 41 overlaps the second inductor wiring 22A of the second wiring layer 22 without any other wiring therebetween.

[0156] The second wiring layer 22 further includes other wiring 22B. The other wiring 22B extends in an arbitrary pattern in the third layer L3. The first via 51 penetrates the first interlayer insulating layer 81 to connect the first wiring layer 21 and the second wiring layer 22. The second insulating layer 92 is located in a portion of the third layer L3 excluding the second wiring layer 22.

[0157] 20, the maximum dimension of the substrate 11 in a direction perpendicular to the first main surface 11A is smaller than the maximum dimension of the semiconductor device 100 mounted on the first main surface 11A in a direction perpendicular to the first main surface 11A. With this configuration, the dimension of the semiconductor device 100 in a direction perpendicular to the first main surface 11A is relatively large, thereby reducing the thermal resistance of the semiconductor device 100. Note that in the area shown as region A in FIG. 20, wiring layers, vias, insulating layers, and the like are arranged in any pattern. Furthermore, the area shown as region A may also include functional layers, electrodes, core portions, and other components. Detailed illustration of this region A is omitted.

[0158] 21, the inductor portion R surrounded by the dashed line in Fig. 20 is viewed in a perspective direction along the first axis X. Note that Fig. 21 illustrates only the first functional layer 41, the first inductor wiring 21A, the second inductor wiring 22A, and some of the first vias 51.

[0159] The first wiring layer 21 has five first inductor wirings 21A. Each of the first inductor wirings 21A extends parallel to the third axis Z. The first inductor wirings 21A are lined up in a direction along the second axis Y. The second wiring layer 22 has four second inductor wirings 22A. Each of the second inductor wirings 22A extends along the third axis Z as a whole.

[0160] The first inductor wiring 21A, the second inductor wiring 22A, and the plurality of first vias 51 form a continuous built-in inductor extending from a first end on the second positive direction Y1 side to a second end on the second negative direction Y2 side. That is, the inductor portion R functions as a built-in inductor.

[0161] Here, the five first inductor wirings 21A are designated, in order from the second positive direction Y1 side, as a first line W1, a second line W2, a third line W3, a fourth line W4, and a fifth line W5. The four second inductor wirings 22A are designated, in order from the second positive direction Y1 side, as a sixth line W6, a seventh line W7, an eighth line W8, and a ninth line W9.

[0162] The first line W1 is connected to the sixth line W6 via five first vias 51. The five first vias 51 are aligned in a direction along the third axis Z. The end of the sixth line W6 on the third negative direction Z2 side is connected to the end of the second line W2 on the third negative direction Z2 side via the first vias 51. The end of the second line W2 on the third positive direction Z1 side is connected to the end of the seventh line W7 on the third positive direction Z1 side via the first vias 51. The end of the seventh line W7 on the third negative direction Z2 side is connected to the end of the third line W3 on the third negative direction Z2 side via the first vias 51. The end of the third line W3 on the third positive direction Z1 side is connected to the end of the eighth line W8 on the third positive direction Z1 side via the first vias 51. The end of the eighth line W8 on the third negative direction Z2 side is connected to the end of the fourth line W4 on the third negative direction Z2 side via the first vias 51. The end of the fourth line W4 on the third positive direction Z1 side is connected to the end of the ninth line W9 on the third positive direction Z1 side via the first vias 51. The ninth line W9 is also connected to the fifth line W5 via five first vias 51.

[0163] The first functional layer 41 is surrounded by the first vias 51. That is, at least a portion of the built-in inductor extends spirally to surround the first functional layer 41 by connecting the first wiring portion, the first vias 51, the second wiring portion, and the first vias 51 in this order. Here, the first wiring portion is the first inductor wiring 21A. The second wiring portion is the second inductor wiring 22A. The five first vias 51 connected to the first line W1 are located on the second positive direction Y1 side of the first functional layer 41. The five first vias 51 connected to the fifth line W5 are located on the second negative direction Y2 side of the first functional layer 41. That is, in the built-in inductor, the first vias 51 connected closest to the first end and the first vias 51 connected closest to the second end are located on both sides of the first functional layer 41 in the direction along the central axis C of the built-in inductor. In FIG. 21, for convenience, the first inductor wiring 21A is illustrated by dots.

[0164] <Regarding the Modification Shown in FIG. 22> In the first and second embodiments, the substrate 11 may include a passive component 800 therein.

[0165] 22 , the substrate 11 includes a first layer L1. The first layer L1 includes a through wiring 710, a core portion 700, a passive component 800, a plurality of lead wirings 810, and a first insulating layer 91.

[0166] The through wirings 710 extend in a direction intersecting the first main surface 11A. Each through wiring 710 penetrates the first layer L1 in a direction perpendicular to the first main surface 11A. The core portion 700 covers the entire periphery of each through wiring 710. That is, the through wiring 710 penetrates the core portion 700 in a direction perpendicular to the first main surface 11A. In the example shown in FIG. 22 , the core portion 700 has a through hole 720 that penetrates the core portion 700 in a direction along the first axis X.

[0167] The passive component 800 is located at the same location as the core section 700 in a direction perpendicular to the first main surface 11A. Specifically, the passive component 800 is located inside the through-hole 720 of the core section 700. Note that the passive component 800 is not in contact with the through-hole 720 in a direction parallel to the first main surface 11A. The passive component 800 is an inductor component, a capacitor component, an IPD (integrated passive device), or the like. Note that the inductor component may include multiple inductors or may include only one inductor. This also applies to the capacitor component.

[0168] Each of the lead-out wirings 810 extends from the passive component 800 in a direction perpendicular to the first main surface 11A. Specifically, the lead-out wirings 810 extend from the first positive direction X1 side of the passive component 800 toward the first positive direction X1 side. The material of the lead-out wirings 810 is the same as the material of the first wiring layer 21 in the first embodiment. Although not shown, the lead-out wirings 810 are connected to vias or wiring layers adjacent to the first positive direction X1 side. With this configuration, it is not necessary to align the wiring layer with the layout of the passive component 800, and connection to the wiring layer is possible via the lead-out wirings 810. In other words, with this configuration, the degree of freedom in designing the wiring layer is improved.

[0169] The first insulating layer 91 is located in a portion of the first layer L1 excluding the through wiring 710, the core portion 700, the passive components 800, and the plurality of lead-out wirings 810. In other words, the first insulating layer 91 fills the periphery of the passive components 800 and the lead-out wirings 810 inside the through hole 720 of the core portion 700.

[0170] 22, there may be multiple passive components 800. In the example shown in FIG. 22, the relationship between the maximum dimension of the passive component 800 in the direction orthogonal to the first main surface 11A and the maximum dimension of the core section 700 in the direction orthogonal to the first main surface 11A is not limited to the above example. However, in order to maintain the flatness of the first layer L1 during the manufacturing process, the maximum dimension of the passive component 800 in the direction orthogonal to the first main surface 11A is preferably greater than 0.7 times and less than 1.3 times the maximum dimension of the core section 700 in the direction orthogonal to the first main surface 11A. From the viewpoint of maintaining the flatness of the first layer L1 during the manufacturing process, the dimensional difference between the passive component 800 and the core section 700 in the direction orthogonal to the first main surface 11A is preferably less than 10%, and more preferably less than 5%.

[0171] In addition, in the area shown as region A in Figure 22, wiring layers, vias, insulating layers, etc. are arranged in any pattern. Furthermore, the area shown as region A may also include functional layers, electrodes, core parts, and other components. Detailed illustration of this region A is omitted. As the configuration of the region A, for example, a substrate including a first functional layer 41, like the substrate 11 of the first embodiment, can be applied.

[0172] <Regarding the modified example shown in Figure 23> - In the first and second embodiments, the maximum dimension of the first functional layer 41, 410 in a direction perpendicular to the first main surface 11A may be larger than the maximum dimension of the first wiring layer 21, 210 in a direction perpendicular to the first main surface 11A.

[0173] - In the example shown in Figure 19, in addition to the third wiring layer 23, the substrate 11 may have a wiring layer located in the same location as the first functional layer 41, but at a different location from the third wiring layer 23 in a direction perpendicular to the first main surface 11A.

[0174] 22 , the passive component 800 may be in contact with the core portion 700 in a direction parallel to the first main surface 11A. For example, in the example shown in Fig. 23 , the substrate 11 includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, a fifth layer L5, a sixth layer L6, a seventh layer L7, an eighth layer L8, and a ninth layer L9, which are arranged in this order from the first positive direction X1 side.

[0175] The first layer L1 includes a first wiring layer 21 and a first insulating layer 91. The first wiring layer 21 extends in an arbitrary pattern in the first layer L1. The first insulating layer 91 is located in a portion of the first layer L1 excluding the first wiring layer 21.

[0176] The second layer L2 includes a first via 51 and a first interlayer insulating layer 81. The first via 51 penetrates the second layer L2. The first interlayer insulating layer 81 is located in a portion of the second layer L2 excluding the first via 51.

[0177] The seventh layer L7 includes a second wiring layer 22 and a second insulating layer 92. The second wiring layer 22 extends in an arbitrary pattern in the seventh layer L7. The second insulating layer 92 is located in a portion of the seventh layer L7 excluding the second wiring layer 22.

[0178] The sixth layer L6 includes a second via 52 and a second interlayer insulating layer 82. The second via 52 penetrates the second layer L2. The second interlayer insulating layer 82 is located in a portion of the sixth layer L6 excluding the second via 52.

[0179] The third layer L3 includes a first functional unit 41A that is a part of the first functional layer 41, a third wiring layer 23, and a third insulating layer 93. When viewed in a direction perpendicular to the first main surface 11A, the first functional unit 41A overlaps the first wiring layer 21 without any other wiring therebetween.

[0180] The third wiring layer 23 extends parallel to the first main surface 11A. That is, the third wiring layer 23 is a wiring layer located at a different location from the first wiring layer 21 in the direction perpendicular to the first main surface 11A. The third wiring layer 23 is located at the same location as the first functional section 41A of the first functional layer 41 in the direction perpendicular to the first main surface 11A. The maximum dimension of the third wiring layer 23 in the direction perpendicular to the first main surface 11A is the same as the maximum dimension of the first wiring layer 21 in the direction perpendicular to the first main surface 11A. The third insulating layer 93 is located in a portion of the third layer L3 excluding the third wiring layer 23.

[0181] The fourth layer L4 includes a second functional unit 41B that is part of the first functional layer 41, a third via 53, and a third interlayer insulating layer 83. The second functional unit 41B is connected to the first negative direction X2 side of the first functional unit 41A. The third via 53 penetrates the fourth layer L4. The third interlayer insulating layer 83 is located in a portion of the fourth layer L4 excluding the third via 53. Note that, as in the example shown in FIG. 23 , if a portion of the first functional layer 41 is located inside the third interlayer insulating layer 83, it can be said that the first functional layer 41 "extends inside the interlayer insulating layer."

[0182] The fifth layer L5 includes a third functional unit 41C that is part of the first functional layer 41, a fourth wiring layer 24, and a fourth insulating layer 94. The third functional unit 41C is connected to the second functional unit 41B in the first negative direction X2. That is, when viewed through the first functional layer 41 including the first functional units 41A to 41C in a direction perpendicular to the first main surface 11A, the first functional layer 41 overlaps the first wiring layer 21 without any other wiring therebetween. The relative magnetic permeability of the first functional layer 41 is at least twice the relative magnetic permeability of the first interlayer insulating layer 81.

[0183] The fourth wiring layer 24 extends parallel to the first main surface 11A. That is, the fourth wiring layer 24 is a wiring layer located at a different location from the first wiring layer 21 in a direction perpendicular to the first main surface 11A. The fourth wiring layer 24 is located at the same location as the third functional section 41C of the first functional layer 41 in a direction perpendicular to the first main surface 11A. The maximum dimension of the fourth wiring layer 24 in a direction perpendicular to the first main surface 11A is the same as the maximum dimension of the first wiring layer 21 in a direction perpendicular to the first main surface 11A. The fourth insulating layer 94 is located in a portion of the fifth layer L5 excluding the fourth wiring layer 24. In this way, the first functional layer 41 spans the third layer L3, the fourth layer L4, and the fifth layer L5. That is, the maximum dimension of the first functional layer 41 in the direction orthogonal to the first main surface 11A is the same as the maximum dimension of the third wiring layer 23, the fourth wiring layer 24, and the third via 53 combined in the direction orthogonal to the first main surface 11A. In other words, the maximum dimension of the first functional layer 41 in the direction orthogonal to the first main surface 11A is the same as the sum of twice the maximum dimension of the third wiring layer 23 in the direction orthogonal to the first main surface 11A and one time the maximum dimension of the third interlayer insulating layer 83 in the direction orthogonal to the first main surface 11A. That is, the maximum dimension of the first functional layer 41 in the direction orthogonal to the first main surface 11A is at least twice the maximum dimension of the first wiring layer 21 in the direction orthogonal to the first main surface 11A. 23 , if the maximum dimension of the first functional layer 41 in the direction perpendicular to the first main surface 11A is the same as the sum of an integer multiple of the maximum dimension of the third wiring layer 23 in the direction perpendicular to the first main surface 11A and an integer multiple of the maximum dimension of the third interlayer insulating layer 83 in the direction perpendicular to the first main surface 11A, the first functional layer 41 can be formed together with an insulating layer in the same layer as the wiring layer and an interlayer insulating layer. In other words, because the insulating layer is formed to match the thickness of the first functional layer 41, the flatness is not significantly impaired during the manufacturing process, such as when only the first functional layer 41 protrudes.

[0184] The eighth layer L8 includes a fourth via 54 and a fifth insulating layer 95. The fourth via 54 penetrates the eighth layer L8. The fifth insulating layer 95 is located in a portion of the eighth layer L8 excluding the fourth via 54.

[0185] The ninth layer L9 includes a through wiring 710, a core portion 700, a passive component 800, and a plurality of lead wirings 810. The through wiring 710 extends in a direction intersecting with the first main surface 11A. The through wiring 710 penetrates the ninth layer L9 in a direction perpendicular to the first main surface 11A.

[0186] The passive component 800 is located at the same location as the through wiring 710 in a direction perpendicular to the first main surface 11A. A portion of the lead wiring 810 extends from the first positive direction X1 side of the passive component 800 toward the first positive direction X1 side. In addition, a portion of the lead wiring 810 extends from the first negative direction X2 side of the passive component 800 toward the first negative direction X2 side.

[0187] The core portion 700 is located in a location on the ninth layer L9 excluding the through wirings 710, the passive components 800, and the lead wirings 810. That is, the through wirings 710 penetrate the core portion 700 in a direction perpendicular to the first main surface 11A. The passive components 800 are in contact with the core portion 700 in a direction parallel to the first main surface 11A.

[0188] 23, wiring layers, vias, insulating layers, etc. are arranged in any pattern in the area shown as area A. Functional layers, electrodes, core parts, and other components may also be included in the area shown as area A. Detailed illustration of this area A is omitted.

[0189] <Other Modifications> In the first and second embodiments, the number of semiconductor devices 100 mounted on the first main surface 11A is not limited. Similarly, the number of semiconductor devices 100 mounted on the second main surface 11B is not limited. Furthermore, the types of semiconductor devices 100 mounted on each main surface are not limited.

[0190] In the first and second embodiments, it is sufficient that the volume of at least the first functional layers 41, 410 is 0.5 times or less the volume of the substrate 11. The same applies to the second functional layers 42, 420. That is, the combined volume of the second functional layers 42, 420 and the first functional layers 41, 410 may be greater than 0.5 times the volume of the substrate 11. Note that as long as the volume of each functional layer is sufficiently smaller than the volume of the substrate 11, the effect described in (1-6) above is achieved.

[0191] In the first embodiment, the substrate 11 only needs to include at least the first wiring layer 21, the first interlayer insulating layer 32, and the first functional layer 41 having a relative permeability at least twice that of the first interlayer insulating layer 32. Other wiring, insulating layers, vias, electrodes, etc. may be changed as appropriate.

[0192] In the first embodiment, the maximum dimension of the first functional layer 41 in the direction perpendicular to the first main surface 11A may be different from the maximum dimension of the second functional layer 42 in the direction perpendicular to the first main surface 11A. In the first embodiment, the relative permeability of the first functional layer 41 may be smaller than 5. This is also true for the second functional layer 420 in the second embodiment.

[0193] In the first embodiment, the material of the first functional layer 41 may have magnetic anisotropy. Furthermore, the first virtual line V1 and the second virtual line V2 may extend parallel to each other. That is, the first inductor wiring 21A and the second inductor wiring 21B may extend parallel to each other.

[0194] In the second embodiment, the substrate 11 only needs to include at least a first wiring layer 210, a second wiring layer 220, a first interlayer insulating layer 303 located between the first wiring layer 210 and the second wiring layer 220, and a first functional layer 410 having a relative dielectric constant that is at least twice that of the first interlayer insulating layer 303. In the second embodiment, the number of first electrodes 211 only needs to be at least one.

[0195] In the second embodiment, the first functional layer 410 may be in contact with a surface of the first electrode 211 that faces in a direction parallel to the first major surface 11A. In addition, in the second embodiment, the first functional layer 410 does not have to be in contact with a surface of both the first electrode 211 and the second electrode 221 that faces in a direction parallel to the first major surface 11A.

[0196] In the second embodiment, the first functional layer 410 does not have to be in contact with the surfaces of both the first electrode 211 and the second electrode 221 that are orthogonal to the first main surface 11A. Alternatively, the first functional layer 410 may be in contact with the surface of either the first electrode 211 or the second electrode 221 that is orthogonal to the first main surface 11A.

[0197] In the second embodiment, the semiconductor package 10 does not have to include the land portion 650. In the second embodiment, the second interlayer insulating layer 308 may be located closer to the first main surface 11A than the first interlayer insulating layer 303. In other words, when a current is passed from the second main surface 11B side, the current may flow through the capacitor and then the inductor.

[0198] In the second embodiment, the maximum dimension of the core portion 700 in the direction along the first axis X may be smaller than the maximum dimension of the first interlayer insulating layer 303 in the direction along the first axis X. In this case, however, it is preferable to select a material for the core portion 700 such that the bending strength of the core portion 700 is greater than that of the first interlayer insulating layer 303. Furthermore, the bending strength of the core portion 700 may be smaller than the bending strength of the first interlayer insulating layer 303.

[0199] In the second embodiment, the substrate 11 does not need to include the through wiring 710. The through wiring 710, that is, the through wiring 710 on the first main surface 11A side and the second main surface 11B side with respect to the core portion 700 may function as different components.

[0200] In the second embodiment, the substrate 11 may have a layer made of the same material as the first functional layer 410 on the side of the core portion 700 farther from the first main surface 11A. Similarly, the substrate 11 may have a layer made of the same material as the second functional layer 420 on the side of the core portion 700 closer to the first main surface 11A.

[0201]

[0013] <Supplementary Notes> The following describes technical ideas that can be understood from the above-described embodiments and modified examples. [1] A semiconductor package comprising: a substrate having a first main surface; and a semiconductor device mounted on the first main surface, wherein the substrate has a first wiring layer extending parallel to the first main surface, a first interlayer insulating layer located at a position different from the first wiring layer in a direction perpendicular to the first main surface, and a flat first functional layer extending parallel to the first main surface within the first interlayer insulating layer, wherein, when viewed in a see-through manner in the direction perpendicular to the first main surface, the first functional layer overlaps the first wiring layer without any other wiring therebetween, a volume of the first functional layer is 0.5 times or less the volume of the substrate, and a relative magnetic permeability of the first functional layer is two or more times the relative magnetic permeability of the first interlayer insulating layer.

[0202] [2] The semiconductor package described in [1], wherein the first wiring layer has a first inductor wiring, the number of turns of the first inductor wiring is 0.5 turns or less, and the relative permeability of the first functional layer is 5 or more.

[0203] [3] The first wiring layer has a first inductor wiring and a second inductor wiring that are not connected to each other within the layer in which the first wiring layer is located, the number of turns of the first inductor wiring is 0.5 turns or less, the number of turns of the second inductor wiring is 0.5 turns or less, the material of the first functional layer does not have magnetic anisotropy, and when a first virtual line passing through a first line end and a second line end of the first inductor wiring is imagined and a second virtual line passing through the first line end and the second line end of the second inductor wiring is imagined, the first virtual line and the second virtual line intersect with each other.

[0204] [4] The substrate has a second wiring layer located on the opposite side of the first wiring layer with the first interlayer insulating layer sandwiched therebetween, extending parallel to the first main surface, and a plurality of vias penetrating the first interlayer insulating layer to connect the first wiring layer and the second wiring layer, the first wiring layer having a first wiring portion, the second wiring layer having a second wiring portion, the first wiring portion, the second wiring portion, and the plurality of vias forming a continuous built-in inductor extending from a first end to a second end, at least a portion of the built-in inductor extending spirally to surround the first functional layer by connecting the first wiring portion, the via, the second wiring portion, and the via in this order, and the via connected furthest to the first end and the via connected furthest to the second end are located on both sides of the first functional layer in between in a direction along the central axis of the built-in inductor.

[0205] [5] A semiconductor package comprising: a substrate having a first main surface; and a semiconductor device mounted on the first main surface, wherein the substrate has a first wiring layer extending parallel to the first main surface; a second wiring layer located at a different location from the first wiring layer in a direction perpendicular to the first main surface and extending parallel to the first main surface; a first interlayer insulating layer located between the first wiring layer and the second wiring layer; and a flat first functional layer extending parallel to the first main surface within the first interlayer insulating layer, wherein when viewed in a direction perpendicular to the first main surface, the first functional layer overlaps the first wiring layer and the second wiring layer without any other wiring therebetween, and the volume of the first functional layer is 0.5 times or less the volume of the substrate, and the dielectric constant of the first functional layer is at least twice the dielectric constant of the first interlayer insulating layer.

[0206] [6] The semiconductor package described in [5], wherein the first functional layer is in contact with one or more surfaces selected from a surface of the first wiring layer facing in a direction parallel to the first main surface and a surface of the second wiring layer facing in a direction parallel to the first main surface.

[0207] [7] A semiconductor package described in [5] or [6], wherein the first functional layer is in contact with one or more surfaces selected from a surface of the first wiring layer facing in a direction perpendicular to the first main surface and a surface of the second wiring layer facing in a direction perpendicular to the first main surface.

[0208] [8] A semiconductor package described in any one of [1] to [7], wherein the substrate further comprises a second interlayer insulating layer located at a different location from the first interlayer insulating layer in a direction perpendicular to the first main surface, and a flat second functional layer extending parallel to the first main surface within the second interlayer insulating layer, wherein the combined volume of the second functional layer and the first functional layer is 0.5 times or less the volume of the substrate, and the material of the second functional layer is the same as the material of the first functional layer.

[0209] [9] A semiconductor package described in any one of [1] to [8], wherein the substrate further comprises a second interlayer insulating layer located at a different location from the first interlayer insulating layer in a direction perpendicular to the first main surface, and a flat second functional layer extending parallel to the first main surface within the second interlayer insulating layer, and the maximum dimension of the second functional layer in the direction perpendicular to the first main surface is the same as the maximum dimension of the first functional layer in the direction perpendicular to the first main surface.

[0210]

[10] A semiconductor package described in any one of [1] to [9], wherein the substrate has a plurality of vias that penetrate the first interlayer insulating layer in a direction perpendicular to the first main surface, and one or more selected from the plurality of vias penetrate the first functional layer in a direction perpendicular to the first main surface.

[0211]

[11] The semiconductor package according to

[10] , wherein the substrate covers a peripheral surface of the via penetrating the first functional layer and includes an insulating material having higher insulating properties than the first functional layer.

[12] The semiconductor package according to any one of [1] to

[11] , wherein the substrate further includes a third wiring layer located at a position different from the first wiring layer in a direction perpendicular to the first main surface and extending parallel to the first main surface, the third wiring layer being located at the same position as the first functional layer in the direction perpendicular to the first main surface.

[0212]

[13] A semiconductor package as described in

[12] , wherein the maximum dimension of the first functional layer in a direction perpendicular to the first main surface is larger than the maximum dimension of the first interlayer insulating layer in a direction perpendicular to the first main surface, and the maximum dimension of the first functional layer in a direction perpendicular to the first main surface is the same as the sum of an integer multiple of the maximum dimension of the third wiring layer in a direction perpendicular to the first main surface and an integer multiple of the maximum dimension of the first interlayer insulating layer in a direction perpendicular to the first main surface.

[0213]

[14] A semiconductor package described in any one of [1] to

[13] , wherein the first functional layer has a first functional section and a second functional section that are not connected to each other within the layer in which the first functional layer is located, and the material of the first functional section is different from the material of the second functional section.

[0214]

[15] A semiconductor package described in any one of [1] to

[14] , wherein the maximum dimension of the substrate in a direction perpendicular to the first main surface is smaller than the maximum dimension of the semiconductor device in a direction perpendicular to the first main surface.

[0215]

[16] A semiconductor package described in any one of [1] to

[15] , wherein the substrate further has a second main surface parallel to the first main surface, and the substrate further comprises one or more semiconductor devices including a semiconductor switch mounted on the second main surface, and a land portion for connecting a motherboard mounted on the second main surface.

[0216]

[17] The semiconductor package described in

[16] , wherein the number of the semiconductor devices mounted on the first main surface is two or more, one or more selected from the semiconductor devices mounted on the first main surface is a semiconductor integrated circuit including a plurality of load circuits, and one or more selected from the semiconductor devices mounted on the first main surface is a semiconductor switch.

[0217]

[18] The substrate further has a second main surface parallel to the first main surface, and the substrate further comprises a second interlayer insulating layer located at a position different from the first interlayer insulating layer in a direction perpendicular to the first main surface, a flat second functional layer extending parallel to the first main surface within the second interlayer insulating layer, one or more semiconductor devices including semiconductor switches mounted on the second main surface, and a land portion for connecting a motherboard mounted on the second main surface, wherein the second interlayer insulating layer is located farther from the first main surface than the first interlayer insulating layer, and the relative dielectric constant of the first functional layer is at least twice the relative dielectric constant of the first interlayer insulating layer, and the relative magnetic permeability of the second functional layer is at least twice the relative magnetic permeability of the second interlayer insulating layer. A semiconductor package described in any one of [5] to

[17] .

[0218]

[19] The semiconductor package according to any one of [1] to

[18] , wherein the substrate includes a core portion therein having a bending strength greater than that of the first interlayer insulating layer.

[20] The semiconductor package according to

[19] , wherein the substrate further includes a second wiring layer located at a position different from that of the first wiring layer in a direction perpendicular to the first main surface and extending parallel to the first main surface, the first wiring layer and the second wiring layer being located on either side of the core portion in the direction perpendicular to the first main surface, and the substrate further includes a through-hole wiring that penetrates the core portion in the direction perpendicular to the first main surface and connects the first wiring layer and the second wiring layer.

[0219]

[21] A semiconductor package as described in

[19] or

[20] , wherein the first functional layer is located on either the side closer to the first main surface relative to the core portion or the side farther from the first main surface relative to the core portion in a direction perpendicular to the first main surface, and the substrate does not have a layer made of the same material as the first functional layer on the other side closer to the first main surface relative to the core portion or the side farther from the first main surface relative to the core portion.

[0220]

[22] A semiconductor package according to any one of

[19] to

[21] , wherein the substrate further comprises a passive component located at the same location as the core portion in a direction perpendicular to the first main surface, and the maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than 0.7 times and less than 1.3 times the maximum dimension of the core portion in the direction perpendicular to the first main surface.

[0221]

[23] A semiconductor package according to any one of

[19] to

[22] , wherein the substrate further comprises a passive component located at the same location as the core portion in a direction perpendicular to the first main surface, and the passive component is in contact with the core portion in a direction parallel to the first main surface.

[0222] REFERENCE SIGNS LIST 10...Semiconductor package 11...Substrate 11A...First main surface 11B...Second main surface 21...First wiring layer 41...First functional layer 32...First interlayer insulating layer 51...First via 42...Second functional layer 33...Second interlayer insulating layer 22...Second wiring layer 100...Semiconductor device V1...First imaginary straight line V2...Second imaginary straight line

Claims

1. A semiconductor package comprising a substrate having a first main surface and a semiconductor device mounted on the first main surface, wherein the substrate has a first wiring layer extending parallel to the first main surface, a first interlayer insulating layer located at a position different from the first wiring layer in a direction orthogonal to the first main surface, and a flat first functional layer extending parallel to the first main surface inside the first interlayer insulating layer. When viewed through in a direction orthogonal to the first main surface, the first functional layer overlaps the first wiring layer without sandwiching other wirings therebetween. The volume of the first functional layer is 0.5 times or less of the volume of the substrate, and the relative permeability of the first functional layer is 2 times or more of the relative permeability of the first interlayer insulating layer.

2. The semiconductor package according to claim 1, wherein the first wiring layer has a first inductor wiring, the number of turns of the first inductor wiring is 0.5 turns or less, and the relative permeability of the first functional layer is 5 or more.

3. The semiconductor package according to claim 1 or claim 2, wherein the first wiring layer has a first inductor wiring and a second inductor wiring that are not connected to each other within the layer where the first wiring layer is located, the number of turns of the first inductor wiring is 0.5 turns or less, the number of turns of the second inductor wiring is 0.5 turns or less, the material of the first functional layer does not have magnetic anisotropy, a first virtual straight line passing through the first wire end and the second wire end of the first inductor wiring is assumed, and a second virtual straight line passing through the first wire end and the second wire end of the second inductor wiring is assumed. The first virtual straight line and the second virtual straight line intersect with each other.

4. The substrate is located on the side opposite to the first wiring layer with the first interlayer insulating layer interposed therebetween, and has a second wiring layer extending parallel to the first main surface, and a plurality of vias penetrating the first interlayer insulating layer to connect the first wiring layer and the second wiring layer. The first wiring layer has a first wiring portion, and the second wiring layer has a second wiring portion. The first wiring portion, the second wiring portion, and the plurality of vias form an integrated built-in inductor extending from a first end to a second end. At least a part of the built-in inductor spirally extends so as to surround the first functional layer by connecting the first wiring portion, the via, the second wiring portion, and the via in this order. The via connected to the most first end side and the via connected to the most second end are located on both sides with the first functional layer interposed therebetween in the direction along the central axis of the built-in inductor. The semiconductor package according to claim 1.

5. A semiconductor package comprising a substrate having a first main surface and a semiconductor device mounted on the first main surface. The substrate has a first wiring layer extending parallel to the first main surface, a second wiring layer located at a position different from the first wiring layer in a direction orthogonal to the first main surface and extending parallel to the first main surface, a first interlayer insulating layer located between the first wiring layer and the second wiring layer, and a flat first functional layer extending parallel to the first main surface inside the first interlayer insulating layer. When viewed in a direction facing orthogonal to the first main surface, the first functional layer overlaps the first wiring layer and the second wiring layer without other wirings being interposed therebetween. The volume of the first functional layer is 0.5 times or less of the volume of the substrate, and the relative permittivity of the first functional layer is 2 times or more of the relative permittivity of the first interlayer insulating layer.

6. The semiconductor package according to claim 5, wherein the first functional layer is in contact with one or more surfaces selected from the surface of the first wiring layer facing in the direction parallel to the first main surface and the surface of the second wiring layer facing in the direction parallel to the first main surface.

7. The semiconductor package according to claim 5 or claim 6, wherein the first functional layer is in contact with one or more surfaces selected from the surface of the first wiring layer facing in the direction orthogonal to the first main surface and the surface of the second wiring layer facing in the direction orthogonal to the first main surface.

8. The substrate further includes a second interlayer insulating layer located at a position different from the first interlayer insulating layer in a direction orthogonal to the first main surface, and a flat plate-shaped second functional layer extending parallel to the first main surface inside the second interlayer insulating layer. The combined volume of the volume of the second functional layer and the volume of the first functional layer is 0.5 times or less of the volume of the substrate, and the material of the second functional layer is the same as the material of the first functional layer. The semiconductor package according to any one of claims 1 to 7.

9. The substrate further includes a second interlayer insulating layer located at a position different from the first interlayer insulating layer in a direction orthogonal to the first main surface, and a flat plate-shaped second functional layer extending parallel to the first main surface inside the second interlayer insulating layer. The maximum dimension of the second functional layer in the direction orthogonal to the first main surface is the same as the maximum dimension of the first functional layer in the direction orthogonal to the first main surface. The semiconductor package according to any one of claims 1 to 8.

10. The substrate includes a plurality of vias penetrating the first interlayer insulating layer in a direction orthogonal to the first main surface, and one or more selected from the plurality of vias penetrate the first functional layer in a direction orthogonal to the first main surface. The semiconductor package according to any one of claims 1 to 9.

11. The substrate includes an insulating material that covers the peripheral surface of the via penetrating the first functional layer and has higher insulation than the first functional layer. The semiconductor package according to claim 10.

12. The substrate further includes a third wiring layer located at a position different from the first wiring layer in a direction orthogonal to the first main surface and extending parallel to the first main surface. The third wiring layer is located at the same position as the first functional layer in a direction orthogonal to the first main surface. The semiconductor package according to any one of claims 1 to 11.

13. The maximum dimension of the first functional layer in the direction orthogonal to the first main surface is larger than the maximum dimension of the first interlayer insulating layer in the direction orthogonal to the first main surface, and the maximum dimension of the first functional layer in the direction orthogonal to the first main surface is the same as the sum of an integer multiple of the maximum dimension of the third wiring layer in the direction orthogonal to the first main surface and an integer multiple of the maximum dimension of the first interlayer insulating layer in the direction orthogonal to the first main surface. The semiconductor package according to claim 12.

14. The first functional layer has a first functional part and a second functional part that are not connected to each other within the layer where the first functional layer is located, and the material of the first functional part is different from the material of the second functional part. The semiconductor package according to any one of claims 1 to 13.

15. The maximum dimension in the direction orthogonal to the first main surface of the substrate is smaller than the maximum dimension in the direction orthogonal to the first main surface of the semiconductor device. The semiconductor package according to any one of claims 1 to 14.

16. The substrate further has a second main surface parallel to the first main surface, and the substrate further includes: one or more semiconductor devices including a semiconductor switch mounted on the second main surface; and a land portion for connecting a mother board mounted on the second main surface. The semiconductor package according to any one of claims 1 to 15.

17. There are two or more semiconductor devices mounted on the first main surface, one or more selected from the semiconductor devices mounted on the first main surface is a semiconductor integrated circuit including a plurality of load circuits, and one or more selected from the semiconductor devices mounted on the first main surface is a semiconductor switch. The semiconductor package according to claim 16.

18. The substrate further has a second main surface parallel to the first main surface, and the substrate further includes: a second interlayer insulating layer located at a position different from the first interlayer insulating layer in the direction orthogonal to the first main surface; a flat plate-shaped second functional layer extending parallel to the first main surface inside the second interlayer insulating layer; one or more semiconductor devices including a semiconductor switch mounted on the second main surface; and a land portion for connecting a mother board mounted on the second main surface. The second interlayer insulating layer is located on the side farther from the first main surface than the first interlayer insulating layer, the relative permittivity of the first functional layer is two times or more the relative permittivity of the first interlayer insulating layer, and the relative permeability of the second functional layer is two times or more the relative permeability of the second interlayer insulating layer. The semiconductor package according to any one of claims 5 to 17.

19. The substrate includes a core portion having a greater bending strength than the first interlayer insulating layer inside the substrate. The semiconductor package according to any one of claims 1 to 18.

20. The substrate further includes a second wiring layer that is located at a position different from the first wiring layer in a direction orthogonal to the first main surface and extends parallel to the first main surface. The first wiring layer and the second wiring layer are located on both sides of the core portion with the core portion interposed therebetween in a direction orthogonal to the first main surface. The semiconductor package according to claim 19 further includes a through-wiring that penetrates the core portion and connects the first wiring layer and the second wiring layer in a direction orthogonal to the first main surface.

21. The first functional layer is located on either one of the side closer to the first main surface with respect to the core portion and the side farther from the first main surface with respect to the core portion in a direction orthogonal to the first main surface. The substrate does not have a layer of the same material as the first functional layer on either one of the side closer to the first main surface with respect to the core portion and the side farther from the first main surface with respect to the core portion. The semiconductor package according to claim 19 or claim 20.

22. The substrate further includes a passive component located at the same position as the core portion in a direction orthogonal to the first main surface. The maximum dimension of the passive component in a direction orthogonal to the first main surface is greater than 0.7 times and less than 1.3 times the maximum dimension of the core portion in a direction orthogonal to the first main surface. The semiconductor package according to any one of claims 19 to 21.

23. The substrate further includes a passive component located at the same position as the core portion in a direction orthogonal to the first main surface. The passive component is in contact with the core portion in a direction parallel to the first main surface. The semiconductor package according to any one of claims 19 to 22.

Images