Logic operation circuit

Abstract

The present invention provides a logic operation circuit comprising: a differential logic tree cell; and a digital differential sense amplifier for reading an operation result of the differential logic tree cell. The differential logic tree cell includes: a memory cell including first and second magnetic storage elements for storing data due to a change in resistance value; and a differential logic circuit for performing a logical operation by using the data stored in the memory cell and external data that has been externally input. The digital differential sense amplifier is grounded without passing through the differential logic tree cell.

Description

Logic operation circuit

[0001] The present disclosure relates to a logic operation circuit.

[0002] In recent years, with the dramatic development of various information devices, from large-capacity servers to mobile terminals, further improvements in performance, such as higher integration, higher speed, and lower power consumption, have been pursued in the memory, logic, and other elements that constitute these devices. In particular, progress in nonvolatile semiconductor memory has been remarkable. For example, flash memory, which serves as a large-capacity file memory, is rapidly gaining popularity and is likely to replace hard disk drives. Meanwhile, with a view to application to code storage and even working memory, development is underway on various types of semiconductor memory, such as FeRAM (Ferroelectric random access memory), MRAM (Magnetic random access memory), and PCRAM (Phase-Change Random Access Memory), to replace currently commonly used NOR flash memory, DRAM (Dynamic Random Access Memory), and the like. Some of these technologies have already been put into practical use.

[0003] One of the above-mentioned devices, MRAM (memory device), stores data by changing the magnetization state of the magnetic material in the magnetic memory element of the MRAM, thereby changing the electrical resistance. Such MRAM is capable of high-speed operation and has an almost infinite (10 １５ Because MRAM can be rewritten many times (or more times) and is highly reliable, it is already being used in fields such as industrial automation and aircraft. Furthermore, due to its high speed and high reliability, MRAM is expected to be used in code storage and working memory in the future.

[0004] Conventional MRAMs have multiple memory cells, each of which includes one MTJ (Magnetic Tunnel Junction) element (magnetic memory element) and one access transistor, forming a so-called 1T1R configuration. MRAMs store data "1" and "0" by associating them with the high-resistance state and low-resistance state of the MTJ element in a single memory cell, which constitutes a single storage unit. Furthermore, data is read from such a memory cell by using a sense amplifier to detect the voltage difference (or current difference) between the MTJ element and a reference cell set to a value midway between the high-resistance state and the low-resistance state of the MTJ element.

[0005] Japanese Patent Application Laid-Open No. 2003-187569 Japanese Patent Application Laid-Open No. 2001-236781 Japanese Patent Application Laid-Open No. 2022-60143 Japanese Patent Application Laid-Open No. 2023-516343 Japanese Patent Application Laid-Open No. 2001-185999

[0006] Sudha Vani Yamani et al. , “Design and Performance Benchmarking of Hybrid Tunnel FET / STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency”, IEEE Transactions on Magnetics, Vol. 58, No. 4, April, 2022 Gajanan Jedhe etal. , “A 12nm 137 TOPS / W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications”, 2023 Symposium on VLSL Technology and Circuits Digest of Technical Papers

[0007] In conventional MRAMs (memory devices), a sense amplifier used to read data from each memory cell is not provided near each memory cell, but rather a single sense amplifier is provided corresponding to a predetermined number of memory cells. Therefore, the length of the wiring connecting each memory cell to the reference cell varies from memory cell to memory cell. Therefore, even if the reference cell has an ideal intermediate resistance, the parasitic resistance of the wiring adds to the resistance of each memory cell. Depending on the relative positions of the memory cell and the reference cell, the resistance margin (read margin) between the memory cell and the reference cell becomes narrow, making it difficult to accurately read data from the memory cell using the sense amplifier. Therefore, while it is conceivable to provide a sense amplifier corresponding to each memory cell near each memory cell, this is not preferable because it increases the chip area.

[0008] Therefore, this disclosure proposes a logic operation circuit that can read data accurately while avoiding an increase in chip area, and that can operate at a higher speed if the power supply voltage is the same, and can operate at a lower power supply voltage if the operating speed is the same.

[0009] According to the present disclosure, there is provided a logic operation circuit comprising a differential logic tree cell and a digital type differential sense amplifier that reads the operation result of the differential logic tree cell, wherein the differential logic tree cell includes a memory cell including first and second magnetic memory elements that store data by changes in resistance value, and a differential logic circuit that performs a logical operation using the data stored in the memory cell and external data input from the outside, and the digital type differential sense amplifier is grounded without going through the differential logic tree cell.

[0010] FIG. 1 is a diagram showing a circuit configuration of a memory cell 310a according to the prior art. FIG. 2 is a diagram showing an example of a configuration of an MRAM 10 according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing an example of a circuit configuration of a word line driver 20 according to the first embodiment of the present disclosure. FIG. 4 is a diagram showing an example of a circuit configuration of a memory cell 310 according to the first embodiment of the present disclosure. FIG. 5 is a diagram for explaining the operation of a memory cell 310 according to the first embodiment of the present disclosure. FIG. 6 is a diagram showing an example of a configuration of a memory cell array 30 according to the first embodiment of the present disclosure. FIG. 7 is a diagram showing an example of a configuration of a multiplexer circuit 350 according to the first embodiment of the present disclosure. FIG. 8 is a diagram showing an example of a configuration of a read circuit 400 according to the first embodiment of the present disclosure. FIG. 9 is a diagram showing an example of a circuit configuration of a sense amplifier 410 according to the first embodiment of the present disclosure. FIG. 10 is a diagram showing an example of a circuit configuration of a detector circuit 440 according to the first embodiment of the present disclosure. FIG. 11 is a diagram showing a first example of a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 12 is a diagram showing a second example of a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 13 is a diagram showing a third example of a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 4 is a diagram (part 4) illustrating a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 5 is a diagram (part 5) illustrating a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 6 is a diagram (part 6) illustrating a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 7 is a diagram (part 7) illustrating a read operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 1 is a diagram (part 1) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 2 is a diagram (part 2) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 3 is a diagram (part 3) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 4 is a diagram (part 5) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 6 is a diagram (part 6) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure.FIG. 7 is a diagram (part 7) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 8 is a diagram (part 8) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 9 is a diagram (part 9) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 10 is a diagram (part 10) illustrating a write operation of the MRAM 10 according to the first embodiment of the present disclosure. FIG. 1 is a diagram illustrating a configuration of a logic operation circuit 60a according to the prior art. FIG. 1 is a diagram illustrating a circuit configuration of a logic operation circuit 60a according to the prior art. FIG. 2 is a diagram illustrating an overview of a logic operation circuit 60 according to a second embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a configuration of a logic operation circuit 60 according to a second embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of a circuit configuration of a differential logic tree cell 70 according to a second embodiment of the present disclosure. FIG. 1 is a diagram (part 1) illustrating an example of a circuit configuration of a differential logic tree cell 70 according to a modification of the second embodiment of the present disclosure. FIG. 2 is a diagram (part 2) illustrating an example of a circuit configuration of a differential logic tree cell 70 according to a modification of the second embodiment of the present disclosure. FIG. 3 is a diagram (part 3) illustrating a read operation of the logic operation circuit 60 according to the second embodiment of the present disclosure. FIG. 4 is a diagram (part 4) illustrating a read operation of the logic operation circuit 60 according to the second embodiment of the present disclosure. FIG. 5 is a diagram (part 5) illustrating a read operation of the logic operation circuit 60 according to the second embodiment of the present disclosure. FIG. 6 is a diagram (part 6) illustrating a read operation of the logic operation circuit 60 according to the second embodiment of the present disclosure. FIG. 7 is a diagram (part 7) illustrating a read operation of the logic operation circuit 60 according to the second embodiment of the present disclosure.FIG. 8 is a diagram (part 8) illustrating a read operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 9 is a diagram (part 9) illustrating a read operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 1 is a diagram (part 1) illustrating a write operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 2 is a diagram (part 2) illustrating a write operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 3 is a diagram (part 3) illustrating a write operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 4 is a diagram (part 5) illustrating a write operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 6 is a diagram (part 6) illustrating a write operation of the logic arithmetic circuit 60 according to the second embodiment of the present disclosure. FIG. 1 is a diagram (part 1) illustrating an example of the configuration of a logic arithmetic circuit 60 according to a modification of the second embodiment of the present disclosure. FIG. 2 is a diagram (part 2) illustrating an example of the configuration of a logic arithmetic circuit 60 according to a modification of the second embodiment of the present disclosure. A diagram showing an example of the configuration of a arithmetic device CiM80 according to a third embodiment of the present disclosure. FIG. 1 is a diagram illustrating an example of the configuration of a main part of a CiM80 according to a third embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of the circuit configuration of a differential logic tree cell 70 according to the third embodiment of the present disclosure. FIG. 3 is a diagram illustrating the operation of a differential logic tree cell 70 according to the third embodiment of the present disclosure. FIG. 4 is a diagram illustrating the operation of a CiM80 according to the third embodiment of the present disclosure. FIG. 5 is a diagram illustrating the operation of a CiM80 according to the third embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of the configuration of a CiM80 according to a modified example of the third embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of processing in an electronic device according to the third embodiment of the present disclosure. FIG. 8 is a diagram illustrating a comparison of processing times between the third embodiment of the present disclosure and conventional technology.

[0011] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0012] The drawings referred to in the following description are for explaining and facilitating understanding of the embodiments of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings may be modified as appropriate, taking into consideration the following description and known technologies.

[0013] In the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, in the following description, "electrically connected" includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.

[0014] In the following description, "sharing" means that different elements (e.g., MTJ elements, differential logic tree cells, etc.) share one other element (e.g., a sense amplifier, a write circuit, etc.).

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 1.1 Background 1.2 Detailed configuration 1.3 Operation 2. Second embodiment 2.1 Background 2.2 Detailed configuration 2.3 Operation 2.4 Modified example 3. Third embodiment 3.1 Background 3.2 Detailed configuration 3.3 Operation 3.4 Modified example 3.5 Application example 4. Supplementary information

[0016] <<1. First Embodiment>> <1.1 Background> First, the background that led the inventors to create the first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a diagram showing the circuit configuration of a memory cell 310a according to the prior art.

[0017] As described above, MRAM stores data by changing the magnetization state of the magnetic material in the magnetic memory element of the MRAM, thereby changing the electrical resistance. Specifically, MRAM uses MTJ elements (magnetic memory elements) 320 as memory elements. In conventional technology, MRAM has multiple memory cells 310a as shown in FIG. 1. Each memory cell 310a includes one MTJ element 320 and one access transistor 330, forming a so-called 1T1R configuration. Furthermore, each memory cell 310a is located at the intersection of a bit line and a word line. The MRAM stores data "1" and "0" by corresponding them to a high-resistance state (e.g., about 10 kΩ) and a low-resistance state (e.g., about 5 kΩ) of the MTJ element 320 in one memory cell 310a, which is one storage unit.

[0018] Data is read from such a conventional memory cell 310a by detecting the potential difference between the voltage of the MTJ element 320 and the voltage of a reference cell (not shown) or the current difference between the current of the MTJ element 320 and the current of the reference cell using a sense amplifier (not shown). The reference cell is set to a value (intermediate resistance value) that corresponds to the intermediate state between the high resistance state and the low resistance state of the MTJ element 320. The sense amplifier is, for example, a differential amplifier, which is an analog circuit, and amplifies the detected difference to output data of "1" or "0", i.e., a logical value.

[0019] In conventional MRAMs, a sense amplifier used to read data from each memory cell 310a is not provided near each memory cell 310a, but rather one sense amplifier is provided corresponding to a predetermined number of memory cells 310a. Therefore, the length of the wiring electrically connecting each memory cell 310a to the reference cell varies for each memory cell 310a. Therefore, even if the reference cell has an ideal intermediate resistance, the parasitic resistance of the wiring of each memory cell 310a is added to the resistance of each memory cell 310a. Therefore, depending on the relative positions of the memory cell 310a and the reference cell, the margin in the resistance value (read margin) between the memory cell 310a and the reference cell becomes narrow, making it difficult to accurately read data from the memory cell 310a using the sense amplifier.

[0020] Therefore, it is conceivable to provide a sense amplifier corresponding to each memory cell 310a near the memory cell 310a, but this would naturally result in an increase in chip area, which is undesirable because it makes it difficult to miniaturize the MRAM and increases manufacturing costs.

[0021] Furthermore, in an MRAM, the resistance value of the MTJ element 320 in a high-resistance state generally tends to be small in a high-temperature environment, which may narrow the read margin. Therefore, even if a sense amplifier corresponding to each memory cell 310a is provided near the memory cell 310a, it may be difficult for the sense amplifier to read data accurately. Because of this high probability of data read errors, a redundant circuit and an error correction code (ECC) circuit are provided in the MRAM, which again makes it difficult to avoid an increase in chip area and power consumption.

[0022] In view of this situation, the inventors have come up with the first embodiment of the present disclosure, which will be described below. While the memory cell 310a of the prior art has a 1T1R configuration, the memory cell 310 of this embodiment (see FIG. 4 ) has a so-called 2T2R configuration, which includes two MTJ elements 320 and two access transistors 330. In this embodiment, data is read by detecting the difference in resistance between the two MTJ elements 320 in one memory cell 310, eliminating the need for the reference cell.

[0023] Specifically, in this embodiment, one MTJ element 320 of one memory cell 310, which is one storage unit, is set to a high resistance state and the other MTJ element 320 is set to a low resistance state to store data “1.” Furthermore, in this embodiment, one MTJ element 320 of one memory cell 310 is set to a low resistance state and the other MTJ element 320 is set to a high resistance state to store data “0.” In the conventional technology, data is read by detecting the difference in resistance between one MTJ element 320 in one memory cell 310 and a reference cell. On the other hand, in this embodiment, data is read by detecting the difference in resistance between two MTJ elements 320 in one memory cell 310. In this embodiment, since the difference between the MTJ element 320 in the high resistance state and the MTJ element 320 in the low resistance state is detected, the difference is naturally large. Therefore, in this embodiment, it is easier to read the difference compared to the conventional technology, and data can be read with high accuracy. Therefore, the probability of a read error occurring is low, and there is no need to provide a redundant circuit or an error correction circuit within the MRAM 10. As a result, according to this embodiment, it is possible to avoid an increase in chip area and power consumption. Furthermore, unlike the prior art, this embodiment does not require the provision of a reference cell. Furthermore, in this embodiment, a suitable sense amplifier 410 (see FIG. 9) is combined with the memory cell 310 configured as described above.

[0024] That is, according to this embodiment, it is possible to provide an MRAM (storage device) 10 that can read data with high accuracy while avoiding an increase in chip area. Hereinafter, details of the first embodiment of the present disclosure will be sequentially described.

[0025] 1.2 Detailed Configuration (MRAM 10) First, the overall configuration of the MRAM (storage device) 10 according to the first embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the MRAM 10 according to this embodiment.

[0026] As shown in FIG. 2 , the MRAM 10 according to this embodiment primarily includes a word line driver 20, a memory cell array 30, and a peripheral circuit section 40 including a read circuit 400 and a write circuit 500. The memory cell array 30 also includes a plurality of memory cells 310 arranged in a matrix along the row and column directions. Furthermore, the plurality of memory cells 310 located in the same row are electrically connected to the same word line (WL00-WL0F), and the plurality of memory cells 310 located in the same column are electrically connected to the same bit line (BLT, BLC). Hereinafter, an example will be described in which the plurality of memory cells 310 in the memory cell array 30 are arranged in 16 rows and 16 columns, but this embodiment is not limited to such an arrangement. Below, the details of each element constituting the MRAM 10 according to this embodiment will be sequentially described.

[0027] (Word Line Driver 20) First, the configuration of the word line driver 20 according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the circuit configuration of the word line driver 20 according to this embodiment.

[0028] As explained above, it is assumed here that the memory cells 310 in the memory cell array 30 are arranged in 16 rows and 16 columns. Therefore, 4 bytes of address data (D3, D2, D1, D0) and a detect signal from a read circuit 400 (described later) are input to the word line driver 20. Furthermore, the word line driver 20 outputs a decode signal to 16 word lines (WL00 to WL0F).

[0029] In detail, as shown in FIG. 3 , the word line driver 20 includes an existing address decoder 202, an inverter 204, and 16 pairs each consisting of a NAND circuit 210 and an inverter 212. In response to a 4-byte address input, the address decoder 202 outputs decode signals corresponding to 16 addresses (adrs00 to adrs0F) exclusively as "1" to the pairs. The NAND circuit 210 then performs a logical operation between the signal from the address decoder 202 and the detect signal inverted by the inverter 204, and inverts the signal using the inverter 212 to output a decode signal of "1" exclusively to one of the 16 word lines (WL00 to WL0F). Furthermore, when the detect signal is "0," a decode signal of "0" is forcibly output to the 16 word lines (WL00 to WL0F). In this manner, in this embodiment, the word line driver 20 can select the word line to be controlled.

[0030] (Memory Cell Array 30) Next, the configuration of the memory cell array 30 according to this embodiment will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a diagram showing an example of the circuit configuration of the memory cell 310 according to this embodiment, and Fig. 5 is a diagram for explaining the operation of the memory cell 310 according to this embodiment. Furthermore, Fig. 6 is a diagram showing an example of the configuration of the memory cell array 30 according to this embodiment.

[0031] 4, the memory cell 310 according to this embodiment includes two MTJ elements (first and second magnetic memory elements) 320 and access transistors (first and second access transistors) 330 electrically connected to the two MTJ elements 320. That is, the memory cell 310 according to this embodiment has a 2T2R configuration, and in the following description, the memory cell 310 may also be referred to as a "twin cell."

[0032] Specifically, one terminal (first terminal) of each MTJ element 320 is electrically connected to one of the source and drain terminals (first terminal) of the access transistor 330. The other terminal (second terminal) of each MTJ element 320 is electrically connected to a WCTL / AGND line (common reference potential line) extending in the column direction. The WCTL / AGND line corresponds to the ground line of the memory cell 310. The other terminal (second terminal) of each source and drain terminal of the access transistor 330 is electrically connected to an ABLT line and an ABLC line (first and second bit lines) that are bit lines extending in the column direction. The ABLT line and the ABLC line have opposite polarities. The gate (third terminal) of each access transistor 330 is electrically connected to a word line extending in the row direction. The access transistor 330 is made of, for example, an n-type MOS (metal oxide semiconductor) transistor, and connects the MTJ element 320 to the ABLT line or ABLC line when the word line connected to its gate becomes "1".

[0033] The MTJ element 320 has a stacked structure as shown on the right side of FIG. 4 . Specifically, the MTJ element 320 has a structure in which a fixed layer 326, whose magnetic moment (magnetization direction) is fixed in a predetermined direction, a nonmagnetic layer 324, a free layer 322, whose magnetic moment direction is variable, and a cap layer (not shown) are stacked in this order on an underlayer (not shown). That is, the nonmagnetic layer 324 is sandwiched between the fixed layer 326 and the free layer 322. Note that in this embodiment, the order of stacking does not have to be the order shown on the right side of FIG. 4 as long as the same layer of the two MTJ elements 320 in one memory cell 310 is electrically connected to the access transistor 330 and the WCTL / AGND line, respectively.

[0034] The pinned layer 326 is formed of a magnetic material including a ferromagnetic material, and the direction of the magnetic moment is fixed by a high coercive force or the like. The nonmagnetic layer 324 is formed of various nonmagnetic materials such as magnesium oxide (MgO). The free layer 322 is formed of a magnetic material including a ferromagnetic material, and the direction of the magnetic moment changes depending on the information to be stored. Furthermore, the underlayer and cap layer function as electrodes, a crystal orientation control film, a protective film, etc. In the MTJ element 320, by applying a voltage to the MTJ element 320 to change the direction of the magnetic moment of the free layer 322, the difference in the direction of the magnetic moment of the pinned layer 326 causes a change in the resistance value of the entire MTJ element 320. Specifically, when the magnetic moments of the fixed layer 326 and the free layer 322 are oriented in the same direction, the resistance of the MTJ element 320 is low (low resistance state), and when the magnetic moments of the fixed layer 326 and the free layer 322 are oriented in different directions, the resistance of the MTJ element 320 is high (high resistance state). The MTJ element 320 can store data by utilizing the change in resistance due to such a change in magnetic moment.

[0035] In this embodiment, data is stored in one memory cell 310, which is one storage unit, as shown in FIG. 5 . Specifically, as shown on the left side of FIG. 5 , one MTJ element 320 a is set to a low resistance state (L) and the other MTJ element 320 b is set to a high resistance state (H), thereby causing the memory cell 310 to store data of a logical value “0.” Furthermore, in this embodiment, as shown on the right side of FIG. 5 , one MTJ element 320 a is set to a high resistance state (H) and the other MTJ element 320 b is set to a low resistance state (L), thereby causing the memory cell 310 to store data of a logical value “1.” Note that this embodiment is not limited to storing logical values ​​“0” and “1” as shown in FIG. 5 . In this embodiment, for example, by setting one MTJ element 320a to a low resistance state (L) and the other MTJ element 320b to a high resistance state (H), the memory cell 310 can store data with a logical value of "1." Alternatively, by setting one MTJ element 320a to a high resistance state (H) and the other MTJ element 320b to a low resistance state (L), the memory cell 310 can store data with a logical value of "0."

[0036] In this embodiment, the difference between the high-resistance state MTJ element 320 and the low-resistance state MTJ element 320 in one memory cell 310, which is one storage unit, is detected, resulting in a large difference. Therefore, in this embodiment, reading the difference is easier than with the conventional technology, enabling accurate data reading. As a result, this embodiment reduces the probability of read errors, eliminating the need for a redundant circuit or an error correction circuit (ECC) in the MRAM 10. Therefore, this embodiment can avoid increases in chip area and power consumption. Furthermore, because the difference to be read is large, this embodiment can operate at a higher speed with the same power supply voltage, and can operate at a lower power supply voltage with the same operating speed. In addition, this embodiment, unlike the conventional technology, does not require a reference cell.

[0037] 6, the memory cell array 30 has a plurality of memory cells 310 arranged in a matrix along the row and column directions. As described above, the plurality of memory cells 310 located in the same row are electrically connected to the same word line (WL00 to WL0F), and the plurality of memory cells 310 located in the same column are electrically connected to the same ABLT line and ABLC line (bit line) and the same AGND line (ground line).

[0038] (Multiplexer Circuit 350) Next, the configuration of the multiplexer circuit (Multiplexer; MUX) 350 according to this embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram showing an example of the configuration of the multiplexer circuit 350 according to this embodiment.

[0039] The multiplexer circuit 350 is provided between the memory cell array 30 and the peripheral circuit section 40 including the read circuit 400 and the write circuit 500, and inputs data to one memory cell 310 selected from the plurality of memory cells 310, or outputs data from the selected one memory cell 310. In detail, in this embodiment, the multiplexer circuit 350 is composed of three multiplexer circuits corresponding to the ABLT line, the ABLC line, and the AGND line, respectively. Each multiplexer circuit 350 has a transmission gate 352 connected to each of, for example, 16 lines extending from the memory cell array 30. That is, one multiplexer circuit (first multiplexer circuit) 350 is electrically connected to 16 ABLT lines (first bit lines), another multiplexer circuit (second multiplexer circuit) 350 is electrically connected to 16 ABLC lines (second bit lines), and yet another multiplexer circuit (third multiplexer circuit) 350 is electrically connected to 16 AGND lines (common reference potential lines). Each multiplexer circuit 350 exclusively selects one of the 16 lines and connects it to the BLT and BLC lines of the peripheral circuit section 40. The BLT lines correspond to the ABLT lines, and the BLC lines correspond to the ABLC lines, with the BLT and BLC lines having opposite polarities.

[0040] (Readout Circuit 400) Next, the configuration of the readout circuit 400 according to this embodiment will be described with reference to Fig. 8 to Fig. 10. Fig. 8 is a diagram showing an example of the configuration of the readout circuit 400 according to this embodiment. Fig. 9 is a diagram showing an example of the circuit configuration of a sense amplifier 410 according to this embodiment, and Fig. 10 is a diagram showing an example of the circuit configuration of a detector circuit 440 according to this embodiment.

[0041] The read circuit 400 according to this embodiment is a circuit that reads the difference in resistance values ​​between two MTJ elements 320, and more specifically, can read the difference or ratio between the resistance values ​​of the two MTJ elements 320. As shown in FIG. 8 , the read circuit 400 according to this embodiment includes a digital differential sense amplifier 410 electrically connected to the memory cell array 30, a detector circuit (shutoff circuit) 440 electrically connected to the sense amplifier 410, and a NOR RS latch circuit 470 electrically connected to the detector circuit 440. In this embodiment, the BLT line and the BLC line from the memory cell array 30 are connected to the sense amplifier 410, the detector circuit 440, and the NOR RS latch circuit 470.

[0042] 9 , the sense amplifier 410 includes two inverters 420 whose input / output terminals are connected in a loop, an n-type MOS transistor (first switch) 414 that electrically connects the output terminals of the two inverters 420, and a p-type MOS transistor (second switch) 412 that electrically connects the two inverters 420 to a power supply. Furthermore, the sense amplifier 410 includes a NOR circuit 418 electrically connected to the gate of the n-type MOS transistor 414, and an inverter 416 electrically connected to the gate of the p-type MOS transistor 412.

[0043] Specifically, each inverter 420 is configured such that the source of the p-type MOS transistor is electrically connected to a power supply line, the sources of the p-type MOS transistor and the n-type MOS transistor are electrically connected to each other, the gates of the p-type MOS transistor and the n-type MOS transistor are electrically connected to each other, and the source of the n-type MOS transistor is grounded. The input of the inverter 420 is the node where the gates of the p-type MOS transistor and the n-type MOS transistor are connected to each other, and the output of the inverter 420 is the node where the sources of the p-type MOS transistor and the n-type MOS transistor are connected to each other. In this embodiment, two such inverters 420 are connected in a loop. Furthermore, the n-type MOS transistor 414 can switch the electrical connection of the output terminals of the two inverters 420. Furthermore, the p-type MOS transistor 412 can switch the electrical connection between the two inverters 420 and the power supply. The switching operations of these two transistors 412 and 414 are controlled by an activation (ACT) signal and a write (WRITE) signal.

[0044] Specifically, when the ACT signal is "0," the sense amplifier 410 is in an inactive initial state. At that time, the n-type MOS transistor 414 short-circuits the output terminals of the two inverters 420, so that the BLT line and the BLC line are short-circuited and have the same potential (for example, a potential from 0 V to approximately the threshold voltage Vth of the n-type MOS transistor 414).

[0045] When reading data, the ACT signal is set to "1." This eliminates the short circuit between the output terminals of the two inverters 420 caused by the n-type MOS transistor 414, and simultaneously, the two loop-shaped inverters 420 begin operating and function as the sense amplifier 410. One of the BLT and BLC lines is then connected to the AGND line (ground line) with high resistance by the MTJ element 320 in the high-resistance state, and the other of the BLT and BLC lines is connected to the AGND line (ground line) with low resistance by the MTJ element 320 in the low-resistance state. This creates a difference in the magnitude of the two currents flowing from the sense amplifier 410 to the BLT and BLC lines, causing the potential of the output with the higher resistance of the two outputs of the sense amplifier 410 to rise quickly and quickly reach the potential corresponding to the logical value "1." In this way, the sense amplifier 410 can quickly read data stored in the memory cell 310. Therefore, the MRAM 10 according to this embodiment can operate at a higher speed than the conventional technology at the same voltage. Data read by the sense amplifier 410 is temporarily held in the NOR type RS latch circuit 470 and output to the outputs OUT_T and OUT_C ​​(see FIG. 8 ) of the MRAM 10. The outputs OUT_T and OUT_C ​​have opposite polarities.

[0046] 10 , the detector circuit 440 includes a dynamic NOR logic circuit 442 electrically connected to the sense amplifier 410 and having two input terminals, and a NAND circuit (NAND logic circuit) 444 electrically connected to the dynamic NOR logic circuit 442. The detector circuit 440 can output a DETECT signal to the word line driver 20. The detector circuit 440 can cut off the current from the sense amplifier 410 to the MTJ element 320 by outputting a predetermined DETECT signal to the word line driver 20.

[0047] Specifically, the dynamic circuit has the function of temporarily storing data at a common output node (dynamic node) by utilizing parasitic capacitance generated in the circuit. As shown in FIG. 10 , the dynamic NOR logic circuit 442 has two n-type transistors whose gates, serving as inputs, are electrically connected to the BLT and BLC lines. The drains of these transistors are electrically connected to the dynamic node and to a power supply via a p-type MOS transistor 446. The sources of the two transistors in the dynamic NOR logic circuit 442 are grounded via an n-type MOS transistor 445. The operations of the p-type MOS transistor 446 and the n-type MOS transistor 445 are controlled by an ACT signal. Furthermore, the common output node of the dynamic NOR logic circuit 442 is electrically connected to a NAND circuit 444. In addition to receiving a signal from the dynamic NOR logic circuit 442, the NAND circuit 444 also receives a write word line control signal (WWL signal), and outputs the operation result of these two input signals to the word line driver 20 as a DETECT signal.

[0048] Specifically, when the ACT signal is "0", the detector circuit 440 is in an inactive initial state. At this time, as described above, the BLT line and the BLC line are short-circuited and have the same potential of approximately 0 V. At this time, the common output node of the dynamic NOR logic circuit 442 is initialized to "1" by the p-type MOS transistor 446, and is inverted by the NAND circuit 444, so that the output (DETECT signal) of the detector circuit 440 becomes "0".

[0049] When reading, the ACT signal is set to "1." The WWL signal is a signal controlled during writing and is always set to "1" during reading. As described above, one of the BLT and BLC lines has a logical value of "1" and the other has a logical value of "0" depending on the state (high resistance state or low resistance state) of the MTJ element 320. Therefore, the common output node of the dynamic NOR logic circuit 442 becomes "0." The logical value "0" is then inverted by the NAND circuit 444, so the output (DETECT signal) of the detector circuit 440 becomes "1." The DETECT signal of "1" is then input to the word line driver 20, which inputs a signal of "0" to the word line. As a result, the access transistor 330 electrically connected to the MTJ element 320 from which data has been read is turned off, and the current from the sense amplifier 410 to the MTJ element 320 is cut off. That is, in this embodiment, by having such a configuration, when data reading is completed, the word line can be immediately and autonomously set to "0" and the access transistor 330 corresponding to the read MTJ element 320 can be quickly turned off. As a result, in this embodiment, the current flowing from the sense amplifier 410 to the MTJ element 320 can be minimized, thereby reducing the power consumption of the MRAM 10 and improving its reliability. Details of the read operation in this embodiment will be described later.

[0050] Note that the potential of the common output node of the dynamic NOR logic circuit 442, which should be held, may change due to leakage current, causing incorrect data to be output from the dynamic NOR logic circuit 442 and causing malfunction of the MRAM 10. Therefore, as shown in Figure 10, in order to stably hold the potential of the common output node of the dynamic NOR logic circuit 442, an inverter loop 450 consisting of two inverters whose input / output terminals are connected in a loop may be added to the common output node.

[0051] (Write Circuit 500) Next, the configuration of the write circuit 500 according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a diagram showing an example of the circuit configuration of the write circuit 500 according to this embodiment.

[0052] In this embodiment, the write circuit 500 applies a voltage so that a current flows from one terminal (first terminal) of one MTJ element (first magnetic memory element) 320 of one memory cell 310 to the other terminal (second terminal), and applies a voltage so that a current flows from the other terminal to one terminal of the other MTJ element (second magnetic memory element) 320 of the memory cell 310, thereby writing a logical value of "1" (first value) to the memory cell 310. In this embodiment, the write circuit 500 also applies a voltage so that a current flows from the other terminal of one MTJ element 320 to one terminal, and applies a voltage so that a current flows from one terminal to the other terminal of the other MTJ element 320, thereby writing a logical value of "0" (second value) to the memory cell 310.

[0053] 11, the write circuit 500 includes two tri-state buffers 502 electrically connected to the BLT line and the BLC line (first and second bit lines), respectively, and an inverter (common reference potential line control circuit) 504 electrically connected to the VGAD line (ground line) (common reference potential line). The tri-state buffer 502 can not only switch the output of an input signal ("1" or "0"), but also switch to a high impedance state ("Z"). That is, the tri-state buffer 502 can be switched to three states.

[0054] Specifically, during a read, the two tri-state buffers 502 are controlled by a WRITE signal of "0" and enter a high impedance state. On the other hand, during a write, the two tri-state buffers 502 are controlled by a WRITE signal of "1" and output signals. When "0" is written to the memory cell 310 (write data (WDATA) signal = 0), the tri-state buffer 502 on the BLT line side becomes "0" and the tri-state buffer 502 on the BLC line side becomes "1". When "1" is written to the memory cell 310 (WDATA signal = 1), the tri-state buffer 502 on the BLT line side becomes "1" and the tri-state buffer 502 on the BLC line side becomes "0".

[0055] Furthermore, by setting the bit lines BLT and BCL to the above-described state by two three-state buffers 502, the write control line (WCTL line) is switched from "0" to "1" and then from "1" to "0," thereby switching the potential of the VGND line of the memory cell 310 via the inverter 504. When the potential is switched, the direction of the current flowing through the MTJ element 320 on the bit line side in the "0" state is opposite to the direction of the current flowing through the MTJ element 320 on the bit line side in the "1" state. Therefore, the direction of the current flowing through the two MTJ elements 320 is opposite, and as a result, the direction of the magnetic moment of the free layer 322 of each MTJ element 320 is opposite, resulting in a difference in resistance between the two MTJ elements 320. Details of the write operation in this embodiment will be described later.

[0056] In the embodiment of the present disclosure, the MRAM 10 is not limited to the forms shown in FIGS. 2 to 11, but can be modified into various forms.

[0057] <1.3 Operation> (Read Operation) Next, an example of a read operation of the MRAM 10 according to this embodiment will be described with reference to Figures 12A to 12G. Figures 12A to 12G are diagrams for explaining the read operation of the MRAM 10 according to this embodiment, showing the states of each signal and each node over time. In detail, from the top of the diagram, the address signal, the state of the ABLT line [0], the state of the ABLC line [0], the state of the word line

[00] , the ACT signal, the DETECT signal, and the output signal (OUT_T) of the MRAM 10 are shown.

[0058] First, the operation of the MRAM 10 starts from the initial state shown at the left end of FIG. 12A. The specific states of each signal and each node at this point are described on the right side of FIG. 12A. Then, as shown in FIG. 12B, a read address is input to the MRAM 10 (address "0000" is input). Then, as shown in FIG. 12C, in response to the input read address, word line

[00] rises to "1". At this time, word lines other than word line

[00] maintain "0".

[0059] If nothing is done, the state shown in Figure 12C will be maintained. If the ACT signal is set to "1," reading will begin, as shown in Figure 12D, and either the ABLT[0] line or the ABLC line[0] will become "1." The other of the ABLT[0] line and the ABLC line[0] will change state slightly but will return to "0."

[0060] Next, when either the ABLT[0] line or the ABLC line[0] becomes "1," the DETECT signal becomes "1," as shown in FIG. 12E. At the same time, the output OUT_T, which is the output of the MRAM 10, also changes. In this way, the sense amplifier 410 according to this embodiment can quickly read data stored in the memory cell 310. Therefore, compared to the conventional technology, the MRAM 10 according to this embodiment can operate at a higher speed at the same voltage, and can operate at a lower voltage at the same operating speed.

[0061] 12F, since the DETECT signal becomes "1", the word line

[00] becomes "0". As a result, the access transistor 330 connected to the word line

[00] is turned off, and no current flows to the MTJ element 320 electrically connected to the access transistor 330. That is, in this embodiment, when the data read is completed, the word line

[00] is immediately and autonomously set to "0", thereby quickly turning off the access transistor 330 corresponding to the read MTJ element 320. Also, as shown in FIG. 12F, in this embodiment, the data output to the read output OUT_T is maintained by the NOR type RS latch circuit 470.

[0062] Although there is no particular problem if this state is maintained, the ACT signal is set to "0" in preparation for the next read, as shown in FIG. 12G. When the ACT signal becomes "0," the sense amplifier 410 becomes inactive, the ABLT[0] line and the ABLC line[0] are shorted, and the potentials of the ABLT[0] line and the ABLC line[0] drop to half the power supply potential (VDD / 2). Furthermore, the potentials of the ABLT[0] line and the ABLC line[0] drop to near the threshold (Vth) of the n-type MOS transistor 414, and then reach 0V due to leakage current. In this way, the MRAM 10 returns to its initial state. Furthermore, with the ACT signal becoming "0," the detector circuit 440 also returns to its initial state.

[0063] (Write Operation) Next, an example of a write operation of the MRAM 10 according to this embodiment will be described with reference to Figures 13A to 13J. Figures 13A to 13J are diagrams for explaining the write operation of the MRAM 10 according to this embodiment, showing the states of each signal and each node over time. In detail, from the top of the diagram, the address signal, the WDATA signal, the WRITE signal, the states of the ABLT line / ABLC line, the write-time word line control signal (WWL signal), the state of the word line

[00] corresponding to the memory cell 310 to be written, and the state of the write control (WCLT) line are shown.

[0064] First, the operation of the MRAM 10 starts from the initial state shown on the left side of FIG. 13A. The right side of FIG. 13A shows the specific states of each signal and each node at time . The ACT signal, which is controlled during reads, is fixed to "0" during writes. Then, as shown in FIG. 13B, a write address is input to the MRAM 10 (address "0000" is input). Because the ACT signal is "0," the dynamic NOR logic circuit 442 of the detector circuit 440 is inactive and does not function. Furthermore, the write word line control signal (WWL signal) is inverted via the NAND circuit 444 and output as the DETECT signal, which then controls the word line. In other words, at this point, the word line

[00] is waiting to be controlled by the WWL signal, and the word line

[00] remains at "0."

[0065] 13C, the WDATA signal is input to the MRAM 10. At this point, since the WRITE signal is "0", the three-state buffer 502 that drives the bit lines (ABLT line, ABLC line) is in a high impedance state, and the WDATA signal is not transmitted to the bit lines (ABLT[0] line, ABLC line[0]).

[0066] Next, as shown in Figure 13D, the WRITE signal is set to "1". By doing so, the three-state buffer 502 is activated, and the WDATA signal is transmitted to the bit lines (ABLT line, ABLC line). Then, as shown in Figure 13E, the write word line control signal (WWL signal) is also set to "1". By doing so, the word line

[00] also becomes "1".

[0067] 13F, a current flows from the ABLT line, which is set to "1," to the WCTL line, which is set to "0," and a current flows through the MTJ element 320a. This state is maintained according to the amount of current and time required to rewrite the MTJ element 320a.

[0068] 13G, the WCLT (VGND) line is changed from "0" to "1." This causes a current to flow from the WCLT line to the ABLC line, which is at "0," and a current to flow through the MTJ element 320b. This state is maintained according to the amount of current and time required to rewrite the MTJ element 320b.

[0069] 13H, the WWL signal is returned to "0" and the word line

[00] is set to "0." In this way, no current flows through the MTJ elements 320a and 320b.

[0070] Next, as shown in FIG. 13I, the WRITE signal is set to "0" and the WCLT (VGND) line is set to "0". Note that in this embodiment, the switching does not have to be strictly simultaneous. Then, as shown in FIG. 13J, the ABLT line and the ABLC line are shorted, and the potentials of the ABLT line and the ABLC line drop to half the power supply potential (VDD / 2). In this way, the MRAM 10 returns to its initial state.

[0071] As described above, according to this embodiment, it is possible to provide an MRAM (memory device) 10 that can read data accurately while avoiding an increase in chip area, and that can operate at a higher speed if the power supply voltage is the same, and that can operate at a lower power supply voltage if the operating speed is the same.

[0072] Specifically, in this embodiment, the difference between the high-resistance state MTJ element 320 and the low-resistance state MTJ element 320 of one memory cell 310, which is one storage unit, is detected, and the difference is large. Therefore, in this embodiment, the difference is easier to read than in the conventional technology, enabling accurate data reading. As a result, this embodiment reduces the probability of a read error occurring, and does not require a redundant circuit or an error correction circuit to be provided in the MRAM 10. Therefore, this embodiment can avoid an increase in chip area and power consumption. Furthermore, this embodiment, unlike the conventional technology, does not require a reference cell.

[0073] Furthermore, in this embodiment, since the difference amount to be read is larger than in the conventional technology, the potential of the output with the higher resistance of the two outputs of the sense amplifier 410 rises quickly and quickly reaches the potential corresponding to the logic value "1." Therefore, the sense amplifier 410 according to this embodiment can quickly read data stored in the memory cell 310. Therefore, according to this embodiment, the MRAM 10 can operate faster at the same voltage and at a lower voltage at the same operating speed compared to the conventional technology. In addition, in this embodiment, the detector circuit 440 electrically connected to the sense amplifier 410 can immediately and autonomously set the word line to "0" upon completion of data reading, thereby quickly turning off the access transistor 330 corresponding to the MTJ element 320 from which data was read. Therefore, according to this embodiment, the current flowing from the sense amplifier 410 to the MTJ element 320 can be minimized, thereby reducing the power consumption of the MRAM 10 and improving its reliability.

[0074] <<2. Second Embodiment>> <2.1 Background> Next, the background that led the inventors to create the second embodiment of the present disclosure will be described with reference to Fig. 14 to Fig. 16. Fig. 14 is a diagram showing the configuration of a logic operation circuit 60a according to the prior art, and Fig. 15 is a diagram showing the circuit configuration of the logic operation circuit 60a according to the prior art. Also, Fig. 16 is a diagram illustrating an outline of the logic operation circuit 60 according to the second embodiment of the present disclosure.

[0075] The logic operation circuit 60 discussed here has memory cells 310 each consisting of an MTJ element 320, and a logic circuit that performs a logic operation. The logic operation circuit 60 stores a logic value in advance in the built-in memory cell 310, and can use the built-in logic circuit to perform a logic operation between externally input data and the stored logic value.

[0076] More specifically, as shown in FIG. 14, a logic operation circuit 60a according to the prior art mainly includes, for example, a memory cell 35 including an MTJ element 320, a write circuit 500 that writes a logical value to the memory cell 35, a logic circuit 65 that performs a logical operation, and a sense amplifier 410a that reads out the operation result.

[0077] Various circuit configurations have been proposed for such a logic operation circuit 60a. FIG. 15 shows an example of a circuit configuration of a logic operation circuit 60a that has been proposed in the past. The logic operation circuit 60a shown in FIG. 15 includes a memory cell 310 including two MTJ elements 320, a sense amplifier 410a, and a logic circuit 65 that performs AND / NAND logic operations using a Schmitt trigger precharge sense amplifier (ST-PCSA). In the example shown in FIG. 15, the sense amplifier 410a is grounded (connected to ground) through the memory cell 310, i.e., the MTJ element 320. Various circuit configurations have been proposed for the sense amplifier 410a used in the logic operation circuit 60a, but in all circuit configurations, the sense amplifier 410a is grounded through the MTJ element 320.

[0078] As explained above, the MTJ element 320 has a resistance of about several kΩ even in a low resistance state, and therefore, the operation of the sense amplifier 410a becomes unstable when the sense amplifier 410a is grounded via such an MTJ element 320. Therefore, in the conventional logic operation circuit 60a, it takes a long time to determine the operation result, and low-voltage operation is difficult.

[0079] In light of this situation, the present inventors have developed the second embodiment of the present disclosure, described below, while utilizing the configuration of the first embodiment of the present disclosure. FIG. 16 shows a schematic configuration of a logic operation circuit 60 according to the second embodiment of the present disclosure. As shown on the left side of FIG. 16 , in this embodiment, similar to the prior art, the logic operation circuit 60 mainly includes a differential logic tree cell 70 including two MTJ elements 320 and a logic circuit 65, a sense amplifier 410, and a write circuit 500. Here, the differential logic tree cell 70 refers to a unit cell including a memory element that stores a logical value and a differential logic circuit 65 that can perform a logical operation using the logical value and externally input data. In this embodiment, as shown on the right side of FIG. 16 , the sense amplifier 410 is grounded without passing through the MTJ element 320. Specifically, in this embodiment, the sense amplifier 410 includes two inverters 420 whose input / output terminals are connected in a loop, similar to the sense amplifier 410 of the first embodiment of the present disclosure. The sense amplifier 410 itself is directly connected to ground (grounded). Therefore, according to this embodiment, the operation of the sense amplifier 410 is stable. As a result, according to this embodiment, the logical operation circuit 60 can quickly determine the operation result (high-speed operation) and is also suitable for low-voltage operation.

[0080] Furthermore, no specific configuration of the write circuit 500 for writing data to the memory element has been proposed for the logic operation circuit 60a. Therefore, in the second embodiment of the present disclosure, a suitable write circuit 500 that takes into account the characteristics of the MTJ element 320 will also be described. Details of the second embodiment of the present disclosure will be described below.

[0081] 2.2 Detailed Configuration (Logic Operation Circuit 60) First, with reference to FIG. 17 , the overall configuration of the logic operation circuit 60 according to the second embodiment of the present disclosure will be described. FIG. 17 is a diagram showing an example of the configuration of the logic operation circuit 60 according to this embodiment. As shown in FIG. 17 , in this embodiment, the logic operation circuit 60 mainly includes a differential logic tree cell (MTJ logic tree) 70, a sense amplifier 410, and a write circuit 500. As described above, the differential logic tree cell 70 refers to a unit cell including a memory element that stores a logical value and a differential logic circuit 65 that can perform a logical operation using the logical value and externally input data. Below, the details of each element constituting the logic operation circuit 60 according to this embodiment will be sequentially described.

[0082] (Differential Logic Tree Cell 70) First, the configuration of a differential logic tree cell 70 according to this embodiment will be described with reference to Fig. 18 to Fig. 24. Fig. 18 is a diagram showing an example of the circuit configuration of a differential logic tree cell 70 according to this embodiment, and Fig. 19 is a diagram showing an example of the circuit configuration of a differential logic circuit 700 according to this embodiment. Also, Figs. 20 to 22 are diagrams explaining the operation of the differential logic tree cell 70 according to this embodiment, and Figs. 23 and 24 are diagrams showing an example of the circuit configuration of a differential logic tree cell 70 according to a modification of this embodiment.

[0083] As shown in FIG. 18 , in this embodiment, the differential logic tree cell 70 mainly includes a memory cell 720 including two MTJ elements (first and second magnetic memory elements) 320 and two access transistors (first and second access transistors) 710, and a differential logic circuit (differential logic circuit) 700 that performs a logical operation using the logical value (data) stored in the memory cell 720 and external data (a0, a0b) input from the outside.

[0084] In this embodiment, the memory cell 720 has a 2T2R configuration, similar to the memory cell 310 according to the first embodiment. Specifically, one terminal (first terminal) of the MTJ element 320 is electrically connected to one of the source and drain terminals (first terminal) of the access transistor 710, which is an n-type MOS transistor, and to the differential logic circuit 700. The other terminal (second terminal) of the MTJ element 320 is electrically connected to a write control line (WCTL line) (common reference potential line) extending in the column direction. The other terminal (second terminal) of the source and drain terminals of the access transistor 710 is electrically connected to a WBLT line and a WBLC line (first and second bit lines) extending in the column direction. The gate (third terminal) of the access transistor 710 is electrically connected to a write word line (WWL line) extending in the row direction and transmitting a WWL signal. In this embodiment, such memory cells 720 store logical values ​​used in calculations in a nonvolatile manner.

[0085] 18, the differential logic circuit 700 is a logic circuit that performs AND / NAND logical operations. The differential logic circuit 700 performs AND / NAND logical operations using the logical values ​​stored in the memory cells 720 and external data (a0, a0b) that are inverted from each other and input from the outside, and the operation results are read by the sense amplifier 410 via out / out_b (read bit lines, RBLT line, RBLC line).

[0086] In this embodiment, the differential logic circuit 700 is not limited to being a logic circuit that performs AND / NAND logical operations as shown in Fig. 18, but may also be a logic circuit that performs XNOR / XOR logical operations as shown in Fig. 19. Alternatively, the differential logic circuit 700 may be a logic circuit that performs OR / NOR logical operations as shown in Fig. 19. In other words, in this embodiment, by changing the wiring of the four n-type MOS transistors that constitute the differential logic circuit 700, logic circuits that perform different logical operations can be easily formed.

[0087] Also in this embodiment, similarly to the first embodiment of the present disclosure, data is stored in one memory cell 720, which is one storage unit. Specifically, in this embodiment, as shown on the left side of FIGS. 20 to 22 , one MTJ element 320 a is set to a low-resistance state (L) and the other MTJ element 320 b is set to a high-resistance state (H), thereby causing the memory cell 720 to store data with a logical value of "0." Furthermore, in this embodiment, one MTJ element 320 a is set to a high-resistance state (H) and the other MTJ element 320 b is set to a low-resistance state (L), thereby causing the memory cell 720 to store data with a logical value of "1."

[0088] As shown on the right side of FIGS. 20 to 22 , when external data (a0, a0b) is input to the differential logic circuit 700 and the sense amplifier 410 (described later) is activated, the external data of logic “1” is input. Of the two transistors that are turned ON, a larger current flows through the transistor connected to the MTJ element 320 in the low-resistance state (thick arrow), and a smaller current flows through the transistor connected to the MTJ element 320 in the high-resistance state (thin arrow). A difference occurs between the magnitudes of the two currents flowing from the sense amplifier 410 to the two lines (out / out_b). The output potential of the higher-resistance line of the sense amplifier 410 rises quickly and reaches the potential corresponding to logic “1.” Meanwhile, the output potential of the lower-resistance line quickly reaches the potential corresponding to logic “0.” In other words, the differential logic tree cell 70 can perform logic operations while reading the values ​​of the MTJ elements 320a and 320b.

[0089] 23, instead of the access transistor 710 made of an n-type MOS transistor, a transmission gate 712 made of a combination of an n-type MOS transistor and a p-type MOS transistor may be used. In this case, the WWL_B line electrically connected to the gate of the p-type MOS transistor always has the polarity inverted with respect to the signal on the WWL line. In this way, by using the transmission gate 712 made of a combination of an n-type MOS transistor and a p-type MOS transistor, it is possible to increase the current flowing when writing a logical value to the MTJ element 320, thereby enabling writing to the MTJ element 320 in a short time.

[0090] 24, in this embodiment, a p-type MOS transistor 714 may be used instead of the access transistor 710 made of an n-type MOS transistor. In this case, the WWL_B line electrically connected to the gate of the p-type MOS transistor always has an inverted polarity with respect to the signal on the WWL line described above.

[0091] (Sense Amplifier 410) Next, the configuration of the sense amplifier 410 according to this embodiment will be described with reference to Fig. 25 and Fig. 26. Fig. 25 is a diagram showing an example of the circuit configuration of the sense amplifier 410 according to this embodiment, and Fig. 26 is a diagram showing an example of the circuit configuration of the sense amplifier 410 according to a modification of this embodiment.

[0092] The sense amplifier 410 according to this embodiment is a circuit that reads out the operation result of the differential logic tree cell 70. In detail, as shown in FIG. 25 , the sense amplifier 410 is a digital differential sense amplifier that is electrically connected to the out / out_b of the differential logic tree cell 70, and is further electrically connected to a NOR RS latch circuit 430 and an inverter 432.

[0093] 25, in the same manner as in the first embodiment, the sense amplifier 410 includes two inverters 420 whose input / output terminals are connected in a loop, an n-type MOS transistor 414 that electrically connects the output terminals of the two inverters 420, and a p-type MOS transistor 412 that electrically connects the two inverters to a power supply. Furthermore, in this embodiment, the sense amplifier 410 includes an inverter 416 that is electrically connected to the gates of the n-type MOS transistor 414 and the p-type MOS transistor 412. In this embodiment, the operation result read out to the sense amplifier 410 is temporarily held in a NOR-type RS latch circuit 470, and then inverted by an inverter 432 and output.

[0094] As described in the first embodiment, the sense amplifier 410 according to this embodiment can operate at a higher speed than the conventional technology at the same voltage. Furthermore, in this embodiment, the sense amplifier 410 is grounded without passing through the MTJ element 320 (differential logic tree cell 70). Specifically, in this embodiment, the sense amplifier 410 itself is directly connected to ground (grounded). Therefore, in this embodiment, the operation of the sense amplifier 410 is stable. Therefore, according to this embodiment, the logic operation circuit 60 can quickly determine the operation result (high-speed operation) and is also suitable for low-voltage operation. Details of the read operation in this embodiment will be described later.

[0095] In this embodiment, as shown in FIG. 26 , the sense amplifier 410 may further include a shutoff circuit 448 for autonomously shutting off the sense amplifier 410. The shutoff circuit 448 according to this embodiment has the same configuration as the detector circuit 440 according to the first embodiment of the present disclosure. Specifically, the shutoff circuit 448 includes a dynamic NOR logic circuit 442 electrically connected to the sense amplifier 410 and having two input terminals. In this embodiment, the inclusion of such a shutoff circuit 448 allows the sense amplifier 410 to be immediately and autonomously turned off quickly upon completion of reading of the operation result. Therefore, according to this embodiment, the current flowing from the sense amplifier 410 can be minimized, thereby reducing the power consumption and improving the reliability of the logic operation circuit 60. Note that the shutoff circuit 448 may include an inverter loop 450, similar to the first embodiment, which is composed of two inverters whose input / output terminals are connected in a loop.

[0096] (Write Circuit 500) Next, a description will be given of the configuration of the write circuit 500 according to this embodiment. The write circuit 500 according to this embodiment is a circuit for writing a logical value to the memory cell 720, and is configured in the same manner as the write circuit 500 according to the first embodiment shown in FIG.

[0097] 11, the write circuit 500 in this embodiment also includes two three-state buffers 502 electrically connected to the WBLT line and the WBLC line (first and second bit lines), respectively, and an inverter (common reference potential line control circuit) 504 electrically connected to the WCTL line (common reference potential line). Therefore, the details of the configuration of the write circuit 500 according to this embodiment are the same as those in the first embodiment, and therefore, a description thereof will be omitted. Details of the write operation in this embodiment will be described later.

[0098] In the embodiment of the present disclosure, the logical operation circuit 60 is not limited to the forms shown in FIGS. 17 to 26, but can be modified into various forms.

[0099] 2.3 Operation (Read Operation) Next, an example of a read operation of the logic operation circuit 60 according to this embodiment will be described with reference to Fig. 27A to Fig. 27I. Fig. 27A to Fig. 27I are diagrams illustrating the read operation of the logic operation circuit 60 according to this embodiment.

[0100] 27A, during a read operation, the WWL line is set to "0", the WRITE signal is set to "0", the WCLT line is set to "0", and the WDATA signal is set to "0" or "1". In the example described below, the MTJ element 320a is set to a high resistance state ("H"), and the MTJ element 320b is set to a low resistance state ("L"). At this time, the three-state buffer 502 of the write circuit 500 is set to a high impedance ("Z") state.

[0101] Next, the input data pair (a0, a0b) to which external data is input is "0, 0" in the initial state. When a logical value "0" is input as external data to the logic operation circuit 60, "0, 1" is input to the input data pair (a0, a0b), and when a logical value "1" is input as external data, "1, 0" is input to the input data pair (a0, a0b). In the example described below, a logical value "1" ("1, 0") is input to the logic operation circuit 60 as external data, as shown in FIG. 27B.

[0102] Next, as shown in Figure 27C, the ACT signal is changed from "0" to "1." This activates the sense amplifier 410, and current begins to flow from the RBLT and RBLC lines, which are a pair of read bit lines, toward the MTJ elements 320a and 320b. As shown in Figure 27C, because the MTJ element 320b is in a low resistance state ("L"), the current flowing to the RBLC line increases (thick arrow).

[0103] 27D, due to the difference in current flowing through the RBLT line and the RBLC line, the potential of the RBLT line rises more quickly than that of the RBLC line, and this potential difference is quickly amplified by the sense amplifier 410, causing the RBLC line to assume a logical value of "1." Then, as shown in FIG. 27E, the logical value of "1" is held by the RS latch circuit 470 connected to the sense amplifier 410. In this way, the logical operation circuit 60 according to this embodiment can perform an operation (AND in this example) using the logical values ​​stored in the MTJ elements 320a and 320b and external data.

[0104] Next, as shown in FIG. 27F, the ACT signal is returned to "0." This stops the current flowing from the sense amplifier 410. Furthermore, since the sense amplifier 410 short-circuits the RBLT and RBLC lines, the potentials temporarily drop to half the power supply potential (VDD / 2). The remaining charge in the parasitic capacitance of the sense amplifier 410 then flows to GND via the MTJ element 320, causing the RBLT and RBLC lines to immediately return to 0V potential. Next, as shown in FIG. 27G, the input data pair (a0, a0b) is returned to "0, 0" to return to the initial state. At this time, the logical value "1" as the operation result is held by the RS latch circuit 470.

[0105] In this embodiment, as shown in FIG. 27H, after the calculation result is determined, the input data pair (a0, a0b) may be returned to "0, 0" without returning the ACT signal to "0." In this embodiment, since the loop-shaped inverter 420 of the sense amplifier 410 is grounded, doing so does not cause any operational problems. Thereafter, as shown in FIG. 27I, the ACT signal is returned to "0." By doing so, the RBLT line and the RBLC line are shorted, so the charge remaining in the RBLT line and the RBLC line moves from the high-voltage side to the low-voltage side, and the potentials of the RBLT line and the RBLC line temporarily drop to half the power supply potential (VDD / 2). The potentials of the RBLT line and the RBLC line then drop to near the threshold voltage (Vth) of the n-type MOS transistor 414, which shorts the inverter 420 of the sense amplifier 410, and then reach 0 V due to leakage current. In other words, it takes time for the potentials of the RBLT line and the RBLC line to reach 0 V. Therefore, by performing the next calculation before the potentials of the RBLT and RBLC lines reach 0 V, the remaining charge can be reused, thereby reducing power consumption by the amount of voltage caused by the remaining charge at that time. In addition, by doing this, the calculation time can be shortened because there is no need to wait until the potentials of the RBLT and RBLC lines reach 0 V.

[0106] 28A to 28F, an example of a write operation of the logic operation circuit 60 according to this embodiment will be described. Figures 28A to 28F are diagrams illustrating the write operation of the logic operation circuit 60 according to this embodiment.

[0107] 28A, the ACT signal is set to "0" and the input data pair (a0, a0b) to which external data is input is set to "0, 0." In this way, the sense amplifier 410 is deactivated and is disconnected from the MTJ elements 320a and 320b.

[0108] Next, as shown in FIG. 28B, the WRITE signal is set to "1." In this way, the values ​​of the WBLT line and WBLC line, which are write bit lines, change according to the value of the write data (WDATA) signal. Then, as shown in FIG. 28C, the value of the WWL signal on the write word line (WWL line) is set to "1." In this way, a current flows through the MTJ element 320a, and a logical value is written.

[0109] 28D, the WCTL line is switched from "0" to "1." In this way, a current flows through the MTJ element 320b in the opposite direction to that of the MTJ element 320a in FIG. 28C, and a logical value is written.

[0110] As shown in Figure 28E, the value of the WWL signal on the WWL line is changed from "1" to "0". This causes no current to flow through the MTJ elements 320a and 320b. Then, as shown in Figure 28F, the WRITE signal and the WCTL line are also set to "0". In this way, the logic operation circuit 60 returns to its initial state.

[0111] As described above, in this embodiment, the sense amplifier 410 is grounded without passing through the MTJ element 320 (differential logic tree cell 70). More specifically, in this embodiment, the sense amplifier 410 itself is directly connected to ground. Therefore, according to this embodiment, the operation of the sense amplifier 410 is stable. As a result, according to this embodiment, the logic operation circuit 60 can quickly determine the operation result (high-speed operation) and is also suitable for low-voltage operation.

[0112] 2.4 Modifications Next, the configuration of a logic operation circuit 60 according to a modification of this embodiment will be described with reference to Fig. 29 and Fig. 30. Fig. 29 and Fig. 30 are diagrams showing an example of the configuration of a logic operation circuit 60 according to a modification of this embodiment.

[0113] In this embodiment, the logic operation circuit 60 is not limited to the form shown in FIG. 17 and can be modified in various forms. For example, as shown in FIG. 29, one sense amplifier 410 and one write circuit 500 may be shared by a plurality of differential logic tree cells 70 arranged in a column direction. A plurality of such differential logic tree cells 70 arranged in a column direction may be arranged in a row direction to form a differential logic tree cell array. In this case, of the plurality of differential logic tree cells 70, exclusively one differential logic tree cell 70 is the target of operation. Therefore, the external input data of the non-target differential logic tree cell 70 is "0, 0", and the WRITE signal is "0".

[0114] 30, one sense amplifier 410 may be provided for one differential logic tree cell 70, and multiple pairs of differential logic tree cells 70 and sense amplifiers 410 may be provided. In this manner, operations can be performed simultaneously within multiple differential logic tree cells 70. Even in this case, multiple pairs of differential logic tree cells 70 and sense amplifiers 410 may share one write circuit 500. In the example of FIG. 30, while the circuit shown in FIG. 30 is provided, an operation mode may be provided in which only one differential logic tree cell 70 operates exclusively, as in the example of FIG. 29, in response to an external control signal. In this manner, it is possible to appropriately adjust operation performance and power consumption to meet the constraints of the required operation capacity and power consumption at any given time.

[0115] <<3. Third Embodiment>> <3.1 Background> Next, the background that led the inventors to create the third embodiment of the present disclosure will be described. Computing in Memory (CiM) is a device in which an arithmetic circuit that performs arithmetic operations is incorporated into a storage device, and has been actively researched in recent years.

[0116] However, the CiMs proposed so far use volatile static random access memory (SRAM) as the storage element, so when the CiM is started (powered on), the logical values ​​used for the calculations must be read from an external storage device. Therefore, a problem with CiMs using SRAM is that the processing time increases due to the amount of reading required.

[0117] Furthermore, many of the CiMs proposed to date have been CiMs with analog-type arithmetic circuits. Analog-type CiMs are a method of representing the result of a product-sum operation using the potential of a bit line, and use an AD (analog-digital) converter to convert the voltage value into a binary number (digital value). Specifically, data input to an analog-type CiM is converted into a single pulse, the time width of which corresponds to the data value. The analog-type CiM then lowers the bit line potential according to a predetermined amount of decrease (slope) per time for the duration indicated by the pulse width. Furthermore, each time data is input, the analog-type CiM repeatedly converts the data into a pulse and lowers the bit line potential, and finally converts the determined bit line potential into a binary number to obtain the product-sum operation result.

[0118] Therefore, because analog-type CiMs are analog, it is difficult to change the bit line potential with ideal linearity, making them prone to errors in the product-sum operation results. Furthermore, analog-type CiMs can also suffer from errors due to parasitic resistance and parasitic capacitance in the constituent circuits and manufacturing variations in circuit elements. Additionally, analog-type CiMs are prone to errors in the pulse width indicating the data value and the binary number converted by the AD converter due to noise from the power supply, etc. Furthermore, due to these errors, analog-type CiMs have a low effective calculation precision (bit width) of approximately 8 bits for general use. Furthermore, as the width between the initial bit line potential and the bit line potential corresponding to the final calculation result (limit potential) becomes smaller, the above error becomes even larger, necessitating a higher power supply potential. Therefore, analog-type CiMs have difficulty operating at low voltages, making it difficult to reduce power consumption.

[0119] In light of this situation, the inventors have developed the third embodiment of the present disclosure, described below, while utilizing the configurations of the first and second embodiments of the present disclosure. In this embodiment, a non-volatile MRAM is used as the storage element. Therefore, when the CiM is started (powered on), it is not necessary to read the logic values ​​used for the calculation from an external storage device, and calculation can be started immediately. Furthermore, since calculation can be started immediately according to this embodiment, power consumption can be reduced. Furthermore, since this embodiment is a CiM with a digital calculation circuit, it performs product-sum calculations in binary, eliminating the need for the AD converter. In addition, since this embodiment is a digital CiM, it has low error, can be freely expanded to any calculation precision, and is capable of low-voltage operation. Details of the third embodiment of the present disclosure will be described below.

[0120] 3.2 Detailed Configuration (CiM 80) First, the overall configuration of the CiM 80 according to the third embodiment of the present disclosure will be described with reference to Fig. 31 and Fig. 32. Fig. 31 is a diagram showing an example of the configuration of the CiM 80 according to this embodiment, and Fig. 32 is a diagram showing an example of the configuration of the main parts of the CiM 80 according to this embodiment.

[0121] As shown in FIG. 31 , a CiM (computing memory device) 80 according to this embodiment has a plurality of differential logic tree cells 70. Similar to the second embodiment described above, the plurality of differential logic tree cells 70 include memory cells 720 and differential logic circuits (differential logic circuits) 700 that perform logical operations (AND) using coefficients (data) stored in the memory cells 720 and external data input from the outside. In the CiM 80, the plurality of differential logic tree cells 70 are arranged in a matrix along the row and column directions, and one sense amplifier 410 and one write circuit 500 are shared by the plurality of differential logic tree cells 70 arranged along the column direction. Therefore, each sense amplifier 410 can read the respective operation results of the plurality of differential logic tree cells 70 located in the same column, and the write circuit 500 can write coefficients to each of the plurality of differential logic tree cells 70 located in the same column. As shown in FIG. 31, a plurality of differential logic tree cells 70 sharing one sense amplifier 410 and one write circuit 500 are arranged in the row direction to form a cell array 82 .

[0122] 32 showing the cell array 82, the multiple differential logic tree cells 70 are connected to one another by input data lines to which external data (a, ab) are input and write word lines (WWL lines). In the CiM 80, external data input from the outside is distributed to the multiple differential logic tree cells 70 arranged in the row direction, and operations are performed in parallel between the external data and the coefficients (W) stored in each differential logic tree cell 70. The operation results of each differential logic tree cell 70 are then read out by each sense amplifier 410.

[0123] 31, the CiM80 has an adder (digital arithmetic circuit) (Shift & Adder) 90 that adds the arithmetic results read by each sense amplifier 410. The adder 90 sequentially performs cumulative addition on the arithmetic results of each differential logic tree cell 70 to obtain a multiplication result or a product-sum result. Details of each element constituting the CiM80 according to this embodiment will be described below in order.

[0124] (Differential Logic Tree Cell 70) First, the configuration of the differential logic tree cell 70 according to this embodiment will be described with reference to Fig. 33 and Fig. 34. Fig. 33 is a diagram showing an example of the circuit configuration of the differential logic tree cell 70 according to this embodiment, and Fig. 34 is a diagram explaining the operation of the differential logic tree cell 70 according to this embodiment.

[0125] The differential logic tree cell 70 according to this embodiment utilizes the differential logic tree cell 70 according to the second embodiment of the present disclosure. Specifically, as shown in FIG. 33 , in this embodiment, the differential logic tree cell 70 mainly includes a memory cell 720 including two MTJ elements (first and second magnetic memory elements) 320 and two access transistors (first and second access transistors) 710, and a differential logic circuit (differential logic circuit) 700 that performs a logical operation using a coefficient stored in the memory cell 720 and external data (a0, a0b) input from the outside. In this embodiment, similar to the memory cell 720 according to the second embodiment, one terminal (first terminal) of the MTJ element 320 is electrically connected to one of the source / drain terminals (first terminal) of the access transistor 710, which is an n-type MOS transistor, and to the differential logic circuit 700. The other terminal (second terminal) of the MTJ element 320 is electrically connected to a WCTL line (common reference potential line) extending in the column direction. The other of the source / drain (second terminal) of the access transistor 710 is electrically connected to a WBLT line and a WBLC line (first and second bit lines) extending in the column direction. The gate (third terminal) of the access transistor 710 is electrically connected to a write word line (WWL line) extending in the row direction. In this embodiment, the memory cell 720 stores coefficients and the like used in arithmetic operations in a nonvolatile manner.

[0126] The differential logic circuit 700 is a logic circuit that performs AND / NAND logical operations. The operation result of the differential logic circuit 700, which has a logic circuit that performs AND / NAND logical operations, corresponds to the partial product in binary multiplication. In this embodiment, the differential logic circuit 700 is not limited to a logic circuit that performs AND / NAND logical operations, but may be a logic circuit that performs XNOR / XOR logical operations, or a logic circuit that performs OR / NOR logical operations, or these logic circuits may be mixed within a single CiM. The differential logic circuit 700 performs AND / NAND logical operations using coefficients stored in the memory cells 720 and externally input, mutually inverted external data (a0, a0b). The operation result is read by the sense amplifier 410 via the read bit line, RBLT line, and RBLC line.

[0127] Also in this embodiment, similarly to the first and second embodiments of the present disclosure, data is stored in one memory cell 720, which is one storage unit. Specifically, as shown on the left side of FIG. 34 , one MTJ element 320a is set to a low-resistance state (L) and the other MTJ element 320b is set to a high-resistance state (H), thereby causing the memory cell 720 to store data with a logical value of "0." Furthermore, in this embodiment, one MTJ element 320a is set to a high-resistance state (H) and the other MTJ element 320b is set to a low-resistance state (L), thereby causing the memory cell 720 to store data with a logical value of "1."

[0128] As shown on the right side of FIG. 34 , when external data (a0, a0b) is input to the differential logic circuit 700 and the sense amplifier 410 (described later) is activated, the external data of logic “1” is input. Of the two transistors in the differential logic circuit 700 that are turned on, a larger current flows through the transistor connected to the MTJ element 320 in the low-resistance state (thick arrow), and a smaller current flows through the transistor connected to the MTJ element 320 in the high-resistance state (thin arrow). A difference in magnitude occurs between the two currents flowing from the sense amplifier 410 to the RBLT and RBLC lines. The output potential of the RBLT or RBLC line with the higher resistance rises quickly and reaches the potential corresponding to logic “1.” Meanwhile, the output potential of the low-resistance line quickly reaches the potential corresponding to logic “0.” In other words, the differential logic tree cell 70 can perform logic operations while reading the values ​​of the MTJ elements 320a and 320b.

[0129] (Sense Amplifier 410) Next, the configuration of the sense amplifier 410 according to this embodiment will be described. The sense amplifier 410 according to this embodiment utilizes the sense amplifier 410 according to the second embodiment of the present disclosure described above and is configured similarly to the sense amplifier 410 according to the second embodiment shown in FIG. 25. The sense amplifier 410 is a digital differential sense amplifier, electrically connected to the RBLT line and the RBLC line of the differential logic tree cell 70 and further electrically connected to a NOR RS latch circuit 430. The calculation result read by the sense amplifier 410 is temporarily held in a NOR RS latch circuit 470. More specifically, by synchronizing the ACT signal that controls the sense amplifier 410 with the clock that controls the adder 90, the calculation result is held for one cycle of the clock. This is convenient because it ensures sufficient calculation time for the adder 90 connected subsequently. Note that detailed configuration of the sense amplifier 410 according to this embodiment is similar to that of the sense amplifier 410 according to the second embodiment of the present disclosure described above, and therefore will not be described here.

[0130] (Write Circuit 500) Next, the configuration of the write circuit 500 according to this embodiment will be described. The write circuit 500 according to this embodiment is a circuit for writing logical values ​​to the memory cells 720, and is configured similarly to the write circuit 500 according to the first embodiment shown in Fig. 11. Therefore, detailed description of the configuration of the write circuit 500 according to this embodiment will be omitted.

[0131] (Adder 90) Next, the configuration of the adder 90 according to this embodiment will be described with reference to FIG. 35. FIG. 35 is a diagram showing an example of the circuit configuration of the adder 90 according to this embodiment. As shown in FIG. 35, the adder 90 according to this embodiment is composed of a shift circuit 96, an adder circuit 92, and a register 94. The adder 90 successively adds up the operation results output from the differential logic tree cell 70. In detail, in the adder 90, the shift circuit 96 logically shifts the operation result immediately before the current operation result held in the register 94 to the left by one bit (equivalent to doubling in binary numbers). Then, the adder circuit 92 adds up the shifted operation result immediately before and the newly input operation result.

[0132] That is, since the calculation result of the differential logic circuit 700 having a logic circuit that performs AND / NAND logical operations corresponds to the partial product in the multiplication of binary numbers, the adder 90 is a digital integrating circuit, and the multiplication result can be obtained by summing up the partial products in the adder 90.

[0133] In the embodiment of the present disclosure, the CiM 80 is not limited to the forms shown in FIGS. 31 to 35, but can be modified into various forms.

[0134] 3.3 Operation Next, an example of the operation of the CiM 80 according to this embodiment will be described with reference to Figures 36A to 36E. Figures 36A to 36E are diagrams illustrating the operation of the CiM 80 according to this embodiment. In the example described here, it is assumed that the CiM 80 performs binary multiplication.

[0135] 36A, it is assumed that 4-bit binary coefficients "W3, W2, W1, W0" are stored bit by bit along the row direction in the differential logic tree cell 70. It is also assumed that the external data D to be multiplied by the coefficient W is also a 4-bit binary number "D3, D2, D1, D0."

[0136] Next, as shown in Fig. 36B, first, the most significant bit D3 is input to the CiM 80. Then, as shown in Fig. 36C, the result of an AND operation between the coefficients "W3, W2, W1, W0" stored in each differential logic tree cell 70 and "D3" is output.

[0137] 36D, "D2" is input to CiM80, and the result of the AND operation between "D2" and the coefficients "W3, W2, W1, W0" stored in each differential logic tree cell 70 is output. Furthermore, CiM80 shifts the previous operation result "D3 and W3, W2, W1, W0" one bit to the left, and then adds the current operation result "D2 and W3, W2, W1, W0." As explained above, in binary arithmetic, shifting one bit to the left is equivalent to doubling.

[0138] Then, as shown in FIG. 36E, by performing the same operation on "D1" and "D0", the CiM 80 can obtain the multiplication result.

[0139] As described above, in this embodiment, since the nonvolatile MTJ element 320 is used as the storage element, when the CiM80 is started (powered on), there is no need to read coefficients from an external storage device, and calculations can begin immediately. Therefore, according to this embodiment, since calculations can begin immediately, power consumption can be kept low. Furthermore, since this embodiment uses a CiM80 with a digital calculation circuit, product-sum calculations can be performed in binary numbers, and an AD converter is not required. In addition, since this embodiment uses a digital CiM80, there is little error, it can be freely expanded to any calculation precision, and it is possible to operate at a low voltage.

[0140] <3.4 Modification> Next, the configuration of the CiM 80 according to a modification of this embodiment will be described with reference to Fig. 37. Fig. 37 is a diagram showing an example of the configuration of the CiM 80 according to a modification of this embodiment.

[0141] For example, when handling 8-bit coefficients W "W7, W6, W5, W4, W3, W2, W1, W0," eight differential logic tree cells 70 may be arranged in the row direction, as shown in FIG. 37. In this case, the CiM80 repeats the above-described calculation operation eight times. In this way, the CiM80 according to this embodiment can be easily expanded to any calculation precision (bit width).

[0142] Furthermore, in this embodiment, the differential logic tree cells 70 may be arranged in the column direction, and in this case, different coefficients may be stored in each differential logic tree cell 70. Then, a target row may be selected at each time, and an operation may be performed using the differential logic tree cell 70 in the selected row.

[0143] 3.5 Application Examples Next, applications of the CiM80 according to this embodiment will be described with reference to Fig. 38 and Fig. 39. Fig. 38 is a diagram showing an example of processing in the electronic device according to this embodiment, and Fig. 39 is a diagram illustrating a comparison of processing times between this embodiment and conventional technology.

[0144] In recent years, electronic devices have been proposed that combine sensor devices, such as imaging devices (image sensors) and sound collection devices, with processing devices for analyzing (recognition processing) the sensing data acquired by the sensor devices. For example, devices equipped with AI (Artificial Intelligence) for advanced analytical processing are called edge AI and are being actively researched. In such devices, as shown in FIG. 38 , an "Always On Device" (driver) and a "Normally Off Device" are used to suppress increases in power consumption. The "Always On Device" constantly analyzes the sensing data, but limits the analysis to a rough analysis to suppress power consumption. When the "Always On Device" captures specified sensing data, it sends a trigger to the "Normally Off Device" to activate the "Normally Off Device." Although "Normally Off Device" can perform advanced analysis, it will not operate without the above trigger in order to reduce power consumption.

[0145] When a CiM using a volatile SRAM according to the prior art is used as the "Normally Off Device" as described above, when the CiM is started (powered on), the logical values ​​(coefficients) must be read from an external storage device. Therefore, as shown in the upper part of Figure 39, a CiM using SRAM takes a long time to process.

[0146] Therefore, when the CiM80 according to this embodiment is used as a "Normally Off Device," since the nonvolatile MTJ element 320 is used, when the CiM80 is started (powered on), there is no need to read out logical values ​​from an external storage device, as shown in the lower part of FIG. 39 . In other words, when the CiM80 according to this embodiment is used as a "Normally Off Device," it is possible to start calculations immediately. Therefore, according to this embodiment, since calculations can be started immediately, it is possible to shorten processing time and keep power consumption low.

[0147] <<4. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0148] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0149] The present technology can also be configured as follows: (1) A logic operation circuit comprising: a differential logic tree cell; and a digital differential sense amplifier that reads out an operation result of the differential logic tree cell, wherein the differential logic tree cell includes: memory cells including first and second magnetic memory elements that store data based on a change in resistance value; and a differential logic circuit that performs a logic operation using the data stored in the memory cells and external data input from the outside, and the digital differential sense amplifier is grounded without passing through the differential logic tree cell. (2) The logic operation circuit according to (1), wherein each of the first and second magnetic memory elements has: a fixed layer whose magnetization direction is fixed, a free layer whose magnetization direction is variable, and a nonmagnetic layer sandwiched between the fixed layer and the free layer. (3) The logic operation circuit according to (1) or (2), wherein the digital differential sense amplifier includes: two inverters having input / output terminals connected in a loop; a first switch connecting output terminals of the two inverters; and a second switch connecting the two inverters to a power supply. (4) The logic operation circuit according to (3), wherein the digital differential sense amplifier further includes a shutoff circuit for autonomous shutoff, the shutoff circuit being made of a dynamic NOR logic circuit electrically connected to the digital differential sense amplifier. (5) The logic operation circuit according to (4), wherein the dynamic NOR logic circuit further includes two inverters having input / output terminals connected in a loop, the input / output terminals being electrically connected to an output node of the dynamic NOR logic circuit and holding the state of the output node. (6) The logic operation circuit according to any one of (3) to (5), wherein the digital differential sense amplifier is electrically connected to a NOR RS latch circuit. (7) The logic operation circuit according to any one of (1) to (6), wherein the memory cell further includes first and second access transistors electrically connected to the first and second magnetic memory elements, respectively. (8) The logic operation circuit according to (7), wherein the first and second access transistors are n-type MOS transistors.(9) The logic operation circuit according to (7), wherein the first and second access transistors are p-type MOS transistors. (10) The logic operation circuit according to (7), wherein the first and second access transistors are transmission gates. (11) The logic operation circuit according to any one of (7) to (10), wherein first terminals of the first and second magnetic memory elements are electrically connected to first terminals of the first and second access transistors, respectively, second terminals of the first and second magnetic memory elements are electrically connected to common reference potential lines extending in a column direction, second terminals of the first and second access transistors are electrically connected to first and second bit lines extending in the column direction, and third terminals of the first and second access transistors are electrically connected to word lines extending in a row direction. (12) The logic operation circuit according to (11), further comprising a write circuit that writes the data to the memory cell, wherein the write circuit applies a voltage such that a current flows from the first terminal to the second terminal of the first magnetic memory element and applies a voltage such that a current flows from the second terminal to the first terminal of the second magnetic memory element, thereby writing a first value to the memory cell, and applies a voltage such that a current flows from the second terminal to the first terminal of the first magnetic memory element, thereby writing a second value to the memory cell. (13) The logic operation circuit according to (12), wherein the write circuit includes: two three-state buffers electrically connected to the first and second bit lines, respectively; and a common reference potential line control circuit electrically connected to the common reference potential line. (14) The logic operation circuit according to any one of (1) to (13) above, wherein the differential logic circuit is constituted by an AND / NAND circuit. (15) The logic operation circuit according to any one of (1) to (13) above, wherein the differential logic circuit is constituted by an OR / NOR circuit. (16) The logic operation circuit according to any one of (1) to (13) above, wherein the differential logic circuit is constituted by an XNOR / XOR circuit.(17) The logic operation circuit according to (12), comprising a differential logic tree cell array in which a plurality of the differential logic tree cells are arranged. (18) The logic operation circuit according to (17), in which the digital differential sense amplifier is provided for each of the differential logic tree cells. (19) The logic operation circuit according to (17), in which the digital differential sense amplifier is provided so as to be shared by the plurality of differential logic tree cells. (20) The logic operation circuit according to (17), in which the write circuit is provided so as to be shared by the plurality of differential logic tree cells.

[0150] 10 MRAM 20 Word line driver 30 Memory cell array 35, 310, 310a, 720 Memory cell 40 Peripheral circuit section 60, 60a Logic operation circuit 65 Logic circuit 70 Differential logic tree cell 80 CiM 82 Cell array 90 Adder 92 Addition circuit 94 Register 96 Shift circuit 202 Address decoder 204, 212, 416, 420, 432, 504 Inverter 210, 444 NAND circuit 320, 320a, 320b MTJ element 322 Free layer 324 Non-magnetic layer 326 Fixed layer 330, 710 Access transistor 350 Multiplexer circuit 352 Transmission gate 400 Read circuit 410, 410a Sense amplifier 412, 414, 445, 446, 714 Transistor 418 NOR circuit 430, 470 RS latch circuit 440 Detector circuit 442 Dynamic NOR logic circuit 448 Shut-off circuit 450 Inverter loop 500 Write circuit 502 3-state buffer 700 Differential logic circuit 712 Transmission gate

Claims

1. A differential logic tree cell and a digital differential sense amplifier for reading out the operation result of the differential logic tree cell, the differential logic tree cell including a memory cell including first and second magnetic memory elements for storing data according to a change in resistance value, and a differential logic circuit for performing a logic operation using the data stored in the memory cell and external data input from the outside, the digital differential sense amplifier being a logic operation circuit that is grounded without passing through the differential logic tree cell.

2. Each of the first and second magnetic memory elements has a fixed layer with a fixed magnetization direction, a free layer with a variable magnetization direction, and a non-magnetic layer sandwiched between the fixed layer and the free layer, the logic operation circuit according to claim 1.

3. The digital differential sense amplifier includes two inverters with input / output terminals connected in a loop, a first switch for connecting the output terminals of the two inverters, and a second switch for connecting the two inverters and a power supply, the logic operation circuit according to claim 1.

4. The digital differential sense amplifier further includes a shut-off circuit for self-shutting off, the shut-off circuit being a dynamic NOR logic circuit electrically connected to the digital differential sense amplifier, the logic operation circuit according to claim 3.

5. The dynamic NOR logic circuit further includes two inverters with input / output terminals connected in a loop, which are electrically connected to the output node of the dynamic NOR logic circuit and hold the state of the output node, the logic operation circuit according to claim 4.

6. The digital differential sense amplifier includes being electrically connected to a NOR-type RS latch circuit, the logic operation circuit according to claim 3.

7. The memory cell further includes first and second access transistors electrically connected to each of the first and second magnetic memory elements, the logic operation circuit according to claim 1.

8. The first and second access transistors are n-type MOS transistors, the logic operation circuit according to claim 7.

9. The first and second access transistors are p-type MOS transistors, the logic operation circuit according to claim 7.

10. The first and second access transistors are transmission gates, and the logic operation circuit according to claim 7.

11. Each of the first terminals of the first and second magnetic memory elements is electrically connected to each of the first terminals of the first and second access transistors, the second terminals of the first and second magnetic memory elements are electrically connected to a common reference potential line extending in the column direction, each of the second terminals of the first and second access transistors is electrically connected to first and second bit lines extending in the column direction, and the third terminals of the first and second access transistors are electrically connected to a word line extending in the row direction, and the logic operation circuit according to claim 7.

12. The logic operation circuit according to claim 11, further comprising a writing circuit for writing the data into the memory cell, wherein the writing circuit applies a voltage so that a current flows from the first terminal to the second terminal of the first magnetic memory element, and applies a voltage so that a current flows from the second terminal to the first terminal of the second magnetic memory element to write a first value into the memory cell, and applies a voltage so that a current flows from the second terminal to the first terminal of the first magnetic memory element, and applies a voltage so that a current flows from the first terminal to the second terminal of the second magnetic memory element to write a second value into the memory cell.

13. The writing circuit includes two three-state buffers electrically connected to each of the first and second bit lines, and a common reference potential line control circuit electrically connected to the common reference potential line, and the logic operation circuit according to claim 12.

14. The differential logic circuit is composed of an AND / NAND circuit, and the logic operation circuit according to claim 1.

15. The differential logic circuit is composed of an OR / NOR circuit, and the logic operation circuit according to claim 1.

16. The differential logic circuit is composed of an XNOR / XOR circuit, and the logic operation circuit according to claim 1.

17. The logic operation circuit according to claim 12, comprising a differential logic tree cell array in which a plurality of the differential logic tree cells are arranged.

18. For each of the differential logic tree cells, a digital differential sense amplifier is provided, and the logic operation circuit according to claim 17.

19. The logic operation circuit according to claim 17, wherein the digital differential sense amplifier is provided so as to be shared by the plurality of differential logic tree cells.

20. The logic operation circuit according to claim 17, wherein the writing circuit is provided so as to be shared by the plurality of differential logic tree cells.

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