Semiconductor module and manufacturing method for semiconductor module

Abstract

A semiconductor module (1) comprises: a semiconductor device (100) provided with n-number of pads (101); and a mounting substrate (200) provided with n-number of lands (201) corresponding to the n-number of pads (101) in a one-to-one manner. Each of the n-number of pads (101) is joined to, among the n-number of lands (201), one land (201) corresponding to the pad (101) via a solder bonding material (301). When the area of a nearest pad (101a) that is nearest to the center of the semiconductor device (100) among the n-number of pads (101) is defined as Pa, the area of a farthest pad (101b) that is farthest from said center is defined as Pb, the area of a nearest land (201a) corresponding to the nearest pad (101a) among the n-number of lands (201) is defined as La, and the area of a farthest land (201b) corresponding to the farthest pad (101b) is defined as Lb, Pa / La is less than 1 and Pb / Lb is greater than 1, or Pa / La is greater than 1 and Pb / Lb is less than 1.

Description

Semiconductor module and method for manufacturing the semiconductor module

[0001] The present disclosure relates to a semiconductor module in which a semiconductor device is mounted on a mounting substrate.

[0002] 2. Description of the Related Art Conventionally, semiconductor modules in which a semiconductor device is mounted on a mounting substrate have been known.

[0003] JP 2019-129312 A JP 2020-038999 A

[0004] Conventionally, a technique has been known for manufacturing a semiconductor module in which a semiconductor device is mounted on a mounting substrate by reflow mounting, using a solder bonding material, a semiconductor device having n (n is an integer of 2 or more) pads to a mounting substrate having n lands that correspond one-to-one to the n pads.

[0005] On the other hand, in semiconductor modules manufactured in this manner, it is necessary to prevent defects related to the solder bonding material that joins the pads and lands, such as the solder bonding material overflowing from the pad or land, or chipping off the pad or land.

[0006] Therefore, an object of the present disclosure is to provide a semiconductor module or the like that can suppress the occurrence of defects related to solder bonding materials.

[0007] A semiconductor module according to one aspect of the present disclosure is a semiconductor module in which a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors is mounted face-down on a mounting substrate, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a plan view of the semiconductor device is curved convexly in a direction away from the mounting substrate or convexly in a direction toward the mounting substrate, the mounting substrate includes n lands corresponding to the n pads in a one-to-one relationship, and each of the n pads is a pad among the n lands corresponding to the pad. When the area of ​​the nearest pad, which is closest to the center of the semiconductor device in the planar view of the semiconductor device, among the n pads joined to one land with a solder bonding material, is Pa, the area of ​​the farthest pad, which is farthest from the center of the semiconductor device in the planar view of the semiconductor device, is Pb, the area of ​​the nearest land, which is the n lands and corresponds to the nearest pad, is La, and the area of ​​the farthest land, which is the farthest pad, in the planar view of the mounting board, is Lb, Pa / La is smaller than 1 and Pb / Lb is greater than 1, or Pa / La is greater than 1 and Pb / Lb is smaller than 1.

[0008] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module by face-down mounting a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors onto a mounting substrate using a stencil, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a planar view of the semiconductor device is convexly curved in a direction away from the mounting substrate, the mounting substrate includes n lands corresponding one-to-one to the n pads, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings being an opening for forming a solder bonding material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, and the nearest pad from the center of the semiconductor device in a planar view of the semiconductor device is the nearest pad from the center of the semiconductor device. and a second step of performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and bonding each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step.

[0009] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module by face-down mounting a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors onto a mounting substrate using a stencil, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a planar view of the semiconductor device is convexly curved in a direction approaching the mounting substrate, the mounting substrate includes n lands corresponding one-to-one to the n pads, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings being an opening for forming a solder bonding material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, the solder bonding material being used to bond the one of the n pads corresponding to the opening, the nearest pad from the center of the semiconductor device in a planar view of the semiconductor device. and a second step of performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and bonding each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step.

[0010] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module using a stencil, wherein the semiconductor device has a center in a plan view of the semiconductor device that is convex in a direction away from the mounting substrate, the stencil has n openings that correspond one-to-one to the n pads, and each of the n openings is an opening for forming a solder joint material above one of the pads that corresponds to the opening and one of the n lands that corresponds to the opening, and a pad that is closest to the center of the semiconductor device in a plan view of the semiconductor device is formed by forming a solder joint material above the one of the pads that corresponds to the opening and the land that corresponds to the opening, and where Pa is the area of ​​the semiconductor device in a planar view, La is the area of ​​the mounting substrate in a planar view of the nearest land among the n lands that corresponds to the nearest pad, and Sa is the area of ​​the stencil in a planar view of the nearest opening among the n openings that corresponds to the nearest pad, Sa is larger than both Pa and La, and the method includes a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one of the n lands that corresponds to the pad using the solder bonding material formed above the one land by performing the first step.

[0011] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module using a stencil, wherein the semiconductor device has a center of the semiconductor device in a plan view of the semiconductor device that is convex in a direction away from the mounting substrate, the stencil has n openings that correspond one-to-one to the n pads, and each of the n openings is an opening for forming a solder joint material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, and a farthest pad from the center of the semiconductor device in a plan view of the semiconductor device is formed by forming a solder joint material above the one of the pads corresponding to the opening and one of the n lands corresponding to the opening. where Pb is the area of ​​the semiconductor device in a planar view, Lb is the area of ​​the mounting substrate of the farthest land of the n lands that corresponds to the farthest pad, and Sb is the area of ​​the stencil of the farthest opening of the n openings that corresponds to the farthest pad, Sb is smaller than both Pb and Lb, and the method includes a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one of the n lands that corresponds to the pad using the solder bonding material formed above the one land by performing the first step.

[0012] According to a semiconductor module and the like according to one aspect of the present disclosure, the occurrence of defects related to solder joint materials can be suppressed.

[0013] FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. FIG. 3 is a circuit diagram of a semiconductor device according to an embodiment. FIG. 4 is a plan view showing an example of the structure of a mounting substrate according to an embodiment. FIG. 5 is an exploded perspective view showing an example of the structure of a semiconductor module according to an embodiment. FIG. 6 is a perspective view schematically showing a state in which warpage occurs in a semiconductor device according to an embodiment. FIG. 7 is an example of a plan view of a semiconductor device according to an embodiment. FIG. 8 is a cross-sectional schematic view showing a state in which a reference radius r according to an embodiment is calculated. FIG. 9 is a cross-sectional view showing an example of a cross-section of a semiconductor module according to an embodiment. FIG. 10 is a schematic view showing an example of the positions and shapes of each pad, each land, and each solder bonding material in a semiconductor module according to an embodiment. FIG. 11 is a schematic view showing an example of the positions and shapes of each pad, each land, and each solder bonding material in a semiconductor module according to an embodiment. FIG. 12 is a plan view of a semiconductor module schematically showing an example of the shapes of each pad and each land in a semiconductor module according to an embodiment. FIG. 13 is a plan view of a semiconductor module, schematically showing an example of the shape of each pad and each land in the semiconductor module according to the first embodiment. FIG. 14 is a cross-sectional view showing an example of a cross section of a semiconductor module according to the embodiment. FIG. 15 is a schematic diagram showing an example of the position and shape of each pad, each land, and each solder bonding material in a semiconductor module according to the embodiment. FIG. 16 is a schematic diagram showing an example of the position and shape of each pad, each land, and each solder bonding material in a semiconductor module according to the embodiment. FIG. 17 is a perspective view showing an example of the structure of a stencil according to the embodiment. FIG. 18 is a flowchart of a semiconductor module manufacturing process according to the embodiment. FIG. 19 is a schematic diagram showing a state in which a first step according to the embodiment is being performed. FIG. 20 is a schematic diagram showing an example of the position and shape of each pad, each land, and each opening in a method for manufacturing a semiconductor module according to the embodiment.FIG. 21 is a schematic diagram showing an example of the position and shape of each pad, each land, and each opening in a manufacturing method of a semiconductor module according to an embodiment. FIG. 22 is a schematic cross-sectional view for explaining a desirable relationship between the shape of the pad and the shape of the land according to an embodiment. FIG. 23 is a schematic plan view for explaining a desirable relationship between the shape of the pad and the shape of the land according to an embodiment. FIG. 24 is a schematic cross-sectional view for explaining a desirable relationship between the shape of the pad and the shape of the land according to an embodiment. FIG. 25 is a schematic perspective view for explaining a desirable relationship between the shape of the pad and the shape of the land according to an embodiment. FIG. 26 is a schematic perspective view for explaining a desirable relationship between the shape of the pad and the shape of the opening according to an embodiment.

[0014] (How one aspect of the present disclosure was achieved) Conventionally, when a semiconductor device having n pads is reflow-mounted using a solder bonding material to a mounting substrate having n lands that correspond one-to-one to the n pads, a phenomenon has been known in which the center of the semiconductor device in a planar view of the semiconductor device warps in a manner that is convex away from the mounting substrate or convex toward the mounting substrate.

[0015] The frequency of occurrence of the above-mentioned warpage phenomenon increases when, for example, a semiconductor device is configured by stacking a semiconductor layer and a metal layer having a thermal expansion coefficient different from that of the semiconductor layer.

[0016] The inventors have conducted extensive experiments and studies into the relationship between the phenomenon of warpage and the occurrence of defects related to the solder joint material in the semiconductor module.

[0017] As a result, the inventors have found that when the above-mentioned warping occurs in a semiconductor device, the distance between each of the n pads and the corresponding land becomes uneven, and as a result, this unevenness increases the frequency of defects related to the solder bonding material, such as the solder bonding material bonding the pad to the land overflowing from the pad or land, or the solder bonding material bonding the pad to the land chipping off the pad or land.

[0018] More specifically, the inventors have found that (1) when a semiconductor device warps convexly in a direction away from the center of the semiconductor device, the farther the pad is from the center of the semiconductor device, the closer the distance between the pad and the land, and therefore the more frequently a defect occurs in which the solder joint material joining the pad and the land protrudes from the pad or the land; and the closer the pad is from the center of the semiconductor device, the farther the distance between the pad and the land, and therefore the more frequently a defect occurs in which the solder joint material joining the pad and the land is chipped off the pad or the land; and (2) when a semiconductor device warps convexly in a direction away from the center of the semiconductor device, the closer the pad is from the center of the semiconductor device, the closer the distance between the pad and the land, and therefore the more frequently a defect occurs in which the solder joint material joining the pad and the land protrudes from the pad or the land; and the farther the pad is from the center of the semiconductor device, the farther the distance between the pad and the land, and therefore the more frequently a defect occurs in which the solder joint material joining the pad and the land is chipped off the pad or the land.

[0019] Based on this finding, the inventors conducted further experiments and studies, and as a result, arrived at the following semiconductor module and the like according to the present disclosure.

[0020] A semiconductor module according to one aspect of the present disclosure is a semiconductor module in which a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors is mounted face-down on a mounting substrate, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a plan view of the semiconductor device is curved convexly in a direction away from the mounting substrate or convexly in a direction toward the mounting substrate, the mounting substrate includes n lands corresponding to the n pads in a one-to-one relationship, and each of the n pads is a pad among the n lands corresponding to the pad. When the area of ​​the nearest pad, which is closest to the center of the semiconductor device in the planar view of the semiconductor device, among the n pads joined to one land with a solder bonding material, is Pa, the area of ​​the farthest pad, which is farthest from the center of the semiconductor device in the planar view of the semiconductor device, is Pb, the area of ​​the nearest land, which is the n lands and corresponds to the nearest pad, is La, and the area of ​​the farthest land, which is the farthest pad, in the planar view of the mounting board, is Lb, Pa / La is smaller than 1 and Pb / Lb is greater than 1, or Pa / La is greater than 1 and Pb / Lb is smaller than 1.

[0021] According to the semiconductor module having the above configuration, (1) when the center of the semiconductor device is curved convexly in a direction away from the mounting substrate, (1-A) by making the area Pa of the nearest pad smaller than the area La of the nearest land and making the area Pb of the farthest pad larger than the area Lb of the farthest land, it is possible to prevent the solder bonding material from chipping off the nearest pad and the solder bonding material from overflowing from the farthest pad.

[0022] Alternatively, (1) when the center of the semiconductor device is curved convexly in a direction away from the mounting substrate, (1-B) by making the area La of the nearest land smaller than the area Pa of the nearest pad and making the area Lb of the farthest land larger than the area Pb of the farthest pad, it is possible to prevent the solder joint material from chipping off the nearest land and the solder joint material from overflowing from the farthest land.

[0023] Alternatively, (2) when the center of the semiconductor device is curved convexly in the direction approaching the mounting board, (2-A) the area Pa of the nearest pad is made larger than the area La of the nearest land, and the area Pb of the farthest pad is made smaller than the area Lb of the farthest land, thereby preventing the solder joint material from overflowing from the nearest pad and preventing the solder joint material from chipping off the farthest pad.

[0024] Alternatively, (2) when the center of the semiconductor device is curved convexly in the direction approaching the mounting board, (2-B) by making the area La of the nearest land larger than the area Pa of the nearest pad and making the area Lb of the farthest land smaller than the area Pb of the farthest pad, it is possible to prevent the solder joint material from overflowing from the nearest land and the solder joint material from chipping off the farthest land.

[0025] In this way, the semiconductor module having the above configuration can suppress the occurrence of problems related to the solder joint material.

[0026] Furthermore, using n non-overlapping k's (k is an integer greater than or equal to 1 and less than or equal to n), each of the n pads is referred to as the k'th pad, each of the n lands corresponding to each of the n k'th pads is referred to as the k'th land, the area of ​​each of the n k'th pads in a planar view of the semiconductor device is referred to as P(k), and the area of ​​each of the n k'th lands in a planar view of the mounting substrate is referred to as L(k), then P(k) / L(k) may be expressed as monotonically increasing or monotonically decreasing depending on the distance from the center of the semiconductor device to each of the n k'th pads in a planar view of the semiconductor device.

[0027] Furthermore, when the semiconductor device is rectangular in plan view, and the distance from the center of the semiconductor device to the center of each of the n k-th pads in the plan view of the semiconductor device is referred to as D(k), among the n k-th pads, or a circle centered at the center of the semiconductor device in a planar view of the semiconductor device, the circle having a radius r determined by 1 / 4 of the length of a diagonal of the semiconductor device in a planar view of the semiconductor device, the value of P(k) / L(k) may be smaller than 1 for one or more inner pads located inside the semiconductor device in a planar view of the semiconductor device, and the value of P(k) / L(k) may be greater than 1 for one or more outer pads located outside the circle in a planar view of the semiconductor device, among the n k-th pads.

[0028] Furthermore, when the semiconductor device is rectangular in plan view, and the distance from the center of the semiconductor device to the center of each of the n k-th pads in the plan view of the semiconductor device is referred to as D(k), among the n k-th pads, or r determined by ¼ of the length of a diagonal of the semiconductor device in a planar view of the semiconductor device, P(k) / L(k) may be greater than 1 for each of one or more inner pads located inside a circle centered at the center of the semiconductor device in a planar view of the semiconductor device, and P(k) / L(k) may be less than 1 for each of one or more outer pads located outside the circle among the n kth pads.

[0029] Furthermore, the semiconductor device has a center in a plan view of the semiconductor device that is curved convexly in a direction away from the mounting substrate, and the semiconductor device is a rectangle having a side extending in a first direction and a side extending in a second direction perpendicular to the first direction, and a distance from the center of the semiconductor device to a center of each of the n kth pads in the plan view of the semiconductor device is referred to as D(k), and 1 / 4 of the length of a diagonal of the semiconductor device in the plan view of the semiconductor device is referred to as r the length of each of the n kth pads in the first direction in a plan view of the semiconductor device is referred to as XP(k), the length of each of the n kth pads in the second direction in a plan view of the semiconductor device is referred to as YP(k), the length of each of the n kth lands in the first direction in a plan view of the mounting board is referred to as XL(k), the length of each of the n kth lands in the second direction in a plan view of the mounting board is referred to as YL(k), When the height of the solder joint material at a position that is a distance r from the center of the semiconductor device in a plan view of the semiconductor device is referred to as t, and the amount of curvature of the semiconductor device is referred to as a, among the n k-th pads, for each of one or more inner pads that are located inside a circle centered at the center of the semiconductor device in a plan view of the semiconductor device, |XP(k)-XL(k)|×YL(k) / 2+XL(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k) ) - YL(k)| / 3 = XL(k) x YL(k) / [-t / {(2 x D(k) / R-1 / 2) x a} + 1] or |XP(k) - XL(k)| x YP(k) / 2 + XP(k) x |YP(k) - YL(k)| / 2 - |XP(k) - XL(k)| x |YP(k) - YL(k)| / 3 = XP(k) x YP(k) / [-t / {(2 x D(k) / R-1 / 2) x a} + 1] is established, and in each of the n k-th pads, one or more outer pads that are located outside the circle in a plan view of the semiconductor device,It may also be assumed that |XP(k)-XL(k)|×YL(k) / 2+XL(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k)-YL(k)| / 3=XL(k)×YL(k) / [t / {(2×D(k) / R-½)×a}-1] or |XP(k)-XL(k)|×YP(k) / 2+XP(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k)-YL(k)| / 3=XP(k)×YP(k) / [t / {(2×D(k) / R-½)×a}-1].

[0030] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module by face-down mounting a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors onto a mounting substrate using a stencil, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a planar view of the semiconductor device is convexly curved in a direction away from the mounting substrate, the mounting substrate includes n lands corresponding one-to-one to the n pads, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings being an opening for forming a solder bonding material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, and the nearest pad from the center of the semiconductor device in a planar view of the semiconductor device is the nearest pad from the center of the semiconductor device. and a second step of performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and bonding each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step.

[0031] According to the above-described method for manufacturing a semiconductor module, in manufacturing a semiconductor module using a semiconductor device whose center is convexly curved in a direction away from the mounting substrate, (1) by making the area Sa of the nearest opening larger than the area Pa of the nearest pad and the area La of the nearest land, the amount of solder bonding material formed above the nearest land can be made relatively larger relative to the area Pa of the nearest pad and the area La of the nearest land.

[0032] This makes it possible to manufacture a semiconductor module in which the occurrence of defects such as the solder bonding material chipping off the nearest pad and the solder bonding material chipping off the nearest land is suppressed.

[0033] Alternatively, (2) by making the area Sb of the farthest opening smaller than the area Pb of the farthest pad and the area Lb of the farthest land, the amount of solder bonding material formed above the farthest land can be made relatively small relative to the area Pb of the farthest pad and the area Lb of the farthest land.

[0034] This makes it possible to manufacture a semiconductor module in which the occurrence of problems such as the solder bonding material overflowing from the farthest pad and the solder bonding material overflowing from the farthest land is suppressed.

[0035] In this way, according to the above-described method for manufacturing a semiconductor module, it is possible to suppress the occurrence of defects related to the solder joint material.

[0036] Furthermore, when viewed from above, the semiconductor device is rectangular, and n non-overlapping k pads (k is an integer between 1 and n) are used, where each of the n pads is referred to as a k-th pad, each of the n lands corresponding to each of the n k-th pads is referred to as a k-th land, each of the n openings corresponding to each of the n k-th pads is referred to as a k-th opening, the area of ​​each of the n k-th pads in the planar view of the semiconductor device is referred to as P(k), the area of ​​each of the n k-th lands in the planar view of the mounting substrate is referred to as L(k), the area of ​​each of the n k-th openings in the planar view of the stencil is referred to as S(k), and the distance from the center of the semiconductor device to the center of each of the n k-th pads in the planar view of the semiconductor device is referred to as D(k). Alternatively, for each of one or more inner pads located inside the semiconductor device in a planar view of the semiconductor device, S(k) may be greater than both P(k) and L(k), or for each of one or more outer pads located outside the circle in a planar view of the semiconductor device, S(k) may be smaller than both P(k) and L(k).

[0037] Also, for each of the inner pads, S(k) / P(k) may be greater than 1, and for each of the outer pads, S(k) / P(k) may be less than 1.

[0038] Also, S(k) / L(k) may be greater than 1 for each of the inner pads, and S(k) / L(k) may be less than 1 for each of the outer pads.

[0039] Furthermore, in a plan view of the semiconductor device, the semiconductor device is a rectangle having a side extending in a first direction and a side extending in a second direction perpendicular to the first direction, the shape of each of the k-th pads in the plan view of the semiconductor device is equal to the shape of each of the k-th pads in the plan view of the mounting substrate, the length of each of the n k-th pads in the first direction in the plan view of the semiconductor device is referred to as XP(k), the length of each of the n k-th pads in the second direction in the plan view of the semiconductor device is referred to as YP(k), the length of each of the n k-th openings in the first direction in the plan view of the stencil is referred to as XS(k), and the length of each of the n k-th openings in the second direction in the plan view of the stencil is referred to as Xs(k). is defined as YS(k), the height of the solder joint material at a position that is a distance r from the center of the semiconductor device in a plan view of the semiconductor device is defined as t, and the amount of curvature of the semiconductor device is defined as a, then for each of the inner pads, |XP(k)-XS(k)|×YP(k)+XP(k)×|YP(k)-YS(k)|+|XP(k)-XS(k)|×|YP(k ) - YS(k)| = - {(2 x D(k) / R - 1 / 2) x a} / t x XP(k) x YP(k), and for each of the outer pads, |XP(k) - XS(k)| x YP(k) + XP(k) x |YP(k) - YS(k)| - |XP(k) - XS(k)| x |YP(k) - YS(k)| = {(2 x D(k) / R - 1 / 2) x a} / t x XP(k) x YP(k).

[0040] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module by face-down mounting a chip-size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors onto a mounting substrate using a stencil, the semiconductor device including a semiconductor layer, a metal layer in contact with a lower surface of the semiconductor layer and stacked on the semiconductor layer, and n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the center of the semiconductor device in a planar view of the semiconductor device is convexly curved in a direction approaching the mounting substrate, the mounting substrate includes n lands corresponding one-to-one to the n pads, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings being an opening for forming a solder bonding material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, the solder bonding material being used to bond the one of the n pads corresponding to the opening, the nearest pad from the center of the semiconductor device in a planar view of the semiconductor device. and a second step of performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and bonding each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step. The method further comprises: forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; forming a solder bonding material above each of the n lands using the stencil; and performing a reflow process to bond each of the n pads to one of the n lands using the solder bonding material formed above the corresponding land by performing the first step.

[0041] According to the above-described method for manufacturing a semiconductor module, in manufacturing a semiconductor module using a semiconductor device whose center is curved convexly in the direction approaching the mounting board, (1) by making the area Sa of the nearest opening smaller than the area Pa of the nearest pad and the area La of the nearest land, the amount of solder bonding material formed above the nearest land can be made relatively small relative to the area Pa of the nearest pad and the area La of the nearest land.

[0042] This makes it possible to manufacture a semiconductor module in which the occurrence of problems such as the solder bonding material overflowing from the pad and the land is suppressed.

[0043] Alternatively, (2) by making the area Sb of the farthest opening larger than the area Pb of the farthest pad and the area Lb of the farthest land, the amount of solder bonding material formed above the farthest land can be made relatively larger relative to the area Pb of the farthest pad and the area Lb of the farthest land.

[0044] This makes it possible to manufacture a semiconductor module in which the occurrence of defects such as the solder bonding material chipping off the farthest pad and the solder bonding material chipping off the farthest land is suppressed.

[0045] In this way, according to the above-described method for manufacturing a semiconductor module, it is possible to suppress the occurrence of defects related to the solder joint material.

[0046] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module using a stencil, wherein the semiconductor device has a center in a plan view of the semiconductor device that is convex in a direction away from the mounting substrate, the stencil has n openings that correspond one-to-one to the n pads, and each of the n openings is an opening for forming a solder joint material above one of the pads that corresponds to the opening and one of the n lands that corresponds to the opening, and a pad that is closest to the center of the semiconductor device in a plan view of the semiconductor device is formed by forming a solder joint material above the one of the pads that corresponds to the opening and the land that corresponds to the opening, and where Pa is the area of ​​the semiconductor device in a planar view, La is the area of ​​the mounting substrate in a planar view of the nearest land among the n lands that corresponds to the nearest pad, and Sa is the area of ​​the stencil in a planar view of the nearest opening among the n openings that corresponds to the nearest pad, Sa is larger than both Pa and La, and the method includes a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one of the n lands that corresponds to the pad using the solder bonding material formed above the one land by performing the first step.

[0047] According to the above-described method for manufacturing a semiconductor module, in manufacturing a semiconductor module using a semiconductor device whose center is convexly curved in a direction away from the mounting substrate, by making the area Sa of the nearest opening larger than the area Pa of the nearest pad and the area La of the nearest land, it is possible to make the amount of solder bonding material formed above the nearest land relatively large relative to the area Pa of the nearest pad and the area La of the nearest land.

[0048] This makes it possible to manufacture a semiconductor module in which the occurrence of defects such as the solder bonding material chipping off the nearest pad and the solder bonding material chipping off the nearest land is suppressed.

[0049] In this way, according to the above-described method for manufacturing a semiconductor module, it is possible to suppress the occurrence of defects related to the solder joint material.

[0050] A method for manufacturing a semiconductor module according to one aspect of the present disclosure is a method for manufacturing a semiconductor module using a stencil, wherein the semiconductor device has a center of the semiconductor device in a plan view of the semiconductor device that is convex in a direction away from the mounting substrate, the stencil has n openings that correspond one-to-one to the n pads, and each of the n openings is an opening for forming a solder joint material above one of the pads corresponding to the opening and one of the n lands corresponding to the opening, and a farthest pad from the center of the semiconductor device in a plan view of the semiconductor device is formed by forming a solder joint material above the one of the pads corresponding to the opening and one of the n lands corresponding to the opening. where Pb is the area of ​​the semiconductor device in a planar view, Lb is the area of ​​the mounting substrate of the farthest land of the n lands that corresponds to the farthest pad, and Sb is the area of ​​the stencil of the farthest opening of the n openings that corresponds to the farthest pad, Sb is smaller than both Pb and Lb, and the method includes a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one of the n lands that corresponds to the pad using the solder bonding material formed above the one land by performing the first step.

[0051] According to the above-described method for manufacturing a semiconductor module, by making the area Sb of the farthest opening smaller than the area Pb of the farthest pad and the area Lb of the farthest land, the amount of solder bonding material formed above the farthest land can be made relatively small relative to the area Pb of the farthest pad and the area Lb of the farthest land.

[0052] This makes it possible to manufacture a semiconductor module in which the occurrence of problems such as the solder bonding material overflowing from the farthest pad and the solder bonding material overflowing from the farthest land is suppressed.

[0053] In this way, according to the above-described method for manufacturing a semiconductor module, it is possible to suppress the occurrence of defects related to the solder joint material.

[0054] Specific examples of semiconductor modules according to an aspect of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, component arrangements and connection configurations, steps (processes), and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0055] A semiconductor module according to an embodiment will now be described, in which a chip-size package type semiconductor device including one or more vertical MOS transistors is mounted face-down on a mounting substrate.

[0056] <Structure of Semiconductor Device> FIG. 1 is a plan view showing an example of the structure of a semiconductor device 100 according to an embodiment.

[0057] As shown in FIG. 1, the semiconductor device 100 is a rectangle in plan view having a side extending in a first direction (the X-axis direction in FIG. 1) and a side extending in a second direction (the Y-axis direction in FIG. 1) perpendicular to the first direction.

[0058] FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor device 100, and is a cross-sectional view showing a cut surface along II in FIG.

[0059] FIG. 3 is a circuit diagram of the semiconductor device 100.

[0060] As shown in FIGS. 1 to 3, the semiconductor device 100 includes a semiconductor layer 40, a metal layer 30, an oxide film 34, a protective film 35, a first source electrode 11, a second source electrode 21, a first gate electrode 19 (not shown in FIGS. 1 and 2, and shown only in FIG. 3), and a second gate electrode 29 (not shown in FIGS. 1 and 2, and shown only in FIG. 3).

[0061] The semiconductor device 100 also includes n (n is an integer of 2 or more) pads 101 arranged on the top surface of the semiconductor device 100 .

[0062] Here, as an example that does not necessarily need to be limited, the n pads 101 included in the semiconductor device 100 include one or more first source pads 111 (corresponding to the first source pads 111a to 111f in FIG. 1; hereinafter, when it is not necessary to explicitly distinguish the first source pads 111a to 111f from one another, the first source pads 111a to 111f will also be simply referred to as "first source pads 111") and one or more first gate pads 119 (corresponding to the first source pads 111a to 111f in FIG. 1) that are arranged at positions included in the first region A1 in a plan view of the semiconductor device 100. The second region A2 will be described as including one or more second source pads 121 (corresponding to second source pads 121a to 121f in FIG. 1; hereinafter, when it is not necessary to explicitly distinguish between second source pads 121a to 121f, second source pads 121a to 121f will also be simply referred to as "second source pads 121") and one or more second gate pads 129 (corresponding to second gate pad 129 in FIG. 1) arranged at positions included in second region A2 when viewed in a plane of semiconductor device 100.

[0063] That is, in this description, the n pads 101 provided on the semiconductor device 100 are assumed to be a total of 14 pads, including six first source pads 111, one first gate pad 119, six second source pads 121, and one second gate pad 129.

[0064] However, the n pads 101 provided in the semiconductor device 100 are not necessarily limited to 14, as long as they are two or more.

[0065] The semiconductor layer 40 is configured by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33 .

[0066] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities at a first concentration.

[0067] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is made of silicon of the first conductivity type containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0068] Generally, there are two types of conductivity types for semiconductors: N-type and P-type. The first conductivity type may be N-type or P-type. Here, the first conductivity type is described as N-type, and the second conductivity type described below is described as P-type. However, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0069] In the first region A1 of the low concentration impurity layer 33, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0070] A first source region 14 of the first conductivity type containing impurities is formed in the first body region 18 in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the first body region 18 .

[0071] In addition, in the first region A1 of the low-concentration impurity layer 33, a plurality of first gate trenches 17 extending in the second direction are formed in a range from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a third predetermined depth to a part of the low-concentration impurity layer 33.

[0072] Then, inside each of the plurality of first gate trenches 17, a first gate conductor 15 is formed, which is surrounded by a first gate insulating film 16 and extends in the second direction.

[0073] The first gate conductor 15 is electrically connected to a first gate electrode 19 .

[0074] First gate conductor 15 may be, by way of non-limiting example, impurity-doped polysilicon.

[0075] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of the second conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0076] A second source region 24 of the first conductivity type containing impurities is formed in the second body region 28 in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the second body region 28.

[0077] In addition, in the second region A2 of the low-concentration impurity layer 33, a plurality of second gate trenches 27 are formed extending in the second direction within a range from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a third predetermined depth to a part of the low-concentration impurity layer 33.

[0078] Then, a second gate conductor 25 is formed inside each of the plurality of second gate trenches 27, the second gate conductor 25 being surrounded by a second gate insulating film 26 and extending in a second direction.

[0079] The second gate conductor 25 is electrically connected to a second gate electrode 29 .

[0080] The second gate conductor 25 may be, by way of non-limiting example, impurity-doped polysilicon.

[0081] With the above-described configuration of the semiconductor layer 40, the semiconductor device 100 includes a first vertical MOS transistor 10 formed in the first region A1 of the semiconductor layer 40 and a second vertical MOS transistor 20 formed in the second region A2 of the semiconductor layer 40.

[0082] Furthermore, due to the above-described configuration of the semiconductor layer 40, the semiconductor substrate 32 functions as a common drain region in which the first drain region of the first vertical MOS transistor 10 and the second drain region of the second vertical MOS transistor 20 are commonized.

[0083] Here, the semiconductor device 100 is described as having two vertical MOS transistors, namely, the first vertical MOS transistor 10 and the second vertical MOS transistor 20. However, the semiconductor device 100 is not necessarily limited to a configuration having two vertical MOS transistors, as long as it has one or more vertical MOS transistors.

[0084] The metal layer 30 is made of metal and is formed in contact with the lower surface of the semiconductor layer 40 and stacked on the semiconductor layer 40. The metal has a multi-layer structure including, for example, a layer whose main component is silver or copper, as a non-limiting example.

[0085] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33 .

[0086] The protective film 35 is a protective film that covers the upper surfaces of the oxide film 34 , the first source electrode 11 , the second source electrode 21 , the first gate electrode 19 , and the second gate electrode 29 .

[0087] The protective film 35 has an opening that exposes a portion of the upper surface of the first source electrode 11 to the outside of the protective film 35, an opening that exposes a portion of the upper surface of the second source electrode 21 to the outside of the protective film 35, an opening that exposes a portion of the upper surface of the first gate electrode 19 to the outside of the protective film 35, and an opening that exposes a portion of the upper surface of the second gate electrode 29 to the outside of the protective film 35.

[0088] The first source electrode 11 is an electrode whose lower surface is in contact with and connected to the first source region 14 and the first body region 18 , and is made of metal, and functions as the source electrode of the first vertical MOS transistor 10 .

[0089] A portion of the upper surface of the first source electrode 11 is exposed on the upper surface of the semiconductor device 100 through the opening in the protective film 35. The upper surface of the first source electrode 11 exposed on the upper surface of the semiconductor device 100 through the opening in the protective film 35 serves as a first source pad 111.

[0090] That is, the first source pad 111 is a portion of the upper surface of the first source electrode 11 that is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 .

[0091] The first gate electrode 19 is an electrode electrically connected to the first gate conductor 15 , is made of metal, and functions as the gate electrode of the first vertical MOS transistor 10 .

[0092] A portion of the upper surface of the first gate electrode 19 is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35. The upper surface of the first gate electrode 19 exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 serves as a first gate pad 119.

[0093] That is, the first gate pad 119 is a portion of the upper surface of the first gate electrode 19 that is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 .

[0094] The second source electrode 21 is an electrode whose lower surface is in contact with and connected to the second source region 24 and the second body region 28 , and is made of metal, and functions as the source electrode of the second vertical MOS transistor 20 .

[0095] A portion of the upper surface of the second source electrode 21 is exposed on the upper surface of the semiconductor device 100 through the opening in the protective film 35. The upper surface of the second source electrode 21 exposed on the upper surface of the semiconductor device 100 through the opening in the protective film 35 serves as a second source pad 121.

[0096] That is, the second source pad 121 is a portion of the upper surface of the second source electrode 21 that is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 .

[0097] The second gate electrode 29 is an electrode electrically connected to the second gate conductor 25 , is made of metal, and functions as the gate electrode of the second vertical MOS transistor 20 .

[0098] A portion of the upper surface of the second gate electrode 29 is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35. The upper surface of the second gate electrode 29 exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 serves as a second gate pad 129.

[0099] That is, the second gate pad 129 is a portion of the upper surface of the second gate electrode 29 that is exposed to the upper surface of the semiconductor device 100 through the opening in the protective film 35 .

[0100] <Structure of Mounting Board> FIG. 4 is a plan view showing an example of the structure of the mounting board 200 according to the embodiment.

[0101] The mounting substrate 200 is a mounting substrate on which the semiconductor device 100 is mounted face down.

[0102] The dashed lines in FIG. 4 schematically show the outer shape of the semiconductor device 100 when the semiconductor device 100 is mounted face-down on the mounting substrate 200 .

[0103] 4, the ratio between the outer size of the semiconductor device 100 in a plan view of the semiconductor device 100 and the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 does not reflect the actual ratio. For example, the actual ratio of the outer size of the semiconductor device 100 in a plan view of the semiconductor device 100 to the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 may be larger than the ratio exemplified in FIG.

[0104] As shown in FIG. 4, the mounting substrate 200 has n lands 201 that correspond one-to-one to the n pads 101 that the semiconductor device 100 has.

[0105] That is, when the semiconductor device 100 includes the first source pads 111a to 111f, the second source pads 121a to 121f, the first gate pad 119, and the second gate pad 129 as shown in FIG. 3, the mounting substrate 200 includes the first source land 211a corresponding to the first source pad 111a, the first source land 211b corresponding to the first source pad 111b, the first source land 211c corresponding to the first source pad 111c, the first source land 211d corresponding to the first source pad 111d, and the first source land 211e corresponding to the first source pad 111e as shown in FIG. a first source land 211f corresponding to the first source pad 111f, a second source land 221a corresponding to the second source pad 121a, a second source land 221b corresponding to the second source pad 121b, a second source land 221c corresponding to the second source pad 121c, a second source land 221d corresponding to the second source pad 121d, a second source land 221e corresponding to the second source pad 121e, a second source land 221f corresponding to the second source pad 121f, a first gate land 219 corresponding to the first gate pad 119, and a second gate land 229 corresponding to the second gate pad 129.

[0106] When the semiconductor device 100 is mounted face-down on the mounting substrate 200, each of the n lands 201 is joined to one of the n pads 101 provided on the semiconductor device 100 that corresponds to the land 201 by means of a solder joining material 301 (see Figure 5 described below).

[0107] In other words, when the semiconductor device 100 is mounted face-down on the mounting substrate 200, each of the n pads 101 is joined to one of the n lands 201 provided on the mounting substrate 200 that corresponds to the pad 101 by means of solder bonding material 301.

[0108] Furthermore, when the semiconductor device 100 is mounted face-down on the mounting substrate 200, each of the n lands 201 at least partially overlaps with one pad 101 corresponding to the land 201 among the n pads 101 provided on the semiconductor device 100 in a planar view of the mounting substrate 200.

[0109] <Structure of Semiconductor Module> FIG. 5 is an exploded perspective view showing an example of the structure of the semiconductor module 1 according to the embodiment.

[0110] In FIG. 5, the n pads 101 are illustrated as if they could be seen through the semiconductor device 100, but in reality, they cannot be seen directly through the semiconductor device 100.

[0111] 5, the ratio between the outer size of the semiconductor device 100 in a plan view of the semiconductor device 100 and the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 does not reflect the actual ratio. For example, the actual ratio of the outer size of the semiconductor device 100 in a plan view of the semiconductor device 100 to the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 may be larger than the ratio exemplified in FIG.

[0112] As shown in FIG. 5, the semiconductor module 1 includes a semiconductor device 100, a mounting substrate 200, and n solder bonding materials 301 that correspond one-to-one to the n pads 101 provided on the semiconductor device 100.

[0113] Each of the n solder joint materials 301 joins a pad 101 corresponding to the solder joint material 301 in a one-to-one relationship and a land 201 corresponding to the solder joint material 301 in a one-to-one relationship.

[0114] As will be described later, the semiconductor module 1 is manufactured through a process in which a reflow process is performed to join each of the n pads 101 to one of the n lands 201 corresponding to that pad 101 using a solder joining material 301 formed above that land 201.

[0115] Therefore, the semiconductor device 100 is mounted face-down on the mounting substrate 200 in a state where it has been heated by a reflow process in the manufacturing process of the semiconductor module 1 .

[0116] On the other hand, as described above, the semiconductor device 100 is configured by stacking the semiconductor layer 40 and the metal layer 30. In general, the semiconductor layer 40 made of silicon and the metal layer 30 made of metal have different thermal expansion coefficients.

[0117] Therefore, when the semiconductor device 100 is heated during the reflow process in the manufacturing process of the semiconductor module 1, the center of the semiconductor device 100 in a planar view of the semiconductor device 100 warps, bending convexly away from or towards the mounting substrate 200.

[0118] For example, if the thermal expansion coefficient of the metal layer 30 is greater than that of the semiconductor layer 40, when the semiconductor device 100 is heated in the reflow process, the center of the semiconductor device 100 will warp in a convex shape away from the mounting substrate 200.

[0119] Furthermore, when the semiconductor device 100 is heated in the reflow process, for example, if the thermal expansion coefficient of the metal layer 30 is smaller than that of the semiconductor layer 40, the center of the semiconductor device 100 will warp in a convex shape in the direction approaching the mounting substrate 200.

[0120] Therefore, in the semiconductor module 1, the semiconductor device 100 is mounted face-down on the mounting substrate 200 in a state in which the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is curved convexly away from the mounting substrate 200 or convexly toward the mounting substrate 200.

[0121] FIG. 6 is a perspective view that schematically shows the state in which the semiconductor device 100 is heated by the reflow process, and the center of the semiconductor device 100 is warped in a convex shape in a direction away from the mounting substrate 200.

[0122] As shown in Figure 6, when the semiconductor device 100 is heated by the reflow process and the center of the semiconductor device 100 warps convexly in a direction away from the mounting substrate 200, the semiconductor device 100 warps concentrically from the center of the semiconductor device 100 when viewed in a plane.

[0123] In this case, as shown in FIG. 6, the center of the semiconductor device 100 is highest in a plan view of the semiconductor device 100, and the four corners of the semiconductor device 100 are lowest in a plan view of the semiconductor device 100.

[0124] Similarly, when the semiconductor device 100 is heated by the reflow process and the center of the semiconductor device 100 warps convexly in the direction approaching the mounting substrate 200, the semiconductor device 100 warps concentrically from the center of the semiconductor device 100 when viewed in a plane.

[0125] In this case, the center of the semiconductor device 100 is lowest when viewed from above, and the four corners of the semiconductor device 100 are highest when viewed from above.

[0126] In this specification, the center of the semiconductor device 100 in a plan view of the semiconductor device 100 refers to the position of the intersection of diagonal lines of the semiconductor device 100 in a plan view of the semiconductor device 100.

[0127] In addition, in this specification, the center of the semiconductor device 100 in a plan view of the semiconductor device 100 may be simply referred to as the center of the semiconductor device 100.

[0128] In addition, in this specification, the center of the mounting substrate 200 in a planar view of the mounting substrate 200 refers to the position that coincides with the center of the semiconductor device 100 in a planar view of the mounting substrate 200 when the semiconductor device 100 is mounted face-down on the mounting substrate 200.

[0129] In this specification, the center of the mounting substrate 200 in a plan view of the mounting substrate 200 may be simply referred to as the center of the mounting substrate 200 .

[0130] In this specification, the center of the pad 101 in a plan view of the semiconductor device 100 refers to the position of the center of gravity of the pad 101 in a plan view of the semiconductor device 100.

[0131] In this specification, the center in a planar view refers to the intersection of the diagonals of a rectangle in a structure that is rectangular in a planar view, such as the semiconductor device 100 illustrated in FIG. 1; for example, for a structure that is oval in a planar view, such as the first source pads 111a to 111f and the second source pads 121a to 121f illustrated in FIG. 4, the center refers to the intersection of the axis of symmetry extending in the longitudinal direction of the oval and the axis of symmetry extending in the lateral direction of the oval; for example, for a structure that is circular in a planar view, such as the first gate pad 119 and the second gate pad 129 illustrated in FIG. 4, the center refers to the center of the circle; and for example, for a structure that is elliptical in a planar view, the center refers to the intersection of the major axis and minor axis of the ellipse.

[0132] However, when viewed in a plane of the semiconductor device 100, if the pad 101 straddles a center line extending in a first direction (the X-axis direction in FIG. 1) of the semiconductor device 100 or a center line extending in a second direction (the Y-axis direction in FIG. 1) (hereinafter, such a pad 101 will also be referred to as a "center line straddling pad"), that single center line straddling pad is considered to be two pads 101, one on one side of the center line and one on the other side of the center line, arranged in succession across the center line.

[0133] The position of the center of gravity of pad 101 on one side of the center line in a planar view of semiconductor device 100 is referred to as the center of pad 101 on one side of the center line in a planar view of semiconductor device 100 (hereinafter also referred to as the "first center"), and the position of the center of gravity of pad 101 on the other side of the center line in a planar view of semiconductor device 100 is referred to as the center of pad 101 on the other side of the center line in a planar view of semiconductor device 100 (hereinafter also referred to as the "second center").

[0134] In other words, in this specification, if a center line straddling pad exists, the center line straddling pad is considered to consist of two pads 101: a pad 101 centered on the first center and a pad 101 centered on the second center.

[0135] FIG. 7 is an example of a plan view of the semiconductor device 100 when the semiconductor device 100 includes a center line straddling pad.

[0136] As shown in FIG. 7, in this specification, each center line straddling pad is considered to consist of two pads 101, one centered on the first center and the other centered on the second center.

[0137] In this specification, the center of the land 201 in a plan view of the mounting substrate 200 refers to the position of the center of gravity of the land 201 in a plan view of the mounting substrate 200.

[0138] However, when viewed in a plane of the mounting substrate 200, if the land 201 straddles the center line extending in the first direction (the X-axis direction in FIG. 1 ) of the semiconductor device 100 or the center line extending in the second direction (the Y-axis direction in FIG. 1 ) of the semiconductor device 100 when the semiconductor device 100 is mounted face-down on the mounting substrate 200 (hereinafter, this land 201 will also be referred to as a “center line straddling land”), then that single center line straddling land is considered to be two lands 201, one on one side of the center line and one on the other side of the center line, arranged continuously across the center line.

[0139] The position of the center of gravity of the land 201 on one side of the center line in a planar view of the mounting substrate 200 is referred to as the center of the land 201 on one side of the center line in a planar view of the mounting substrate 200 (hereinafter also referred to as the "third center"), and the position of the center of gravity of the land 201 on the other side of the center line in a planar view of the mounting substrate 200 is referred to as the center of the land 201 on the other side of the center line in a planar view of the mounting substrate 200 (hereinafter also referred to as the "fourth center").

[0140] In other words, in this specification, if a center line straddling land exists, the center line straddling land is considered to consist of two lands 201: a land 201 centered on the third center and a land 201 centered on the fourth center.

[0141] In addition, in this specification, the distance from the center of semiconductor device 100 to pad 101 when viewed in a plane of semiconductor device 100 refers to the distance from the center of semiconductor device 100 to the center of pad 101 when viewed in a plane of semiconductor device 100.

[0142] In this specification, the distance from the center of the semiconductor device 100 to the pad 101 in a plan view of the semiconductor device 100 may be simply referred to as the distance from the center of the semiconductor device 100 to the pad 101.

[0143] In addition, in this specification, the distance from the center of the mounting substrate 200 to the land 201 when viewed in a plane of the mounting substrate 200 refers to the distance from the center of the mounting substrate 200 to the center of the land 201 when viewed in a plane of the mounting substrate 200.

[0144] In this specification, the distance from the center of the mounting substrate 200 to the land 201 in a plan view of the mounting substrate 200 may be simply referred to as the distance from the center of the mounting substrate 200 to the land 201.

[0145] In this specification, the diagonal length R of the semiconductor device 100 refers to the length of the diagonal line of the semiconductor device 100 when viewed from above.

[0146] In addition, in this specification, the amount of curvature a of the semiconductor device 100 refers to the difference in height between the highest position on the underside of the semiconductor device 100 when mounted face-down on the mounting substrate 200, i.e., the center of the semiconductor device 100 in a planar view of the semiconductor device 100, and the lowest position, i.e., one of the four corners of the semiconductor device 100 in a planar view of the semiconductor device 100, when the semiconductor device 100 is mounted face-down on the mounting substrate 200, when warping occurs in the semiconductor device 100 such that the center of the semiconductor device 100 is convexly curved in a direction away from the mounting substrate 200; and in the case where warping occurs in the semiconductor device 100 such that the center of the semiconductor device 100 is convexly curved in a direction approaching the mounting substrate 200, the amount of curvature a of the semiconductor device 100 refers to the difference in height between the lowest position on the underside of the semiconductor device 100 when mounted face-down on the mounting substrate 200, i.e., the center of the semiconductor device 100 in a planar view of the semiconductor device 100, and the highest position, i.e., one of the four corners of the semiconductor device 100 in a planar view of the semiconductor device 100.

[0147] That is, the amount of curvature a of the semiconductor device 100 refers to the maximum amount of warpage of the semiconductor device 100 .

[0148] In addition, in this specification, the reference radius r of the semiconductor device 100 refers to the distance from the center of the semiconductor device 100 to the position where the amount of warping of the semiconductor device 100 is average, in a planar view of the semiconductor device 100, when the semiconductor device 100 is mounted face-down on the mounting substrate 200.

[0149] In this specification, the reference radius r is described as being calculated by one of the following two calculation methods.

[0150] Calculation method 1: A method of simply calculating the reference radius r by assuming that the warpage of the semiconductor device 100 changes linearly in a cross-sectional view of the semiconductor device 100.

[0151] FIG. 8 is a schematic cross-sectional view showing how the reference radius r is calculated by calculation method 1.

[0152] FIG. 8 illustrates the semiconductor device 100 as if the warpage of the semiconductor device 100 were a linear change. However, this is because the illustration shows the state in which the warpage of the semiconductor device 100 is assumed to be a linear change in order to simply calculate the reference radius r, and does not actually mean that the warpage of the semiconductor device 100 is a linear change.

[0153] As shown in FIG. 8, in calculation method 1, the reference radius r is calculated as 1 / 4 of the diagonal length R, which is the distance from the center of the semiconductor device 100 to the position where the amount of warping of the semiconductor device 100 is 1 / 2 of the amount of curvature a.

[0154] That is, the reference radius r is calculated by the following formula.

[0155] r = R / 4

[0156] Calculation method 2: A method of calculating the reference radius r by weighting the average of the distance from the center of the semiconductor device 100 to each pad 101 with the area of ​​each pad 101 .

[0157] That is, using n non-overlapping k's (k is an integer greater than or equal to 1 and less than or equal to n), each of the n pads 101 is referred to as the kth pad 101, the area of ​​each of the n kth pads 101 in a planar view of the semiconductor device 100 is referred to as P(k), and the distance from the center of the semiconductor device 100 to the center of each of the n kth pads 101 is referred to as D(k), then the reference radius r is calculated using the following formula.

[0158]

[0159] Figure 9 is a cross-sectional view that schematically shows an example of a cross-section of a semiconductor module 1 when the semiconductor device 100 is mounted on a mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200.

[0160] As shown in Figure 9, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200, the pad 101 that is farther away from the center of the semiconductor device 100 will be closer to the pad 101 and the land 201, and the pad 101 that is closer to the center of the semiconductor device 100 will be farther away from the pad 101 and the land 201.

[0161] Therefore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200, if the area of ​​the nearest pad, of the n pads 101, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pa, the area of ​​the farthest pad, of the n lands 201, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pb, the area of ​​the nearest land, of the n lands 201, that corresponds to the nearest pad is defined as La, and the area of ​​the farthest land, of the farthest pad, is defined as Lb, then it is desirable that Pa / La is smaller than 1 and Pb / Lb is greater than 1, or that Pa / La is greater than 1 and Pb / Pb is smaller than 1.

[0162] This makes it possible to prevent the occurrence of defects such as the solder bonding material 301 chipping off from the nearest pad, the solder bonding material 301 overflowing from the farthest pad, or the solder bonding material 301 chipping off from the nearest land, and the solder bonding material 301 overflowing from the farthest land.

[0163] Figure 10 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each solder bonding material 301 in a semiconductor module 1 in which the conditions that Pa / La is smaller than 1 and Pb / Lb is greater than 1 are satisfied when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200.

[0164] Figure 11 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each solder bonding material 301 in a semiconductor module 1 in which the conditions that Pa / La is greater than 1 and Pb / Lb is less than 1 are satisfied when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200.

[0165] The positions and shapes of the solder bonding materials 301 in the lower designs of FIGS. 10 and 11 show examples of the positions and shapes before bonding the one-to-one corresponding pads 101 and lands 201.

[0166] The upper images in Figures 10 and 11 are cross-sectional views that schematically show an example of a cross section of a semiconductor module 1, and the lower images are plan views that schematically show an example of each pad 101, each land 201, and each solder bonding material 301.

[0167] As shown in FIG. 10, for example, the area Pa of the nearest pad 101a may be made smaller than the area La of the nearest land 201a, and the area Pb of the farthest pad 101b may be made larger than the area Lb of the farthest land 201b, thereby satisfying the condition that Pa / La is smaller than 1 and Pb / Lb is greater than 1.

[0168] This makes it possible to prevent the solder joint material 301 from chipping off the nearest pad 101a and the solder joint material 301 from overflowing from the farthest pad 101b.

[0169] Alternatively, as shown in FIG. 11, for example, the area La of the nearest land 201a may be made smaller than the area Pa of the nearest pad 101a, and the area Lb of the farthest land 201b may be made larger than the area Pb of the farthest pad 101b, thereby satisfying the condition that Pa / La is greater than 1 and Pb / Lb is less than 1.

[0170] This makes it possible to prevent the solder joint material 301 from chipping off the nearest land 201a and the solder joint material 301 from overflowing from the farthest land 201b.

[0171] 12 is a plan view of a semiconductor module 1, schematically showing an example of the shapes of n pads 101 and n lands 201 in a semiconductor module 1 configured as illustrated in FIG. 10, in which the area Pa of the nearest pad 101a is smaller than the area La of the nearest land 201a, and the area Pb of the farthest pad 101b is larger than the area Lb of the farthest land 201b.

[0172] In Figure 12, n pads 101 are shown with dashed lines as if they could be seen from the top surface of the semiconductor module 1, and n lands 201 are shown with solid lines as if they could be seen from the top surface of the semiconductor module 1, but in reality, these cannot be seen directly from the top surface of the semiconductor module 1.

[0173] 12, the ratio between the external size of the semiconductor device 100 and the external size of the mounting substrate 200 in a plan view of the semiconductor module 1 does not reflect the actual ratio. For example, the actual ratio of the external size of the mounting substrate 200 to the external size of the semiconductor device 100 in a plan view of the semiconductor module 1 may be larger than the ratio exemplified in FIG.

[0174] 13 is a plan view of a semiconductor module 1, schematically showing an example of the shapes of n pads 101 and n lands 201 in a semiconductor module 1 configured as illustrated in FIG. 11, in which the area La of the nearest land 201a is smaller than the area Pa of the nearest pad 101a and the area Lb of the farthest land 201b is larger than the area Pb of the farthest pad 101b.

[0175] In Figure 13, n pads 101 are shown with dashed lines as if they could be seen from the top surface of the semiconductor module 1, and n lands 201 are shown with solid lines as if they could be seen from the top surface of the semiconductor module 1, but in reality, these cannot be seen directly from the top surface of the semiconductor module 1.

[0176] 13, the ratio between the external size of the semiconductor device 100 and the external size of the mounting substrate 200 in a plan view of the semiconductor module 1 does not reflect the actual ratio. For example, the actual ratio of the external size of the mounting substrate 200 to the external size of the semiconductor device 100 in a plan view of the semiconductor module 1 may be larger than the ratio exemplified in FIG.

[0177] Furthermore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200 as shown in FIG. 9, furthermore, as shown in FIGS. 10 and 11, using n k's (k is an integer greater than or equal to 1 and less than or equal to n), each of the n pads 101 is referred to as the k-th pad 101, each of the n lands 201 corresponding to each of the n k-th pads 101 is referred to as the k-th land 201, the area of ​​each of the n k-th pads 101 in the planar view of the semiconductor device 100 is referred to as P(k), and the area of ​​each of the n k-th lands 201 in the planar view of the mounting substrate 200 is referred to as L(k), it is desirable that P(k) / L(k) monotonically increase or decrease depending on the distance from the center of the semiconductor device 100 to each of the n k-th pads 101 in the planar view of the semiconductor device 100.

[0178] This makes it possible to further suppress the occurrence of problems related to the solder joint material 301.

[0179] In this specification, "monotonically increasing" refers to a monotonically increasing function in a broad sense, i.e., a function f(x) such that f(x1)≦f(x2) when x1<x2.

[0180] In this specification, "monotonically decreasing" refers to a monotonically decreasing function in a broad sense, i.e., a function f(x) such that f(x1) ≥ f(x2) when x1 < x2.

[0181] 10 , in the case where the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in a direction away from the mounting substrate 200, in the semiconductor module 1 configured such that the area Pa of the nearest pad 101a is smaller than the area La of the nearest land 201a and the area Pb of the farthest pad 101b is larger than the area Lb of the farthest land 201b, when the distance from the center of the semiconductor device 100 to the center of each of the n k-th pads 101 in a plan view of the semiconductor device 100 is referred to as D(k), then among the n k-th pads 101, or a circle centered at the center of semiconductor device 100 in a planar view of semiconductor device 100, the circle having a radius equal to ¼ of the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100 (i.e., a reference radius r determined by ¼ of the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100), for each of one or more inner pads located inside semiconductor device 100 in a planar view of semiconductor device 100, is preferably smaller than 1, and P(k) / L(k) is preferably greater than 1 for each of one or more outer pads located outside semiconductor device 100 in a planar view of semiconductor device 100 of the circle.

[0182] This makes it possible to further suppress the occurrence of problems related to the solder joint material 301.

[0183] 11, in the case where the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in a direction away from the mounting substrate 200, in the semiconductor module 1 configured such that the area La of the nearest land 201a is smaller than the area Pa of the nearest pad 101a and the area Lb of the farthest land 201b is larger than the area Pb of the farthest pad 101b, among the n number of k-th pads 101, For each of one or more inner pads located inside a circle centered at the center of semiconductor device 100 in a planar view of semiconductor device 100, and having a radius of reference radius r determined by ¼ the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100 (i.e., ¼ the diagonal length of semiconductor device 100), it is desirable that P(k) / L(k) be greater than 1, and for each of one or more outer pads located outside the circle among the n kth pads, P(k) / L(k) be less than 1.

[0184] This makes it possible to further suppress the occurrence of problems related to the solder joint material 301.

[0185] Figure 14 is a cross-sectional view that schematically shows an example of a cross-section of a semiconductor module 1 when the semiconductor device 100 is mounted on a mounting substrate 200 with the center of the semiconductor device 100 curved convexly in a direction approaching the mounting substrate 200.

[0186] As shown in Figure 14, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly toward the mounting substrate 200, the closer the pad 101 is to the center of the semiconductor device 100, the closer the distance between the pad 101 and the land 201, and the farther the pad 101 is from the center of the semiconductor device 100, the farther the distance between the pad 101 and the land 201.

[0187] Therefore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly toward the mounting substrate 200, if the area of ​​the nearest pad, of the n pads 101, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pa, the area of ​​the farthest pad, of the n lands 201, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pb, the area of ​​the nearest land, of the n lands 201, that corresponds to the nearest pad is defined as La, and the area of ​​the farthest land, of the farthest pad, is defined as Lb, then it is desirable that Pa / La be greater than 1 and Pb / Lb be less than 1, or that Pa / La be smaller than 1 and Pb / Lb be greater than 1.

[0188] This makes it possible to prevent the occurrence of problems such as the solder bonding material 301 overflowing from the nearest pad and the solder bonding material 301 chipping off from the farthest pad, or the occurrence of problems such as the solder bonding material 301 overflowing from the nearest land and the solder bonding material 301 chipping off from the farthest land.

[0189] Figure 15 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each solder bonding material 301 in a semiconductor module 1 in which the conditions that Pa / La is greater than 1 and Pb / Lb is less than 1 are satisfied when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in the direction approaching the mounting substrate 200.

[0190] Figure 16 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each solder bonding material 301 in a semiconductor module 1 in which the conditions that Pa / La is smaller than 1 and Pb / Lb is greater than 1 are satisfied when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in the direction approaching the mounting substrate 200.

[0191] The upper images in Figures 15 and 16 are cross-sectional views that schematically show an example of a cross section of a semiconductor module 1, and the lower images are plan views that schematically show an example of each pad 101, each land 201, and each solder bonding material 301.

[0192] As shown in FIG. 15, for example, the area Pa of the nearest pad 101a may be made larger than the area La of the nearest land 201a, and the area Pb of the farthest pad 101b may be made smaller than the area Lb of the farthest land 201b, thereby satisfying the condition that Pa / La is larger than 1 and Pb / Lb is smaller than 1.

[0193] This makes it possible to prevent the solder joint material 301 from overflowing from the nearest pad 101a and the solder joint material 301 from being insufficient for the farthest pad 101b.

[0194] Alternatively, as shown in FIG. 16, for example, the area La of the nearest land 201a may be made larger than the area Pa of the nearest pad 101a, and the area Lb of the farthest land 201b may be made smaller than the area Pb of the farthest pad 101b, thereby satisfying the condition that Pa / La is larger than 1 and Pb / Lb is smaller than 1.

[0195] This makes it possible to prevent the solder joint material 301 from overflowing from the nearest land and the solder joint material 301 from being insufficient for the farthest land.

[0196] Furthermore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly toward the mounting substrate 200 as shown in FIG. 14 , furthermore, as shown in FIGS. 15 and 16 , when n k's are used to refer to each of the n pads 101 as the k-th pad 101, and each of the n lands 201 corresponding to each of the n k-th pads 101 as the k-th land 201, the area of ​​each of the n k-th pads 101 in the planar view of the semiconductor device 100 is referred to as P(k), and the area of ​​each of the n k-th lands 201 in the planar view of the mounting substrate 200 is referred to as L(k), it is desirable that P(k) / L(k) monotonically increase or decrease depending on the distance from the center of the semiconductor device 100 to each of the n k-th pads 101 in the planar view of the semiconductor device 100.

[0197] 16, in the case where the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in the direction approaching the mounting substrate 200, in the semiconductor module 1 configured such that the area Pa of the nearest pad 101a is smaller than the area La of the nearest land 201a and the area Pb of the farthest pad 101b is larger than the area Lb of the farthest land 201b, when the distance from the center of the semiconductor device 100 to the center of each of the n k-th pads 101 in a plan view of the semiconductor device 100 is referred to as D(k), among the n k-th pads 101, or a circle centered at the center of semiconductor device 100 in a planar view of semiconductor device 100, the circle having a radius equal to ¼ of the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100 (i.e., a reference radius r determined by ¼ of the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100), for each of one or more inner pads located inside semiconductor device 100 in a planar view of semiconductor device 100, is preferably smaller than 1, and P(k) / L(k) is preferably greater than 1 for each of one or more outer pads located outside semiconductor device 100 in a planar view of semiconductor device 100 of the circle.

[0198] This makes it possible to further suppress the occurrence of problems related to the solder joint material 301.

[0199] 15, in the case where the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in the direction approaching the mounting substrate 200, in the semiconductor module 1 configured such that the area La of the nearest land 201a is smaller than the area Pa of the nearest pad 101a and the area Lb of the farthest land 201b is larger than the area Pb of the farthest pad 101b, among the n number of k-th pads 101, For each of one or more inner pads located inside a circle centered at the center of semiconductor device 100 in a planar view of semiconductor device 100, and having a radius of reference radius r determined by ¼ the length of the diagonal of semiconductor device 100 in a planar view of semiconductor device 100 (i.e., ¼ the diagonal length of semiconductor device 100), it is desirable that P(k) / L(k) be greater than 1, and for each of one or more outer pads located outside the circle among the n kth pads, P(k) / L(k) be less than 1.

[0200] This makes it possible to further suppress the occurrence of problems related to the solder joint material 301.

[0201] <Method for Manufacturing Semiconductor Module> A method for manufacturing the semiconductor module 1 having the above configuration will now be described.

[0202] The semiconductor module 1 having the above configuration is manufactured by a semiconductor module manufacturing process in which the semiconductor device 100 is mounted face-down onto the mounting substrate 200 using a stencil 400 (see FIG. 17 ) described below to manufacture the semiconductor module 1.

[0203] Fig. 17 is a perspective view showing an example of the structure of the stencil 400. In Fig. 17, perspective views of the semiconductor device 100 and the mounting substrate 200 are also shown to show that the n openings 401 provided in the stencil 400 correspond one-to-one to the n pads 101 provided in the semiconductor device 100 and the n lands 201 provided in the mounting substrate 200.

[0204] In FIG. 17, the n pads 101 are depicted as if they could be seen through the semiconductor device 100, but in reality, they cannot be seen directly through the semiconductor device 100.

[0205] 17 , the ratios of the external size of the semiconductor device 100 to the external size of the mounting substrate 200 to the external size of the stencil 400 in a plan view of the semiconductor module 1 do not reflect the actual ratios. For example, the actual ratio of the external size of the stencil 400 to the external size of the semiconductor device 100 in a plan view of the semiconductor module 1 may be larger than the ratio exemplified in FIG. 17 , and the actual ratio of the external size of the mounting substrate 200 to the external size of the stencil 400 in a plan view of the semiconductor module 1 may be larger than the ratio exemplified in FIG.

[0206] As shown in FIG. 17, the stencil 400 has n openings 401 that correspond one-to-one to the n pads of the semiconductor device 100 .

[0207] Each of the n openings 401 is an opening for forming a solder bonding material 301 above one of the n pads 101 corresponding to the opening 401 and one of the n lands 201 corresponding to the opening 401.

[0208] The stencil 400 is made of, for example, metal and has a thickness of, for example, 80 μm.

[0209] FIG. 18 is a flowchart of the semiconductor module manufacturing process.

[0210] As shown in FIG. 18, the semiconductor module manufacturing process includes a first step (step S10) and a second step (step S20) in this order.

[0211] When the semiconductor module manufacturing process is started, the first step is executed.

[0212] The first step is to form the solder joint material 301 above each of the n lands 201 using a stencil 400 .

[0213] FIG. 19 is a schematic diagram showing the first step being performed.

[0214] As shown in FIG. 19, the first step is a step in which a placing step, a transferring step, and a plate separating step are carried out in this order.

[0215] 19 , the ratio between the outer size of the stencil 400 in a plan view of the stencil 400 and the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 does not reflect the actual ratio. For example, the actual ratio of the outer size of the stencil 400 in a plan view to the outer size of the mounting substrate 200 in a plan view of the mounting substrate 200 may be larger than the ratio exemplified in FIG.

[0216] The placing step is a step of placing the stencil 400 at a predetermined position on the upper surface of the mounting substrate 200 .

[0217] At this time, a paste-like solder joint material 501 is placed on the upper surface of the stencil 400 in an amount sufficiently larger than the volume of the n solder joint materials 301 .

[0218] The transfer process is a process in which a squeegee 500 is slid on the top surface of the stencil 400 to fill the inside of each of the n openings 401 with a paste-like solder bonding material 501, thereby forming n solder bonding materials 301 above each of the n lands 201 provided on the mounting substrate 200.

[0219] The stencil detachment step is a step of detaching the stencil 400 from the upper surface of the mounting substrate 200 .

[0220] Returning to FIG. 18, the semiconductor module manufacturing process will be further described.

[0221] Once the first step is completed, the second step is then carried out.

[0222] The second process is a process in which a reflow process is performed to join each of the n pads 101 to one of the n lands 201 corresponding to that pad 101 using the solder joining material 301 formed above that one land 201 by performing the first process.

[0223] The reflow process is performed with the semiconductor device 100 placed face down above the mounting substrate 200 so that each of the n solder bonding materials 301 formed above each of the n lands 201 overlaps each of the n pads 101 one-to-one in a planar view of the mounting substrate 200.

[0224] When the second process is completed, the semiconductor module manufacturing process ends.

[0225] As described above, the semiconductor module 1 manufactured by carrying out the above-mentioned semiconductor module manufacturing process has the semiconductor device 100 mounted on the mounting substrate 200 in a state in which the center of the semiconductor device 100 is curved convexly away from the mounting substrate 200 or convexly toward the mounting substrate 200.

[0226] Therefore, as shown in FIG. 9 , when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200, if the area of ​​the nearest pad, of the n pads 101, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pa, the area of ​​the farthest pad, of the n lands, that corresponds to the nearest pad is defined as La, the area of ​​the farthest land, of the n lands, that corresponds to the farthest pad is defined as Lb, the area of ​​the nearest opening, of the n openings 401, that corresponds to the nearest pad is defined as Sa, and the area of ​​the farthest opening, of the farthest pad, is defined as Sb, it is desirable that Sa be larger than both Pa and La, or that Sb be smaller than both Pb and Lb.

[0227] This allows (1) a relatively large amount of solder joint material to be formed above the nearest land relative to the area Pa of the nearest pad and the area La of the nearest land, or (2) a relatively small amount of solder joint material to be formed above the farthest land relative to the area Pb of the farthest pad and the area Lb of the farthest land.

[0228] Therefore, it is possible to manufacture a semiconductor module 1 in which the occurrence of (1) the defect of the solder bonding material 301 chipping off the nearest pad and the defect of the solder bonding material 301 chipping off the nearest land, or (2) the defect of the solder bonding material 301 overflowing from the farthest pad and the defect of the solder bonding material 301 overflowing from the farthest land is suppressed.

[0229] Figure 20 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each opening 401 in a semiconductor module 1 manufactured using a stencil 400 that satisfies the condition that Sa is greater than both Pa and La, or Sb is smaller than both Pb and Lb, when manufacturing a semiconductor module 1 in which a semiconductor device 100 is mounted on a mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200, as shown in Figure 9.

[0230] The upper image in Figure 20 is a cross-sectional view that schematically shows an example of a cross section of a semiconductor module 1 manufactured by executing a semiconductor module manufacturing process, and the lower image is a plan view that schematically shows an example of each pad 101, each land 201, and each opening 401.

[0231] As shown in FIG. 20, it is desirable to manufacture the semiconductor module 1 using a stencil 400 in which Sa is larger than both Pa and La, thereby making the amount of solder bonding material 301 formed above the nearest land 201a relatively large relative to the area Pa of the nearest pad 101a and the area La of the nearest land 201a.

[0232] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of defects such as the solder joint material 301 chipping off the nearest pad 101a and the occurrence of defects such as the solder joint material 301 chipping off the nearest land 201a is suppressed.

[0233] Alternatively, as shown in FIG. 20, it is desirable to manufacture the semiconductor module 1 using a stencil 400 in which Sb is smaller than both Pb and Lb, thereby making the amount of solder bonding material 301 formed above the farthest land 201b relatively small relative to the area Pb of the farthest pad 101b and the area Lb of the farthest land 201b.

[0234] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of problems such as the solder joint material 301 overflowing from the farthest pad 101b and the occurrence of problems such as the solder joint material 301 overflowing from the farthest land 201b is suppressed.

[0235] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of problems such as the solder joint material 301 overflowing from the farthest pad 101b and the occurrence of problems such as the solder joint material 301 overflowing from the farthest land 201b is suppressed.

[0236] 9, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly in a direction away from the mounting substrate 200, as shown in FIG. 20, n pads 101 are referred to as k-th pads 101, and n lands 201 corresponding to the n k-th pads 101 are referred to as k-th lands 201, and n openings 401 corresponding to the n k-th pads 101 are referred to as k-th lands 201. Each of the n k-th pads 101 is referred to as the k-th opening 401, the area of ​​each of the n k-th pads 101 in the planar view of the semiconductor device 100 is referred to as P(k), the area of ​​each of the n k-th lands 201 in the planar view of the mounting substrate 200 is referred to as L(k), the area of ​​each of the n k-th openings 401 in the planar view of the stencil 400 is referred to as S(k), and the distance from the center of the semiconductor device 100 to the center of each of the n k-th pads 101 in the planar view of the semiconductor device 100 is referred to as D(k). It is desirable that, for each of one or more inner pads located inside the semiconductor device 100 in a planar view of the semiconductor device 100, S(k) is greater than both P(k) and L(k), or that, for each of one or more outer pads located outside the semiconductor device 100 in a planar view of the semiconductor device 100, S(k) is smaller than both P(k) and L(k), and that, for each of one or more outer pads located outside the semiconductor device 100 in a planar view of the semiconductor device 100, S(k) is greater than both P(k) and L(k).

[0237] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of defects related to the solder joint material 301 is further suppressed.

[0238] Furthermore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200 as shown in FIG. 9, it is desirable that S(k) / P(k) be greater than 1 for each of the inner pads and that S(k) / P(k) be less than 1 for each of the outer pads as shown in FIG.

[0239] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of defects related to the solder joint material 301 is further suppressed.

[0240] Furthermore, when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly away from the mounting substrate 200 as shown in FIG. 9, it is desirable that S(k) / L(k) be greater than 1 for each of the inner pads and that S(k) / L(k) be less than 1 for each of the outer pads as shown in FIG.

[0241] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of defects related to the solder joint material 301 is further suppressed.

[0242] Furthermore, as shown in FIG. 14 , when the semiconductor device 100 is mounted on the mounting substrate 200 with the center of the semiconductor device 100 curved convexly toward the mounting substrate 200, if the area of ​​the nearest pad, among the n pads 101, that is closest to the center of the semiconductor device 100 in the planar view of the semiconductor device 100 is defined as Pa, the area of ​​the farthest pad, that is farthest, in the planar view of the semiconductor device 100 is defined as Pb, the area of ​​the nearest land, among the n lands 201, that corresponds to the nearest pad is defined as La, the area of ​​the farthest land, corresponding to the farthest pad, in the planar view of the mounting substrate 200 is defined as Lb, the area of ​​the nearest opening, among the n openings 401, that corresponds to the nearest pad is defined as Sa, and the area of ​​the farthest opening, corresponding to the farthest pad, in the planar view of the stencil 400 is Sb, it is desirable that Sa be smaller than both Pa and La, or that Sb be larger than both Pb and Lb.

[0243] This allows (1) the amount of solder joint material formed above the nearest land to be relatively small relative to the area Pa of the nearest pad and the area La of the nearest land, or (2) the amount of solder joint material formed above the farthest land to be relatively large relative to the area Pb of the farthest pad and the area Lb of the farthest land.

[0244] Therefore, it is possible to manufacture a semiconductor module 1 in which the occurrence of (1) the defect that the solder bonding material 301 overflows from the nearest pad and the defect that the solder bonding material 301 overflows from the nearest land, or (2) the defect that the solder bonding material 301 is chipped off from the farthest pad and the defect that the solder bonding material 301 is chipped off from the farthest land, is suppressed.

[0245] Figure 21 is a schematic diagram showing an example of the position and shape of each pad 101, the position and shape of each land 201, and the position and shape of each opening 401 in a semiconductor module 1 manufactured using a stencil 400 that satisfies the condition that Sa is smaller than both Pa and La, or Sb is larger than both Pb and Lb, when manufacturing a semiconductor module 1 in which a semiconductor device 100 is mounted on a mounting substrate 200 with the center of the semiconductor device 100 curved convexly toward the mounting substrate 200, as shown in Figure 14.

[0246] The upper image in Figure 21 is a cross-sectional view that schematically shows an example of a cross section of a semiconductor module 1 manufactured by executing a semiconductor module manufacturing process, and the lower image is a plan view that schematically shows an example of each pad 101, each land 201, and each opening 401.

[0247] As shown in FIG. 21, by manufacturing the semiconductor module 1 using a stencil 400 in which Sa is smaller than both Pa and La, it is desirable to make the amount of solder joint material 301 formed above the nearest land 201a relatively small relative to the area Pa of the nearest pad 101a and the area La of the nearest land 201a.

[0248] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of the problem of the solder joint material 301 overflowing from the front pad 101a and the problem of the solder joint material 301 overflowing from the front land 201a is suppressed.

[0249] Furthermore, as shown in FIG. 21, it is desirable to manufacture the semiconductor module 1 using a stencil 400 in which Sb is larger than both Pb and Lb, thereby making the amount of solder bonding material 301 formed above the farthest land 201b relatively large relative to the area Pb of the farthest pad 101b and the area Lb of the farthest land 201b.

[0250] This makes it possible to manufacture a semiconductor module 1 in which the occurrence of defects such as the solder joint material 301 chipping off the farthest pad 101b and the occurrence of defects such as the solder joint material 301 chipping off the farthest land 201b is suppressed.

[0251] Incidentally, semiconductor devices distributed on the market are usually accompanied by product data sheets. In addition to the pad pattern of the semiconductor device, the product data sheets may also include recommended land patterns and recommended stencil patterns for mounting the semiconductor device face-down on a mounting board. In the case of mounting using a stencil in the manufacturing method of the semiconductor module of the present disclosure, the features described in the present disclosure can be understood in association with the recommended stencil patterns listed in the product data sheets of the semiconductor devices used in the semiconductor module.

[0252] For example, in the present disclosure, there is a method for manufacturing a semiconductor module by mounting a semiconductor device face-down on a mounting substrate using a stencil, the semiconductor device comprising n (n is an integer of 2 or more) pads arranged on an upper surface of the semiconductor device, the mounting substrate comprising n lands corresponding one-to-one to the n pads, the stencil comprising n openings corresponding one-to-one to the n pads, an area of ​​the nearest pad closest to the center of the semiconductor device in a planar view of the semiconductor device is defined as Pa, an area of ​​the farthest pad farthest from the center of the semiconductor device in a planar view of the semiconductor device is defined as Pb, and the area of ​​the n lands corresponding to the nearest pad is defined as Pc. The feature that "Sa is smaller than both Pa and La, or Sb is larger than both Pb and Lb," can be said to be equivalent to being able to confirm the relationship in the above feature between the pad pattern and recommended land pattern listed in the product data sheet of the semiconductor device used in the semiconductor module, and the recommended stencil pattern."

[0253] <Discussion> Below, we will consider the desirable relationship between the shapes of the n pads 101 and the shapes of the n lands 201 in the semiconductor module 1 described above, in the case where the shape of the pad 101 in a planar view of the semiconductor device 100 is not necessarily identical to the shape of the land 201 corresponding to the pad 101 in a planar view of the mounting board 200.

[0254] FIG. 22 is a schematic cross-sectional view for explaining a desirable relationship between the shapes of the n pads 101 and the n lands 201. In FIG.

[0255] As shown in FIG. 22 , here, the warping of the semiconductor device 100 is approximated as a linear change, and the distance from the center of the semiconductor device 100 to the center of each of the n kth pads in a planar view of the semiconductor device 100 is referred to as D(k), 1 / 4 of the length of the diagonal of the semiconductor device 100 in a planar view of the semiconductor device 100 is referred to as the reference radius r, the height of the solder bonding material 301 at a position where the distance from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is the reference radius r is referred to as t, and the amount of curvature of the semiconductor device 100 is referred to as a.

[0256] As shown in Figure 22, when the semiconductor device 100 is warped in such a way that the center of the semiconductor device 100 is curved convexly in a direction away from the mounting substrate 200, generally, the amount of solder joint material 301 at a position that is a distance r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is neither excessive nor insufficient, the amount of solder joint material 301 at a position that is a distance less than r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is insufficient, and the amount of solder joint material 301 at a position that is a distance greater than r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is excessive.

[0257] Here, when considering the solder joint material 301 on the pad 101 where D(k) is larger than r, the solder joint material 301 is pressed into the land 201 side due to the warpage of the semiconductor device 100 .

[0258] Therefore, if the pushing amount (height) of the solder joint material 301 is Δt(k), Δt(k) is expressed by the following formula A.

[0259] Δt(k)=2×(D(k) / R-1 / 2)×a (Formula A)

[0260] Here, as described above, the diagonal length R is the length of the diagonal line of the semiconductor device 100 when viewed from above.

[0261] FIG. 23 is a schematic plan view for explaining a desirable relationship between the shapes of the n pads 101 and the n lands 201. In FIG.

[0262] As shown in Figure 23, here, the length of each of the n kth lands 201 in the first direction (X-axis direction in Figure 23) when viewed in a plane of the mounting substrate 200 is referred to as XL(k), the length of each of the n kth lands 201 in the second direction (Y-axis direction in Figure 23) when viewed in a plane of the mounting substrate 200 is referred to as YL(k), the length of each of the n kth pads 101 in the first direction when viewed in a plane of the semiconductor device 100 is referred to as XP(k), and the length of each of the n kth pads 101 in the second direction when viewed in a plane of the semiconductor device 100 is referred to as YP(k).

[0263] In addition, the following description will be given assuming that the shape of each kth land 201 in a plan view of the mounting substrate 200 is the same as the shape of the solder bonding material 301 formed above the kth land 201.

[0264] Note that, here, as shown in Figure 23, the case will be discussed as an example in which the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is larger than the area of ​​the kth land 201 in a planar view of the mounting substrate 200. However, a similar discussion will also hold if the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is smaller than the area of ​​the kth land 201 in a planar view of the mounting substrate 200 by swapping XP(k) and XL(k) and swapping YP(k) and YL(k).

[0265] FIG. 24 is a schematic cross-sectional view for explaining a desirable relationship between the shapes of the n pads 101 and the n lands 201. In FIG.

[0266] FIG. 25 is a schematic perspective view for explaining a desirable relationship between the shapes of the n pads 101 and the n lands 201. In FIG.

[0267] As can be seen from FIGS. 23 and 24, the excess volume of the solder joint material 301 corresponding to the k-th land 201 is Δt(k)×XL(k)×YL(k).

[0268] Therefore, it is desirable to make the area of ​​the kth pad 101 in the plan view of the semiconductor device 100 larger than the area of ​​the kth land 201 in the plan view of the mounting substrate 200 to release this excess volume.

[0269] In this case, if the shape of the kth pad 101 in the planar view of the semiconductor device 100 is expanded by ΔX(k) in the first direction and ΔY(k) in the second direction relative to the shape of the kth land 201 in the planar view of the mounting substrate 200, and this excess volume can be released, then, as shown in Figure 25, this excess volume V(k) can be expressed by the following equation B.

[0270] V(k)=t(k)×ΔX(k)×YL(k) / 2+t(k)×XL(k)×ΔY(k) / 2+t(k)×ΔX(k)×ΔY(k) / 3=t(k)×(ΔX(k)×YL(k) / 2+XL(k)×ΔY(k) / 2+ΔX(k)×ΔY(k) / 3) (Formula B)

[0271] Here, t(k)=t−Δt(k).

[0272] Therefore, from the fact that t(k) = t - Δt(k) and from equations A and B, when the center of the semiconductor device 100 is warped in a convex shape in a direction away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is larger than the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it can be said that it is desirable for the following relationship to hold for pads 101 for which D(k) is larger than r.

[0273] ΔX(k)×YL(k) / 2+XL(k)×ΔY(k) / 2-ΔX(k)×ΔY(k) / 3=XL(k)×YL(k) / [-t{(2×D(k) / R-1 / 2)×a}+1]

[0274] Similarly, when the center of the semiconductor device 100 is warped in a convex shape away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is larger than the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it is desirable that the following relationship hold for pads 101 where D(k) is smaller than r.

[0275] ΔX(k)×YL(k) / 2+XL(k)×ΔY(k) / 2−ΔX(k)×ΔY(k) / 3=XL(k)×YL(k) / [t{(2×D(k) / R-1 / 2)×a}-1]

[0276] Similarly, when the center of the semiconductor device 100 is warped in a convex shape away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is smaller than the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it is desirable that the following relationship hold for pads 101 for which D(k) is greater than r.

[0277] ΔX(k)×YP(k) / 2+XP(k)×ΔY(k) / 2−ΔX(k)×ΔY(k) / 3=XP(k)×YP(k) / [−t{(2×D(k) / R−1 / 2)×a}+1]

[0278] Similarly, when the center of the semiconductor device 100 is warped in a convex shape away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is smaller than the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it is desirable that the following relationship hold for pads 101 for which D(k) is smaller than r.

[0279] ΔX(k)×YL(k) / 2+XL(k)×ΔY(k) / 2−ΔX(k)×ΔY(k) / 3=XL(k)×YL(k) / [t{(2×D(k) / R-1 / 2)×a}-1]

[0280] Here, ΔX(k)=|XP(k)−XL(k)| and ΔY(k)=|YL(k)−YL(k)|.

[0281] Therefore, in each of the n k-th pads 101, one or more inner pads located inside a circle centered at the center of the semiconductor device 100 in a plan view of the semiconductor device 100,

[0282] |XP(k)-XL(k)|×YL(k) / 2+XL(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k ) |

[0283] Alternatively, |XP(k)-XL(k)|×YP(k) / 2+XP(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k)-YL(k)| / 3=XP(k)×YP(k) / [-t / {(2×D(k) / R-½)×a}+1] holds,

[0284] Among the n k-th pads 101, in each of one or more outer pads located outside the circle in plan view of the semiconductor device 100, |XP(k)-XL(k)|×YL(k) / 2+XL(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k)-YL(k)| / 3=XL(k)×YL(k) / [t / {(2×D(k) / R-½)×a}-1]

[0285] Alternatively, it is desirable that |XP(k)-XL(k)|×YP(k) / 2+XP(k)×|YP(k)-YL(k)| / 2-|XP(k)-XL(k)|×|YP(k)-YL(k)| / 3=XP(k)×YP(k) / [t / {(2×D(k) / R-½)×a}-1] be satisfied.

[0286] Next, in the semiconductor module 1, for each of the n pads 101, when the shape of the pad 101 in a planar view of the semiconductor device 100 is the same as the shape of the land 201 corresponding to the pad 101 in a planar view of the mounting substrate 200, we will consider the desirable relationship between the shape of the n pads 101 and the shape of the n openings 401.

[0287] As shown in FIG. 22 , here too, the warping of the semiconductor device 100 is approximated as a linear change, and the distance from the center of the semiconductor device 100 to the center of each of the n kth pads in a planar view of the semiconductor device 100 is referred to as D(k), 1 / 4 of the length of the diagonal of the semiconductor device 100 in a planar view of the semiconductor device 100 is referred to as the reference radius r, the height of the solder bonding material 301 at a position whose distance from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is the reference radius r is referred to as t, and the amount of curvature of the semiconductor device 100 is referred to as a.

[0288] As described above, when the semiconductor device 100 is warped such that the center of the semiconductor device 100 is curved convexly in a direction away from the mounting substrate 200 as shown in FIG. 22 , generally, the amount of solder joint material 301 at a position that is a distance r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is neither excessive nor insufficient, the amount of solder joint material 301 at a position that is a distance less than r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is insufficient, and the amount of solder joint material 301 at a position that is a distance greater than r from the center of the semiconductor device 100 in a planar view of the semiconductor device 100 is excessive.

[0289] FIG. 26 is a schematic perspective view for explaining a desirable relationship between the shapes of the n pads 101 and the shapes of the n openings 401. In FIG.

[0290] As shown in Figure 26, here, the length of each of the n kth openings 401 in a first direction (X-axis direction in Figure 25) when viewed in a plane of the stencil 400 will be referred to as XS(k), and the length of each of the n kth openings 401 in a second direction (Y-axis direction in Figure 25) when viewed in a plane of the stencil 400 will be referred to as YS(k).

[0291] Also, as shown in Figure 23, the length of each of the n kth pads 101 in the first direction (X-axis direction in Figure 2) when viewed in a plane of the semiconductor device 100 will be referred to as XP(k), and the length of each of the n kth pads 101 in the second direction (Y-axis direction in Figure 23) when viewed in a plane of the semiconductor device 100 will be referred to as YP(k).

[0292] As can be seen from Figure 26, if we consider the solder bonding material 301 in a pad 101 where D(k) is greater than r, and the area of ​​the opening 401 corresponding to the kth pad 101 in a planar view of the stencil 400 is equal to the area of ​​the kth pad 101 in a planar view of the semiconductor device 100, the excess volume of the solder bonding material 301 corresponding to the kth pad 101 is Δt(k) × XL(k) × YL(k).

[0293] Therefore, it is desirable to reduce this excess volume by making the area of ​​the opening 401 corresponding to the kth pad 101 in a planar view of the stencil 400 smaller than the area of ​​the kth pad 101 in a planar view of the semiconductor device 100.

[0294] In this case, if the shape of the opening 401 corresponding to the kth pad 101 in the planar view of the stencil 400 is narrowed by ΔX(k) in the first direction and ΔY(k) in the second direction from the shape of the kth land 201 in the planar view of the semiconductor device 100, thereby reducing the excess volume, as shown in FIG. 26 , the excess volume V(k) can be expressed by the following equation C.

[0295] V(k)=t×ΔX(k)×YP(k)+t×XP(k)×ΔY(k)−t×ΔX(k)×ΔY(k) (Formula C)

[0296] Therefore, from equations A and C, when the center of the semiconductor device 100 is warped in a convex shape away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is equal to the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it can be said that it is desirable for the following relationship to hold for pads 101 whose D(k) is greater than r.

[0297] ΔX(k)×YP(k)+XP(k)×ΔY(k)−ΔX(k)×ΔY(k)={(2×D(k) / R-1 / 2)×a} / t×XP(k)×YP(k)

[0298] Similarly, when the center of the semiconductor device 100 is warped in a convex shape away from the mounting substrate 200, and the area of ​​the kth pad 101 in a planar view of the semiconductor device 100 is equal to the area of ​​the kth land 201 in a planar view of the mounting substrate 200, it is desirable that the following relationship hold for pads 101 for which D(k) is smaller than r.

[0299] ΔX(k)×YP(k)+XP(k)×ΔY(k)+ΔX(k)×ΔY(k)=-{(2×D(k) / R-1 / 2)×a} / t×XP(k)×YP(k)

[0300] Here, ΔX(k)=|XP(k)−XL(k)| and ΔY(k)=|YL(k)−YL(k)|.

[0301] Therefore, in each of the n k-th pads 101, one or more inner pads located inside a circle centered at the center of the semiconductor device 100 in a plan view of the semiconductor device 100,

[0302] |XP(k)-XS(k)|×YP(k)+XP(k)×|YP(k)-YS(k)|+|XP(k)-XS( k) |×|YP(k)-YS(k)|=-{(2×D(k) / R-1 / 2)×a} / t×XP(k)×YP(k) is established,

[0303] Of the n kth pads 101, it is desirable that for each of one or more outer pads located outside the circle in a planar view of the semiconductor device 100, the following holds: |XP(k)-XS(k)|×YP(k)+XP(k)×|YP(k)-YS(k)|-|XP(k)-XS(k)|×|YP(k)-YS(k)|={(2×D(k) / R-1 / 2)×a} / t×XP(k)×YP(k).

[0304] (Supplementary Note) While the semiconductor device according to one aspect of the present disclosure has been described above based on an embodiment, the present disclosure is not limited to this embodiment. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art may also be included within the scope of one or more aspects of the present disclosure.

[0305] The present disclosure is widely applicable to semiconductor modules in which a semiconductor device is mounted on a mounting substrate.

[0306] 1 Semiconductor module 10 First vertical MOS transistor 11 First source electrode 14 First source region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First body region 19 First gate electrode 20 Second vertical MOS transistor 21 Second source electrode 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Lightly doped impurity layer 34 Oxide film 35 Protective film 40 Semiconductor layer 100 Semiconductor device 101 Pad 111, 111a, 111b, 111c, 111d, 111e, 111f First source pad 119 First gate pad 121, 121a, 121b, 121c, 121d, 121e, 121f second source pad 129 second gate pad 101a nearest pad 101b farthest pad 200 mounting substrate 201 land 201a nearest land 201b farthest land 211a, 211b, 211c, 211d, 211e, 211f first source land 219 first gate land 221a, 221b, 221c, 221d, 221e, 221f second source land 229 second gate land 301 solder joint material 400 stencil 401 opening 500 squeegee 501 paste-like solder joint material

Claims

1. A semiconductor module in which a chip size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors is face-down mounted on a mounting substrate, wherein the semiconductor device includes: a semiconductor layer; a metal layer laminated on the semiconductor layer in contact with the lower surface of the semiconductor layer; and n (n is an integer of 2 or more) pads disposed on the upper surface of the semiconductor device. In a plan view of the semiconductor device, the center of the semiconductor device is curved convexly in a direction away from the mounting substrate or convexly in a direction approaching the mounting substrate. The mounting substrate includes n lands corresponding one-to-one to the n pads. Each of the n pads is joined to one of the n lands corresponding to the pad by a solder bonding material. Among the n pads, when the area of the nearest pad closest to the center of the semiconductor device in a plan view of the semiconductor device is Pa, the area of the farthest pad farthest from the center of the semiconductor device in a plan view of the semiconductor device is Pb, the area of the nearest land corresponding to the nearest pad among the n lands in a plan view of the mounting substrate is La, and the area of the farthest land corresponding to the farthest pad in a plan view of the mounting substrate is Lb, a semiconductor module in which Pa / La is less than 1 and Pb / Lb is greater than 1, or Pa / La is greater than 1 and Pb / Lb is less than 1.

2. Using n k's (k is an integer from 1 to n) that do not overlap with each other, each of the n pads is referred to as the k-th pad, each of the n lands corresponding to each of the n k-th pads is referred to as the k-th land, the area of each of the n k-th pads in a plan view of the semiconductor device is referred to as P(k), and the area of each of the n k-th lands in a plan view of the mounting substrate is referred to as L(k). In the semiconductor module according to claim 1, P(k) / L(k) increases monotonically or decreases monotonically according to the distance from the center of the semiconductor device to each of the n k-th pads in a plan view of the semiconductor device.

3. In a plan view of the semiconductor device, the semiconductor device is rectangular. When the distance from the center of the semiconductor device to the center of each of the n k-th pads in the plan view of the semiconductor device is denoted as D(k), among the n k-th pads, For each of one or more inner pads located inside the semiconductor device in the plan view of the semiconductor device, P(k) / L(k) is less than 1 with respect to a circle centered at the center of the semiconductor device in the plan view of the semiconductor device and having a radius r determined by, or a circle centered at the center of the semiconductor device in the plan view of the semiconductor device and having a radius r determined by 1 / 4 of the length of the diagonal of the semiconductor device in the plan view of the semiconductor device. For each of one or more outer pads located outside the circle in the plan view of the semiconductor device among the n k-th pads, P(k) / L(k) is greater than 1. The semiconductor module according to claim 2.

4. In a plan view of the semiconductor device, the semiconductor device is rectangular. When the distance from the center of the semiconductor device to the center of each of the n k-th pads in the plan view of the semiconductor device is denoted as D(k), among the n k-th pads, for each of one or more inner pads located inside a circle centered at the center of the semiconductor device in the plan view of the semiconductor device, with a radius r determined by or r determined by 1 / 4 of the length of the diagonal of the semiconductor device in the plan view of the semiconductor device, P(k) / L(k) is greater than 1, and for each of one or more outer pads located outside the circle among the n k-th pads, P(k) / L(k) is less than 1. The semiconductor module according to claim 2.

5. In a plan view of the semiconductor device, the center of the semiconductor device is convexly curved in a direction away from the mounting substrate. In the plan view of the semiconductor device, the semiconductor device is rectangular and has a side extending in a first direction and a side extending in a second direction orthogonal to the first direction. In the plan view of the semiconductor device, the distance from the center of the semiconductor device to the center of each of the n k-th pads is denoted as D(k). In the plan view of the semiconductor device, one-fourth of the length of the diagonal of the semiconductor device is denoted as r. In the plan view of the semiconductor device, the length of each of the n k-th pads in the first direction is denoted as XP(k). In the plan view of the semiconductor device, the length of each of the n k-th pads in the second direction is denoted as YP(k). In the plan view of the mounting substrate, the length of each of the n k-th lands in the first direction is denoted as XL(k). In the plan view of the mounting substrate, the length of each of the n k-th lands in the second direction is denoted as YL(k). In the plan view of the semiconductor device, the height of the solder bonding material at a position where the distance from the center of the semiconductor device is r is denoted as t. When the amount of curvature of the semiconductor device is denoted as a, for each of one or more inner pads located inside the circle centered on the center of the semiconductor device in the plan view of the semiconductor device among the n k-th pads, |XP(k) - XL(k)|×YL(k) / 2 + XL(k)×|YP(k) - YL(k)| / 2 - |XP(k) - XL(k)|×|YP(k) - YL(k)| / 3 = XL(k)×YL(k) / [-t / {(2×D(k) / R - 1 / 2)×a} + 1] or |XP(k) - XL(k)|×YP(k) / 2 + XP(k)×|YP(k) - YL(k)| / 2 - |XP(k) - XL(k)|×|YP(k) - YL(k)| / 3 = XP(k)×YP(k) / [-t / {(2×D(k) / R - 1 / 2)×a} + 1] holds. For each of one or more outer pads located outside the circle in the plan view of the semiconductor device among the n k-th pads,|XP(k) - XL(k)| × YL(k) / 2 + XL(k) × |YP(k) - YL(k)| / 2 - |XP(k) - XL(k)| × |YP(k) - YL(k)| / 3 = XL(k) × YL(k) / [(t / {(2 × D(k) / R - 1 / 2) × a} - 1)] or |XP(k) - XL(k)| × YP(k) / 2 + XP(k) × |YP(k) - YL(k)| / 2 - |XP(k) - XL(k)| × |YP(k) - YL(k)| / 3 = XP(k) × YP(k) / [(t / {(2 × D(k) / R - 1 / 2) × a} - 1)] holds. The semiconductor module according to claim 2.

6. A method for manufacturing a semiconductor module, comprising face-down mounting a chip size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors on a mounting substrate using a stencil, wherein: The semiconductor device includes: A semiconductor layer; A metal layer laminated on the semiconductor layer in contact with the lower surface of the semiconductor layer; N (where n is an integer of 2 or more) pads disposed on the upper surface of the semiconductor device; The center of the semiconductor device in a plan view of the semiconductor device is convexly curved in a direction away from the mounting substrate; The mounting substrate includes n lands corresponding one-to-one to the n pads; The stencil includes n openings corresponding one-to-one to the n pads; Each of the n openings is an opening for forming a solder bonding material for bonding one pad corresponding to the opening among the n pads and one land corresponding to the opening among the n lands above the one land; Among the n pads, the area of the nearest pad closest to the center of the semiconductor device in a plan view of the semiconductor device is defined as Pa, the area of the farthest pad farthest from the center in a plan view of the semiconductor device is defined as Pb, among the n lands, the area of the nearest land corresponding to the nearest pad in a plan view of the mounting substrate is defined as La, the area of the farthest land corresponding to the farthest pad in a plan view of the mounting substrate is defined as Lb, and among the n openings, the area of the nearest opening corresponding to the nearest pad in a plan view of the stencil is defined as Sa, the area of the farthest opening corresponding to the farthest pad in a plan view of the stencil is defined as Sb, when: Sa is larger than either Pa or La, or Sb is smaller than either Pb or Lb; A first step of forming the solder bonding material above each of the n lands using the stencil; A second step of performing a reflow process to bond each of the n pads to one land corresponding to the pad among the n lands using the solder bonding material formed above the one land by executing the first step.Method for manufacturing a semiconductor module.

7. In a plan view of the semiconductor device, the semiconductor device is rectangular. Using n k's (where k is an integer from 1 to n) that do not overlap with each other, each of the n pads is referred to as the k-th pad, each of the n lands corresponding to each of the n k-th pads is referred to as the k-th land, each of the n openings corresponding to each of the n k-th pads is referred to as the k-th opening, the area of each of the n k-th pads in the plan view of the semiconductor device is denoted as P(k), the area of each of the n k-th lands in the plan view of the mounting substrate is denoted as L(k), the area of each of the n k-th openings in the plan view of the stencil is denoted as S(k), and the distance from the center of the semiconductor device to the center of each of the n k-th pads in the plan view of the semiconductor device is denoted as D(k). Among the n k-th pads, at each of one or more inner pads located inside the semiconductor device in the plan view of the semiconductor device, with r determined by, or with r being the radius of a circle centered at the center of the semiconductor device in the plan view of the semiconductor device and determined by 1 / 4 of the length of the diagonal of the semiconductor device in the plan view of the semiconductor device, S(k) is larger than either P(k) or L(k), or at each of one or more outer pads located outside the semiconductor device in the plan view of the semiconductor device of the circle, S(k) is smaller than either P(k) or L(k). The method for manufacturing a semiconductor module according to claim 6.

8. In each of the inner pads, S(k) / P(k) is greater than 1, and in each of the outer pads, S(k) / P(k) is less than 1. The method for manufacturing a semiconductor module according to claim 7.

9. In each of the inner pads, S(k) / L(k) is greater than 1, and in each of the outer pads, S(k) / L(k) is less than 1. The method for manufacturing a semiconductor module according to claim 7.

10. In a plan view of the semiconductor device, the semiconductor device is a rectangle having a side extending in a first direction and a side extending in a second direction orthogonal to the first direction. The shape of each of the k-th pads in the plan view of the semiconductor device is equal to the shape of each of the k-th pads in the plan view of the mounting substrate. The length of each of the n k-th pads in the first direction in the plan view of the semiconductor device is referred to as XP(k). The length of each of the n k-th pads in the second direction in the plan view of the semiconductor device is referred to as YP(k). The length of each of the n k-th openings in the first direction in the plan view of the stencil is referred to as XS(k). The length of each of the n k-th openings in the second direction in the plan view of the stencil is referred to as YS(k). The height of the solder bonding material at a position where the distance from the center of the semiconductor device is r in the plan view of the semiconductor device is referred to as t. When the amount of curvature of the semiconductor device is referred to as a, In each of the inner pads, |XP(k) - XS(k)|×YP(k) + XP(k)×|YP(k) - YS(k)| + |XP(k) - XS(k)|×|YP(k) - YS(k)| = -{(2×D(k) / R - 1 / 2)×a} / t×XP(k)×YP(k) holds. In each of the outer pads, |XP(k) - XS(k)|×YP(k) + XP(k)×|YP(k) - YS(k)| - |XP(k) - XS(k)|×|YP(k) - YS(k)| = {(2×D(k) / R - 1 / 2)×a} / t×XP(k)×YP(k) holds. The method for manufacturing a semiconductor module according to claim 8 or claim 9.

11. A method for manufacturing a semiconductor module, comprising face-down mounting a chip size package type semiconductor device including one or more vertical MOS (Metal Oxide Semiconductor) transistors on a mounting substrate using a stencil, wherein: The semiconductor device includes: A semiconductor layer; A metal layer laminated on the semiconductor layer in contact with the lower surface of the semiconductor layer; N (where n is an integer of 2 or more) pads disposed on the upper surface of the semiconductor device; The center of the semiconductor device in a plan view of the semiconductor device is convexly curved in a direction approaching the mounting substrate; The mounting substrate includes n lands corresponding one-to-one to the n pads; The stencil includes n openings corresponding one-to-one to the n pads; Each of the n openings is an opening for forming a solder bonding material for bonding one pad corresponding to the opening among the n pads and one land corresponding to the opening among the n lands above the one land; Among the n pads, when the area of the nearest pad closest to the center of the semiconductor device in a plan view of the semiconductor device is Pa, the area of the farthest pad farthest from the center in a plan view of the semiconductor device is Pb, among the n lands, the area of the nearest land corresponding to the nearest pad in a plan view of the mounting substrate is La, the area of the farthest land corresponding to the farthest pad in a plan view of the mounting substrate is Lb, and among the n openings, the area of the nearest opening corresponding to the nearest pad in a plan view of the stencil is Sa, and the area of the farthest opening corresponding to the farthest pad in a plan view of the stencil is Sb, then Sa is smaller than either Pa or La, or Sb is larger than either Pb or Lb; A first step of forming the solder bonding material above each of the n lands using the stencil; A second step of performing a reflow process to bond each of the n pads to one land corresponding to the pad among the n lands using the solder bonding material formed above the one land by executing the first step.Method for manufacturing a semiconductor module.

12. A method for manufacturing a semiconductor module for manufacturing the semiconductor module according to claim 1 using a stencil, wherein the center of the semiconductor device in a plan view of the semiconductor device is convex in a direction away from the mounting substrate, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings is an opening for forming a solder bonding material for bonding one pad corresponding to the opening among the n pads and one land corresponding to the opening among the n lands above the one land, when an area of the nearest pad, which is the nearest to the center of the semiconductor device in the plan view of the semiconductor device, among the n pads is Pa, an area of the nearest land corresponding to the nearest pad, in the plan view of the mounting substrate, among the n lands is La, and an area of the nearest opening corresponding to the nearest pad, in the plan view of the stencil, among the n openings is Sa, Sa is larger than both Pa and La, a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one land corresponding to the pad among the n lands using the solder bonding material formed above the one land by executing the first step. A method for manufacturing a semiconductor module.

13. A method for manufacturing a semiconductor module for manufacturing the semiconductor module according to claim 1 using a stencil, wherein in a plan view of the semiconductor device, the center of the semiconductor device is convex in a direction away from the mounting substrate, the stencil includes n openings corresponding one-to-one to the n pads, each of the n openings is an opening for forming a solder bonding material for bonding one pad corresponding to the opening among the n pads and one land corresponding to the opening among the n lands above the one land, when the area of the farthest pad, which is the pad among the n pads that is the farthest from the center of the semiconductor device in a plan view of the semiconductor device, is Pb, the area of the farthest land, which is the land corresponding to the farthest pad among the n lands, in a plan view of the mounting substrate is Lb, and the area of the farthest opening, which is the opening corresponding to the farthest pad among the n openings, in a plan view of the stencil is Sb, Sb is smaller than both Pb and Lb, a first step of forming the solder bonding material above each of the n lands using the stencil, and a second step of performing a reflow process to bond each of the n pads to one land corresponding to the pad among the n lands using the solder bonding material formed above the one land by executing the first step. A method for manufacturing a semiconductor module.

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