Light detection apparatus and electronic device

Abstract

Provided is a light detection apparatus in which deterioration in performance is suppressed. The light detection apparatus comprises: a semiconductor layer in which one surface is a light entering surface and the other surface is an element formation surface and which has a plurality of cell regions isolated from each other by an isolation wall extending from the light entering surface to the element formation surface; an element isolation structure that is made of an insulating material, is provided on the element formation surface side in the corresponding cell region, and divides the element formation surface side in the cell region into a plurality of active regions in a plan view; a through hole that penetrates the element isolation structure along the thickness direction; and a conductor which is provided in the through hole and of which a first end portion, which is the end portion on the light entering surface side, is in contact with a semiconductor part in the cell region. The cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor.

Description

Photodetector and electronic equipment

[0001] The present technology (technology according to the present disclosure) relates to a light detection device and an electronic device.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a structure in which a conductor is buried in a part of a trench for separating pixels as a reference potential contact of an image sensor, and the side surface of the conductor is electrically connected to a silicon substrate.

[0003] Patent Document 2 discloses that the generation of dark current is suppressed by forming p+ type impurity regions not only on the surface of the pixel but also on the bottom and sidewalls of the STI region.

[0004] JP 2016-39315 A JP 2013-153174 A JP 2023-179619 A JP 2022-135130 A

[0005] There are cases where the image sensor performance is not sufficient.

[0006] The present technology aims to provide a photodetector and electronic device in which degradation of performance is suppressed.

[0007] A photodetector according to one aspect of the present technology includes a semiconductor layer having a plurality of cell regions, one surface of which is a light incident surface and the other surface of which is an element formation surface, the cell regions being separated from each other by separation walls extending from the light incident surface to the element formation surface; an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and dividing the element formation surface side of the cell region into a plurality of active regions in a planar view; a through hole penetrating the element isolation structure in a thickness direction; and a conductor provided in the through hole and having a first end, which is an end on the light incident surface side, in contact with a semiconductor portion in the cell region, wherein the cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor.

[0008] According to another aspect of the present technology, there is provided a photodetector device comprising: a semiconductor layer having a light incident surface on one side and an element formation surface on the other side, the semiconductor layer including a matrix of a plurality of cell regions each including a photoelectric conversion region of a first conductivity type; and an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and partitioning the element formation surface side of the cell region into a plurality of active regions in a planar view, wherein the cell region includes a first impurity region that is a semiconductor region of a second conductivity type at a depth position between the photoelectric conversion region and the active region, the first impurity region including an impurity that imparts the semiconductor with the second conductivity type, and a concentration of the impurity in the first impurity region having a gradient that gradually increases from a depth position of a bottom surface of the element isolation structure toward a deeper position.

[0009] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device.

[0010] 5A . FIG. 5B is a chip layout diagram showing a configuration example of the photodetector according to the first embodiment of the present technology. FIG. 5C is a block diagram showing a configuration example of the photodetector according to the first embodiment of the present technology. FIG. 5D is an equivalent circuit diagram of a pixel of the photodetector according to the first embodiment of the present technology. FIG. 6A is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first comparative example. FIG. 6B is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second comparative example. FIG. 6C is a longitudinal sectional view showing an enlarged view of a main portion of a pixel included in a photodetector according to a second comparative example. FIG. 6D is an explanatory view showing an element formation surface side of a cell region included in a photodetector according to a second comparative example. FIG. 6D is an explanatory view showing a positional relationship between an element isolation structure and a conductor on the element formation surface side of a cell region included in a photodetector according to the first embodiment of the present technology. 11A and 11B are longitudinal cross-sectional views showing, on an enlarged scale, a portion of a cross-sectional configuration of a pixel included in a photodetector according to a first modified example of the first embodiment of the present technology; FIG. 11B is a longitudinal cross-sectional view showing, on an enlarged scale, a portion of a cross-sectional configuration of a pixel included in a photodetector according to a second modified example of the present technology; FIG. 11C is a longitudinal cross-sectional view showing, on an enlarged scale, a portion of a cross-sectional configuration of a pixel included in a photodetector according to a third modified example of the first embodiment of the present technology; FIG. 11D is a longitudinal cross-sectional view showing, on an enlarged scale, a portion of a cross-sectional configuration of a pixel included in a photodetector according to a second modified example of the present technology; FIG. 11E is a longitudinal cross-sectional view showing, on an enlarged scale, a portion of a cross-sectional configuration of a pixel included in a photodetector according to a second modified example of the present technology;18 is a diagram showing an example of a schematic configuration of an electronic device. FIG. 19 is an explanatory diagram showing a positional relationship between an element isolation structure and an active region on the element formation surface side of a cell region of a photodetector according to a second modification of the second embodiment of the present technology. FIG. 20 is a longitudinal cross-sectional view showing, in enlarged form, a portion of a cross-sectional configuration of a cell region of a photodetector according to a third modification of the second embodiment of the present technology, when viewed in a plane along the A-A' cutting line of FIG. 10. FIG. 19 is a diagram showing an impurity distribution along the B-B' line of FIG. 18. FIG. 21 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel transistor of a photodetector according to a fourth modification of the present technology. FIG. 22 is a longitudinal cross-sectional view showing a cross-sectional configuration of a cell region of a photodetector according to a fourth embodiment of the present technology, when viewed in a plane along the A-A cutting line of FIG. 22. FIG. 22 is a longitudinal cross-sectional view showing a cross-sectional configuration of a cell region of a photodetector according to a fourth embodiment of the present technology, when viewed in a plane along the B-B line of FIG. 22. 29 is a cross-sectional view of a process continuing from FIG. 26 . FIG. 29 is a cross-sectional view of a process continuing from FIG. 27 . FIG. 35 is an explanatory diagram showing the positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to a first modified example of the fourth embodiment of the present technology. FIG. 36 is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in a plane along the D-D cutting line of FIG. 29 . FIG. 37 is an explanatory diagram showing the positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to a second modified example of the fourth embodiment of the present technology. FIG. 38 is an explanatory diagram showing the positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to a third modified example of the fourth embodiment of the present technology. FIG. 39 is a longitudinal cross-sectional view showing a cross-sectional configuration of a conductor included in a photodetector according to a fourth modified example of the present technology. FIG. 39 is a cross-sectional view showing a cross-sectional configuration of a shield wall included in a photodetector according to a fifth modified example of the fourth embodiment of the present technology. FIG. 39 is an explanatory diagram showing the positional relationship between a conductor, a shield wall, and a via on the element formation surface side of a cell region included in a photodetector according to a sixth modified example of the fourth embodiment of the present technology. FIG. 39 is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in a plane along the B-B line of FIG.10 is an explanatory diagram showing a positional relationship between a conductor, a shield wall, and a via on the element formation surface side of a cell region included in a photodetector according to a seventh modified example of the fourth embodiment of the present technology. FIG. 11 is an explanatory diagram showing a positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to an eighth modified example of the fourth embodiment of the present technology. FIG. 12 is an explanatory diagram showing a positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to an eighth modified example of the fourth embodiment of the present technology. FIG. 13 is an explanatory diagram showing a positional relationship between a conductor and a shield wall on the element formation surface side of a cell region included in a photodetector according to an eighth modified example of the fourth embodiment of the present technology.

[0011] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0012] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0013] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0014] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0015] The description will be given in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment (application to electronic devices) 4. Fourth embodiment

[0016] First Embodiment In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0017] <Overall Configuration of Photodetection Device> First, the overall configuration of the photodetection device 1 will be described. As shown in Fig. 1 , the photodetection device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape in a plan view. That is, the photodetection device 1 is mounted on the semiconductor chip 2. As shown in Fig. 21 , the photodetection device 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0018] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes, in a two-dimensional plane including an X direction and a Y direction that intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0019] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 21 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other within the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction, depth direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0020] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0021] 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0022] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0023] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0024] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0025] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0026] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0027] <Pixel> The pixel 3 is, for example, a phase difference detection pixel. As shown in FIG. 3 , the pixel 3 includes a photoelectric conversion unit 16. The photoelectric conversion unit 16 includes photoelectric conversion elements PD1 and PD2, charge accumulation regions (floating diffusions) FD1 and FD2 that accumulate (hold) signal charges photoelectrically converted by the photoelectric conversion elements PD1 and PD2, and transfer transistors TR1 and TR2 that transfer the signal charges photoelectrically converted by the photoelectric conversion elements PD1 and PD2 to the charge accumulation regions FD1 and FD2. Each of the multiple pixels 3 also includes a readout circuit 15 electrically connected to the photoelectric conversion unit 16, more specifically, to the charge accumulation regions FD1 and FD2.

[0028] Each of the two photoelectric conversion elements PD1 and PD2 generates a signal charge according to the amount of light received. The photoelectric conversion elements PD1 and PD2 also temporarily accumulate (hold) the generated signal charge. The cathode side of the photoelectric conversion element PD1 is electrically connected to the source region of the transfer transistor TR1, and the anode side is electrically connected to a reference potential line (e.g., ground). The cathode side of the photoelectric conversion element PD2 is electrically connected to the source region of the transfer transistor TR2, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, photodiodes are used as the photoelectric conversion elements PD1 and PD2.

[0029] Of the two transfer transistors TR1 and TR2, the drain region of the transfer transistor TR1 is electrically connected to the charge storage region FD1. The gate electrode of the transfer transistor TR1 is electrically connected to a transfer transistor drive line of the pixel drive lines 10 (see FIG. 2). The drain region of the transfer transistor TR2 is electrically connected to the charge storage region FD2. The gate electrode of the transfer transistor TR2 is electrically connected to a transfer transistor drive line of the pixel drive lines 10.

[0030] Of the two charge storage regions FD1 and FD2, the charge storage region FD1 temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD1 via the transfer transistor TR1, while the charge storage region FD2 temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD2 via the transfer transistor TR2.

[0031] The readout circuit 15 reads out the signal charges accumulated in the charge accumulation regions FD1 and FD2 and outputs a pixel signal based on the signal charges. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are made of, for example, a silicon oxide film (SiO ２ These transistors are configured as MOSFETs having a gate insulating film made of a silicon nitride film (Si film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. ３ N ４ Alternatively, a metal insulator semiconductor FET (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0032] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage regions FD1 and FD2 and the source region of the reset transistor RST.

[0033] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0034] The reset transistor RST has a source region electrically connected to the charge storage regions FD1 and FD2 and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0035] An electronic device equipped with the photodetector 1 performs autofocusing based on the phase difference between the signal charges accumulated in the two photoelectric conversion elements PD1 and PD2. When the device is out of focus, a phase difference occurs between the amount Q1 of signal charges accumulated in the photoelectric conversion element PD1 and the amount Q2 of signal charges accumulated in the photoelectric conversion element PD2. The electronic device adjusts the focus by operating the objective lens or the like to reduce the phase difference.

[0036] After the focus adjustment is completed, the electronic device generates an image based on the sum of the signal charge Q1 accumulated in the photoelectric conversion element PD1 and the signal charge Q2 accumulated in the photoelectric conversion element PD2, that is, the sum of the signal charge Q3 (Q3 = Q1 + Q2). In other words, the sum of the signal charge Q3 corresponds to the pixel signal.

[0037] <<Overview>> First, an overview of the present technology will be described below using Comparative Example 1 shown in Fig. 4A and Comparative Example 2 shown in Fig. 4B to Fig. 4D. First, Comparative Example 1 shown in Fig. 4A will be described.

[0038] Comparative Example 1 In a portion of the semiconductor layer 20 corresponding to the pixel region 2A, an island-shaped cell region 20a partitioned by an isolation region 20b is provided for each pixel 3. A well region 21A, which is a p-type semiconductor region, is provided in the cell region 20a. The well region 21A has a contact region 21A1, and a reference potential is supplied to the well region 21A via the contact region 21A1. An inter-pixel isolation structure 40A, which mainly partitions the pixels 3, is provided in the isolation region 20b. The inter-pixel isolation structure 40A does not reach the first surface S1 and does not completely separate the pixels. Therefore, the well region 21A can extend across multiple pixels 3, and the contact region 21A1 for supplying a reference potential to the well region 21A can also be shared by multiple pixels 3. The contact region 21A1 is formed by partitioning the region of the cell region 20a on the first surface S1 side with an isolation structure 50A.

[0039] Comparative Example 2 Next, Comparative Example 2 shown in FIGS. 4B to 4D will be described. As shown in FIG. 4B , the photodetector 1B has an inter-pixel isolation structure 40 extending from the second surface S2 to the first surface S1 of the semiconductor layer 20. In recent years, in order to improve the optical and electrical characteristics of photodetector devices, an inter-pixel isolation structure 40 having a full trench isolation (FTI) structure that completely isolates the cell regions 20 a from one another has been used. When such an inter-pixel isolation structure 40 is provided, the pixels 3 are completely isolated from one another, and the well region 21 cannot extend across multiple pixels 3, but is isolated from each other by the inter-pixel isolation structure 40. Furthermore, the contact region 22 of the well region 21 also needs to be provided for each pixel 3.

[0040] FIG. 4C shows an example of the configuration of the well region 21 and the contact region 22. The contact region 22 is a partial region of the semiconductor layer 20 and is made of single-crystal silicon in this embodiment. An isolation structure 50B is provided around the contact region 22. The isolation structure 50B is formed by forming a groove in the semiconductor layer 20 using known lithography and etching techniques and filling the formed groove with an insulating material. By providing the isolation structure 50B around the contact region 22, the contact region 22 is separated from other semiconductor regions. To provide the contact region 22, a dimension d must be secured, which is the sum of twice the width of the isolation structure 50B and the dimension between the isolation structures 50B (the width of the contact region 22). This dimension d must be secured for each pixel 3. Therefore, the contact region 22 may restrict the space for providing other elements, such as the transistor T, within the pixel 3. In Comparative Example 2 shown in FIG. 4D, the isolation structure 50B is provided so that the contact region 22 remains as an active region. If the dimension d is ensured, the space for providing the transistor T will be constricted, and it may become difficult to provide the transistor T with a large dimension.

[0041] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 according to the first embodiment of the present technology will be described. The longitudinal cross-sectional configuration of the pixel 3 included in the photodetector 1 will be described with reference to FIG. 4B according to the above-described comparative example 2. While the pixel 3 according to this embodiment is a phase difference detection pixel, the pixel 3 according to comparative example 2 is a normal pixel. Furthermore, the photodetector 1 according to this embodiment differs from comparative example 2 in that it has a conductor 60 instead of the contact region 22. Thus, although there are differences between the two, there are also commonalities. Therefore, the commonalities will be described with reference to FIG. 4B. In this case, the photodetector 1B in FIG. 4B will be read as the photodetector 1.

[0042] 4B , the photodetector 1 includes, for example, a semiconductor layer 20 having a first surface S1 and a second surface S2, and a wiring layer 30 stacked on the second surface S2. Note that the first surface S1 may be referred to as an element formation surface or a main surface, and the second surface S2 may be referred to as a light incident surface or a back surface. The photodetector 1 may also include, for example, a color filter CF and a microlens LN on the second surface S2 side of the semiconductor layer 20.

[0043] The semiconductor layer 20 is made of a semiconductor substrate. The semiconductor layer 20 is made of, for example, a single-crystal silicon substrate, but is not limited thereto. The semiconductor layer 20 includes a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type. In this embodiment, a case will be described in which the first conductivity type is n-type and the second conductivity type is p-type. In the following description, a semiconductor region described as n-type corresponds to a semiconductor region of the first conductivity type, and a semiconductor region described as p-type corresponds to a semiconductor region of the second conductivity type. However, the present technology is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0044] In the portion of the semiconductor layer 20 corresponding to the pixel region 2A, a plurality of island-shaped cell regions 20a partitioned by isolation regions 20b are provided in a matrix. For example, one cell region 20a is provided for each pixel 3. In the isolation region 20b, an inter-pixel isolation structure 40 is provided to separate the cell regions 20a from each other. The inter-pixel isolation structure 40 is a separation wall that extends in the thickness direction of the semiconductor layer 20 from the second surface S2 to the first surface S1 and penetrates the semiconductor layer 20 in the thickness direction. The inter-pixel isolation structure 40 has a configuration in which an isolation material is buried in a groove provided in the semiconductor layer 20, for example. The isolation material may be, for example, silicon oxide (SiO ２ Examples of the isolation material include insulating materials such as silicon dioxide, silicon dioxide, and silicon dioxide. Examples of the isolation material include conductive materials such as polysilicon and metal. When the isolation material is made of a conductive material, the inner wall of the trench is first covered with an insulating film and then the conductive material is filled in.

[0045] FIG. 4B shows an example in which the pixel isolation structure 40 is composed of multiple portions. The pixel isolation structure 40 includes a first portion 41 that mainly separates the photoelectric conversion elements PD and is located on the second surface S2 side, and a second portion 42 that is connected to the first portion 41 along the thickness direction and is located on the first surface S1 side. The dimension of the second portion 42 along the Z direction is smaller than the dimension of the first portion 41 along the Z direction. For example, the second portion 42 is shallow trench isolation (STI), and the first portion 41 is deep trench isolation (DTI). The second portion 42 is made of an insulating material such as silicon oxide. Note that the present technology is not limited to the pixel isolation structure 40 shown in FIG. 4B , and the pixel isolation structure 40 may include only the first portion 41. In this case, the first portion 41 extends from the second surface S2 to the first surface S1.

[0046] The wiring layer 30 is a multi-layer wiring layer. The wiring layer 30 includes, but is not limited to, an insulating film 31 including a layer made of a known insulating material, and wiring such as horizontal wiring and vertical wiring provided within the insulating film 31. FIG. 4B shows a via 32, which is an example of vertical wiring. The via 32 is made of a metal such as tungsten (W). Furthermore, a gate electrode G of a transistor is provided in the wiring layer 30.

[0047] The microlens LN is an on-chip lens that focuses incident light onto the semiconductor layer 20. The color filter CF separates the incident light into colors after passing through the microlens LN. The color filter CF and the microlens LN are provided, for example, for each pixel 3. The color filter CF and the microlens LN are made of, for example, a resin material.

[0048] Next, the photodetector 1 according to this embodiment will be further described with reference to FIGS. 5A to 5C . In this embodiment, as an example, a case where the present technology is applied to a dual-PD phase difference detection pixel will be described. As shown in FIG. 5C , pixel 3 is a dual-PD pixel in which, for example, a pair of left and right photoelectric conversion elements PD1 and PD2 are configured within one pixel 3. A single microlens LN overlapping both the photoelectric conversion elements PD1 and PD2 is provided for pixel 3. Pixel 3 is a split-pupil pixel in which a light beam passing through a common microlens LN (the same single microlens LN) is split and incident on the photoelectric conversion element PD1 and the photoelectric conversion element PD2. The photoelectric conversion element PD1 includes a photoelectric conversion region 23a, which is an n-type semiconductor region, and the photoelectric conversion element PD2 includes a photoelectric conversion region 23b, which is an n-type semiconductor region. The photoelectric conversion regions 23a and 23b photoelectrically convert incident light. When the photoelectric conversion regions 23a and 23b are not distinguished from each other, they are simply referred to as the photoelectric conversion regions 23.

[0049] As shown in FIG. 5B , a well region 21, which is a p-type semiconductor region, is provided in the cell region 20a of the pixel 3. The well region 21 is a semiconductor region containing a known impurity (dopant) that makes the semiconductor p-type. Since the pixels 3 are separated from each other by an inter-pixel isolation structure 40, the well region 21 cannot extend across multiple pixels 3 and is provided for each pixel 3. A conductor 60 is connected to the first surface S1 side of the well region 21, and a reference potential is supplied to the well region 21 via the conductor 60. The conductor 60 is provided in a through-hole 51 that penetrates the element isolation structure 50. The element isolation structure 50 and the conductor 60 will be described below.

[0050] <Element Isolation Structure> An element isolation structure 50 is provided on the first surface S1 side of the cell region 20a. The element isolation structure 50 is a shallow trench isolation (STI) structure in which a trench 52 is formed in the cell region 20a from the first surface S1 side and an insulating material such as silicon oxide is filled in the formed trench 52. The second portion 42 of the inter-pixel isolation structure 40 is also formed in the same manner as the element isolation structure 50. The element isolation structure 50 and the second portion 42 may be integrally configured in a plan view as shown in FIG. 5A . As shown in FIGS. 5A and 5B , the element isolation structure 50 divides the first surface S1 side of the cell region 20a into multiple semiconductor regions. The semiconductor regions divided by the element isolation structure 50 are called active regions 24. For example, elements such as transistors and charge accumulation regions FD, which are n-type semiconductor regions, are formed in the active region 24. As shown in FIG. 5A , the active region 24 is surrounded by the element isolation structure 50 and the second portion 42. The region between the active regions 24 may be called a field region. As shown in Fig. 5B, the bottom surface 53 of the element isolation structure 50 is in contact with the well region 21. The well region 21 is provided at a position closer to the second surface S2 than the active region 24, and at a position closer to the first surface S1 than the photoelectric conversion region 23. In other words, the well region 21 is provided at a depth position between the photoelectric conversion region 23 and the active region 24 in the thickness direction of the semiconductor layer 20.

[0051] For example, in the example shown in FIG. 5A , four active regions 24 and four transistors, T1, T2, T3, and T4, are configured in the cell region 20a. One transistor is formed in each active region 24. The source region, drain region, channel formation region, etc. of the transistor are formed in the active region. Transistor T1 is a transfer transistor TR1, and transistor T2 is a transfer transistor TR2. Transistors T3 and T4 are pixel transistors other than transfer transistors, such as an amplifier transistor AMP, a select transistor SEL, or a reset transistor RST. An element isolation structure 50 electrically isolates the above-mentioned transistors from each other. The larger the area of ​​the active region 24, the larger the channel length and channel width of the transistor can be.

[0052] <Conductor> The conductor 60 functions as a contact for supplying a reference potential to the semiconductor layer 20. More specifically, the conductor 60 functions as a contact for supplying a reference potential to a semiconductor portion in the cell region 20a. As shown in FIG. 5B , a through-hole 51 is provided in the element isolation structure 50 in a thickness direction in a portion that overlaps with the well region 21 in a plan view. The conductor 60 is provided to fill the through-hole 51. A first end 61, which is the end of the conductor 60 on the second surface S2 side, is exposed from a bottom surface 53 of the element isolation structure 50 and is connected to the cell region 20a of the semiconductor layer 20, more specifically, to the well region 21. An end surface 62 of the first end 61 is located at a depth approximately the same as the bottom surface 53 of the element isolation structure 50 and is in contact with the well region 21. An end of the conductor 60 on the wiring layer 30 side is connected to a via 32, and a reference potential is supplied to the conductor 60 as a base voltage via the via 32. The via 32 connected to the end face of the conductor 60 on the first surface S1 side may be referred to as a contact plug. Although this modification describes a case where the transistor is an NMOS, a PMOS transistor may also be used as long as an appropriate reference potential is supplied to the conductor 60 via the via 32. As shown in FIGS. 5A and 5B , the conductor 60 is isolated from the active region 24 by an element isolation structure 50. More specifically, the side surface of the conductor 60 is surrounded by the element isolation structure 50, isolating it from the active region 24. The material constituting the conductor 60 is, for example, polysilicon containing a known impurity (dopant) that makes the semiconductor p-type. The position and number of the conductors 60 are not limited to those shown in FIG. 5A .

[0053] <<Method of Manufacturing Photodetector>> A method of manufacturing the photodetector 1 will be described below. In this embodiment, only the steps related to the element isolation structure 50 and the conductor 60 will be described, and other steps will be described. First, as shown in FIG. 6A , a trench 52 for embedding the element isolation structure 50 is formed in the semiconductor layer 20 from the first surface S1 side using known lithography and etching techniques. Then, an insulating film such as silicon oxide is formed to fill the trench 52, and excess portions are removed. This results in the element isolation structure 50. Thereafter, a well region 21 is formed by ion implantation of a known impurity that makes the semiconductor p-type. Note that the element isolation structure 50 may be formed after ion implantation of the impurity.

[0054] Next, as shown in FIG. 6B , a resist pattern R1 having an opening R1a is formed using known lithography techniques. The opening R1a is provided at a position in the element isolation structure 50 where the conductor 60 is to be provided. Then, a portion of the element isolation structure 50 that overlaps with the opening R1a in a plan view is etched to form a through-hole 51 that penetrates the element isolation structure 50. This forms a region in the element isolation structure 50 for filling with polysilicon. Next, as shown in FIG. 6C , a polysilicon film m1 is formed as a material that constitutes the conductor 60, and the through-hole 51 is filled.

[0055] Next, as shown in FIG. 6D, excess portions of the polysilicon film m1 are removed, and the exposed surface is planarized. Thereafter, as shown in FIG. 6E, a resist pattern R2 having openings R2a is formed on the exposed surface using known lithography techniques. The openings R2a are provided at positions that overlap the polysilicon film embedded in the through holes 51 in a plan view, and impurity ions are implanted through the openings R2a to convert the polysilicon into a conductor. Thus, the conductor 60 is obtained.

[0056] Main Effects of the First Embodiment The main effects of the first embodiment are described below. In the photodetector 1 according to the first embodiment of the present technology, the conductor 60 is provided in the through-hole 51 that penetrates the element isolation structure 50 in the thickness direction, allowing the conductor 60 to be provided in a space-saving manner. Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the conductor 60 is used as a well contact to supply a reference potential to the semiconductor portion in the cell region 20a. This prevents the area required for providing the well contact from increasing, allowing the reference potential to be supplied to the semiconductor portion in the cell region 20a in a space-saving manner. This prevents the area occupied by other elements, such as transistors, from being compressed by the conductor 60 and from becoming too small. This is expected to improve characteristics such as the roll-off characteristics and random noise of the transistor.

[0057] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, rather than forming the element isolation structure 50 so as to leave a contact region of the well region 21, a through hole 51 is formed in the element isolation structure 50 and a conductor 60 is embedded in the through hole 51. Therefore, it is not necessary to leave a semiconductor layer as a contact region when forming the element isolation structure 50. This makes it possible to form the conductor 60 without considering the minimum dimension of the trench 52 in which the element isolation structure 50 is provided, and thus it is possible to form the conductor 60 in a space-saving manner.

[0058] In Patent Document 1, a substrate contact electrode is provided on the top surface of the FDTI that separates pixels, and the substrate contact electrode is shared between adjacent pixels. However, in Patent Document 1, the substrate contact electrode and the active region are in contact with each other, so when heat treatment is performed, impurities in the substrate contact electrode may diffuse into the active region and interfere with the impurities in the active region. It is thought that the electric field may become large in the proximity of the substrate contact electrode and the active region, which may increase dark current.

[0059] In contrast, in the photodetector 1 according to the first embodiment of the present technology, the side surfaces of the conductor 60 made of p-type polysilicon are surrounded by the element isolation structure 50, and therefore the conductor 60 is isolated from the active region 24. This makes it possible to prevent p-type impurities in the conductor 60 from diffusing into the active region 24, and to prevent the dark current from increasing.

[0060] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the conductor 60 is made of p-type polysilicon, not a metal material. While a metal material may spread to the semiconductor layer 20 as contamination, the polysilicon conductor 60, unlike a metal material, is less likely to cause contamination.

[0061] <Modification of First Embodiment> Modifications of the first embodiment will be described below.

[0062] <Variation 1> In the photodetector 1 according to Variation 1 of the first embodiment, as shown in FIG. 7 , the first end 61 of the conductor 60 protrudes from the bottom surface 53 of the element isolation structure 50, and the end surface 62 and the side surface 63 of the first end 61 contact the well region 21.

[0063] The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0064] Furthermore, in the photodetector 1 according to the first modification of the first embodiment, the side surface 63 as well as the end surface 62 contacts the well region 21, so that the contact area between the conductor 60 and the well region 21 increases, and the contact resistance between the conductor 60 and the well region 21 can be reduced.

[0065] <Modification 2> In a photodetector 1 according to Modification 2 of the first embodiment, as shown in FIG. 8 , a conductor 60 and a via (contact plug) 32 connected to the conductor 60 are provided at positions overlapping between sidewalls W provided on the gate electrodes G in a plan view. Sidewalls W are provided at the edges of the gate electrodes G of the transistors T3 and T4. The gate electrodes G of the transistors T3 and T4 are adjacent to each other, and sidewalls W are provided on the adjacent portions. In a plan view, the conductor 60 is provided at a position overlapping between the adjacent sidewalls W, and a via 32 that supplies a reference potential to the conductor 60 is connected to the end face of the conductor 60 on the first surface S1 side. That is, the via 32, which is a contact plug, is also provided at a position overlapping between the adjacent sidewalls W in a plan view. In this modification, the via 32 is formed by utilizing the recess between the sidewalls W as a self-alignment.

[0066] The photodetector 1 according to the second modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0067] Furthermore, in the photodetector 1 according to the second modification of the first embodiment, the recess between the sidewalls W of the gate electrodes G is used for self-alignment, so that it is possible to prevent the overlay misalignment between the via 32 and the conductor 60 from becoming large when the via 32 is formed. This allows the width (diameter) of the conductor 60 to be made narrower than in the first embodiment, thereby further saving space. Furthermore, if the width of the element isolation structure 50 in the portion where the conductor 60 is provided is the same as in the first embodiment, making the conductor 60 narrower relatively widens the width of the element isolation structure 50, thereby improving the breakdown voltage performance.

[0068] 9 , in the photodetector 1 according to the third modification of the first embodiment, a pad 64 is provided between the end face of the conductor 60 on the first surface S1 side and the via 32, which is a contact plug. In plan view, the area of ​​the pad 64 is larger than the area of ​​the end face of the conductor 60 on the first surface S1 side. The pad 64 is made of, for example, the same material as the conductor 60.

[0069] The photodetector 1 according to the third modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0070] Furthermore, in the photodetector 1 according to the third modification of the first embodiment, by providing the pad 64, it is possible to reduce the width of the conductor 60 while ensuring an overlap margin between the via 32, which is a contact plug, and the conductor 60.

[0071] Second Embodiment A photodetector 1 according to a second embodiment of the present technology, as shown in FIGS. 10 to 14 , will be described below. First, an overview will be provided. Overview: In order to improve the low-illumination characteristics of solid-state imaging devices, studies have been conducted to suppress dark currents generated by crystal defects in silicon around element isolations that separate transfer gates and pixel transistors. Patent Document 2 suppresses the generation of dark currents by forming p+-type impurity regions not only on the surface of the pixel but also on the bottom and sidewalls of the STI region. However, even a small amount of dark current may flow into the photodiode, affecting noise characteristics and making it difficult to improve the low-illumination characteristics of the photodetector.

[0072] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 according to the second embodiment of the present technology will be described. Note that components similar to those of the photodetector 1 according to the first embodiment described above will be assigned the same reference numerals and descriptions thereof will be omitted.

[0073] As in the first embodiment, a plurality of island-shaped cell regions 20a separated by isolation regions 20b are provided in a matrix pattern in the portion corresponding to the pixel region 2A of the semiconductor layer 20. As shown in Fig. 10 , in this embodiment, the isolation region 20b is provided with a first portion 41 as an inter-pixel separation structure that mainly separates the pixels 3 from each other.

[0074] The photodetector 1 has a plurality of active regions 24 partitioned by an element isolation structure 50. To distinguish the plurality of active regions 24 from one another, they are referred to as a plurality of active regions 24a, 24b, and 24c, respectively. When the active regions 24a, 24b, and 24c are not distinguished from one another, they are simply referred to as the active region 24. The active region 24a includes transistors T3 and T4, which are pixel transistors, and a well contact 25, which is a p-type semiconductor region, provided between the transistors T3 and T4. The pair of main electrode regions of the transistors T3 and T4 are n+-type semiconductor regions. The diffusion region 26 provided in the active region 24a is a semiconductor region that constitutes one of the pair of main electrode regions of the transistor T3, and the diffusion region 27 is a semiconductor region that constitutes one of the pair of main electrode regions of the transistor T4. The diffusion regions 26 and 27 are positioned to overlap the first impurity region 28 in a plan view. The active region 24b is provided with a transistor T1, which is a transfer transistor, and a charge storage region FD, and the active region 24c is provided with a transistor T2, which is a transfer transistor, and a charge storage region FD. The photodetector 1 also has a plug 33 electrically connected to the charge storage region FD. The plug 33 is made of, for example, polysilicon.

[0075] Furthermore, a first impurity region 28, which is a p-type semiconductor region, is provided across the entire cell region 20a of the pixel 3 in a planar view. All of the transistors T1, T2, T3, and T4 are provided in positions overlapping the first impurity region 28 in a planar view. The first impurity region 28 will be described in more detail with reference to FIGS. 11 to 13. FIG. 11 is a longitudinal cross-sectional view showing the cross-sectional configuration when viewed along the A-A' section line in FIG. 10. The first impurity region 28 is a semiconductor region containing a known impurity (dopant) that makes the semiconductor p-type. In this embodiment, the bottom surface 53 of the element isolation structure 50 is in contact with the first impurity region 28. The first impurity region 28 is provided closer to the light incident surface (second surface S2) than the active region 24 and closer to the element formation surface (first surface S1) than the photoelectric conversion region 23. That is, the first impurity region 28 is provided at a depth position between the photoelectric conversion region 23 and the active region 24 in the thickness direction of the semiconductor layer 20 .

[0076] FIG. 12 shows the distribution of impurities (impurities that make the semiconductor p-type) along line B-B' in FIG. 11. The vertical axis represents silicon depth, and the horizontal axis represents impurity concentration. The description assumes that the depth increases from the device formation surface (first surface S1) toward the light incident surface. The dashed-dotted line in FIG. 12 indicates the depth position of the bottom surface 53 of the device isolation structure 50. The impurity concentration has two peaks, peak P1 and peak P2, along the depth direction. Peak P1 is a peak formed by the well contact 25, and peak P2 is a peak formed by the first impurity region 28. Peak P2 is located in the region of the first impurity region 28 where the impurity concentration is highest along the depth direction. The impurity concentration gradually decreases from peak P2 toward the shallower side (toward the device formation surface), forming a valley at the depth position between the first impurity region 28 and the well contact 25. 12 , the impurity concentration has a gradient that gradually increases (gets higher) from the depth of the valley and the depth of the bottom surface 53 toward the deeper side, more specifically, toward the photoelectric conversion region 23. The depth of the peak P2 is shallower than the photoelectric conversion region 23. The peak P2 is also deeper than the bottom surface 53 of the element isolation structure 50. That is, the first impurity region 28 has an impurity concentration at a position deeper than the bottom surface 53 that is higher than the impurity concentration at the depth of the bottom surface 53.

[0077] The impurity concentration at peak P2 may be about 8 times or more, more specifically about 10 times or more, the impurity concentration at the valley. The impurity concentration at peak P2 may be about 8 times or more, more specifically about 10 times or more, the impurity concentration at the depth position of bottom surface 53.

[0078] FIG. 13 shows the potential distribution along line B-B' in FIG. 11. The magnitude of the potential is determined by the impurity concentration in FIG. 12, and therefore behaves similarly to the impurity concentration. As shown by the arrows in FIG. 13, the magnitude of the potential has a gradient that gradually increases from the valley depth position and the depth position of the bottom surface 53 toward the photoelectric conversion region 23, more specifically, toward the photoelectric conversion region 23. Because of this gradient, charges (electrons) generated as noise are less likely to exceed peak P2 and flow deeper than peak P2 in the semiconductor layer 20. The impurity concentration of the first impurity region 28 increases in the direction from the depth position of the bottom surface 53 toward the photoelectric conversion region 23, forming a potential barrier between the bottom surface 53 and the photoelectric conversion region 23, making it difficult for dark current generated from the semiconductor surrounding the element isolation structure 50 to flow toward the photoelectric conversion region 23. As shown in FIG. 11, the dark current moves along at least one of the bottom surface 53 and side surfaces of the element isolation structure 50 and flows toward the diffusion region 26.

[0079] The transistors T3 and T4 are pixel transistors, and are, for example, any one of an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switch transistor SW. The switch transistor SW will be described below with reference to FIG. 14. Note that FIG. 14 shows an equivalent circuit of a normal pixel, not an equivalent circuit of a phase difference pixel. The switch transistor SW is a conversion efficiency switching transistor. The charge accumulation region FD and the reset transistor RST are connected via the switch transistor SW. That is, one of the source and drain of the switch transistor SW is connected to the charge accumulation region FD, and the other is connected to one of the source and drain of the reset transistor RST. The other of the source and drain of the reset transistor RST is connected to the power supply line Vdd.

[0080] By using a pixel with this configuration, when the gate of the switch transistor SW is turned off, the charge storage region FD is separated from the source / drain of the reset transistor RST, resulting in a small capacitance. Because the charge storage region FD has a small capacitance, the potential drops significantly with a small number of electrons, resulting in a highly sensitive signal. However, when there is a large amount of signal charge, the charge overflows from the charge storage region FD, making it difficult to obtain the original signal corresponding to the amount of incident charge. When the gate of the switch transistor SW is turned on, the charge storage region FD is connected to the source / drain of the reset transistor RST, resulting in a large capacitance. Because the capacitance is large, the pixel can receive more electrons, but its sensitivity is lowered. In this way, by switching the gate of the switch transistor SW, an image in which charges are read out in a high-sensitivity operating mode and an image in which charges are read out in a low-sensitivity operating mode are combined, thereby expanding the dynamic range.

[0081] <<Method of Manufacturing Photodetector>> A method of manufacturing the photodetector 1 will be described below. In this embodiment, only the steps related to the element isolation structure 50 and the first impurity region 28 will be described, and other steps will be described. First, as shown in FIG. 15A , a photoelectric conversion region 23 is formed in a desired region in the semiconductor layer 20 using ion implantation. Next, using known lithography and dry etching techniques, the semiconductor layer 20 is etched from the first surface S1 side, and an insulating material is embedded to form the element isolation structure 50. This defines the active region 24.

[0082] 15B, a resist pattern having openings in desired regions is formed using known lithography techniques. Then, an impurity that converts the semiconductor to p-type is ion-implanted to form first impurity region 28 such that the impurity concentration has a gradient that gradually increases in the depth direction from bottom surface 53 of element isolation structure 50.

[0083] 15C, a resist pattern is formed using known lithography techniques, and impurities are ion-implanted into desired regions. More specifically, well contacts 25 and the like are formed by ion-implanting impurities that make the semiconductor p-type, and diffusion regions 26 and the like are formed by ion-implanting impurities that make the semiconductor n-type.

[0084] Main Effects of the Second Embodiment The main effects of the second embodiment are described below. In the photodetector 1 according to the second embodiment of the present technology, the cell region includes a first impurity region 28, which is a p-type semiconductor region, at a depth position between the photoelectric conversion region 23 and the active region 24. The first impurity region 28 contains an impurity that imparts a second conductivity type to the semiconductor. The impurity concentration in the first impurity region 28 has a gradient that gradually increases from the depth position of the bottom surface 53 of the element isolation structure 50 toward the depth. Therefore, the magnitude of the potential also has a gradient that gradually increases from the depth position of the bottom surface 53 toward the depth, more specifically, toward the photoelectric conversion region 23. Due to this gradient, charge (electrons) generated as noise are less likely to flow toward the depth. This makes it less likely for dark current to flow into the photoelectric conversion region 23, thereby suppressing deterioration of noise characteristics.

[0085] Furthermore, in the photodetector 1 according to the second embodiment of the present technology, the region of the first impurity region 28 where the impurity concentration is highest in the depth direction is located at a position deeper than the depth position of the bottom surface 53. This forms a potential barrier between the bottom surface 53 and the photoelectric conversion region 23, making it difficult for dark current generated from the semiconductor around the element isolation structure 50 to flow into the photoelectric conversion region 23.

[0086] <Modification of Second Embodiment> A modification of the second embodiment will now be described.

[0087] 16 , in the photodetector 1 according to the first modification of the second embodiment, the diffusion region 26 is the drain region of the transistor T3, and the diffusion region 27 is the drain region of the transistor T4. Each of the diffusion regions 26 and 27 is electrically connected to the power supply line Vdd through a via 32. Dark current flowing through the diffusion regions 26 and 27 is discharged to the power supply line Vdd. The transistors T3 and T4 are, for example, reset transistors, of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the switch transistor SW, whose drain regions are connected to the power supply line Vdd.

[0088] The photodetector 1 according to the first modified example of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0089] Furthermore, in the photodetector 1 according to the first modification of the second embodiment, when dark current flows into the drain region electrically connected to the power supply line Vdd, the dark current is discharged toward the power supply line Vdd. This makes it possible to suppress the effect of the generated dark current on the characteristics of the pixel transistor. Note that, although the present embodiment has been described with reference to an NMOS pixel transistor, if the pixel transistor is a PMOS, it is sufficient that the dark current is discharged from an appropriate one of the pair of main electrode regions toward an appropriate potential line.

[0090] <Modification 2> In the photodetector 1 according to Modification 2 of the second embodiment, as shown in FIG. 17, the first impurity region 28 is located so as not to overlap with the channel formation regions of the transistors T1 and T2, which are transfer transistors, in a plan view.

[0091] Transfer transistors and charge storage regions FD are provided in active regions 24b and 24c of the multiple active regions 24. In this modification, the first impurity regions 28 are not provided at positions overlapping with the transistors T1 and T2 and the charge storage regions FD. The transistors T3 and T4 are provided at positions overlapping with the first impurity regions 28 in plan view.

[0092] The photodetector 1 according to the second modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0093] Furthermore, in the photodetector 1 according to the modified example of the second embodiment, the transfer path can be easily secured by excluding the first impurity region 28 from the path for transferring the signal charge generated in the photoelectric conversion region 23 to the charge accumulation region FD.

[0094] 18 , the photodetector 1 according to the third modification of the second embodiment has second impurity regions 29, which are semiconductor regions of the second conductivity type, along the side surfaces 54 and the bottom surface 53 of the element isolation structure 50. By providing the second impurity regions 29, it is possible to suppress the generation of dark current from the semiconductor regions around the element isolation structure 50.

[0095] The impurity concentration in the second impurity region 29 is set lower than the impurity concentration in the first impurity region 28. In FIG. 19 , the dashed line AA indicates the impurity distribution in the second embodiment, and the solid line BB indicates the impurity distribution in this modification. As shown in the figure, the solid line BB, which includes the second impurity region 29, has a shallower valley in the impurity distribution than the dashed line AA, and the gradient of the impurity concentration from the depth position of the valley and the depth position of the bottom surface 53 toward the photoelectric conversion region 23 is gentler. Therefore, in order to suppress the flow of dark current into the photoelectric conversion region 23, it is desirable to keep the impurity concentration in the second impurity region 29 as low as possible.

[0096] The photodetector 1 according to the third modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0097] Furthermore, in the photodetector 1 according to the third modification of the second embodiment, the second impurity region 29 is provided, thereby making it possible to suppress the generation of dark current from the semiconductor region around the element isolation structure 50 .

[0098] 20, in the photodetector 1 according to the fourth modification of the second embodiment, the first impurity region 28 functions as a well region of the transistors T3 and T4, which are pixel transistors. The symbol CH denotes a channel formation region of the transistors T3 and T4.

[0099] The photodetector 1 according to the fourth modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0100] Furthermore, in the photodetector 1 according to the fourth modification of the second embodiment, the first impurity region 28 is used as a well region of the pixel transistor, thereby reducing the number of manufacturing steps.

[0101] [Third Embodiment] <1. Application Example to Electronic Device> Next, an electronic device 100 according to a third embodiment of the present technology shown in Fig. 21 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector device 1 as the solid-state imaging device 101.

[0102] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0103] With this configuration, the electronic device 100 can prevent the performance of the solid-state imaging device 101 from deteriorating, thereby improving the image quality of the video signal.

[0104] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0105] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 relating to any of the first embodiment to the second embodiment and modified versions of those embodiments, or a photodetector 1 relating to a combination of at least two of the first embodiment to the second embodiment and modified versions of those embodiments.

[0106] Fourth Embodiment A photodetector 1 according to a fourth embodiment of the present technology will be described below with reference to Fig. 22 to Fig. 24. First, an overview will be described.

[0107] <<Summary>> In some cases, pixel transistors and charge accumulation regions are formed side by side in one pixel (see, for example, Patent Document 3). In such pixels, STI is used to separate, for example, the space between the pixel transistor and the charge accumulation region, or between pixel transistors. However, when an active region in which a pixel transistor is provided is adjacent to an active region in which a charge accumulation region is provided, the potential of the source region / drain region (n+ region) of the pixel transistor causes a breakdown of the STI interface (Si / SiO ２ Depletion of the surface (interface) can cause dark current to be generated, resulting in white spots.

[0108] The element isolation region described in Patent Document 4 has an STI (Shallow Trench Isolation) structure. The element isolation region described in Patent Document 4 includes a conductive film provided in a trench with a first insulating film interposed therebetween, and a second insulating film provided on the first surface side of the semiconductor layer so as to overlap the conductive film in a planar view. The conductive film 68 is provided over the entire element isolation region 65 in a planar view, although this is not limited thereto, and is provided with a contact portion for applying a reference potential to the conductive film 68. However, with the recent trend toward miniaturization, restrictions on wiring design rules have become stricter, making it difficult to provide a contact portion for applying a reference potential to the conductive film 68.

[0109] <Specific Configuration of Photodetector> Next, a specific configuration of the photodetector 1 according to the fourth embodiment of the present technology will be described. Note that components similar to those of the photodetector 1 according to the first embodiment described above are denoted by the same reference numerals, and their description will be omitted. As shown in FIG. 23 , an element isolation structure 50 is provided on the first surface S1 side of the cell region 20 a. The element isolation structure 50 is shallow trench isolation (STI) formed by forming a trench in the cell region 20 a from the first surface S1 side and filling the trench with an insulating material such as silicon oxide. As shown in FIG. 22 , the semiconductor region partitioned by at least one of the element isolation structure 50 and the second portion 42 of the inter-pixel isolation structure 40 is the active region 24. The element isolation structure 50 and the second portion 42 may be configured as a continuous, integrated structure. Both the element isolation structure 50 and the second portion 42 are STI, and the second portion 42 can be used to partition the active region 24 in addition to partitioning pixels. The element isolation structure 50 and the second portion 42 may be combined to form the element isolation structure (42, 50).

[0110] In the example shown in FIG. 22 , four active regions 24 are provided in the cell region 20a, which is the semiconductor region of the pixel 3. Note that the number of active regions is not limited to that shown in FIG. 22 . To distinguish the four active regions from one another, they are referred to as active regions 24d, 24e, 24f, and 24g. When the four active regions are not distinguished from one another, they are simply referred to as active regions 24. A transistor T1 and a charge storage region FD1 are provided in the active region 24d. A transistor T2 and a charge storage region FD2 are provided in the active region 24e. A transistor T3 is provided in the active region 24f. A transistor T4 is provided in the active region 24g. When the charge storage regions FD1 and FD2 are not distinguished from one another, they are simply referred to as charge storage regions FD. The transistors T3 and T4 are pixel transistors, and the active regions 24f and 24g in which the pixel transistors are provided correspond to first active regions. The active regions 24d and 24e in which the charge storage regions FD1 and FD2 are provided correspond to second active regions.

[0111] As shown in FIGS. 22 and 24 , the photodetector 1 according to this embodiment includes the conductor 60 described in the first embodiment of the present technology. As shown in FIG. 24 , a first end 61, which is an end of the conductor 60 on the second surface S2 side, is connected to the well region 21. More specifically, the first end 61 is connected to a contact portion 21B, which is a p+-type semiconductor region with a higher impurity concentration than the well region 21. An end of the conductor 60 on the first surface S1 side is exposed on the upper surface of the element isolation structure 50, and a via 32 that supplies a reference potential is directly connected to the end. The via 32 that supplies the reference potential to the conductor 60 may be referred to as a via 32a to distinguish it from other vias 32. The reference potential is supplied to the contact portion 21B of the well region 21 via the via 32a and the conductor 60.

[0112] As shown in FIG. 22 , the photodetector 1 according to this embodiment includes a shield wall 70 embedded in the element isolation structure 50 and connected to the conductor 60. The shield wall 70 may be made of, for example, conductive polysilicon, and may be formed integrally with the conductor 60 using the same material as the conductor 60 (e.g., p-type polysilicon). The shield wall 70 is supplied with a reference potential, just like the conductor 60. That is, the shield wall 70 is a conductor connected to the reference potential. For example, the shield wall 70 is fixed to the reference potential. As shown in FIG. 23 , the shield wall 70 is embedded in a trench 55 provided in the element isolation structure 50, and its upper surface is also covered with the insulating material that constitutes the element isolation structure 50. The upper surface (surface on the first surface S1 side), lower surface (surface on the second surface S2 side), and side surfaces of the shield wall 70 are in contact with the insulating material that constitutes the element isolation structure 50. The lower surface of the shield wall 70 does not penetrate the element isolation structure 50 and is located shallower than the lower surface of the conductor 60 (end surface 62 shown in FIG. 5B ).

[0113] As shown in FIG. 22 , a shield wall 70 is provided between adjacent active regions 24f and 24d in the Y direction to shield at least a portion of the electric field generated between the active regions 24f and 24d. Similarly, a shield wall 70 is provided between active regions 24g and 24e to shield at least a portion of the electric field generated between the active regions 24g and 24e. The electric field is generated, for example, by the n-type main electrode regions (one of the source and drain regions) of transistors T3 and T4. The shield wall 70 is provided to suppress the influence of the electric field generated by the n-type main electrode regions on other active regions. As shown in FIG. 23 , the lower surface of the shield wall 70 is located deeper than the lower surface of the n-type main electrode region (one of the source and drain regions) of transistor T3. Although not shown, the lower surface of the shield wall 70 is also located deeper than the lower surface of the n-type main electrode region of transistor T4. This configuration of the shield wall 70 allows for more efficient electric field shielding. The shield wall 70 is long along the X direction in a plan view. The shield wall 70 long along the X direction may be referred to as a shield wall 71 to distinguish it from shield walls long along other directions, which will be described later.

[0114] <<Method of Manufacturing Photodetector>> A method of manufacturing the photodetector 1 will be described below with reference to FIGS. 25 to 28. In this embodiment, only the steps related to the shield wall 70 and the conductor 60 will be described, and other steps will be described. FIGS. 25 to 28 show a cross-sectional configuration when viewed in a plane along the C-C cutting line in FIG. 22. As shown in FIG. 25, first, the shield wall 70 is embedded in the element isolation structure 50. Then, as shown in FIG. 26, a resist pattern R3 having an opening R3a is formed using known lithography techniques. The opening R3a is provided at a position in the element isolation structure 50 where the conductor 60 is to be provided. Note that a hard mask may be provided instead of the resist pattern R3. Then, the portion of the element isolation structure 50 that overlaps with the opening R3a in a plan view is etched to form a through-hole 51 that penetrates the element isolation structure 50.

[0115] 27, p-type impurities are ion-implanted into the well region 21 exposed from the through-hole 51 to form the contact portion 21B. Thereafter, the through-hole 51 is filled with a material for forming the conductor 60, and the excess portion is removed to obtain the conductor 60. Then, as shown in FIG. 28, the resist pattern R3 is removed, and a wiring layer such as a via 32a is formed.

[0116] <<Major Effects of the Fourth Embodiment>> The photodetector 1 according to the fourth embodiment of the present technology includes a shield wall 70 embedded in the element isolation structure 50, which is an STI. Therefore, at least a portion of the electric field generated between the active regions 24 is shielded, thereby suppressing the effects of voltage modulation and coupling via the STI. This makes it possible to suppress dark current and white spots. Furthermore, because the shield wall 70 is embedded in the trench 55, it can be formed even in small gaps.

[0117] Furthermore, in the photodetector 1 according to the fourth embodiment of the present technology, the shield wall 70 is provided between the active regions 24f and 24g in which the transistors T3 and T4 are provided and the active regions 24d and 24e in which the charge accumulation regions FD are provided, so that it is possible to suppress the influence of the electric field generated by the n-type main electrode region on the active regions in which the charge accumulation regions FD are provided, thereby suppressing dark current and white spots.

[0118] Furthermore, in the photodetector 1 according to the fourth embodiment of the present technology, the shield wall 70 is connected to the conductor 60 that supplies a reference potential to the well region, and therefore there is no need for a dedicated contact portion for applying a reference potential to the shield wall 70. Therefore, even when pixels are miniaturized, the shield wall 70 can be provided in a space-saving manner, and restrictions on the dimensions of the pixel transistors can be suppressed.

[0119] <Modification of Fourth Embodiment> A modification of the fourth embodiment will now be described.

[0120] <Modification 1> In a photodetector 1 according to Modification 1 of the fourth embodiment, as shown in Fig. 29 , a shield wall 70 is provided between transistors T3 and T4 that are adjacent to each other along the X direction. The shield wall 70 according to this modification is long along the Y direction in a plan view, and is referred to as shield wall 72 to distinguish it from shield wall 71. When there is no need to distinguish between the shield walls 71 and 72, they are simply referred to as shield wall 70. As shown in Fig. 30 , the shield wall 72 is provided between the active region 24f and the active region 24g, and shields at least a portion of the electric field generated between the main electrode region of transistor T3 and the main electrode region of transistor T4.

[0121] In the photodetector 1 according to the first modification of the fourth embodiment of the present technology, the shield wall 70 is provided between the transistor T3 and the transistor T4, so that the influence of voltage modulation and coupling between the transistors can be suppressed, thereby suppressing dark current and white spots.

[0122] <Modification 2> The shape of the transistors T3 and T4 is not limited to a rectangle as shown in Fig. 22. In a photodetector 1 according to Modification 2 of the fourth embodiment, the shape of the transistors T3 and T4 is a trapezoid as shown in Fig. 31.

[0123] <Modification 3> A photodetector 1 according to Modification 3 of the fourth embodiment will be described with reference to FIG. 32 . FIG. 32 shows pixels 3 arranged in two rows and four columns. The pixels 3 in the second row and second column on the left side of the page are referred to as pixels 3a, and the pixels 3 in the second row and second column on the right side of the page are referred to as pixels 3b to distinguish them from each other. The pixels 3a and 3b are provided with color filters of different colors. For example, all of the pixels 3a in the second row and second column are provided with green color filters, and all of the pixels 3b in the second row and second column are provided with blue color filters. In this way, the pixels 3a in the second row and second column constitute one same-color pixel unit Ca, and the pixels 3b in the second row and second column constitute one same-color pixel unit Cb. When the same-color pixel units Ca and Cb are not distinguished from each other, they are simply referred to as same-color pixel units C. Of the multiple charge accumulation regions FD included in the same-color pixel unit Ca, the charge accumulation region FD located closest to the same-color pixel unit Cb is called charge accumulation region FDa to distinguish it from the other charge accumulation regions. Furthermore, of the multiple charge accumulation regions FD included in the same-color pixel unit Cb, the charge accumulation region FD located closest to the same-color pixel unit Ca is called charge accumulation region FDb to distinguish it from the other charge accumulation regions. Charge accumulation region FDa and charge accumulation region FDb are adjacent to each other in the X direction.

[0124] A shield wall 72 is provided between adjacent same-color pixel units C along the X direction. The shield wall 72 is provided between the charge accumulation region FDa and the charge accumulation region FDb adjacent along the X direction, and shields at least a part of the electric field generated between the charge accumulation region FDa and the charge accumulation region FDb.

[0125] The shield wall 72 may be provided continuously across multiple pixels 3. The photodetector 1 according to this modification also has a shield wall 71 provided between the charge accumulation region FD and the transistors T3 and T4 adjacent to each other in the Y direction. The shield wall 71 may be provided continuously across multiple pixels 3.

[0126] In the photodetector 1 according to the third modification of the fourth embodiment of the present technology, the charge accumulation regions FDa and FDb are adjacent to each other across the boundary between the same-color pixel units Ca and Cb, and a shield wall 72 is provided between the charge accumulation regions FDa and FDb. This makes it possible to suppress the effects of voltage modulation and coupling between the charge accumulation regions FDa and FDb. This makes it possible to suppress dark current and white spots. This also makes it possible to suppress color mixing.

[0127] <Modification 4> In a photodetector 1 according to Modification 4 of the fourth embodiment, as shown in FIG. 33, a first end 61 of a conductor 60 protrudes from the bottom surface of the element isolation structure 50 and reaches into a contact portion 21B.

[0128] 34 , in the photodetector 1 according to the fifth modification of the fourth embodiment, the lower surface of the shield wall 70 is provided at the same depth as the lower surface of the conductor 60. As a result, the lower end of the shield wall 70 protrudes from the bottom surface of the element isolation structure 50 and reaches into the well region 21.

[0129] In the manufacturing method of the photodetector 1 according to the fourth embodiment, the embedding of the material constituting the shield wall 70 and the embedding of the material constituting the conductor 60 are performed separately. In contrast, in the photodetector 1 according to the fifth modified example of the fourth embodiment of the present technology, the lower surface of the shield wall 70 is provided at the same depth as the lower surface of the conductor 60, so that the embedding of the material constituting the shield wall 70 and the embedding of the material constituting the conductor 60 can be performed together.

[0130] <Modification 6> In FIG. 32 , a via 32 a is provided for each conductor 60. However, in a photodetector 1 according to Modification 6 of the fourth embodiment, as shown in FIG. 35 , a via 32 a does not have to be provided for each conductor 60. In this modification, a single via 32 a supplies a reference potential to multiple conductors 60. Also, in FIG. 32 , the via 32 a that supplies the reference potential is directly connected to the conductor 60. However, in a photodetector 1 according to Modification 6 of the fourth embodiment, as shown in FIG. 35 , the via 32 a does not have to be directly connected to the conductor 60. In this modification, a shield wall 70 is provided to connect multiple conductors 60, and the via 32 a is connected to the shield wall 70, thereby supplying a reference potential to the multiple conductors 60 via the shield wall 70.

[0131] In the example shown in FIG. 35 , a shield wall 72 is provided to connect the conductors 60 in different cell regions 20 a. More specifically, a shield wall 72 is provided to connect the conductors 60 in two adjacent cell regions 20 a among the multiple cell regions 20 a. A via 32 a is connected to the shield wall 72 to supply a reference potential to the shield wall 72. As shown in FIG. 36 , the upper surface of the shield wall 72 is covered with an insulating material. Therefore, a connection portion 70A connected to the shield wall 72 but not covered with an insulating material may be provided, and the via 32 a may be connected to the upper surface of the connection portion 70A. The connection portion 70A is a part of the shield wall 70. In the example shown in FIG. 35 , a reference potential is supplied to the multiple conductors 60 using the shield wall 72, but a reference potential may also be supplied to the multiple conductors 60 using the shield wall 71.

[0132] In the photodetector 1 according to the sixth modification of the fourth embodiment, a single via 32a is shared by a plurality of conductors 60, so that the number of vias 32a can be reduced and the degree of freedom in wiring design can be improved.

[0133] <Seventh Modification> In a photodetector 1 according to a seventh modification of the fourth embodiment, as shown in Fig. 37 , shield walls 71, 72 are provided in a grid pattern for a plurality of pixels 3, and the conductors 60 of each pixel 3 are connected. In the example shown in Fig. 37 , by providing the shield walls 71, 72 in a grid pattern, four conductors 60 included in two rows and two columns of pixels 3 are electrically connected to each other. In the example shown in Fig. 37 , one via 32 a is provided, and a reference potential is supplied to the four conductors 60.

[0134] In the photodetector 1 according to the seventh modification of the fourth embodiment, one via 32a is shared by multiple conductors 60, so the number of vias 32a can be reduced and the degree of freedom in wiring design can be improved. Furthermore, the multiple conductors 60 are connected by providing the shield walls 71, 72 in a lattice pattern, so the number of vias 32a can be further reduced compared to the sixth modification.

[0135] <Modification 8> In a photodetector 1 according to Modification 8 of the fourth embodiment, the present technology may be applied to a square pixel, as shown in FIGS. 38 to 41 . A square pixel is a structure in which an inter-pixel isolation structure 40 is formed in a square shape in the X and Y directions, and one photoelectric conversion region 23 is formed in one pixel, as shown in FIG. 38 . As shown in FIG. 38 , the photodetector according to this modification includes a plurality of transistors T, such as pixel transistors, transfer transistors, and transfer gates (TG, Vertical Gate). A shield wall 70 is provided to surround an active region 24 in which a charge accumulation region FD is provided in a plan view.

[0136] 39, the charge storage regions FD of each pixel 3 are not separated from each other by an inter-pixel isolation structure 40, and the charge storage regions FD of each pixel 3 are integrally provided. In addition, the shape of the pixel transistor is not limited to that shown in FIG. 38, and may be the shape shown in FIG. 40 or 41.

[0137] [Other Embodiments] As described above, the present technology has been described by the first to fourth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0138] For example, it is possible to combine the technical concepts described in the first to fourth embodiments. For example, various combinations according to the technical concepts are possible, such as combining the first and second embodiments. Furthermore, the electronic device 100 described in the third embodiment may include the photodetector 1 described in the fourth embodiment.

[0139] Furthermore, the present technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until when the reflected light is received. The pixel structure described above can be adopted as the structure of this distance measurement sensor.

[0140] Furthermore, for example, the materials cited as constituting the above-described components may contain additives, impurities, etc. Furthermore, in the drawings relating to the embodiments of the present technology, illustration of some elements such as a gate oxide film is omitted.

[0141] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0142] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0143] The present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having a plurality of cell regions, one surface of which is a light incident surface and the other surface of which is an element formation surface, the cell regions being separated from each other by separation walls extending from the light incident surface to the element formation surface; an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and dividing the element formation surface side of the cell region into a plurality of active regions in a plan view; a through hole penetrating the element isolation structure in a thickness direction; and a conductor provided in the through hole and having a first end portion, which is an end portion on the light incident surface side, in contact with a semiconductor portion in the cell region, wherein the cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor. (2) The photodetector according to (1), wherein the photoelectric conversion region is of a first conductivity type, and the cell region includes a well region of a second conductivity type at a depth position between the photoelectric conversion region and the active region, and the first end portion is in contact with the well region. (3) The photodetector according to (2), wherein the element isolation structure is embedded in a groove provided in the cell region from the element formation surface side, and a bottom surface of the element isolation structure is in contact with the well region. (4) The photodetector according to any one of (1) to (3), wherein the first end protrudes from the bottom surface of the element isolation structure, and an end face and a side face of the first end are in contact with a semiconductor portion in the cell region. (5) The photodetector according to any one of (1) to (4), comprising two transistors arranged with gate electrodes adjacent to each other, wherein sidewalls made of an insulating material are provided on adjacent edges of the gate electrodes, the conductor is provided in a position overlapping between the sidewalls in a plan view, and a contact plug that supplies a reference potential to the conductor is connected to an end face of the conductor on the element formation surface side. (6) The photodetector according to (5), wherein a pad is provided between the contact plug and the end face of the conductor on the element formation surface side, and the area of ​​the pad is larger than the area of ​​the end face of the conductor on the element formation surface side in a plan view. (7) The photodetector according to any one of (1) to (6), wherein the conductor is made of polysilicon of a second conductivity type.(8) An electronic device comprising: a photodetector; and an optical system that forms an image light from a subject on the photodetector, wherein the photodetector comprises: a semiconductor layer having a plurality of cell regions, one surface of which is a light incident surface and the other surface of which is an element formation surface, and which are separated from each other by separation walls extending from the light incident surface to the element formation surface; an element isolation structure made of an insulating material, which is provided on the element formation surface side of the cell region and which divides the element formation surface side of the cell region into a plurality of active regions in a planar view; a through hole that penetrates the element isolation structure in a thickness direction; and a conductor that is provided in the through hole and has a first end that is an end on the light incident surface side and is in contact with a semiconductor portion in the cell region, wherein the cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor. (9) A photodetector comprising: a semiconductor layer having one surface which is a light incident surface and the other surface which is an element formation surface, the semiconductor layer having a plurality of cell regions arranged in a matrix, each cell region including a first conductivity type photoelectric conversion region; and an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and which divides the element formation surface side of the cell region into a plurality of active regions in a plan view, the cell region including a first impurity region which is a semiconductor region of a second conductivity type at a depth position between the photoelectric conversion region and the active region, the first impurity region including an impurity which imparts the semiconductor with the second conductivity type, and a concentration of the impurity in the first impurity region having a gradient which gradually increases from a depth position of a bottom surface of the element isolation structure toward a depth direction. (10) The photodetector according to (9), wherein a region of the first impurity region having the highest concentration of the impurity along the depth direction is located at a depth position deeper than the depth position of the bottom surface. (11) The photodetector according to claim 9, further comprising a diffusion region of a first conductivity type provided in the active region and positioned to overlap the first impurity region in a plan view. (12) The photodetector according to (11), wherein the diffusion region is one of a pair of main electrode regions of a pixel transistor provided in the active region and is electrically connected to a power supply line.(13) The photodetector according to any one of (9) to (12), wherein some of the active regions include a charge accumulation region that is a semiconductor region of a first conductivity type and a transfer transistor that can transfer signal charges from the photoelectric conversion region to the charge accumulation region, and the first impurity region is located so as not to overlap a channel formation region of the transfer transistor in a planar view. (14) The photodetector according to any one of (9) to (13), wherein a pixel transistor is provided in the active region, and the first impurity region is located so as to overlap the pixel transistor in a planar view. (15) The photodetector according to any one of (9) to (14), further including a second impurity region that is a semiconductor region of a second conductivity type along a side surface and a bottom surface of the element isolation structure. (16) The photodetector according to (15), wherein an impurity concentration contained in the second impurity region is lower than an impurity concentration contained in the first impurity region. (17) The photodetector according to claim 14, wherein the first impurity region functions as a well region of the pixel transistor. (18) The photodetector according to (14), wherein the pixel transistor is an amplification transistor, a selection transistor, a reset transistor, or a conversion efficiency switching transistor. (19) An electronic device comprising: a photodetector; and an optical system that forms an image of image light from a subject on the photodetector, wherein the photodetector comprises: a semiconductor layer having one surface that is a light incident surface and the other surface that is an element formation surface, and having a plurality of cell regions arranged in a matrix, each cell region including a photoelectric conversion region of a first conductivity type; and an element isolation structure made of an insulating material that is provided on the element formation surface side of the cell region and divides the element formation surface side of the cell region into a plurality of active regions in a plan view, wherein the cell region includes a first impurity region that is a semiconductor region of a second conductivity type at a depth position between the photoelectric conversion region and the active region, the first impurity region containing an impurity that imparts the semiconductor with the second conductivity type, and a concentration of the impurity in the first impurity region has a gradient that gradually increases from a depth position of a bottom surface of the element isolation structure toward a depth. (20) The photodetector according to (1), further comprising: a shielding wall embedded in the element isolation structure, and the shielding wall is connected to the conductor.(21) The photodetector according to (20), wherein the plurality of active regions include a first active region in which a pixel transistor is provided and a second active region in which a charge accumulation region that is a semiconductor region of a first conductivity type is provided, and the shielding wall is provided between the first active region and the second active region. (22) The photodetector according to (20) or (21), wherein a surface of the shielding wall on the light incident surface side is provided at the same depth as a surface of the conductor on the light incident surface side. (23) The photodetector according to any of (20) to (22), further comprising a via for supplying a reference potential, wherein the shielding wall is provided to connect the conductor provided in one of the plurality of cell regions and the conductor provided in another of the plurality of cell regions, and the via is connected to the shielding wall. (24) The photodetector according to any one of (20) to (23), including a plurality of pixel transistors provided in the active region, and the shielding wall is provided between the pixel transistors. (25) The photodetector according to any one of (20) to (24), wherein the first end protrudes from a bottom surface of the element isolation structure, and end faces and side faces of the first end contact a semiconductor portion in the cell region. (26) The photodetector according to any one of (20) to (25), including a square pixel made up of the cell regions arranged in two rows and two columns.

[0144] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0145] DESCRIPTION OF SYMBOLS 1 Photodetector 3 Pixel 20 Semiconductor layer 20a Cell region 20b Isolation region 21 Well region 21B Contact portion 23, 23a, 23b Photoelectric conversion region 24, 24a, 24b, 24c, 24d, 24e, 24f, 24g Active region 26, 27 Diffusion region (main electrode region) 28 First impurity region 29 Second impurity region 32, 32a Via (contact plug) 40 Inter-pixel isolation structure (isolation wall) 50 Element isolation structure 51 Through hole 52 Groove 53 Bottom surface 54 Side surface 60 Conductor 61 First end 62 End surface 63 Side surface 64 Pad 70, 71, 72 Shield wall 70A Connection portion 100 Electronic device 102 Optical system AMP Amplifying transistor FD, FD1, FD2 Charge storage region G Gate electrode RST Reset transistor SEL Select transistor T1, T2, T3, T4, T Transistor TR1, TR2 Transfer transistor Vdd Power line W Sidewall

Claims

1. A semiconductor layer having a plurality of cell regions separated from each other by a separation wall extending from one surface serving as a light incident surface to the other surface serving as an element formation surface; an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and partitioning the element formation surface side of the cell region into a plurality of active regions in a plan view; a through hole penetrating the element isolation structure along the thickness direction; and a conductor provided in the through hole and having a first end portion, which is an end portion on the light incident surface side, in contact with a semiconductor portion in the cell region. The cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor. A photodetector.

2. The photoelectric conversion region has a first conductivity type, the cell region includes a well region of a second conductivity type at a depth position between the photoelectric conversion region and the active region, and the first end portion is in contact with the well region. The photodetector according to claim 1.

3. The element isolation structure is embedded in a groove provided in the cell region from the element formation surface side, and a bottom surface of the element isolation structure is in contact with the well region. The photodetector according to claim 2.

4. The first end portion protrudes from a bottom surface of the element isolation structure, and an end surface and a side surface of the first end portion are in contact with a semiconductor portion in the cell region. The photodetector according to claim 1.

5. Having two transistors arranged at positions where gate electrodes are adjacent to each other, a side wall made of an insulating material is provided at an edge portion where the gate electrodes are adjacent to each other, the conductor is provided at a position overlapping between the side walls in a plan view, and a contact plug for supplying a reference potential to the conductor is connected to an end surface of the conductor on the element formation surface side. The photodetector according to claim 1.

6. A pad is provided between the end surface of the conductor on the element formation surface side and the contact plug, and in a plan view, an area of the pad is larger than an area of the end surface of the conductor on the element formation surface side. The photodetector according to claim 5.

7. The conductor is made of polysilicon of a second conductivity type. The photodetector according to claim 1.

8. An optical detection device and an optical system that forms an image of subject light on the optical detection device, wherein the optical detection device includes: a semiconductor layer having a plurality of cell regions separated from each other by a separation wall that extends from one surface, which is a light incident surface, to the other surface, which is an element formation surface; an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and partitioning the element formation surface side of the cell region into a plurality of active regions in a plan view; a through hole penetrating the element isolation structure in a thickness direction; and a conductor provided in the through hole and having a first end, which is an end on the light incident surface side, in contact with a semiconductor portion in the cell region. The cell region includes a photoelectric conversion region, and a reference potential is supplied to the cell region via the conductor. An electronic device.

9. A semiconductor layer having a plurality of cell regions including a photoelectric conversion region of a first conductivity type in a matrix shape, where one surface is a light incident surface and the other surface is an element formation surface, and an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and partitioning the element formation surface side of the cell region into a plurality of active regions in a plan view. The cell region includes a first impurity region, which is a semiconductor region of a second conductivity type, at a depth position between the photoelectric conversion region and the active region. The first impurity region contains an impurity that makes the semiconductor of the second conductivity type, and the concentration of the impurity in the first impurity region has a gradient that gradually increases toward the deeper side from the depth position of the bottom surface of the element isolation structure. An optical detection device.

10. The optical detection device according to claim 9, wherein the region having the highest concentration of the impurity in the first impurity region is located at a position deeper than the depth position of the bottom surface.

11. The optical detection device according to claim 9, further comprising a diffusion region of a first conductivity type provided in the active region and overlapping the first impurity region in a plan view.

12. The optical detection device according to claim 11, wherein the diffusion region is one of a pair of main electrode regions of a pixel transistor provided in the active region and is electrically connected to a power line.

13. In some of the plurality of active regions, a charge storage region which is a semiconductor region of a first conductivity type, and a transfer transistor capable of transferring signal charges from the photoelectric conversion region to the charge storage region are provided. The first impurity region is located at a position that does not overlap with the channel formation region of the transfer transistor in plan view. The photodetection device according to claim 9.

14. A pixel transistor is provided in the active region. The first impurity region is located at a position that overlaps with the pixel transistor in plan view. The photodetection device according to claim 9.

15. Along the side surface and the bottom surface of the element isolation structure, a second impurity region which is a semiconductor region of a second conductivity type is provided. The photodetection device according to claim 9.

16. The impurity concentration contained in the second impurity region is lower than the impurity concentration contained in the first impurity region. The photodetection device according to claim 15.

17. The first impurity region functions as a well region of the pixel transistor. The photodetection device according to claim 14.

18. The pixel transistor is an amplification transistor, a selection transistor, a reset transistor, or a conversion efficiency switching transistor. The photodetection device according to claim 14.

19. An electronic device includes a photodetection device and an optical system that forms an image of subject light on the photodetection device. The photodetection device includes a semiconductor layer having a plurality of cell regions including a photoelectric conversion region of a first conductivity type in a matrix shape, one surface of which is a light incident surface and the other surface of which is an element formation surface, and an element isolation structure made of an insulating material provided on the element formation surface side of the cell region and partitioning the element formation surface side of the cell region into a plurality of active regions in plan view. The cell region includes a first impurity region which is a semiconductor region of a second conductivity type at a depth position between the photoelectric conversion region and the active region. The first impurity region contains an impurity for making the semiconductor of the second conductivity type. The impurity concentration in the first impurity region has a gradient that gradually increases toward the deeper side from the depth position of the bottom surface of the element isolation structure.

20. The photodetection device according to claim 1 includes a shield wall embedded in the element isolation structure, and the shield wall is connected to the conductor.

21. The plurality of the active regions include a first active region which is the active region where the pixel transistor is provided, and a second active region which is the active region where the charge storage region which is a semiconductor region of a first conductivity type is provided, and the shield wall is provided between the first active region and the second active region. The photodetection device according to claim 20.

22. The surface on the light incident surface side of the shield wall is provided at the same depth as the surface on the light incident surface side of the conductor. The photodetection device according to claim 20.

23. It includes a via for supplying a reference potential, the shield wall is provided to connect between the conductor provided in one cell region among the plurality of cell regions and the conductor provided in another one cell region among the plurality of cell regions, and the via is connected to the shield wall. The photodetection device according to claim 20.

24. It includes a plurality of pixel transistors provided in the active region, and the shield wall is provided between the pixel transistors. The photodetection device according to claim 20.

25. The first end portion protrudes from the bottom surface of the element isolation structure, and the end surface and the side surface of the first end portion are in contact with the semiconductor portion in the cell region. The photodetection device according to claim 20.

26. It includes a square pixel composed of the cell regions of two rows and two columns. The photodetection device according to claim 20.

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