Light detection device

Abstract

[Problem] To provide a light detection device capable of suppressing variation in parasitic capacitance. [Solution] Provided is a light detection device comprising: a plurality of photoelectric conversion elements, each of which accumulates electric charge corresponding to the amount of incident light; a floating diffusion region which is shared by the plurality of photoelectric conversion elements and which retains the electric charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer the electric charge stored in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending in the stacking direction from the floating diffusion region; a plurality of second contacts extending in the stacking direction from the gates of the plurality of transfer transistors; and a plurality of first interconnect layers respectively connected to the plurality of second contacts, wherein, among the plurality of first interconnect layers, first interconnect layers connected to some of the second contacts extend to a place closer to the first contact than first interconnects connected to the other second contacts.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] In order to achieve miniaturization of photodetector devices and high pixel density, photodetector devices with three-dimensional structures have been proposed (see Patent Documents 1 and 2). Patent Document 1 describes arranging sensor pixels and readout circuits on separate substrates. Patent Document 2 describes reducing the parasitic capacitance between a through-hole wiring extending from a floating diffusion region in the stacking direction and a through-hole wiring extending from a gate of a transfer transistor in the stacking direction by using a wiring layer provided between two stacked substrates to increase the distance between the two through-hole wirings, thereby reducing the parasitic capacitance.

[0003] International Publication No. 2020 / 189473 International Publication No. 2019 / 130702

[0004] However, Patent Documents 1 and 2 do not take into account that when multiple pixels share one floating diffusion region, the parasitic capacitance between the multiple through-wires extending in the stacking direction from the gates of multiple transfer transistors and the through-wire extending in the stacking direction from the floating diffusion region fluctuates.

[0005] Therefore, the present disclosure provides a photodetector capable of suppressing variations in parasitic capacitance.

[0006] In order to solve the above problems, according to the present disclosure, there is provided a photodetector device comprising: a plurality of photoelectric conversion elements, each of which accumulates a charge corresponding to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and which holds the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors which transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; first contacts extending in a stacking direction from the floating diffusion region; a plurality of second contacts extending in the stacking direction from gates of the plurality of transfer transistors; and a plurality of first wiring layers connected to the plurality of second contacts, respectively, wherein, of the plurality of first wiring layers, first wiring layers connected to some of the second contacts extend to a position closer to the first contacts than first wirings connected to the other second contacts.

[0007] The semiconductor device may further include a plurality of third contacts extending in a stacking direction from the plurality of first wiring layers, and the first wiring layers may be connected to corresponding third contacts and extend to a side closer to the first contacts than the connection points with the corresponding third contacts.

[0008] Among the plurality of second contacts, at least two or more second contacts may be arranged in one direction, and the two first wiring layers connected to the two second contacts arranged on both sides of the one direction may extend to a position closer to the first contacts than the first wiring layers connected to the other second contacts.

[0009] The photoelectric conversion element may include two floating diffusion regions shared by the plurality of photoelectric conversion elements and arranged in the one direction, two first contacts connected to the two floating diffusion regions, the first wiring layer arranged at one end of the one direction being arranged closer to the first contact arranged at one end of the one direction than the other first wiring layers, and the first wiring layer arranged at the other end of the one direction being arranged closer to the first contact arranged at the other end of the one direction than the other first wiring layers.

[0010] The semiconductor device may also include two second wiring layers connected to the two first contacts extending from the two floating diffusion regions in the stacking direction, and arranged along the two first wiring layers arranged at one end and the other end in the one direction.

[0011] A fourth contact may be provided to connect the two second wiring layers together.

[0012] The pixel may further include an amplifying transistor that generates a pixel signal according to the charge held in the floating diffusion region, and a fourth wiring layer that is connected to the first contact and is disposed in a direction away from the amplifying transistor in a plan view.

[0013] According to the present disclosure, there is provided a photodetector device comprising: a plurality of photoelectric conversion elements, each of which accumulates a charge corresponding to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and which holds the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors which transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending from the floating diffusion region in a stacking direction; a plurality of second contacts extending from gates of the plurality of transfer transistors in the stacking direction; a plurality of first wiring layers connected to the plurality of second contacts, respectively; and a second wiring layer arranged along at least some of the first wiring layers among the plurality of first wiring layers, and which adjusts the capacitance between the plurality of first wiring layers and the first contacts.

[0014] The second wiring layer may be disposed at a location where variations in capacitance between the plurality of first wiring layers and the first contacts are reduced.

[0015] The plurality of first wiring layers may be arranged around the first contact, and the plurality of second wiring layers may be arranged along two or more of the first wiring layers.

[0016] The second wiring layer may be disposed between two adjacent first wiring layers among the plurality of first wiring layers.

[0017] The second wiring layer may be disposed in a position facing the first contact.

[0018] The pixel transistor may include a first substrate on which the photoelectric conversion element, the transfer transistor, and the floating diffusion region are arranged, and a second substrate stacked on the first substrate on which a pixel transistor used to generate a pixel signal according to the charge held in the floating diffusion region is arranged, wherein the first wiring layer and the second wiring layer may be arranged in a first wiring region between the first substrate and the second substrate.

[0019] The second substrate may have a second wiring region arranged on the opposite side of the first substrate to the first substrate and having a third wiring layer, and the dielectric constant of a first insulating layer covering the first wiring layer and the second wiring layer in the first wiring region may be higher than the dielectric constant of a second insulating layer covering the third wiring layer in the second wiring region.

[0020] The second wiring layer may transmit a boost voltage, a power supply voltage, a ground voltage, or a signal connected to a conversion efficiency switching transistor.

[0021] The second wiring layer may include polysilicon, tungsten (W), copper (Cu), or aluminum (Al).

[0022] According to the present disclosure, there is provided a photodetection device comprising: a plurality of photoelectric conversion elements, each of which accumulates a charge corresponding to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and which holds the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors which transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first substrate on which the photoelectric conversion elements, the transfer transistors, and the floating diffusion region are arranged; a second substrate stacked on the first substrate and on which pixel transistors used to generate pixel signals corresponding to the charge held in the floating diffusion region are arranged; and a plurality of contacts connecting the first substrate and the second substrate, wherein at least one transistor constituting the pixel transistor is arranged in a position which does not face the plurality of contacts in a planar view.

[0023] The pixel transistor arrangement region may be rectangular in plan view, and at least one transistor constituting the pixel transistor may be arranged in a location where none of the sides of the transistor arrangement region faces the plurality of contacts.

[0024] The plurality of contacts may be arranged in a diagonal direction of the pixel transistor when viewed in a plan view.

[0025] a plurality of pixels sharing the floating diffusion region and the pixel transistor; each of the plurality of pixels having the photoelectric conversion element, the floating diffusion region, and the transfer transistor; the pixel transistor having an amplification transistor, a selection transistor, a reset transistor, and a conversion efficiency switching transistor; the reset transistor and the conversion efficiency switching transistor being connected in series or in parallel; and the floating diffusion region may be connected to the source of the conversion efficiency switching transistor and the gate of the amplification transistor, or to the source of the reset transistor, the drain of the conversion efficiency switching transistor, and the gate of the amplification transistor.

[0026] 9A and 9B are cross-sectional views of a photodetector according to the present disclosure; a circuit diagram of a pixel circuit according to the present disclosure; a diagram showing an example of a longitudinal cross-sectional configuration of a photodetector according to the present disclosure; a layout diagram showing a plan view of a first substrate and an intermediate layer of a photodetector according to a first embodiment; a layout diagram showing a plan view of a first substrate and an intermediate layer of a photodetector according to a second embodiment; a layout diagram showing a plan view of a first substrate and an intermediate layer of a photodetector according to a third embodiment; a layout diagram showing a plan view of a first substrate, an intermediate layer, and a second substrate of a photodetector according to a fourth embodiment; a layout diagram showing a plan view of a first substrate and an intermediate layer of a photodetector according to a fifth embodiment; a layout diagram of a second substrate of a photodetector according to the fifth embodiment; FIG. 10A is a cross-sectional view taken along line A-A in FIG. 8; and FIG. 10B is a cross-sectional view taken along line B-B in FIG. 9; a diagram showing parasitic capacitances between an FD wiring layer, a TG wiring layer, and an adjustment wiring layer; a diagram showing the location and parasitic capacitance of an adjustment wiring layer according to a first modification; and a diagram showing the location and parasitic capacitance of an adjustment wiring layer according to a second modification. 18B. A layout diagram of the second substrate of the photodetector according to the sixth embodiment. A layout diagram of the second substrate of the photodetector according to a comparative example. A cross-sectional view taken along line A-A in FIG. 18A. A cross-sectional view taken along line B-B in FIG. 18B. A layout diagram when the amplification transistor and the selection transistor are arranged horizontally. A layout diagram when the amplification transistor and the selection transistor are arranged vertically. A diagram explaining the positional relationship between the amplification transistor and the TG contact when the amplification transistor and the selection transistor are arranged horizontally. A diagram explaining the positional relationship between the amplification transistor and the TG contact when the amplification transistor and the selection transistor are arranged vertically. A perspective view showing the structure of a planar-type pixel transistor. A perspective view showing the structure of a fin-type pixel transistor. A perspective view showing the structure of a GAA-type pixel transistor. A plan view showing the structure of an L-type transfer transistor. 1 is a plan view showing a first example of a pixel structure applicable to the photodetector devices according to the first to sixth embodiments; FIG. 2 is a plan view showing a second example of a pixel structure applicable to the photodetector devices according to the first to sixth embodiments; FIG. 3 is a plan view showing a third example of a pixel structure applicable to the photodetector devices according to the first to sixth embodiments.31 is a layout diagram of a second substrate when a reset transistor and a conversion efficiency switching transistor are connected in series. 32 is a layout diagram of a second substrate when a reset transistor and a conversion efficiency switching transistor are connected in parallel. 33 is a circuit diagram showing a modified example of the circuit configuration of a pixel circuit for one pixel block having a Recta structure applicable to the photodetector devices according to the first to sixth embodiments. 34 is a layout diagram of a second substrate for one pixel block shown in FIG. 28. 35 is a layout diagram of a photodetector device according to a tenth embodiment. 36 is a cross-sectional view taken along line A-A' in FIG. 30. 37 is a diagram showing a first example of a cross-sectional shape of a third contact according to the tenth embodiment. 38 is a diagram showing a second example of a cross-sectional shape of a third contact. 39 is a layout diagram of a photodetector device according to a modified example of the tenth embodiment. 39 is a cross-sectional view taken along line A-A' in FIG. 33. 39 is a block diagram showing an example of a schematic configuration of a vehicle control system. 39 is an explanatory diagram showing an example of the installation positions of an outside-of-vehicle information detection unit and an imaging unit.

[0027] Hereinafter, an embodiment of a photodetector will be described with reference to the drawings. The following description will focus on the main components of the photodetector, but the photodetector may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] (Schematic Configuration of Photodetector) FIG. 1 is a diagram showing a schematic configuration of a photodetector 1 according to the present disclosure. As shown in FIG. 1, the photodetector 1 includes three substrates: a first substrate 10, a second substrate 20, and a third substrate 30. The structure of the photodetector 1 is a three-dimensional structure formed by bonding together the first substrate 10, the second substrate 20, and the third substrate 30. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order. The first substrate 10 is the uppermost first layer, the second substrate 20 is the second layer, and the third substrate 30 is the lowermost third layer. The top surface of the first substrate 10 is a light incident surface.

[0029] The first substrate 10 includes a semiconductor substrate 11 and a plurality of sensor pixels 12 that perform photoelectric conversion. Hereinafter, the sensor pixels 12 will be simply referred to as pixels. The semiconductor substrate 11 includes a plurality of pixels 12. These pixels 12 are arranged in a matrix (two-dimensional array) within a pixel region 13 on the first substrate 10. Each pixel 12 includes a photoelectric conversion element and a transfer transistor, as will be described later. A pixel circuit is connected to each pixel 12.

[0030] The second substrate 20 includes a semiconductor substrate 21, a pixel circuit 22 that outputs a pixel signal, a plurality of pixel drive lines 23 extending in the row direction, and a plurality of vertical signal lines 24 that extend in the column direction. The semiconductor substrate 21 has one pixel circuit 22 for every four pixels 12. This pixel circuit 22 outputs a pixel signal based on the charge output from the pixel 12. The pixel circuit 22 is also called a readout circuit.

[0031] The third substrate 30 includes a semiconductor substrate 31 and a logic circuit 32 that processes pixel signals. The semiconductor substrate 31 includes the logic circuit 32. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36.

[0032] The logic circuit 32 outputs to the outside an output voltage Vout for each pixel 12. In the logic circuit 32, for example, a low-resistance region made of silicide such as CoSi2 or NiSi formed using a salicide (self-aligned silicide) process may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0033] The vertical drive circuit 33 selects, for example, a plurality of pixels 12 in order on a row-by-row basis.

[0034] The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on pixel signals output from each pixel 12 in a row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 extracts the signal level of each pixel signal by performing CDS processing and holds pixel data corresponding to the amount of light received by each pixel 12.

[0035] The horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside, for example.

[0036] The system control circuit 36 ​​controls, for example, the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0037] (Example of pixel circuit) Next, an example of a pixel circuit according to the present disclosure will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of a pixel circuit according to the present disclosure.

[0038] In the photodetection device 1 according to the present disclosure, a plurality of pixels 12 share one pixel circuit 22. Fig. 2 shows an example of a pixel structure in which 2 x 4 = 8 pixels share one pixel circuit 22. Note that the number of pixels 12 sharing one pixel circuit 22 is arbitrary, and does not necessarily have to be the configuration shown in Fig. 2 .

[0039] 2 performs phase difference detection between two pixels 12 adjacent in a first direction (for example, the horizontal direction), and 2×2 pixels 12 share one floating diffusion region (FD), and 2×4 pixels share one pixel circuit 22. The pixel structure in FIG. 2 is called a Recta structure.

[0040] Each pixel 12 that performs phase difference detection (hereinafter, may be referred to as a phase difference detection pixel 12) has a photoelectric conversion element PD and a transfer transistor TR. The photoelectric conversion element PD is, for example, a photodiode.

[0041] The pixel circuit 22 shared by the eight pixels 12 includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG. The conversion efficiency switching transistor FDG may be omitted. In this specification, the transistors constituting the pixel circuit 22 may be collectively referred to as pixel transistors. The pixel transistors are configured, for example, by NMOS (N-type Metal Oxide Semiconductor) transistors.

[0042] The amplifier transistor AMP and the select transistor SEL form a source follower circuit. The gate of the amplifier transistor AMP is connected to two floating diffusion regions FD and to the source of the conversion efficiency switching transistor FDG. The conversion efficiency switching transistor FDG switches the photoelectric conversion efficiency and may be omitted. The drain of the conversion efficiency switching transistor FDG is connected to the source of the reset transistor RST. The drains of the reset transistor RST and the amplifier transistor AMP are connected to a power supply voltage node. The source of the amplifier transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to a vertical signal line VSL. The vertical signal lines VSL extend in the second direction (column direction) and are arranged at predetermined intervals in the first direction (row direction). A current source 14 is connected to each vertical signal line VSL. In this specification, the two floating diffusion regions FD in each pixel circuit 22 in the Recta structure may be referred to as FD1 and FD2.

[0043] (Cross-sectional Structure of Photodetector 1) FIG. 3 is a diagram showing an example of a longitudinal cross-sectional structure (vertical cross-sectional structure) of a photodetector 1 according to the present disclosure.

[0044] 3, the photodetector 1 is configured by stacking a first substrate 10, a second substrate 20, and a third substrate 30 in this order, and further includes a color filter 40 and a light-receiving lens 50 on the back surface side (light incident surface side) of the first substrate 10. For example, one color filter 40 and one light-receiving lens 50 are provided for each pixel 12. In other words, the photodetector 1 is a back-illuminated type.

[0045] The first substrate 10 is configured by laminating an insulating layer 46 on a semiconductor substrate 11. The insulating layer 46 is also called an interlayer insulating layer. The insulating layer 46 is provided in the gap between the semiconductor substrate 11 and a semiconductor substrate 21, which will be described later.

[0046] The semiconductor substrate 11 is made of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 in and near a portion of the surface, and a photodiode PD of a different conductivity type from the p-well layer 42 in the remaining region (a region deeper than the p-well layer 42). The p-well layer 42 is made of a p-type semiconductor region. The photodiode PD is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The semiconductor substrate 11 has a floating diffusion region FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0047] 3, one floating diffusion region FD has four adjacent diffusion layers (floating diffusion layers) FDa and one connection layer FDb. A diffusion layer FDa is provided for each photodiode PD, and the diffusion layers FDa of the four adjacent photodiodes PD are electrically connected by one connection layer FDb. The connection layer FDb is positioned above each diffusion layer FDa so as to be in contact with each diffusion layer FDa, and is provided in the insulating layer 46. This connection layer FDb is formed of the same material (e.g., polysilicon) as the transfer gate TG.

[0048] The first substrate 10 has a photodiode PD and a transfer transistor TR for each pixel 12, and further has a floating diffusion region FD and a well tap WT shared by four pixels 12. The transfer transistor TR, floating diffusion region FD, and well tap WT are provided on the front surface side of the semiconductor substrate 11 (the side opposite the light incident surface, the second substrate 20 side). The well tap WT is electrically connected to the p-well layer 42 (e.g., a well contact formed in the p-well layer 42).

[0049] The first substrate 10 has an element isolation portion 43 that isolates each pixel 12. The element isolation portion 43 is formed to extend in the normal direction of the semiconductor substrate 11 (a direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is provided between two adjacent pixels 12. The element isolation portion 43 electrically isolates the adjacent pixels 12. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the semiconductor substrate 11 (full trench), and completely electrically isolates two or more adjacent pixels 12.

[0050] The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the back surface of the semiconductor substrate 11 and at a position facing the pixels 12. The light receiving lens 50 is provided, for example, in contact with the back surface of the color filter 40 and at a position facing the pixels 12 with the color filter 40 interposed therebetween.

[0051] The second substrate 20 is formed by laminating an insulating layer 52 on a semiconductor substrate 21. The insulating layer 52 is also called an interlayer insulating layer. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and a semiconductor substrate 31 (described later). The semiconductor substrate 21 is formed of a silicon substrate.

[0052] The second substrate 20 has one pixel circuit 22 for every four pixels 12 (see FIGS. 2 and 3). The pixel circuits 22 are provided on the back surface side (first substrate 10 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back.

[0053] The second substrate 20 further includes an insulating layer 53 that is in the same layer as the semiconductor substrate 21 and penetrates the semiconductor substrate 21. The insulating layer 53 is also called an interlayer insulating layer. The insulating layer 53 is provided so as to cover the side surfaces of the through-wires 54, which will be described later.

[0054] As described above, the stacked body made up of the first substrate 10 and the second substrate 20 has the interlayer insulating layer 51 including the insulating layer 46, the insulating layer 52, and the insulating layer 53, and the through wiring 54 provided in the interlayer insulating layer 51. The stacked body has one through wiring 54 for every four pixels 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided so as to penetrate the portion of the interlayer insulating layer 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through wiring 54. The through wiring 54 is, for example, a through contact for the floating diffusion region FD (FD1 to FD4).

[0055] The stacked body made up of the first substrate 10 and the second substrate 20 also has another through-wiring (not shown) provided in the interlayer insulating layer 51. Like the above-mentioned through-wiring 54, this through-wiring also extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a portion of the interlayer insulating layer 51 that includes an insulating layer having the same configuration as the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wiring. This through-wiring is, for example, a through contact for the transfer gate TG or a through contact for the well tap WT.

[0056] The second substrate 20 has, for example, a plurality of connection portions 59 electrically connected to the pixel circuits 22 and the semiconductor substrate 21 within the insulating layer 52. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel 12 drive lines 23 and a plurality of vertical signal lines 24 provided within the insulating layer 57. The wiring layer 56 further has, for example, connection wiring 55 within the insulating layer 57 for each floating diffusion region FD. The connection wiring 55 is electrically connected to the through wiring 54 connected to the floating diffusion region FD.

[0057] Here, the total number of through wirings 54 functioning as through contacts for the floating diffusion region FD is smaller than the total number of pixels 12 included in the first substrate 10, and for example, since the number of pixels 12 sharing the floating diffusion region FD is four, it is ¼ times the total number of pixels 12 included in the first substrate 10. Similarly, the total number of through wirings (not shown) functioning as through contacts for the transfer gates TG and the total number of through wirings (not shown) functioning as through contacts for the well taps WT are, for example, ¼ times the total number of pixels 12 included in the first substrate 10.

[0058] The wiring layer 56 further includes, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used to electrically connect the second substrate 20 and the third substrate 30 and to bond the second substrate 20 and the third substrate 30 together. Each pad electrode 58 is provided, for example, for each pixel 12 drive line 23 and each vertical signal line 24.

[0059] The third substrate 30 is configured, for example, by laminating an interlayer insulating layer 61 on a semiconductor substrate 31. The semiconductor substrate 31 is configured of a silicon substrate. As will be described later, the third substrate 30 is bonded to the second substrate 20 with their front surfaces facing each other. Therefore, when describing the internal configuration of the third substrate 30, the description of the top and bottom is reversed from the top and bottom direction in the drawings.

[0060] The third substrate 30 has a configuration in which a logic circuit 32 is provided on the surface side of a semiconductor substrate 31. The third substrate 30 has, for example, a wiring layer 62 on an interlayer insulating layer 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. Each pad electrode 64 is electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used to electrically connect the second substrate 20 and the third substrate 30 and to bond the second substrate 20 and the third substrate 30 together. Note that the number of pad electrodes 64 does not necessarily have to be multiple.

[0061] The third substrate 30 and the second substrate 20 are electrically connected to each other by bonding the pad electrodes 58, 64. The third substrate 30 is bonded to the second substrate 20 with the surface of the semiconductor substrate 31 facing the surface of the semiconductor substrate 21. In other words, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0062] First Embodiment As described above, an insulating layer (interlayer insulating layer) 46 is disposed between the first substrate 10 and the second substrate 20. In this specification, the insulating layer 46 may be referred to as an intermediate layer 70. In the cross-sectional structure of the photodetector 1 shown in FIG. 3 , all of the wiring layers 71 disposed in the intermediate layer 70 have the same layer height (hereinafter referred to as layers). The intermediate layer 70 includes multiple types of wiring layers, including an FD wiring layer FDW electrically connected to the floating diffusion region FD and a TG wiring layer (first wiring layer) TGW electrically connected to the transfer gate of the transfer transistor TR. The FD wiring layer FDW and the TG wiring layer TGW are disposed separately in the same layer of the intermediate layer 70. The FD wiring layer FDW and the TG wiring layer TGW are made of a conductive material such as polysilicon, tungsten (W), copper (Cu), or gold (Au).

[0063] In addition, a plurality of contacts CT extending in the stacking direction are arranged in the intermediate layer 70. The contacts include a contact CT0 extending from the wiring layer of the intermediate layer 70 to the second substrate, a contact CT1 extending from the first substrate 10 through the intermediate layer 70 to the second substrate, and a contact CT2 extending from the first substrate 10 to the wiring layer of the intermediate layer 70. In this specification, the contacts CT0 to CT2 are collectively referred to as contacts (third contacts) CT. In this specification, of the plurality of contacts CT, a contact (first contact) electrically connected to the floating diffusion region FD is referred to as an FDC, and a contact (second contact) electrically connected to the gate of the transfer transistor TR is referred to as a TG contact TGC.

[0064] FIG. 4 is a planar layout diagram of the first substrate 10 and intermediate layer 70 of the photodetector 1 according to the first embodiment. FIG. 4 shows the layout of a pixel region for one pixel block consisting of 2×4 pixels 12 with a Recta pixel structure. As shown in FIG. 2, eight transfer gates TRG0 to TRG7 of eight transfer transistors TR are provided within one pixel block. These transfer transistors TR are arranged on the first substrate 10 as shown in FIG. 3. Contacts TGC0 to TRC7 extend from each gate of these transfer transistors TR (hereinafter referred to as transfer gates) to the intermediate layer 70.

[0065] In the example of FIG. 4, among the eight transfer gates TRG0 to TRG7 of the Recta structure, the contacts TGC0 to TGC3 of the transfer gates TRG0 to TRG3 are arranged along the first direction X, and the contacts (TG contacts TGC) TGC4 to TGC7 of the transfer gates TRG4 to TRG7 are arranged along the first direction X so as to face the contacts of the transfer gates TRG0 to TRG3 in the second direction Y.

[0066] Eight TG wiring layers TGW0 to TGW7 connected to the TG contacts TGC of the transfer gates TRG0 to TRG7 are arranged in the intermediate layer 70. Furthermore, two FD contacts FDC0 and FDC1 aligned along the first direction X are arranged in approximately the center of a pixel region equivalent to one pixel block in the intermediate layer 70. These FD contacts FDC0 and FDC1 are connected to a floating diffusion region FD arranged in the first substrate 10. These FD contacts FDC0 and FDC1 are arranged separately from each other in the intermediate layer 70, but are electrically connected to each other on the first substrate 10.

[0067] Because the distances between the two FD contacts FDC0, FDC1 and the eight TG wirings TGW0 to TGW7 are not necessarily the same, the magnitude of the parasitic capacitance between the two FD contacts FDC0, FDC1 and the eight TG wirings TGW0 to TGW7 fluctuates. When the parasitic capacitance between the FD contact FDC and the TG wirings TGW fluctuates, deviations occur in the phase difference detection results in the Recta structure, making it impossible to accurately detect the defocus amount. Furthermore, in the case of a pixel structure for imaging, fluctuations in the parasitic capacitance between the FD contact FDC and the TG wirings adversely affect the quality of the captured image.

[0068] Therefore, in the first embodiment, of the eight TG wiring layers TGW0 to TGW7, the TG wiring layers TGW connected to some of the TG contacts TGC extend to a location closer to the FD contact FDC than the TG wiring layers TGW connected to the other TG contacts TGC. Also, each TG wiring layer TGW extends to a location closer to the FD contact FDC than the connection point with the contact CT extending to the second substrate 20.

[0069] More specifically, of the four TG contacts TGC0 to TGC3 aligned in the first direction X, the two TG wiring layers TGW respectively connected to the two TG contacts TGC0, TGC3 arranged on both ends extend to a position closer to the FD contact FDC than the two TG wiring layers TGW respectively connected to the remaining two TG contacts TGC1, TGC2. Similarly, of the four TG contacts TGC4 to TGC7 aligned in the first direction X, the two TG wiring layers TGW respectively connected to the two TG contacts TGC4, TGC7 arranged on both ends extend to a position closer to the FDC than the two TG wiring layers TGW respectively connected to the remaining two TG contacts TGC5, TGC6. The TG wiring layers TGW connected to these TG contacts TGC0, TGC3, TGC4, and TGC7 respectively extend to a side closer to the FD contact FDC than the connection points with the contacts CT0, CT3, CT4, and CT7 that extend to the second substrate 20.

[0070] In the example of FIG. 4, the two TG wiring layers TGW0 and TGW4 connected to the TG contacts TGC0 and TGC4 are arranged along one FD contact FDC0 of two FD contacts FDC0 and FDC1 arranged along the first direction X in the center of the pixel block, and the two TG wiring layers TGW connected to the TG contacts TGC3 and TGC7 are arranged along the other FD contact FDC1.

[0071] The reason why the TG wiring layers TGW connected to the TG contacts TGC0, TGC3, TGC4, and TGC7 arranged on both ends of the TG contacts TGC0 to TGC3 and TGC4 to TCG7 are extended to approach the FD contact FDC is because the TG wiring layers TGW on both ends have smaller parasitic capacitance with the FD contact FDC than the other TG wiring layers TGW. By extending the TG wiring layers TGW on both ends close to the FD contact FDC, it is possible to suppress variations in the parasitic capacitance between each TG wiring layer TGW and the FD contact FDC.

[0072] The parasitic capacitance between the FD contact FDC and the multiple TG wiring layers TGW changes depending on the location of the FD contact FDC. Therefore, depending on the location of the FD contact FDC and the locations of the multiple TG wiring layers TGW, the TG wiring layer TGW that is closer to the FD contact FDC may be switched among the multiple TG wiring layers TGW.

[0073] As described above, in the first embodiment, depending on the locations of the FD contacts FDC and the plurality of TG wiring layers TGW arranged on the intermediate layer 70, some of the TG wiring layers TGW are extended close to the FD contacts FDC, which can suppress variations in parasitic capacitance between the FD contacts FDC and the plurality of TG wiring layers TGW and can improve the electrical characteristics of the photodetector 1, such as phase difference detection or the image quality of captured images. More specifically, of the plurality of TG wiring layers TGW arranged in the first direction X, the TG wiring layers TGW on both ends tend to have smaller parasitic capacitance with the FD contacts FDC, so by extending the TG wiring layers TGW on both ends to locations close to the FD contacts FDC, it is possible to suppress variations in parasitic capacitance between the FD contacts FDC and the plurality of TG wiring layers TGW.

[0074] Second Embodiment Fig. 5 is a planar layout diagram of the first substrate 10 and intermediate layer 70 of a photodetector 1 according to a second embodiment. The photodetector 1 according to the second embodiment is configured similarly to the first embodiment except for the layout arrangement in the intermediate layer 70. As shown in Fig. 5, the intermediate layer 70 of the photodetector 1 according to the second embodiment has FD wiring layers FDW (FDW0, FDW1) connected to two FD contacts FDC0, FDC1, respectively.

[0075] The FD wiring layer FDW extends close to the TG wiring layer TGW having the smallest parasitic capacitance with the FD contact FDC among the four TG wiring layers TGW0 to TGW3, TGW4 to TGW7 connected to the four TG contacts TGC0 to TGC3, TGC4 to TGC7 aligned in the first direction X. For example, if the parasitic capacitance between the two TG wiring layers TGW0, TGW3, TGW4, TGW7 at both ends in the first direction X and the FD contacts FDC0, FDC1 is smaller than the parasitic capacitance between the other TG wiring layer TGW and the FD contact FDC, the FD wiring layer FDW is disposed close to the two TG wiring layers TGW0, TGW3, TGW4, TGW7 at both ends in the first direction X.

[0076] Furthermore, in the photodetector 1 according to the second embodiment, like the photodetector 1 according to the first embodiment shown in FIG. 4, some of the TG wiring layers TGW0, TGW3, TGW4, and TGW7 are extended to the vicinity of the FD contact FDC.

[0077] In this way, in the second embodiment, the FD wiring layer FDW is connected to the FD contact FDC in the intermediate layer 70, and the FD wiring layer FDW is extended to the vicinity of the TG wiring layer TGW, which has a smaller parasitic capacitance, so that the variation in parasitic capacitance between the FD contact FDC and the multiple TG wiring layers TGW can be suppressed more than in the first embodiment.

[0078] 6 is a planar layout diagram of the first substrate 10 and intermediate layer 70 of a photodetector 1 according to a third embodiment. The photodetector 1 according to the third embodiment includes an FD wiring layer FDW (FDW0, FDW1) that connects two FD contacts FDC0, FDC1 together, and an FD contact (fourth contact) FDC that connects these FD wiring layers FDW0, FDW1 together. This reduces the parasitic capacitance between the FD contacts FDC, and allows the two FD contacts FDC0, FDC1 to be set to the same potential. In other words, the FD contacts can be consolidated into one, reducing the FD wiring capacitance itself and improving the flexibility of pixel transistor placement.

[0079] 4 and 5, in the photodetector 1 according to the third embodiment, some of the TG wiring layers TGW are disposed close to the FD contacts FDC, thereby suppressing variations in parasitic capacitance between the FD contacts FDC and the plurality of TG wiring layers TGW.

[0080] 7 is a planar layout diagram of the first substrate 10, intermediate layer 70, and second substrate 20 of a photodetector 1 according to a fourth embodiment. More specifically, FIG. 7 shows a planar layout of the FD contact FDC, FD wiring layer FDW, TG contact TGC, and TG wiring layer TGW in the intermediate layer 70, and the pixel transistors in the second substrate 20. FIG. 7 illustrates the amplifier transistor AMP, selection transistor SEL, reset transistor RST, and conversion efficiency switching transistor FDG that constitute the pixel transistors. Note that there are no restrictions on the placement of pixel transistors other than the amplifier transistor AMP.

[0081] The intermediate layer 70 shown in FIG. 7 is provided with an FD wiring layer FDW0 that connects two FD contacts FDC0 and FDC1 together, an FD contact FDC that is arranged on FDW1 (third wiring layer) and extends to the second substrate 20, and an FD wiring layer FDW2 (fourth wiring layer) that is connected to this FD contact FDC and is arranged in a direction away from the amplification transistor AMP in a planar view.

[0082] Furthermore, in the photodetector 1 according to the fourth embodiment, like the photodetector 1 according to the first to third embodiments shown in Figures 4 to 6, some of the TG wiring layers TGW are arranged close to the FD contacts FDC.

[0083] In this way, in the fourth embodiment, the FD wiring layer FDW is arranged in a direction away from the amplification transistor AMP from the FD contact FDC in a planar view, so that variations in parasitic capacitance between the FD contact FDC and the multiple TG wiring layers TGW can be suppressed.

[0084] 8 is a plan view of a layout of the first substrate 10 and intermediate layer 70 of a photodetector 1 according to a fifth embodiment, and Fig. 9 is a layout of the second substrate 20 of the photodetector 1 according to the fifth embodiment. Fig. 10A is a cross-sectional view taken along line A-A in Fig. 8, and Fig. 10B is a cross-sectional view taken along line B-B in Fig. 9.

[0085] The photodetector 1 according to the fifth embodiment includes adjustment wiring layers (second wiring layers) 15 (15a, 15b) arranged along at least some of the TG wiring layers TGW of the plurality of TG wiring layers TGW0-TGW3, TGW4-TGW7 extending in the second direction Y from the plurality of TG contacts (second contacts) TGC0-TGC3, TGC4-TGC7 aligned in the first direction X. The adjustment wiring layers 15 adjust the parasitic capacitance between the plurality of TG wiring layers TGW0-TGW3, TGW4-TGW7 and the FD contacts FDC0, FDC1. The adjustment wiring layers 15 are arranged in locations where variations in the parasitic capacitance between the plurality of TG wiring layers TGW and the FD contacts (first contacts) FDC are reduced. For example, as shown in FIG. 10B , the adjustment wiring layers 15 are arranged in an intermediate layer 70 between the first substrate 10 and the second substrate 20.

[0086] For example, a plurality of TG wiring layers TGW are arranged around the FD contacts FDC, and a plurality of adjustment wiring layers 15 are arranged along two or more TG wiring layers TGW.

[0087] In FIG. 8, a first adjustment wiring layer 15a is arranged between the two TG wiring layers TGW1, TGW2 that are closest to the FD wiring layers FDW0, FDW1 that connect two FD contacts FDC0, FDC1 that are arranged approximately in the center of one pixel block, and a second adjustment wiring layer 15b is arranged between the two TG wiring layers TGW5, TGW6 that are similarly closest to these two FD contacts FDC0, FDC1.

[0088] 11 is a diagram showing the parasitic capacitance between the FD wiring layer FDW, the TG wiring layer TGW, and the adjustment wiring layer 15. As shown in the figure, a parasitic capacitance occurs between the FD wiring layer FDW and the TG wiring layer TGW, and the magnitude of the parasitic capacitance varies depending on the distance between the FD wiring layer FDW and the TG wiring layer TGW. In particular, the closer the TG wiring layer TGW is located to the FD wiring layer FDW, the larger the parasitic capacitance becomes. In the fifth embodiment, an adjustment wiring layer 15 is located between two TG wiring layers TGW that are located opposite the FD wiring layer FDW. This generates a new parasitic capacitance between each TG wiring layer TGW and the adjustment wiring layer 15, thereby reducing the variation in parasitic capacitance between the FD wiring layer FDW and multiple TG wiring layers TGW.

[0089] In Figures 8 and 11, of the multiple TG wiring layers TGW arranged along the first direction X, an adjustment wiring layer 15 is arranged between two adjacent TG wiring layers TGW, but the location of the adjustment wiring layer 15 does not necessarily have to be the same as in Figures 8 and 11, and it is desirable to arrange the adjustment wiring layer 15 in an optimal location depending on the degree of variation in parasitic capacitance between the FD wiring layer FDW and the multiple TG wiring layers TGW.

[0090] 10B , the dielectric constants of the multiple insulating layers arranged in the stacking direction are different. The dielectric constant K1 of the insulating layers in the first substrate 10 and the intermediate layer 70 is smaller than the dielectric constant K2 of the insulating layer on the second substrate 20 closer to the intermediate layer 70. The dielectric constant K3 of the insulating layer on the second substrate 20 farther from the intermediate layer 70 is smaller than the dielectric constants K1 and K2. Therefore, by arranging the adjustment wiring layer 15 in the region of the insulating layer with the larger dielectric constant K1 or K2, the variation in parasitic capacitance can be efficiently adjusted.

[0091] 12 is a diagram showing the arrangement locations and parasitic capacitances of the adjustment wiring layers 15 according to the first modification. As shown in Fig. 12, in the first modification, a first adjustment wiring layer 15a and a second adjustment wiring layer 15b are arranged in association with the two TG wiring layers TGW closest to the FD wiring layer FDW, and a third adjustment wiring layer 15c and a fourth adjustment wiring layer 15d are arranged in association with the two TG wiring layers TGW closest to the FD wiring layer FDW.

[0092] The first adjustment wiring layer 15a and the second adjustment wiring layer 15b are not disposed between two TG wiring layers TGW, but are disposed so as to sandwich the two TG wiring layers TGW therebetween. Similarly, the third adjustment wiring layer 15c and the fourth adjustment wiring layer 15d are not disposed between two TG wiring layers TGW, but are disposed so as to sandwich the two TG wiring layers TGW therebetween.

[0093] 13 is a diagram showing the arrangement location and parasitic capacitance of the adjustment wiring layer 15 according to the second modification. In the second modification, the adjustment wiring layer 15 is arranged between two TG wiring layers TGW adjacent to each other in the first direction X. The example of FIG. 13 includes four TG wiring layers TGW arranged in the first direction X, three adjustment wiring layers 15a, 15b, and 15c arranged between the two adjacent TG wiring layers TGW, and four TG wiring layers TGW similarly arranged in the first direction X, and three adjustment wiring layers 15d, 15e, and 15f arranged between the two adjacent TG wiring layers TGW.

[0094] The shapes and sizes of the adjustment wiring layers 15 shown in Figures 11 to 13 are arbitrary. Figure 14 is a diagram showing various modified shapes and sizes of the adjustment wiring layers 15. Although Figure 14 shows a plurality of adjustment wiring layers 15 with different widths and lengths, these are merely examples, and adjustment wiring layers 15 having at least one of other shapes and sizes may be disposed.

[0095] 15 is a diagram showing the arrangement locations and parasitic capacitances of the adjustment wiring layers 15 according to the third modification. In the third modification, a plurality of adjustment wiring layers 15a to 15f are arranged between two TG wiring layers TGW adjacent to each other in the first direction X and on the opposite side thereof.

[0096] The adjustment wiring layer 15 according to the fifth embodiment may be a wiring layer for a power supply voltage, a wiring layer for a ground voltage, a wiring layer for a boost voltage, a wiring layer for a floating diffusion region, or a wiring layer for a conversion efficiency switching signal. In this specification, the adjustment wiring layer electrically connected to the wiring layer for a floating diffusion region is referred to as Sub_FD.

[0097] The adjustment wiring layer 15 according to the fifth embodiment is made of any conductive material such as polysilicon, tungsten (W), copper (Cu), or aluminum (Al).

[0098] In the fifth embodiment, the insulating layer disposed between the adjustment wiring layer 15 and the TG wiring layer TGW has a larger parasitic capacitance as the dielectric constant increases, and therefore has a greater effect in suppressing the variation in parasitic capacitance between the FD wiring layer FDW and the multiple TG wiring layers TGW.

[0099] FIG. 16 is a circuit diagram of a pixel circuit 22 of a photodetector 1 according to a fifth embodiment. The pixel circuit 22 in FIG. 16 has a Recta structure. In FIG. 16, components common to those in FIG. 2 are assigned the same reference numerals, and the following description will focus on the differences. As shown in FIG. 16, the pixel circuit 22 according to the fifth embodiment includes an adjustment wiring layer (Sub_FD) 15 connected between the source of the reset transistor RST and the drain of the conversion efficiency switching transistor FDG. In this way, the adjustment wiring layer 15 in FIG. 16 is disposed on a path connecting the reset transistor RST and the conversion efficiency switching transistor FDG in series.

[0100] Fig. 17 is a circuit diagram of a pixel circuit 22 of a photodetector 1 according to a modified example of the fifth embodiment. The pixel circuit 22 in Fig. 17 includes a reset transistor RST and a conversion efficiency switching transistor FDG connected in parallel. An adjustment wiring layer (Sub_FD) 15 is connected to the source of the conversion efficiency switching transistor FDG. The adjustment wiring layer 15 can be connected to a power supply voltage VDD node.

[0101] In this way, in the fifth embodiment, the adjustment wiring layer 15 is disposed along at least one of the plurality of TG wiring layers TGW, which generates a new parasitic capacitance between the adjustment wiring layer 15 and the TG wiring layer TGW, thereby making it possible to suppress variations in the parasitic capacitance between the FD contact FDC (FD wiring layer FDW) and the plurality of TG wiring layers TGW.

[0102] Sixth Embodiment A sixth embodiment is characterized in that a plurality of contacts that connect the first substrate 10 and the second substrate 20 are arranged in a position that does not face the pixel transistors in a plan view.

[0103] 18A is a layout diagram of the second substrate 20 of the photodetector 1 according to the sixth embodiment, and Fig. 18B is a layout diagram of the second substrate 20 of the photodetector 1 according to a comparative example. The locations of the arrangement regions of the amplification transistors AMP differ between Fig. 18A and Fig. 18B.

[0104] 18A, the arrangement region of the amplifier transistor AMP is arranged so as not to face the TG contact TGC. The dashed line in Fig. 18A indicates the location of the arrangement region of the amplifier transistor AMP according to a comparative example shown in Fig. 18B.

[0105] In the comparative example, the arrangement region of the amplifier transistor AMP is disposed opposite the TG contact TGC, so the parasitic capacitance between the arrangement region of the APM transistor and the TG contact TGC increases, and the variation in the parasitic capacitance between the FD contact FDC and the TG wiring increases. In contrast, in the sixth embodiment, the arrangement region of the amplifier transistor AMP is disposed in a location that does not face the TG contact TGC, so the variation in the parasitic capacitance between the FD contact FDC and the TG wiring can be suppressed.

[0106] Fig. 19A is a cross-sectional view taken along line A-A in Fig. 18A, and Fig. 19B is a cross-sectional view taken along line B-B in Fig. 18B. The amplifier transistor AMP according to this embodiment shown in Fig. 19A does not have a TG contact TGC arranged opposite it. In contrast, the amplifier transistor AMP according to a comparative example shown in Fig. 19B has a TG contact TGC arranged opposite it, and the parasitic capacitance between this TG contact TGC is larger than the parasitic capacitance between other TG contacts TGC and the amplifier transistor AMP.

[0107] Figure 18A shows a layout diagram of one pixel block with a Recta structure, but the layout differs depending on the arrangement direction of the amplifier transistor AMP and the select transistor SEL within one pixel block. Figure 20A is a layout diagram when the amplifier transistor AMP and the select transistor SEL are arranged horizontally, and Figure 20B is a layout diagram when the amplifier transistor AMP and the select transistor SEL are arranged vertically. The layout in Figure 20A is basically the same as the layout in Figure 18A. Here, horizontal arrangement means that the amplifier transistor AMP and the select transistor SEL are arranged in a first direction X (horizontal direction), and vertical arrangement means that the amplifier transistor AMP and the select transistor SEL are arranged in a second direction Y (vertical direction).

[0108] 20A and 20B, the amplification transistor AMP and the TG contact TGC are not disposed opposite each other, so there is no risk that the parasitic capacitance between the amplification transistor AMP and one of the TG contacts TGC will be larger than the parasitic capacitance between the amplification transistor AMP and the other TG contact TGC. This makes it possible to suppress variations in the parasitic capacitance between the FD contact FDC and the multiple TG wirings TGW.

[0109] 21 is a diagram illustrating the positional relationship between the amplifier transistor AMP and the TG contacts TGC when the amplifier transistor AMP and the select transistor SEL are arranged horizontally. In this embodiment, the TG contacts TGC are not arranged in locations facing each side of the rectangular arrangement region of the amplifier transistor AMP (regions marked "prohibited" in FIG. 21). The TG contacts TGC are arranged in regions diagonally opposite the amplifier transistor AMP, i.e., regions facing the four corners of the rectangular region.

[0110] More specifically, the TG contact TGC is disposed in a region facing at least one of the four corners of the rectangular region of the amplification transistor AMP.

[0111] 22 is a diagram illustrating the positional relationship between the amplifier transistor AMP and the TG contact TGC when the amplifier transistor AMP and the select transistor SEL are vertically disposed. In the case of Fig. 22 as well, the TG contact TGC is disposed in a region facing at least one of the four corners of the rectangular region of the amplifier transistor AMP.

[0112] In the above explanation, an example was described in which the TG contact TGC is arranged so as not to face each side of the rectangular arrangement area of ​​the amplification transistor AMP, but the TG contact TGC may also be arranged so as not to face the arrangement area of ​​at least one pixel transistor other than the amplification transistor AMP.

[0113] In this way, in the sixth embodiment, by arranging the TG contact TGC so as not to face each side of the arrangement region of at least one pixel transistor, it is possible to suppress variations in the parasitic capacitance between the FD contact FDC and a plurality of TG wirings.

[0114] Seventh Embodiment The pixel transistor in the photodetector 1 according to the first to sixth embodiments described above may have any structure, and various structures may be used. Fig. 23A is a perspective view showing the structure of a planar pixel transistor. In a planar pixel transistor, the drain region and source region are diffusion regions, and a gate electrode is disposed thereon with a gate insulating film sandwiched therebetween. The gate electrode is made of a conductive material such as polysilicon, metal, or metal silicide.

[0115] 23B is a perspective view showing the structure of a fin-type pixel transistor. The fin-type pixel transistor has a semiconductor layer in which a source region and a drain region are formed, which is disposed on, for example, SOI (Silicon On Insulator), and a gate electrode disposed across this semiconductor layer. Since the gate voltage is applied from the periphery of the channel, the fin-type pixel transistor can achieve lower power consumption and improved operating speed than a planar-type pixel transistor.

[0116] 23C is a perspective view showing the structure of a GAA (Gate-All-Around) pixel transistor. In a GAA pixel transistor, the entire periphery of the channel is covered with a gate electrode, which enables lower power consumption and improved operating speed compared to a fin-type pixel transistor.

[0117] 23D is a plan view showing the structure of an L-type transfer transistor TR. The L-type transfer transistor TR has gate electrodes extending in two directions perpendicular to each other. Since the gate electrodes face the photoelectric conversion region on two sides in a plan view, the charges photoelectrically converted by the photoelectric conversion element PD can be efficiently collected, thereby improving quantum efficiency.

[0118] Eighth Embodiment The photodetector 1 according to the first to sixth embodiments described above can be applied to pixels 12 having various pixel structures. Below, first to third examples of representative pixel structures that can be applied to the photodetector 1 according to the first to sixth embodiments will be described in order. Note that the pixel structures that can be applied to the photodetector 1 according to the first to sixth embodiments are not limited to the first to third examples shown below.

[0119] FIG. 24 is a plan view showing a first example of a pixel structure applicable to the photodetector 1 according to the first to sixth embodiments. The pixel structure according to the first example is called a Recta structure. As shown in FIG. 24 , one pixel block of the Recta structure has a total of eight pixels, four pixels in a first direction X (e.g., the horizontal direction) and two pixels in a second direction Y (e.g., the vertical direction). Color filters of the same color are arranged on two pixels 12 adjacent to each other in the first direction X, and these two pixels 12 are the left phase difference detection pixel 12 and the right phase difference detection pixel 12. Of the eight pixels, four diagonally adjacent pixels 12 are arranged with green color filters, the remaining two pixels 12 are arranged with red color filters, and the remaining two pixels 12 are arranged with blue color filters. In FIG. 24 , the red, green, and blue color filters are denoted as R, G, and B, respectively.

[0120] The right side of Figure 24 shows an enlarged planar configuration of one pixel block of the Recta structure. One pixel block of the Recta structure has two pixels 12 arranged in the first direction X and two pixels 12 arranged in the second direction Y. These two pixels 12 share one floating diffusion region FD. Since one pixel block of the Recta structure has 2 x 4 = 8 pixels, two floating diffusion regions FD are provided in one pixel block. A transfer transistor TR is provided for each pixel 12. A TG contact TGC is provided extending from the arrangement region of the transfer gate TRG of the transfer transistor TR to the intermediate layer 70. The pixel transistor is shared by eight pixels 12. Contacts CT for power supply voltage, ground voltage, etc. are provided at the corners of the pixel region of each pixel 12.

[0121] FIG. 25 is a plan view showing a second example of a pixel structure applicable to the photodetector 1 according to the first to sixth embodiments. The pixel structure according to the second example is called an Octa structure. One pixel block of the Octa structure has a total of 32 pixels, 8 pixels in the first direction X and 4 pixels in the second direction Y. Color filters of the same color are arranged on two pixels 12 adjacent to each other in the first direction X, and these two pixels 12 are a left phase difference detection pixel and a right phase difference detection pixel. The 32 pixels are divided into four small pixel blocks, each consisting of 2 × 4 = 8 pixels. Green color filters are arranged on two diagonally arranged small pixel blocks, a red color filter is arranged on the remaining small pixel block, and a blue color filter is arranged on the remaining small pixel block.

[0122] In the Octa structure, 2 × 2 = 4 pixels share one floating diffusion region FD. Since one pixel block in the Octa structure has 32 pixels, one pixel block has eight floating diffusion regions FD. Each pixel 12 has a transfer transistor TR, and a TG contact TGC is arranged extending from each transfer gate of each transfer transistor TR to the intermediate layer 70.

[0123] 26 is a plan view showing a third example of a pixel structure applicable to the photodetector 1 according to the first to sixth embodiments. The pixel structure according to the third example is called a square pixel structure. One pixel block of the square pixel structure has 4 × 4 = 16 pixels. The 16 pixels are divided into four small pixel blocks, each consisting of 2 × 2 = 4 pixels, and green color filters are arranged in two small pixel blocks arranged diagonally, a red color filter is arranged in the remaining small pixel block, and a blue color filter is arranged in the remaining small pixel block.

[0124] In the square pixel structure, 2 × 2 = 4 pixels share one floating diffusion region FD. Since one pixel block in the square pixel structure has 16 pixels, one pixel block has four floating diffusion regions FD. Each pixel 12 has a transfer transistor TR, and a TG contact TGC is arranged extending from each transfer gate of each transfer transistor TR to the intermediate layer 70.

[0125] Ninth Embodiment When the photodetector 1 according to the first to sixth embodiments described above has a pixel 12 with a Recta structure, the pixel circuit 22 may have a circuit configuration in which the reset transistor RST and the conversion efficiency switching transistor FDG are connected in series as shown in FIG. 16 , or may have a circuit configuration in which the reset transistor RST and the conversion efficiency switching transistor FDG are connected in parallel as shown in FIG. 17 .

[0126] The layout of the first substrate 10 is the same when the reset transistor RST and the conversion efficiency switching transistor FDG are connected in series and when they are connected in parallel, but the layout of the second substrate 20 is different.

[0127] Fig. 27A is a layout diagram of the second substrate 20 when the reset transistor RST and the conversion efficiency switching transistor FDG are connected in series, and Fig. 27B is a layout diagram of the second substrate 20 when the reset transistor RST and the conversion efficiency switching transistor FDG are connected in parallel. Note that Figs. 27A and 27B are examples of the second substrate 20, and various layout changes are possible.

[0128] The pixel circuit 22 in the photodetector 1 according to the first to sixth embodiments described above may have a circuit configuration in which the conversion efficiency switching transistor FDG is omitted from the circuit configuration of FIG. 2, FIG. 16, or FIG.

[0129] Fig. 28 is a circuit diagram showing a modified circuit configuration of the pixel circuit 22 for one pixel block having a Recta structure that can be applied to the photodetector 1 according to the first to sixth embodiments. The pixel circuit 22 in Fig. 28 has a circuit configuration in which the conversion efficiency switching transistor FDG is omitted from that shown in Fig. 2. The source of the reset transistor is connected to the floating diffusion region FD.

[0130] Fig. 29 is a layout diagram of the second substrate 20 for one pixel block shown in Fig. 28. The layout in Fig. 29 is an example, and various modifications are possible.

[0131] (Tenth embodiment) When the photodetector 1 has a stacked structure of a first substrate 10 and a second substrate 20 as shown in FIG. 3, the length of the contact extending from the floating diffusion region FD arranged on the first substrate 10 to the wiring layer of the second substrate 20 becomes long, which may cause capacitive coupling between adjacent floating diffusion regions FD, making it impossible to accurately read out the charges held in the floating diffusion regions FD.

[0132] Fig. 30 is a layout diagram of the photodetector 1 according to the tenth embodiment. Fig. 31 is a cross-sectional view taken along line AA' in Fig. 30.

[0133] The photodetector 1 according to the tenth embodiment includes two first contacts FDC1 connected to two floating diffusion regions FD spaced apart along the first direction X and extending in the stacking direction, two first wiring layers FDW connected to the first contacts FDC1, a second wiring layer SHW arranged between the two first wiring layers FDW, a plurality of second contacts FDC2 extending in the stacking direction from the two first wiring layers FDW, and a third contact SHC extending in the stacking direction from the second wiring layer SHW.

[0134] Hereinafter, the first wiring layer FDW may be referred to as an FD wiring layer, and the second wiring layer SHW may be referred to as a shield layer. As will be described later, the second wiring layer SHW (shield layer) is provided to prevent capacitive coupling between two floating diffusion regions FD adjacent to each other in the first direction X.

[0135] The floating diffusion region FD according to the tenth embodiment is shared by a plurality of photoelectric conversion elements and holds the charges transferred from the plurality of photoelectric conversion elements.

[0136] 3 , the photodetector 1 according to the tenth embodiment includes a first substrate 10, an intermediate layer 70, and a second substrate 20, which are stacked one on top of the other. Two floating diffusion regions FD adjacent to each other in the first direction X are disposed on the first substrate 10. A first contact FDC1, a first wiring layer FDW, and a second wiring layer SHW are disposed on the intermediate layer 70. A second contact FDC2 and a third contact SHC are disposed on the second substrate 20. Hereinafter, the intermediate layer 70 may be referred to as a wiring region 70. In the wiring region 70, wiring layers and contacts for various signals transmitted and received between the first substrate 10 and the second substrate 20 are mainly disposed.

[0137] The photodetector 1 according to the tenth embodiment includes two or more floating diffusion regions FD arranged along the first direction X, but the following description focuses on two floating diffusion regions FD adjacent to each other in the first direction X and the structure surrounding them. Similar structures are repeatedly arranged along the first direction X.

[0138] The two first wiring layers FDW and the second wiring layer SHW connected to the two first contacts FDC1 adjacent in the first direction X are arranged along the first direction X. More specifically, the two first wiring layers FDW and at least a part of the second wiring layer SHW are arranged in a line along the first direction X.

[0139] The second wiring layer SHW is set to, for example, a predetermined voltage. The predetermined voltage is arbitrary, but may be, for example, a power supply voltage. Two first wiring layers FDW adjacent to each other in the first direction X are electrically connected to two floating diffusion regions FD via two first contacts FDC1 extending in the stacking direction. By disposing the second wiring layer SHW between the two first wiring layers FDW, capacitive coupling between the two first wiring layers FDW can be prevented.

[0140] 30 , the second wiring layer SHW extends in a second direction Y intersecting the first direction X. The third contact SHC extending from the second wiring layer SHW in the stacking direction may be a columnar shape extending in the stacking direction, or a wall shape extending in the stacking direction and the second direction Y. In other words, the shape of the third contact SHC is arbitrary. The second wiring layer SHW is, for example, a polysilicon layer. Note that the material of the second wiring layer SHW is not limited to a polysilicon layer.

[0141] FIG. 32A is a diagram showing a first example of the cross-sectional shape of the third contact SHC according to the tenth embodiment, and FIG. 32B is a diagram showing a second example of the cross-sectional shape of the third contact SHC.

[0142] 32A , the third contact SHC has a wall-like structure extending in the second direction Y and the stacking direction. This results in the second wiring layer SHW and the third contact SHC being disposed between two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2 that are adjacent to each other in the first direction X, and makes it possible to prevent capacitive coupling between the two floating diffusion regions FD, the two first contacts FDC1, the two first wiring layers FDW, and the two second contacts FDC2.

[0143] 32B includes a plurality of third contacts SHC that extend in the stacking direction and are connected to, at a distance from, second wiring layers SHW that extend in the second direction Y. There are no limitations on the number or spacing of the third contacts SHC. These third contacts SHC have a columnar structure. These third contacts SHC and second wiring layers SHW are arranged between two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and multiple second contacts FDC2 that are adjacent in the first direction X. This makes it possible to prevent capacitive coupling between the two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2.

[0144] Fig. 33 is a layout diagram of a photodetector 1 according to a modified example of the tenth embodiment, and Fig. 34 is a cross-sectional view taken along line A-A' in Fig. 33. The photodetector 1 according to the modified example shown in Figs. 33 and 34 differs from those in Figs. 30 and 31 in the structures of the second wiring layer SHW and the third contact SHC.

[0145] Two second wiring layers SHW are arranged between two first wiring layers FDW adjacent to each other in the first direction X. These two second wiring layers SHW are electrically connected to different transfer gates TRG (TRG4 in this case) via different fourth contacts TGC. Two third contacts SHC extending in the stacking direction are connected to these two second wiring layers SHW.

[0146] In this way, in one modification, at least a portion of the two first wiring layers FDW and the two second wiring layers SHW are arranged in a line along the first direction X.

[0147] The floating diffusion region FD and the transfer gate TRG are disposed on the first substrate 10. A first contact FDC1 connected to the floating diffusion region FD, a first wiring layer FDW connected to the first contact FDC1, a fourth contact TGC connected to the transfer gate TRG, and a second wiring layer SHW connected to the fourth contact TGC are disposed on the intermediate layer 70. A second contact FDC2 connected to the first wiring layer FDW and a third contact SHC connected to the second wiring layer SHW are disposed on the second substrate 20.

[0148] In one modification, the second wiring layer SHW is connected to the transfer gate TRG via the fourth contact TGC, and therefore has the same potential as the transfer gate TRG. The fourth contact TGC, the second wiring layer SHW (shield layer), and the third contact SHC are arranged between two floating diffusion regions FD adjacent to each other in the first direction X, and therefore, capacitive coupling between these two floating diffusion regions FD can be prevented.

[0149] The third contact SHC connected to the second wiring layer SHW in one modification has, for example, the same structure and arrangement as those in FIG. 32A or FIG. 32B.

[0150] As described above, in the tenth embodiment, the second wiring layer SHW (shield layer) is disposed between the two first contacts FDC1 and the two first wiring layers FDW connected to the two floating diffusion regions FD adjacent in the first direction X. Furthermore, the third contact SHC extending from the second wiring layer SHW in the stacking direction is disposed between the two second contacts FDC2 extending from the two first wiring layers FDW in the stacking direction. The second wiring layer SHW and the third contact SHC are set to, for example, a predetermined potential or the same potential as the transfer gate TRG. By arranging the second wiring layer SHW and the third contact SHC between two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2 adjacent to each other in the first direction X, it is possible to prevent capacitive coupling between the two floating diffusion regions FD, the two first contacts FDC1, the two first wiring layers FDW, and the two second contacts FDC2.

[0151] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0152] FIG. 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0153] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0154] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0155] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0156] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0157] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0158] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0159] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0160] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0161] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0162] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 35, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0163] FIG. 36 is a diagram showing an example of the installation position of the imaging unit 12031.

[0164] In FIG. 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0165] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0166] 36 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0167] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0168] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0169] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0170] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0171] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 among the components described above. Specifically, by applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0172] The present technology may have the following configurations: (1) A photodetector comprising: a plurality of photoelectric conversion elements, each accumulating a charge corresponding to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending from the floating diffusion region in a stacking direction; a plurality of second contacts extending from gates of the plurality of transfer transistors in the stacking direction; and a plurality of first wiring layers connected to the plurality of second contacts, respectively, wherein first wiring layers connected to some of the second contacts of the plurality of first wiring layers extend to a position closer to the first contacts than first wirings connected to the other second contacts. (2) The photodetector according to (1), further comprising: a plurality of third contacts extending from the plurality of first wiring layers in the stacking direction, wherein the first wiring layers are connected to corresponding third contacts and extend to a position closer to the first contacts than the connection points with the corresponding third contacts. (3) The photodetector according to (1) or (2), wherein at least two of the plurality of second contacts are arranged in one direction, and the two first wiring layers connected to the two second contacts arranged on both sides of the one direction extend to a position closer to the first contacts than the first wiring layers connected to the other second contacts. (4) The photodetector according to (3), wherein the photodetector includes two floating diffusion regions shared by the plurality of photoelectric conversion elements and arranged in the one direction, and two first contacts are connected to the two floating diffusion regions, and the first wiring layer arranged on one end side of the one direction is arranged to a position closer to the first contacts arranged on one end side of the one direction than the other first wiring layers, and the first wiring layer arranged on the other end side of the one direction is arranged to a position closer to the first contacts arranged on the other end side of the one direction than the other first wiring layers.(5) The photodetector according to (4), further comprising: two second wiring layers connected to the two first contacts extending from the two floating diffusion regions in a stacking direction and arranged along the two first wiring layers arranged on one end side and the other end side in the one direction. (6) The photodetector according to (5), further comprising: a fourth contact connecting the two second wiring layers together. (7) The photodetector according to any one of (1) to (6), further comprising: an amplifier transistor that generates a pixel signal according to charges held in the floating diffusion region; and a fourth wiring layer connected to the first contacts and arranged in a direction away from the amplifier transistor in a planar view. (8) A photodetector comprising: a plurality of photoelectric conversion elements, each accumulating a charge corresponding to the amount of incident light, a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements, a plurality of transfer transistors transferring the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region, a first contact extending from the floating diffusion region in a stacking direction, a plurality of second contacts extending in the stacking direction from gates of the plurality of transfer transistors, a plurality of first wiring layers connected to the plurality of second contacts, and a second wiring layer arranged along at least some of the first wiring layers among the plurality of first wiring layers and adjusting capacitance between the plurality of first wiring layers and the first contacts. (9) The photodetector according to (8), wherein the second wiring layer is arranged in a position where variation in capacitance between the plurality of first wiring layers and the first contacts is reduced. (10) The photodetector according to (8) or (9), wherein the plurality of first wiring layers are arranged around the first contact, and the plurality of second wiring layers are arranged along two or more of the first wiring layers. (11) The photodetector according to (8) or (9), wherein the second wiring layer is arranged between two of the plurality of first wiring layers that are adjacent to each other. (12) The photodetector according to (11), wherein the second wiring layer is arranged at a location facing the first contact.(13) The photodetector according to any one of (8) to (12), comprising: a first substrate on which the photoelectric conversion element, the transfer transistor, and the floating diffusion region are arranged; and a second substrate stacked on the first substrate and on which a pixel transistor used to generate a pixel signal according to the charge held in the floating diffusion region is arranged, wherein the first wiring layer and the second wiring layer are arranged in a first wiring region between the first substrate and the second substrate. (14) The photodetector according to (13), comprising: a second wiring region arranged on the second substrate opposite to the first substrate and having a third wiring layer, wherein a first insulating layer covering the first wiring layer and the second wiring layer in the first wiring region has a higher dielectric constant than a second insulating layer covering the third wiring layer in the second wiring region. (15) The photodetector according to any one of (8) to (14), wherein the second wiring layer transmits a boost voltage, a power supply voltage, a ground voltage, or a signal connected to a conversion efficiency switching transistor. (16) The photodetector according to any one of (8) to (15), wherein the second wiring layer includes polysilicon, tungsten (W), copper (Cu), or aluminum (Al). (17) A photodetector comprising: a plurality of photoelectric conversion elements, each accumulating a charge corresponding to an amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first substrate on which the photoelectric conversion elements, the transfer transistors, and the floating diffusion region are arranged; a second substrate stacked on the first substrate and on which pixel transistors used to generate pixel signals corresponding to the charge held in the floating diffusion region are arranged; and a plurality of contacts connecting the first substrate and the second substrate, wherein at least one transistor constituting the pixel transistor is arranged so as not to face the plurality of contacts in a plan view. (18) The photodetector according to (17), wherein the pixel transistor arrangement region has a rectangular shape in a plan view, and at least one transistor constituting the pixel transistor is arranged in a location where none of the sides of the transistor arrangement region faces the plurality of contacts.(19) The photodetector according to (18), wherein the plurality of contacts are arranged diagonally across the pixel transistor in a plan view. (20) The photodetector according to any one of (1) to (19), wherein the plurality of pixels share the floating diffusion region and the pixel transistor, and each of the plurality of pixels has the photoelectric conversion element, the floating diffusion region, and the transfer transistor, the pixel transistor has an amplification transistor, a selection transistor, a reset transistor, and a conversion efficiency switching transistor, the reset transistor and the conversion efficiency switching transistor are connected in series or in parallel, and the floating diffusion region is connected to a source of the conversion efficiency switching transistor and a gate of the amplification transistor, or to a source of the reset transistor, a drain of the conversion efficiency switching transistor, and a gate of the amplification transistor. (21) A photodetector comprising: a plurality of photoelectric conversion elements, each accumulating a charge corresponding to the amount of incident light; and a floating diffusion region shared by the plurality of photoelectric conversion elements and holding charge transferred from the plurality of photoelectric conversion elements, the photodetector comprising: two of the floating diffusion regions spaced apart in a first direction, two first contacts connected to the two floating diffusion regions, respectively, and extending in a stacking direction, two first wiring layers connected to the two first contacts, respectively, and spaced apart in the first direction, a second wiring layer spaced apart between the two first wiring layers along the first direction, a second contact extending from the first wiring layer in the stacking direction, and a third contact extending from the second wiring layer in the stacking direction. (22) The photodetector according to (21), wherein the two first wiring layers and at least a portion of the second wiring layer are arranged in a line along the first direction. (23) The photodetector according to (21) or (22), wherein two or more second wiring layers are arranged between the two first wiring layers along the first direction, and the third contact is connected to each of the two or more first wiring layers. (24) The photodetector according to any one of (21) to (23), wherein the second wiring layer and the third contact are set to a predetermined potential.(25) The photodetector according to any one of (21) to (24), comprising: a plurality of transfer transistors that transfer charges accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; and fourth contacts that extend in a stacking direction and connect transfer gates of the transfer transistors to the second wiring layer. (26) The photodetector according to any one of (21) to (25), wherein the second wiring layer extends in a second direction intersecting the first direction. (27) The photodetector according to (26), wherein the third contact extends in both the stacking direction and the second direction. (28) The photodetector according to (26), comprising: a plurality of the third contacts that are arranged at a distance from each other along the second direction of the second wiring layer. (29) The photodetector according to any one of (21) to (28), wherein at least one of the first wiring layer and the second wiring layer is a polysilicon layer. (30) A photodetector device according to any one of (21) to (29), comprising: a first substrate on which the photoelectric conversion element and the floating diffusion region are arranged; a second substrate stacked on the first substrate on which pixel transistors used to generate pixel signals according to the charges held in the floating diffusion region are arranged; and a wiring region arranged between the first substrate and the second substrate, wherein the two first contacts, the two first wiring layers, the two first wiring layers, and the second wiring layer are arranged in the wiring region, and the second contact and the third contact are arranged on the second substrate.

[0173] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0174] 1 Photodetector device, 10 First substrate, 11 Semiconductor substrate, 12 Pixel, 13 Pixel region, 14 Current source, 15 Adjustment wiring layer, 20 Second substrate, 21 Semiconductor substrate, 22 Pixel circuit, 23 Drive line, 23 Pixel drive line, 24 Vertical signal line, 30 Third substrate, 31 Semiconductor substrate, 32 Logic circuit, 33 Vertical drive circuit, 34 Column signal processing circuit, 35 Horizontal drive circuit, 36 System control circuit, 40 Color filter, 42 p-well layer, 43 Element isolation portion, 46 Insulating layer, 50 Light receiving lens, 51 Interlayer insulating layer, 52 Insulating layer, 53 Insulating layer, 54 Through wiring, 55 Connection wiring, 56 Wiring layer, 57 Insulating layer, 58 Pad electrode, 59 Connection portion, 61 Interlayer insulating layer, 62 Wiring layer, 63 Insulating layer, 64 Pad electrode, 70 Intermediate layer, 71 wiring layer

Claims

1. A photodetector comprising: a plurality of photoelectric conversion elements each accumulating charges according to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charges transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors transferring the charges accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending in the stacking direction from the floating diffusion region; a plurality of second contacts extending in the stacking direction from the gates of the plurality of transfer transistors; and a plurality of first wiring layers respectively connected to the plurality of second contacts, wherein among the plurality of first wiring layers, the first wiring layer connected to some of the second contacts extends closer to the first contact than the first wiring connected to the other second contacts.

2. The photodetector according to claim 1, further comprising a plurality of third contacts extending in the stacking direction from the plurality of first wiring layers, wherein the first wiring layer is connected to the corresponding third contact and extends closer to the first contact than the connection location with the corresponding third contact.

3. The photodetector according to claim 1, wherein at least two of the plurality of second contacts are arranged in one direction, and the two first wiring layers connected to the two second contacts arranged on both sides of the one direction extend closer to the first contact than the first wiring layers connected to the other second contacts.

4. The photodetector according to claim 3, further comprising two floating diffusion regions shared by the plurality of photoelectric conversion elements and arranged in the one direction, wherein two first contacts are connected to the two floating diffusion regions, the first wiring layer arranged on one end side of the one direction is arranged closer to the first contact arranged on the one end side than the other first wiring layers, and the first wiring layer arranged on the other end side of the one direction is arranged closer to the first contact arranged on the other end side than the other first wiring layers.

5. The photodetector according to claim 4, further comprising two second wiring layers respectively connected to the two first contacts extending in the stacking direction from the two floating diffusion regions and arranged along the two first wiring layers arranged on one end side and the other end side of the one direction.

6. The photodetection device according to claim 5, further comprising a fourth contact that connects the two second wiring layers to each other.

7. The photodetection device according to claim 1, further comprising an amplification transistor that generates a pixel signal according to the holding charge of the floating diffusion region, and a fourth wiring layer that is connected to the first contact and is arranged in a direction away from the amplification transistor in plan view.

8. A photodetection device comprising: a plurality of photoelectric conversion elements each accumulating charge according to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charge transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer the charge accumulated in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending in the stacking direction from the floating diffusion region; a plurality of second contacts extending in the stacking direction from the gates of the plurality of transfer transistors; a plurality of first wiring layers respectively connected to the plurality of second contacts; and a second wiring layer arranged along at least a part of the plurality of first wiring layers and adjusting the capacitance between the plurality of first wiring layers and the first contact.

9. The photodetection device according to claim 8, wherein the second wiring layer is arranged at a location where the variation in capacitance between the plurality of first wiring layers and the first contact is reduced.

10. The photodetection device according to claim 8, wherein the plurality of first wiring layers are arranged around the first contact, and a plurality of the second wiring layers are arranged along two or more of the first wiring layers.

11. The photodetection device according to claim 8, wherein the second wiring layer is arranged between two adjacent ones of the plurality of first wiring layers.

12. The photodetection device according to claim 11, wherein the second wiring layer is arranged at a location facing the first contact.

13. The photodetection device according to claim 8, comprising: a first substrate on which the photoelectric conversion element, the transfer transistor, and the floating diffusion region are arranged; and a second substrate laminated on the first substrate and on which a pixel transistor used to generate a pixel signal according to the holding charge of the floating diffusion region is arranged, wherein the first wiring layer and the second wiring layer are arranged in a first wiring region between the first substrate and the second substrate.

14. A second wiring region disposed on the side of the second substrate opposite to the first substrate and having a third wiring layer, wherein a dielectric constant of a first insulating layer covering the first wiring layer and the second wiring layer in the first wiring region is higher than a dielectric constant of a second insulating layer covering the third wiring layer in the second wiring region. The photodetection device according to claim 13.

15. The second wiring layer transmits a signal connected to a boosted voltage, a power supply voltage, a ground voltage, or a conversion efficiency switching transistor. The photodetection device according to claim 8.

16. The second wiring layer contains polysilicon, tungsten (W), copper (Cu), or aluminum (Al). The photodetection device according to claim 8.

17. A plurality of photoelectric conversion elements each accumulating charges corresponding to the amount of incident light, a floating diffusion region shared by the plurality of photoelectric conversion elements and holding the charges transferred from the plurality of photoelectric conversion elements, a plurality of transfer transistors transferring the charges accumulated in the plurality of photoelectric conversion elements to the floating diffusion region, a first substrate on which the photoelectric conversion elements, the transfer transistors, and the floating diffusion region are disposed, a second substrate laminated on the first substrate and on which pixel transistors used to generate a pixel signal according to the held charges of the floating diffusion region are disposed, and a plurality of contacts connecting the first substrate and the second substrate. At least one transistor constituting the pixel transistor is disposed at a location not facing the plurality of contacts in a plan view. A photodetection device.

18. An arrangement region of the pixel transistor is rectangular in a plan view, and at least one transistor constituting the pixel transistor is disposed at a location where none of the sides of the arrangement region of this transistor faces the plurality of contacts. The photodetection device according to claim 17.

19. The plurality of contacts are disposed in a diagonal direction of the pixel transistor in a plan view. The photodetection device according to claim 18.

20. A plurality of pixels sharing the floating diffusion region and the pixel transistor, each of the plurality of pixels having the photoelectric conversion element, the floating diffusion region, and the transfer transistor, the pixel transistor having an amplification transistor, a selection transistor, a reset transistor, and a conversion efficiency switching transistor, the reset transistor and the conversion efficiency switching transistor being connected in series or in parallel, the floating diffusion region being connected to the source of the conversion efficiency switching transistor and the gate of the amplification transistor, or being connected to the source of the reset transistor, the drain of the conversion efficiency switching transistor, and the gate of the amplification transistor, the photodetection device according to claim 1.

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