Semiconductor memory device using electric field effect of Anti-ferroelectric and manufacturing method thereof

Abstract

A semiconductor memory device according to the present disclosure comprises: a substrate; a hafnium zirconium oxide thin film formed by depositing hafnium oxide and zirconium oxide on the substrate; and a second electrode formed by depositing a metal on the hafnium zirconium oxide thin film, wherein an oxygen vacancy is formed in an upper portion of the hafnium zirconium oxide thin film.

Description

Semiconductor memory device and manufacturing method utilizing the electric field effect of an antiferroelectric

[0001] The disclosed subject matter relates to semiconductor memory devices, and more specifically, to semiconductor memory devices based on NAND arrays utilizing antiferroelectric field effects.

[0002]

[0003] Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application, and their inclusion in this section is not intended to be admitted as prior art.

[0004] Semiconductor memory devices are semiconductor devices used for data storage. Driven by the Fourth Industrial Revolution and the storage and processing of big data, semiconductor memory devices are finding expanded applications in areas such as IoT sensors, artificial intelligence, robotics, and the cloud. Semiconductor memory devices, designed to store large amounts of data, require low power consumption, high performance, and high-speed data processing.

[0005] Currently, Charge Trap Flash (CTF) is mainly used in NAND flash structures that enable high-density semiconductor memory devices. Charge Trap Flash can create data '0' and '1' depending on whether electrons are trapped or not in the floating gate, which is an insulator. However, although Charge Trap Flash has the feature of high-density, it has low endurance (~10) due to its electron tunneling-based operating principle. 6 ), slow operating speed (~ 1.5 ms), and high operating voltage (>10 V).

[0006] An alternative proposed for next-generation computing is memory devices using ferroelectrics. Ferroelectrics possess the property of maintaining electrical polarization even in the absence of an external electric field. Depending on the state of the electronic polarization, the basic data storage structure, "0" and "1," can be distinguished. Despite their excellent durability, fast operating speed, and low operating voltage, memory devices using ferroelectrics suffer from the inherent disadvantage of incapable of non-destructive read operations, a key feature of semiconductor memory devices (900), due to the nature of the material.

[0007]

[0008] The disclosed content aims to provide a semiconductor memory device capable of operating at high durability, high operating speed, low operating voltage, and non-destructive read operation essential for use as a memory semiconductor, by using an antiferroelectric material that forms an internal electric field through a defect process in the gate stack of a semiconductor memory device to solve the above-mentioned problems.

[0009]

[0010] A semiconductor memory device according to the present disclosure includes a substrate, a hafnium zirconium oxide thin film formed by depositing hafnium oxide and zirconium oxide on the substrate, and a second electrode formed by depositing metal on the hafnium zirconium oxide thin film, wherein an oxygen vacancy is formed on an upper portion of the hafnium zirconium oxide thin film.

[0011] As an example, the semiconductor memory device may further include a first electrode formed by depositing a metal between the substrate and the hafnium zirconium oxide thin film.

[0012] The above hafnium zirconium oxide thin film is Hf 1-x Z x 02(0.6 <x<1)의 조성비를 가지는 것을 특징으로 한다.

[0013] The above hafnium zirconium oxide thin film is characterized by depositing hafnium oxide and zirconium oxide in a solid solution form using ozone (O3) as an oxygen source to a thickness of 0.5 to 10 nm through atomic layer deposition (ALD).

[0014] It is characterized in that the following process is performed on the hafnium zirconium oxide thin film before depositing the second electrode.

[0015] - Deposition of metallic materials

[0016] - Annealing in nitrogen (N2) atmosphere

[0017] - Removal of the metallic material by etching with SC-1 solution (H2O: H2O2: NH3= 250: 10: 5)

[0018] A method for manufacturing a semiconductor memory device according to the present disclosure includes the steps of (A) etching a substrate using a 5% hydrofluoric acid (HF) aqueous solution diluted with distilled water, (B) depositing a hafnium zirconium oxide thin film using hafnium oxide and zirconium oxide on the substrate, (C) depositing a metallic material on the hafnium zirconium oxide thin film, (D) annealing in a nitrogen (N2) atmosphere after depositing the metallic material, (E) removing the metallic material by etching with an SC-1 solution (H2O: H2O2: NH3=250:10:5), and (F) depositing a second electrode using a metal on the hafnium zirconium oxide thin film. As an example, the method for manufacturing a semiconductor memory device may further include a step (G) of depositing a first electrode with metal on the substrate after step (A), and step (B) may be a step of depositing a hafnium zirconium oxide thin film with hafnium oxide and zirconium oxide on the first electrode.

[0019] The above step (B) is to set the temperature of the substrate to 230 to 320 oThe hafnium zirconium oxide thin film is characterized in that it is deposited to a thickness of 0.5 to 10 nm through atomic layer deposition (ALD) using a hafnium precursor and a zirconium precursor as metal precursors in a ratio of 0:10 to 4:6 while maintaining C and using ozone (O3) as an oxygen source.

[0020] The above step (C) is characterized in that the metallic material is made to have a thickness of 10 to 60 nm.

[0021] The above step (D) is 400 to 600 o It is characterized by being performed at a temperature of C for 10 to 60 seconds.

[0022] The above step (E) is 50 to 55 of the above etching o It is characterized by being performed at a temperature of C for 4 minutes.

[0023]

[0024] The semiconductor memory device according to the present disclosure forms an oxygen cavity on the upper portion of the hafnium zirconium oxide thin film within the gate stack, thereby forming an asymmetrical distribution of internal charges in the hafnium zirconium oxide thin film, thereby forming an electric field inside the device, which causes a shift in the hysteresis curve in the polarization-electric field graph, thereby forming an electric polarization even when there is no electric field, and thus can be utilized as a nonvolatile memory device.

[0025] The composition ratio of hafnium zirconium oxide thin film is Hf 1-x Z x 02(0.6 <x<1)됨으로써 하프늄 지르코늄 옥사이드 박막은 반강유전체의 성질을 가질 수 있다.

[0026] Before depositing the second electrode, an oxygen cavity can be formed on the hafnium zirconium oxide thin film by depositing a metallic material on the hafnium zirconium oxide thin film, annealing in a nitrogen (N2) atmosphere, and etching with an SC-1 solution (H2O: H2O2: NH3 = 250: 10: 5) to remove the metallic material.

[0027] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the detailed description of the present invention or the composition of the invention described in the claims.

[0028]

[0029] Figure 1 is a schematic diagram of a semiconductor memory device according to an embodiment.

[0030] Figure 2 is a hysteresis curve in a polarization-electric field graph according to the composition ratio of a hafnium zirconium oxide thin film of a semiconductor memory device according to an embodiment.

[0031] FIG. 3 is a diagram showing the movement of a hysteresis curve in a polarization-electric field graph according to work function control of a semiconductor memory device according to an embodiment.

[0032] FIG. 4 is a diagram showing an erase state and a program state of a semiconductor memory device according to an embodiment.

[0033] FIG. 5 is a diagram showing the principle of non-destructive read operation of a semiconductor memory device according to an embodiment.

[0034] Figure 6 is a table showing a performance comparison of a semiconductor memory device according to an embodiment with a conventional semiconductor memory device.

[0035] Figure 7 is a manufacturing process diagram of a semiconductor memory device according to an embodiment.

[0036]

[0037] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

[0038] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0039] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0040]

[0041] Hereinafter, a semiconductor memory device (900) and a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described in detail with reference to the attached drawings.

[0042] FIG. 1 is a schematic diagram of a semiconductor memory device (900) according to an embodiment, FIG. 2 is a hysteresis curve in a polarization-electric field graph according to the composition ratio of a hafnium zirconium oxide thin film (300) of a semiconductor memory device (900) according to an embodiment, FIG. 3 is a diagram showing the movement of a hysteresis curve in a polarization-electric field graph according to work function control of a semiconductor memory device (900) according to an embodiment, and FIG. 4 is a diagram showing an erase state and a program state of a semiconductor memory device according to an embodiment.

[0043] Referring to FIG. 1, a semiconductor memory device (900) according to an embodiment includes a substrate (100), a hafnium zirconium oxide thin film (300) in which hafnium oxide and zirconium oxide are deposited on the substrate (100), and a second electrode (400) in which a metal is deposited on the hafnium zirconium oxide thin film (300). As an embodiment, the semiconductor memory device (900) may further include a first electrode (200) in which a metal is deposited between the substrate (100) and the hafnium zirconium oxide thin film (300).

[0044] The substrate (100) may be a silicon-based substrate (100), and may be, for example, a P-type substrate. At this time, an N-type junction is formed on each of the two sides of the substrate (100), and a source electrode (10) and a drain electrode (20) are connected to the N-type junctions on each side. When an input voltage is formed between the source electrode (10) and the drain electrode (20), a channel may not be formed or may be formed depending on the electrical polarization state within the hafnium zirconium oxide thin film (300) of the semiconductor memory element (900), which will be described later, so that current may not flow within the silicon substrate (100) or may flow, thereby allowing data of “0” or “1” to be read.

[0045] The first electrode (200) is formed by depositing on the substrate (100). The first electrode (200) may be a metal such as TiN, Mo, SC, W, etc. The deposition of the first electrode (200) uses a sputtering method. As an example, when depositing TiN metal, the plasma power is 200 W, and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Mo metal, the plasma power is 200 W and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Sc metal, the plasma power is 150 W and the base pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing W metal, the plasma power is 150 to 200 W, and the basic pressure is 1 X 10 -6 Torr, process pressure is 1~5 X 10 -3 Deposited for 15 minutes under the condition of 10 Torr. As an example, the thickness of the first electrode (200) can be 10 to 60 nm.

[0046] A hafnium zirconium oxide thin film (300) is formed by depositing hafnium oxide and zirconium oxide in a solid solution form using ozone (O3) as an oxygen source on a substrate (100) or, in the case of including a first electrode, on a first electrode (200) through atomic layer deposition (ALD). The deposition thickness of the hafnium zirconium oxide thin film (300) can have an advantage in that the electric field becomes stronger as the thickness decreases due to the electric field characteristic being inversely proportional to the distance, thereby facilitating the generation of electrical polarization within the hafnium zirconium oxide thin film (300). As an example, the thickness of the hafnium zirconium oxide thin film (300) can be 0.5 to 10 nm.

[0047] Hafnium zirconium oxide thin film (300) is Hf 1-x Z x As 02, x corresponding to the composition ratio of hafnium and zirconium is 0.6 <x<1의 값을 가지는 것이 바람직하다. 도 2에서 보여지는 바와 같이, 하프늄 지르코늄 옥사이드 박막(300)은 하프늄과 지르코늄의 조성비에 따라 강유전체 특성 또는 반강유전체 특성을 가진다. 강유전체란 외부 전기장에 의해 발생한 전기적 분극이 외부 전기장이 사라진 뒤에도 유지되는 물질을 이른다. 반강유전체란 외부 전기장에 의해 전기적 분극이 발생하지만, 외부 전기장이 사라진 뒤에는 발생한 전기적 분극도 사라지는 물질을 이른다. 하프늄의 조성비가 0.4보다 큰 경우 하프늄 지르코늄 옥사이드 박막(300)은 도 2의 분극-전기장 그래프에서 이력곡선에서 볼 수 있듯이 강유전체 특성을 가진다. 하프늄의 조성비가 0.4 이하인 경우 하프늄 지르코늄 옥사이드 박막(300)은 도 2의 분극-전기장 그래프에서 이력곡선에서 볼 수 있듯이 반강유전체의 성질을 가진다.

[0048] When the hafnium zirconium oxide thin film (300) according to the embodiment is formed by the atomic layer deposition method as described above, the temperature of the substrate (100) is 230 to 320 o By maintaining C and using hafnium precursor and zirconium precursor as metal precursors in a ratio of 0:10 to 4:6, Hf 1-x Z x 02(0.6 <x<1)의 조성비를 가지는 하프늄 지르코늄 옥사이드 박막(300)을 형성할 수 있다.

[0049] Hafnium precursors may include [(CH3)(C2H5)N]4Hf(TEMAH) of the TEMA series and organoaminohafnium precursor compounds.Organoaminohafnium precursor compounds include tetrakis(ethylmethylamino)hafnium (TEMAH), trakis(dimethylamino)hafnium (TDMAH), tetrakis(diethylamino)hafnium (TDEAH), tetrakis(pyrrolidino)hafnium, cyclopentadienyltris(dimethylamino)hafnium (CpHf(NMe2)3), methylcyclopentadienyltris(dimethylamino)hafnium (MeCpHf(NMe2)3), ethylcyclopentadienyltris(dimethylamino)hafnium (EtCpHf(NMe2)3), cyclopentadienyltris(ethylmethylamino)hafnium (CpHf(NMeEt)3), Methylcyclopentadienyltris(ethylmethylamino)hafnium (MeCpHf(NMeEt)3), ethylcyclopentadienyltris(ethylmethylamino)hafnium (EtCpHf(NMeEt)3), cyclopentadienyltris(diethylamino)hafnium (CpHf(NEt2)3), methylcyclopentadienyltris(diethylamino)hafnium (MeCpHf(NEt2)3), ethylcyclopentadienyltris(diethylamino)hafnium (EtCpHf(NEt2)3), bis(cyclopentadienyl)bis(dimethylamino)hafnium (Cp2Hf(NMe2)2), bis(methylcyclopentadienyl)bis(dimethylamino)hafnium ((MeCp)2Hf(NMe2)2), Bis(ethylcyclopentadienyl)bis(dimethylamino)hafnium ((EtCp)2Hf(NMe2)2), bis(cyclopentadienyl)bis(ethylmethylamino)hafnium (Cp2Hf(NMeEt)2), bis(methylcyclopentadienyl)bis(ethylmethylamino)hafnium ((MeCp)2Hf(NMeEt)2), bis(ethylcyclopentadienyl)bis(ethylmethylamino)hafnium ((EtCp)2Hf(NMeEt)2), bis(cyclopentadienyl)bis(diethylamino)hafnium ((Cp2Hf(NEt2)2), bis(methylcyclopentadienyl)bis(diethylamino)hafnium ((MeCp)2Hf(NEt2)3) and It may include at least one selected from the group consisting of bis(ethylcyclopentadienyl)bis(diethylamino)hafnium ((EtCp)2Hf(NEt2)2).

[0050] The zirconium precursor may include [(CH3)(C2H5)N]4Zr(TEMAZ) of the TEMA series and organoamino zirconium precursor compounds. Organoaminozirconium precursor compounds include tetrakis(ethylmethylamino)zirconium (TEMAZ), tetrakis(dimethylamino)zirconium (TDMAZ), tetrakis(diethylamino)zirconium (TDEAZ), cyclopentadienyltris(dimethylamino)zirconium (CpZr(NMe2)3), methylcyclopentadienyltris(dimethylamino)zirconium (MeCpZr(NMe2)3), ethylcyclopentadienyltris(dimethylamino)zirconium (EtCpZr(NMe2)3), cyclopentadienyltris(ethylmethylamino)zirconium (CpZr(NMeEt)3), methylcyclopentadienyltris(ethylmethylamino)zirconium (MeCpZr(NMeEt)3), Ethylcyclopentadienyltris(ethylmethylamino)zirconium (EtCpZr(NMeEt)3), cyclopentadienyltris(diethylamino)zirconium (CpZr(NEt2)3), methylcyclopentadienyltris(diethylamino)zirconium (MeCpZr(NEt2)3), ethylcyclopentadienyltris(diethylamino)zirconium (EtCpZr(NEt2)3), bis(cyclopentadienyl)bis(dimethylamino)zirconium (Cp2Zr(NMe2)2), bis(methylcyclopentadienyl)bis(dimethylamino)zirconium ((MeCp)2Zr(NMe2)2), bis(ethylcyclopentadienyl)bis(dimethylamino)zirconium ((EtCp)2Zr(NMe2)2), It may include at least one selected from the group consisting of bis(cyclopentadienyl)bis(ethylmethylamino)zirconium (Cp2Zr(NMeEt)2), bis(methylcyclopentadienyl)bis(ethylmethylamino)zirconium ((MeCp)2Zr(NMeEt)2), bis(ethylcyclopentadienyl)bis(ethylmethylamino)zirconium ((EtCp)2Zr(NMeEt)2), bis(cyclopentadienyl)bis(diethylamino)zirconium ((Cp2Zr(NEt2)2), bis(methylcyclopentadienyl)bis(diethylamino)zirconium ((MeCp)2Zr(NEt2)3), and bis(ethylcyclopentadienyl)bis(diethylamino)zirconium ((EtCp)2Zr(NEt2)2).

[0051] The second electrode (400) is formed by depositing on a hafnium zirconium oxide thin film (300). The second electrode (400) may be a metal such as TiN, Mo, Sc, W, etc., like the first electrode (200) described above. The deposition of the second electrode (400) uses a sputtering method. As an example, when depositing TiN metal, the plasma power is 200 W, and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Mo metal, the plasma power is 200 W and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Sc metal, the plasma power is 150 W and the base pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing W metal, the plasma power is 150 to 200 W, and the basic pressure is 1 X 10 -6 Torr, process pressure is 1~5 X 10 -3 Deposited for 15 minutes under the condition of 10 Torr. As an example, the thickness (400) of the second electrode may be 10 to 60 nm.

[0052] Referring to FIG. 3, an oxygen cavity (310) is formed on the upper portion of the hafnium zirconium oxide thin film (300). The oxygen cavity (310) on the upper portion of the hafnium zirconium oxide thin film (300) is formed through the following process before depositing the second electrode (400).

[0053] - Deposition of metallic materials

[0054] - Annealing in nitrogen (N2) atmosphere

[0055] - Removal of the metallic material by etching with SC-1 solution (H2O: H2O2: NH3= 250: 10: 5)

[0056] The metallic material mentioned above can be a simple metal or a metal nitride. As an example, the metal nitride can be TiN. The metallic material is deposited using a sputtering method, with a plasma power of 1200 W and a base pressure of 3 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit the metallic material for 15 minutes under conditions of 10 Torr. As an example, the thickness of the metallic material can be 10 to 60 nm.

[0057] After that, annealing in a nitrogen (N2) atmosphere is performed at a temperature of, for example, 400 to 600°C for 10 to 60 seconds. After annealing, the metallic material is removed by etching with an SC-1 solution. For example, etching is performed at a temperature of 50 to 55°C for 4 minutes. The SC-1 solution is a solution made by mixing H2O, H2O2, and NH3, and is used to remove the metallic material through a cleaning process that repeats oxidation of the metal with hydrogen peroxide and etching with ammonia water.

[0058] As a process prior to the deposition of the second electrode (400) described above, oxygen cavities (310) are formed on the upper portion of the hafnium zirconium oxide thin film (300), and an asymmetric distribution of charges in the hafnium zirconium oxide thin film (300) is formed due to the oxygen cavities (310). As a result, an electric field is formed inside the hafnium zirconium oxide thin film (300), and due to this electric field, a hysteresis curve shifts in the polarization-electric field graph, as shown in FIG. 3. Since the work function of the substrate (100) becomes greater than the work function of the second electrode (400) due to the oxygen cavities (310) on the hafnium zirconium oxide thin film (300), the hysteresis curve shifts in the minus direction with respect to the axis of the electric field.

[0059] Referring to FIG. 4, when a positive voltage greater than a certain level is applied to the second electrode (400), downward electrical polarization occurs in the hafnium zirconium oxide thin film (300), and even when the voltage applied to the second electrode (400) disappears, a certain amount of downward electrical polarization remains. This state is called an erase state. In this state, when a negative voltage less than a certain level is applied to the second electrode (400), upward electrical polarization occurs in the hafnium zirconium oxide thin film (300), and when the negative voltage applied to the second electrode (400) disappears, the electrical polarization almost disappears. This state is called a program state. In this way, even when the voltage applied to the second electrode (400) disappears, the two aforementioned states of electrical polarization formed in the hafnium zirconium oxide thin film (300) can be utilized as a non-volatile memory element.

[0060] FIG. 5 is a drawing showing the non-destructive read operation principle of a semiconductor memory device (900) according to an embodiment, and FIG. 6 is a table showing a performance comparison of a semiconductor memory device (900) according to an embodiment with a conventional semiconductor memory device (900).

[0061] The second electrode (400) serves as a gate electrode in the semiconductor memory element (900). V ERS is the threshold voltage at which the semiconductor memory element (900) becomes an erase state. V is applied to the second electrode (400). ERS When a negative voltage below V is applied, the semiconductor memory element (900) enters an erase state. th,l is the threshold voltage at which a channel can be formed between the source electrode (10) and the drain electrode (20) in the erase state. In the program state, V is applied to the second electrode (400). th,l When the voltage above is applied, a channel is formed between the source electrode (10) and the drain electrode (20), causing current to flow, which is read as “1”.

[0062] VPRG is the threshold voltage at which the semiconductor memory element (900) becomes a program state. V is applied to the second electrode (400). PRG When the positive voltage above is applied, the semiconductor memory element (900) enters a program state. V th,h is the threshold voltage at which a channel can be formed between the source electrode (10) and the drain electrode (20) in the program state. In the erase state, V is applied to the second electrode (400). th,h When the voltage below is applied, a channel is not formed between the source electrode (10) and the drain electrode (20), so no current flows, and this is read as “0”.

[0063] Referring to Fig. 5, the semiconductor memory actually used is integrated by connecting semiconductor memory elements (900) in series. In general, the gate electrode of the semiconductor memory element (900) to be read is V th,l Higher V read A voltage of V is applied to the gate electrode of the remaining semiconductor memory elements (900). th,h Higher V pass Apply voltage of V pass is V read Compared to the semiconductor memory element (900) to be read, a channel is formed between the source electrode (10) and the drain electrode (20) in the semiconductor memory element (900) other than the semiconductor memory element (900) to be read, and current can flow. When the semiconductor memory element (900) to be read is in the erase state, V read Go V th,l Since it has a higher voltage, a channel is formed between the source electrode (10) and the drain electrode (20) so that current can flow, and as a result, current flows overall, so the semiconductor memory reads it as “1”. In contrast, when the semiconductor memory element (900) to be read is in a program state, V read Go V th,hSince the voltage is lower, no channel is formed between the source electrode (10) and the drain electrode (20), so no current flows, and as a result, no current flows overall, so the semiconductor memory reads this as “0”.

[0064] As shown in Fig. 5, in the case of a memory device using ferroelectric, V th,h Wow V PRG Since they are not separated, V is applied to the gate electrode of a memory element other than the memory element to be read. PRG Higher voltage V pass Voltage must be applied, and in this case, memory elements other than the one being read that were in the programmed state will change to the programmed state. This phenomenon is called pass disturbance. Therefore, memory elements using ferroelectrics have the problem of not being able to perform non-destructive read operations.

[0065] In contrast, the semiconductor memory using the semiconductor memory element (900) according to the embodiment of the present disclosure is V PRG Go V th,h Since it has a higher voltage, V pass to V th,h Wow V PRG There is an advantage in that non-destructive read operation is possible by setting the voltage between them.

[0066] Referring to FIG. 6, compared to a memory device using a ferroelectric, a semiconductor memory device (900) according to an embodiment of the present disclosure has no path disturbance, enabling non-destructive reading, and has an advantage in that the write voltage of the memory device using a ferroelectric is 7 V, while the write voltage of the semiconductor memory device (900) according to the present disclosure is 5 V, which can reduce power consumption. Compared to a CTF memory device, a semiconductor memory device (900) according to an embodiment of the present disclosure exhibits high speeds in erase and program speeds, so it has an advantage in that a high-speed device can be implemented, and in terms of durability, a CTF memory device is ~10 6 In contrast, the semiconductor memory device (900) of the present disclosure is ~10 8 It can have high reliability.

[0067] Figure 7 is a manufacturing process diagram of a semiconductor memory device (900) according to an embodiment.

[0068] Referring to FIG. 7, a method for manufacturing a semiconductor memory device (900) according to the present disclosure includes (A) a step of etching a substrate (100) using a 5% hydrofluoric acid (HF) solution diluted with distilled water, (B) a step of depositing a hafnium zirconium oxide thin film (300) using hafnium oxide and zirconium oxide on the substrate (100), (C) a step of depositing a metallic material on the hafnium zirconium oxide thin film (300), (D) a step of annealing in a nitrogen (N2) atmosphere after the metallic material is deposited, (E) a step of removing the metallic material by etching with an SC-1 solution (H2O: H2O2: NH3=250:10:5), and (F) a step of depositing a second electrode (400) using a metal on the hafnium zirconium oxide thin film (300). As an example, a method for manufacturing a semiconductor memory device (900) may further include a step of depositing a first electrode (200) with metal on a substrate (100) after step (A), and step (B) may be a step of depositing a hafnium zirconium oxide thin film (300) with hafnium oxide and zirconium oxide on the first electrode (200).

[0069] By performing etching of step (A) on the substrate (100), impurities and oxide films that may be present on the substrate (100) can be removed.

[0070] (G) In step 1, the first electrode (200) may be a metal such as TiN, Mo, SC, W, etc. As an example, when depositing TiN metal, the plasma power is 200 W, and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Mo metal, the plasma power is 200 W and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Sc metal, the plasma power is 150 W and the base pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing W metal, the plasma power is 150 to 200 W, and the basic pressure is 1 X 10 -6 Torr, process pressure is 1~5 X 10 -3 Deposited for 15 minutes under the condition of 10 Torr. As an example, the thickness of the first electrode (200) can be 10 to 60 nm.

[0071] In step (B), on the substrate (100) or in the case of further including step (G), hafnium oxide and zirconium oxide are deposited in a solid solution form on the first electrode (200) using ozone (O3) as an oxygen source through atomic layer deposition (ALD). As an example, the thickness of the hafnium zirconium oxide thin film (300) may be 0.5 to 10 nm. When depositing the hafnium zirconium oxide thin film (300) by the above-described atomic layer deposition, the temperature of the substrate (100) is 230 to 320 o By maintaining C and using hafnium precursor and zirconium precursor as metal precursors in a ratio of 0:10 to 4:6, Hf 1-x Z x 02(0.6 <x<1)의 조성비를 가지는 하프늄 지르코늄 옥사이드 박막(300)을 형성할 수 있다.

[0072] In step (C), the metallic material can be a simple metal or a metal nitride. As an example, the metal nitride can be TiN. The metallic material is deposited using sputtering, with a plasma power of 1200 W and a base pressure of 3 X 10 -6 Torr, the process pressure is 1 X 10 -3 The metallic material is deposited for 15 minutes under the condition of 10 Torr, and the thickness of the metallic material can be 10 to 60 nm.

[0073] In step (D), annealing in a nitrogen (N2) atmosphere is performed at, for example, a temperature of 400 to 600°C for 10 to 60 seconds. In step (E), when removing metallic materials by etching with an SC-1 solution, etching is performed at, for example, a temperature of 50 to 55°C for 4 minutes. By performing steps (C), (D), and (E), oxygen cavities (310) are formed on the hafnium zirconium oxide thin film (300), and an asymmetric distribution of charges in the hafnium zirconium oxide thin film (300) can be formed due to the oxygen cavities (310).

[0074] (F) In step 2, the second electrode (400) may be a metal such as TiN, Mo, SC, W, etc., as in the first electrode (200) described above. The deposition of the second electrode (400) uses a sputtering method. As an example, when depositing TiN metal, the plasma power is 200 W, and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Mo metal, the plasma power is 200 W and the basic pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing Sc metal, the plasma power is 150 W and the base pressure is 1 X 10 -6 Torr, the process pressure is 1 X 10 -3 Deposit for 15 minutes under the condition of 10 Torr. As an example, when depositing W metal, the plasma power is 150 to 200 W, and the basic pressure is 1 X 10 -6 Torr, process pressure is 1~5 X 10 -3 Deposited for 15 minutes under the condition of 10 Torr. As an example, the thickness of the first electrode (200) can be 10 to 60 nm.

[0075]

[0076] The disclosed content is merely an example, and various modifications and implementations can be made by a person skilled in the art without departing from the gist of the claims claimed in the patent, so the scope of protection of the disclosed content is not limited to the specific embodiments described above.

[0077]

[0078] The present disclosure can be used in the memory semiconductor related industry.

[0079]

[0080] 10: Source electrode

[0081] 20: Drain electrode

[0082] 100: Substrate

[0083] 200: First electrode

[0084] 300: Hafnium zirconium oxide thin film

[0085] 310: Oxygen pupil

[0086] 400: Second electrode

[0087] 900: Semiconductor memory devices

Claims

1. Substrate; A hafnium zirconium oxide thin film in which hafnium oxide and zirconium oxide are deposited on the above substrate; and A second electrode comprising a metal deposited on the hafnium zirconium oxide thin film; A semiconductor memory device in which an oxygen vacancy is formed in the upper portion of the hafnium zirconium oxide thin film.

2. In claim 1, A semiconductor memory device further comprising a first electrode in which a metal is deposited between the substrate and the hafnium zirconium oxide thin film.

3. In claim 1, The above hafnium zirconium oxide thin film is Hf 1-x Z x 02(0.6 <x<1)의 조성비를 가지는 것을 특징으로 하는 반도체 메모리 소자.

4. In claim 1, The above hafnium zirconium oxide thin film is a semiconductor memory device characterized in that it is deposited in a thickness of 0.5 to 10 nm through atomic layer deposition (ALD) using ozone (O3) as an oxygen source and hafnium oxide and zirconium oxide in a solid solution form.

5. In claim 1, A semiconductor memory device characterized in that the following process is performed on the hafnium zirconium oxide thin film before depositing the second electrode. - Deposition of metallic substances - Annealing in nitrogen (N2) atmosphere - Removal of the metallic material by etching with SC-1 solution (H2O: H2O2: NH3 = 250: 10: 5) 6. In claim 5, A semiconductor memory device characterized in that the metallic material is a metal nitride. 7.(A) Step of etching the substrate using a 5% hydrofluoric acid (HF) aqueous solution diluted with distilled water; (B) a step of depositing a hafnium zirconium oxide thin film using hafnium oxide and zirconium oxide on the substrate; (C) a step of depositing a metallic material on the hafnium zirconium oxide thin film; (D) Step of annealing in a nitrogen (N2) atmosphere after deposition of the metallic material; (E) a step of removing the metallic material by etching with SC-1 solution (H2O: H2O2: NH3 = 250: 10: 5); and (F) a step of depositing a second electrode made of metal on the hafnium zirconium oxide thin film; A method for manufacturing a semiconductor memory device comprising:

8. In claim 7, A method for manufacturing a semiconductor memory device, characterized in that the step (A) further includes a step (G) of depositing a first electrode made of metal on the substrate; and the step (B) is a step of depositing a hafnium zirconium oxide thin film made of hafnium oxide and zirconium oxide on the first electrode.

9. In claim 7, The above step (B) is to set the temperature of the substrate to 230 to 320 o A method for manufacturing a semiconductor memory device, characterized in that a hafnium zirconium oxide thin film is deposited with a thickness of 0.5 to 10 nm through atomic layer deposition (ALD) using a hafnium precursor and a zirconium precursor as metal precursors in a ratio of 0:10 to 4:6 while maintaining C and using ozone (O3) as an oxygen source.

10. In claim 9, The above hafnium precursors are [(CH3)(C2H5)N]4Hf(TEMAH), tetrakis(ethylmethylamino)hafnium (TEMAH), trakis(dimethylamino)hafnium (TDMAH), tetrakis(diethylamino)hafnium (TDEAH), tetrakis(pyrrolidino)hafnium, cyclopentadienyltris(dimethylamino)hafnium (CpHf(NMe2)3), methylcyclopentadienyltris(dimethylamino)hafnium (MeCpHf(NMe2)3), ethylcyclopentadienyltris(dimethylamino)hafnium (EtCpHf(NMe2)3), cyclopentadienyltris(ethylmethylamino)hafnium (CpHf(NMeEt)3), Methylcyclopentadienyltris(ethylmethylamino)hafnium(MeCpHf(NMeEt)3), Ethylcyclopentadienyltris(ethylmethylamino)hafnium(EtCpHf(NMeEt)3), Cyclopentadienyltris(diethylamino)hafnium(CpHf(NEt2)3), Methylcyclopentadienyltris(diethylamino)hafnium(MeCpHf(NEt2)3), Ethylcyclopentadienyltris(diethylamino)hafnium(EtCpHf(NEt2)3), Bis(cyclopentadienyl)bis(dimethylamino)hafnium(Cp2Hf(NMe2)2), Bis(methylcyclopentadienyl)bis(dimethylamino)hafnium((MeCp)2Hf(NMe2)2), Bis(ethylcyclopentadienyl)bis(dimethylamino)hafnium ((EtCp)2Hf(NMe2)2), bis(cyclopentadienyl)bis(ethylmethylamino)hafnium (Cp2Hf(NMeEt)2), bis(methylcyclopentadienyl)bis(ethylmethylamino)hafnium ((MeCp)2Hf(NMeEt)2), bis(ethylcyclopentadienyl)bis(ethylmethylamino)hafnium ((EtCp)2Hf(NMeEt)2), bis(cyclopentadienyl)bis(diethylamino)hafnium ((Cp2Hf(NEt2)2), bis(methylcyclopentadienyl)bis(diethylamino)hafnium ((MeCp)2Hf(NEt2)3), and One of bis(ethylcyclopentadienyl)bis(diethylamino)hafnium ((EtCp)2Hf(NEt2)2), The above zirconium precursors are [(CH3)(C2H5)N]4Zr(TEMAZ), tetrakis(ethylmethylamino)zirconium (TEMAZ), tetrakis(dimethylamino)zirconium (TDMAZ), tetrakis(diethylamino)zirconium (TDEAZ), cyclopentadienyltris(dimethylamino)zirconium (CpZr(NMe2)3), methylcyclopentadienyltris(dimethylamino)zirconium (MeCpZr(NMe2)3), ethylcyclopentadienyltris(dimethylamino)zirconium (EtCpZr(NMe2)3), cyclopentadienyltris(ethylmethylamino)zirconium (CpZr(NMeEt)3), methylcyclopentadienyltris(ethylmethylamino)zirconium (MeCpZr(NMeEt)3), Ethylcyclopentadienyltris(ethylmethylamino)zirconium(EtCpZr(NMeEt)3), cyclopentadienyltris(diethylamino)zirconium(CpZr(NEt2)3), methylcyclopentadienyltris(diethylamino)zirconium(MeCpZr(NEt2)3), ethylcyclopentadienyltris(diethylamino)zirconium(EtCpZr(NEt2)3), bis(cyclopentadienyl)bis(dimethylamino)zirconium(Cp2Zr(NMe2)2), bis(methylcyclopentadienyl)bis(dimethylamino)zirconium((MeCp)2Zr(NMe2)2), bis(ethylcyclopentadienyl)bis(dimethylamino)zirconium((EtCp)2Zr(NMe2)2), A method for manufacturing a semiconductor memory device, characterized in that the semiconductor memory device is one of bis(cyclopentadienyl)bis(ethylmethylamino)zirconium (Cp2Zr(NMeEt)2), bis(methylcyclopentadienyl)bis(ethylmethylamino)zirconium ((MeCp)2Zr(NMeEt)2), bis(ethylcyclopentadienyl)bis(ethylmethylamino)zirconium ((EtCp)2Zr(NMeEt)2), bis(cyclopentadienyl)bis(diethylamino)zirconium ((Cp2Zr(NEt2)2), bis(methylcyclopentadienyl)bis(diethylamino)zirconium ((MeCp)2Zr(NEt2)3), and bis(ethylcyclopentadienyl)bis(diethylamino)zirconium ((EtCp)2Zr(NEt2)2).

11. In claim 7, A method for manufacturing a semiconductor memory device, characterized in that in the step (C), the metallic material is a metal nitride.

12. In claim 7, A method for manufacturing a semiconductor memory device, characterized in that the step (C) above makes the metallic material 10 to 60 nm thick.

13. In claim 7, The above step (D) is annealed at 400 to 600 o A method for manufacturing a semiconductor memory device, characterized by performing the process at a temperature of C for 10 to 60 seconds.

14. In claim 7, The above step (E) is 50 to 55 times the etching o A method for manufacturing a semiconductor memory device, characterized by performing the process at a temperature of C for 4 minutes.

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