Method and system for validating a physical layout of a circuit for electronic design automation

Abstract

A method for validating a physical layout of a circuit for electronic design automation, a 5 system for validating a physical layout of a circuit for electronic design automation, and a computer readable data storage medium having stored thereon instructions executable by a system for validating a physical layout of a circuit for electronic design automation. The system comprises a database having stored therein a design library of parameterized cells, P- Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one 10 or more ray path P-Cells; a processor configured to generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P- Cells; process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; extract one or more optical parameters from the physical layout; and generate validation data, as a third output via the graphical user 15 interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout.

Description

[0001] METHOD AND SYSTEM FOR VALIDATING A PHYSICAL LAYOUT OF A CIRCUIT FOR ELECTRONIC DESIGN AUTOMATION

[0002] FIELD OF INVENTION

[0003] The present invention relates broadly to a method and system for validating a physical layout of a circuit for electronic design automation and a computer readable data storage medium having stored thereon instructions executable by a system for validating a physical layout of a circuit for electronic design automation, specifically to a methodology for integrated circuit design in a fully integrated LED / CMOS wafer technology. This methodology advantageously enables circuit designers to account for and make use of the impact of emitted light on the surrounding electronic devices. This can include the interaction of these optical effects at both device and circuit levels.

[0004] BACKGROUND

[0005] The desire for tighter on-wafer integration of light emitting elements (i.e., lasers and LEDs) with CMOS for photonic and optoelectronic applications poses a number of challenges to the classic analog / mixed signal CMOS design process. Traditionally, this process can be classified by the following steps: schematic design, physical layout, parasitic RC extraction, design verification. However, with tighter integration of optoelectronic elements with CMOS, it has been recognized by the present inventors that the impact of light emitting devices on the surrounding CMOS devices cannot be ignored especially when designing high performance analog mixed systems.

[0006] Although there are some emerging techniques employed in CMOS readout integrated circuit design to simulate the influence of light on the performance of silicon devices within a pixel, these approaches may not provide precise calculation of the amount of light incident on a specific device. Instead, they often utilize a more generalized luminosity function for a single pixel, assuming a relatively constant light intensity across the pixel [1], As imagers are usually receiving lower light intensities than would be expected in an integrated photoemitter CMOS system, these effects are much smaller than are expected in tightly integrated optoelectronic systems. It has been recognized by the present inventors that assumptions of uniform light intensity are sufficient for these applications, but insufficient for tightly integrated optoelectronic systems.

[0007] Furthermore, within the Si photonics industry, there exist plug-in / co-simulation products that employ optical simulation and compact models [2], [3], These tools are utilized to assess the efficiency of on-chip waveguides and photonic circuit components, as well as to analyze charge transport and light absorption in semiconductor devices. It has been recognized by the present inventors that these tools appear to be limited to applications for photonic integrated circuits rather than tightly integrated opto-electronic components with CMOS devices in applications such as micro-LED displays, lighting systems, and similar applications as they do not allow for the unintentional impact of light on surrounding electronic devices.

[0008] Embodiments of the present invention seek to provide a design methodology that allows for the robust simulation of photoinduced modifications to device behavior including both intentional and unintentional photoinduced effects.

[0009] SUMMARY

[0010] In accordance with a first aspect of the present invention, there is provided a method for validating a physical layout of a circuit for electronic design automation, comprising the steps of: providing a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P-Cells; using a processor to generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P-Cells; using the processor to process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; using the processor to extract one or more optical parameters from the physical layout of the circuit; and using the processor to generate validation data, as a third output via the graphical user interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; and wherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

[0011] In accordance with a second aspect of the present invention, there is provided a system for validating a physical layout of a circuit for electronic design automation, comprising: a database having stored therein a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P-Cells; a processor configured to: generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P-Cells; process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; extract one or more optical parameter from the physical layout; and generate validation data, as a third output via the graphical user interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; and wherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

[0012] In accordance with a third aspect of the present invention, there is provided a computer readable data storage medium having stored thereon instructions executable by a system for validating a physical layout of a circuit for electronic design automation by executing the method of the first aspect.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 shows a schematic summary of the optically enabled design process flow according to an example embodiment

[0015] Figure 2a) shows a schematic symbol for an optically-active LED P-Cell (photo-emitter), according to an example embodiment.

[0016] Figure 2b) shows a graph illustrating optical intensity as a function of LED Voltage as detected on the output optical port of the optically-active LED P-Cell (photo-emitter) of Figure 2a), according to an example embodiment.

[0017] Figure 3a) shows a schematic symbol for an optically-active NMOS P-Cell (photodetector), according to an example embodiment.

[0018] Figure 3b) shows a graph illustrating drain current as a function of optical intensity as received on the input optical port of the optically-active NMOS P-Cell (photodetector) of Figure 3a), according to an example embodiment. Figure 4a) shows an example schematic circuit design for an optically active circuit incorporating photo-emitters (LS and RS) and MOSFETs (LD and RD) during, according to an example embodiment.

[0019] Figure 4b) shows an example physical layout for an optically active circuit incorporating photo-emitters (LS and RS) and MOSFETs (LD and RD), according to an example embodiment.

[0020] Figure 4c) shows an example modified schematic circuit diagram for an optically active circuit incorporating photo-emitters (LS and RS) and MOSFETs (LD and RD) after post layout optical back annotation, according to an example embodiment.

[0021] Figure 5a) shows a graph illustrating generated validation data in the form of DC simulation showing optical coupling between RS and RD, according to an example embodiment.

[0022] Figure 5b) shows a graph illustrating generated validation data in the form of DC simulation showing optical coupling between LS and RD, according to an example embodiment.

[0023] Figure 5c) shows a graph illustrating generated validation data in the form of DC simulation showing optical coupling between LS and LD, according to an example embodiment.

[0024] Figure 5d) shows a graph illustrating generated validation data in the form of DC simulation showing optical coupling between RS and LD, according to an example embodiment.

[0025] Figure 6 shows a block diagram representation of the flow of information in an existing P- Cell.

[0026] Figure 7 shows a block diagram representation of a photodetector optically active P-Cell according to an example embodiment.

[0027] Figure 8 shows a block diagram representation of a photo-emitter optically active P-Cell according to an example embodiment.

[0028] Figure 9 shows a block diagram representation of a transceiver optically active P-Cell according to an example embodiment.

[0029] Figure 10 shows a block diagram representation of a ray path P-Cell according to an example embodiment.

[0030] Figure 1 1 shows a flowchart illustrating a method for validating a physical layout of a circuit for electronic design automation

[0031] Figure 12 shows a schematic drawing illustrating a system for validating a physical layout of a circuit for electronic design automation, and a computer readable data storage medium having stored thereon instructions executable by the system for validating a physical layout of a circuit for electronic design automation. DETAILED DESCRIPTION

[0032] Embodiments of the present invention provide a tool kit and its methodology to provide the enhanced capability of photoinduced modifications to device I-V behavior.

[0033] Traditionally, electronic design automation (EDA) tools have been developed to aid circuit designers in the creation of integrated circuits, whether it involves digital design or analog / custom design systems. In EDA tools, P-Cells, which stand for parameterized cells, are used in the automated design of circuits. A P-Cell represents a part or a component of the circuit whose structure is dependent on one or more parameters.

[0034] As is understood by a person skilled in the art, EDA tools typically provide a design library of P-Cells to facilitate generating, via a graphical user interface, of a schematic circuit design; and processing the schematic circuit design to generate a physical layout of the circuit, wherein the P-Cells typically comprise two or more ports for facilitating parametrization of the input / output of electrical signals of a circuit element.

[0035] However, it has been recognized by the present inventors that with the emergence of chip technologies that tightly integrate optical and electronic elements, challenges exist for the existing EDA assisted design process. More specifically, existing EDA tools that predominantly focus on electronic system may encounter limitations in the hybrid optical + electronic chip technologies. These existing EDA tools are hence not well equipped to effectively assist in the design of circuits that involve the integration of electrical and optical components into a single system.

[0036] It has also been recognized by the present inventors that the limitations of existing EDA tools in assisting the design of optoelectronic applications stem, at least, from their inability to account for the impact of emitted light on electronic devices. This includes the light transmission efficiency from an emissive device to other nearby electronic devices, the absorption of photons (and subsequent generation of hole-electron pairs), and the photoinduced modifications to the device electrical behavior (such as in a photodetector). The existing EDA tools typically focus on electronic design systems, disregarding the optical behavior. The conventional assumption, whereby schematic-based electrical ports effectively optically isolate proximal devices, has prevented the robust design of integrated optoelectronic + CMOS systems, which is crucial for their adoption in the optoelectronic market.

[0037] To overcome these limitations and enhance the capabilities of existing EDA tools, the approach according to an example embodiment involves introducing optically active P-Cells, with both electrical and optical ports. These optically active P-Cells enable the characterization of devices' electrical-optical (photo-emitter) and optical-electrical (photodetector) behavior, as well as a combination thereof, by e.g. utilizing measured optical power and photoinduced curves. By employing this approach, a communication protocol between electrical-optical devices can be established using ray path P-Cells, representing the physical optical path or transmission line between the elements. The absorption coefficient of this transmission line can be extracted from the physical layout using ray tracing or other optical simulation techniques, enabling accurate representation of the electrical-optical signal encoding and decoding process in the optically active P-Cells. The method according to an example embodiment advantageously preserves the functionality of existing EDA tools while providing the means to incorporate optical functionalities and facilitate the design of optoelectronic systems.

[0038] Implementation according to an example embodiment

[0039] The traditional analog mixed signal integrated circuit design process using EDA tools is a highly efficient and robust process whereby circuits can be ideated, implemented, simulated, and validated. This process has worked incredibly well for digital, analog and RF circuits alike. However, with the integration of light emitting elements more tightly with traditional CMOS devices, it has been recognized by the present inventors that the impact of light on the performance of circuits cannot be accurately simulated using the current set of tools within the existing EDA environment. Thus, an additional set of plugins and tools are provided according to an example embodiment to improve the accuracy of circuit simulation and performance validation, which in turn enables more robust and creative designs in an optically active fully integrated compound semiconductor + CMOS (i.e., III-V / CMOS) process.

[0040] Figure 1 illustrates the design process flow for an analog mixed signal integrated circuit that integrates light emitting elements, according to an example embodiment. The design process flow comprises the Schematic Design stage 100, the Circuit Simulation stage 102, the Layout and Parasitic Extraction stage 104, the Circuit Validation stage 106, and ultimately the fabrication of the designed circuit in the Circuit Fabrication stage 108 in a semiconductor fabrication plant, also called a fab or a foundry. This process closely resembles the traditional circuit design approach but incorporates specific enhancements and plugins to improve design accuracy by incorporating optical signals, according to example embodiments. These enhancements can include: The provision of optically active P-Cells, comprising P-Cells for photo-emitters and photodetectors, and a combination thereof, provision for encoding and decoding of optical signals, allowing provided ray path P-Cells to function as an optical transmission line between an emitter to a photodetector, and the extraction of optical coupling coefficients for the ray path P-Cells.

[0041] The Schematic Design stage 100 is the phase during which the interconnection between P- Cell elements is performed, resulting in generating a schematic circuit design. The availability of optically active P-Cells and ray path P-Cells according to an example embodiment advantageously allows circuit designers to annotate the communication or transmission of photons between a photo-emitter and photo-detector.

[0042] The Circuit Simulation stage 102 is the phase of the process whereby the electrical behavior of the circuit can be determined. In an example embodiment, this simulation is facilitated by modified compact models which calculate the impact of absorbed photons on the performance of the circuit, and compact models which calculate the quantity of emitted photons.

[0043] The Layout and Parasitic Extraction stage 104 is the translation of the schematic circuit design into a physical layout. This physical layout corresponds to the patterns which will be manufactured on the physical chip at the fab. P-Cells are laid out according to the designers’ preferences. To maintain compatibility with existing layout verification tools (layout versus schematic, LVS) in an example embodiment, the optical information can betemporarily stripped out of the schematic circuit design, leaving only the physical electrical connections between the P-Cells. This optical information includes optical ports, ray path P-Cells, and the nets connecting them. Once the physical layout is complete, extraction of optical coupling coefficients between photo-emitters and photo-detectors can be performed using optical simulation of the physical layout in an example embodiment. The numerical quantification of optical coupling coefficients between photo-emitters and photo-detectors can be performed on all physically proximal sets of photo-emitters and photo-detectors in an example embodiment.

[0044] The Circuit Validation stage 106 entails the final post-layout simulation of the circuit. The original schematic circuit design can be back annotated with additional optical pathways and refined optical coupling coefficients based on the extraction of optical coupling coefficients in the Physical Layout and Parasitic Extraction stage 104, thereby generating a modified schematic circuit design. Final circuit simulations can be performed on this modified schematic circuit design to generate validation data that to prove intended circuit operation. This is effectively the final electrical system simulation accounting for all potential optical effects within the chip, according to an example embodiment

[0045] Finally, the circuit fabrication stage 108 is performed including various semiconductor processing steps understood in the art which create the physical chip based on the designed physical layout.

[0046] Optically active P-Cells according to an example embodiment:

[0047] As is understood by a person skilled in the art, schematic symbols are utilized / created in EDA to represent both photo-emitters and photodetectors. In existing commercial EDA software, these symbols are employed in schematic diagrams for simulating integrated circuits. The SPICE engine [see e.g. https: / / en-academic.com / dic.nsf / enwiki / 8207933, https: / / www.synopsys.com / content / dam / synopsys / verification / datasheets / hspice- ds.pdfhttps: / / www.cadence.com / en_US / home / resources / datasheets / spectre-accelerated- parallel-simulator-ds.html] is then typically used to compute the electrical properties of the circuit, including direct current (DC), alternating current (AC) and radio frequency (RF) characteristics, using compact model equations typically written in VerilogA and in some instances compiled as a binary file.

[0048] Optically active P-Cells for emitters have been created by the present inventors that can calculate both the electronic and optical information associated with the photo-emitters, according to an example embodiment. In commercial EDA software, ports serve the purpose of facilitating the input / output of electrical signals in an integrated circuit diagram. However, in existing EDA software no such paradigm currently exists for the calculation and communication of optical interactions between corresponding cells. In an example embodiment, the use of optical ports enables photon generation, transmission, and absorption between optoelectronic devices. This means that, while providing traditional electrical information at the electrical ports of the optically active P-Cell, e.g. the optical output of a photo-emitter is simultaneously computed in the compact model of the optically active P-Cell according to an example embodiment and shared (encoded as an electrical signal) at the optical port. Characteristics of the emitter device such as internal quantum efficiency and light extraction efficiency are used in determining the quantity of light emitted from a device. An example LED optically active P-Cell with the optical port 200 added and the correlation of device voltage and optical power (curve 202) are shown in Figures 2a) and b). This optical power information can then be communicated to other optically active P-Cells using the encoding protocol which will be described in detail below.

[0049] For Photodetectors / receivers (Si Diodes, MOSFETs, BITs, LEDs, etc.), when the light emitting elements are integrated onto the same wafer as other electronic devices such as MOSFETs, it has been recognized by the inventors that the electrical behavior of these devices can be influenced by the presence of light. To establish a reliable design ecosystem, in an example embodiment the impact of absorbed photons on the performance of individual devices is advantageously considered.

[0050] To achieve this, in an example embodiment the existing P-Cells are modified to incorporate an optical port and thereby optically active P-Cells are created, for example as a modification of foundry-provided P-Cells, according to an example embodiment. As an example, shown in Figures 3a) and b), in the optically active P-Cell 300 for a MOSFET, in addition to the conventional gate, drain, source, and body associated with a MOSFET, an optical port 301 as an additional terminal is introduced and this port 301 similarly influences the electrical behavior of the device alongside with the existing terminals e.g. 302. The optical port 301 detects an analog value, which is then decoded according to the protocol described in detail below. This decoded value alters the generation rate of electron-hole pairs within the device in an example embodiment, subsequently leading to a change in the electrical output. To accommodate these modifications in device behavior resulting from the absorption of light and the generation of electron-hole pairs, the compact model equations of the optically active P-Cells for photodetectors / receivers according to an example embodiment are adjusted to include these optical effects, serving as a type of model plug-in. In an example embodiment, this involves introducing additional model coefficients that are calibrated via experimental data collected from measurements on model development structures. As an example, the correlation of optical power to the device DC electrical behavior, for a MOSFET, resulting from the use of the optically active P-Cell according to an example embodiment is shown in Figure 3b). It is noted that the calibrated model card from foundry process design kits (PDKs) associated with the optically active P-Cells according to an example embodiment can remain unchanged to preserve the device’s performance in the absence of light. Additional details of example implementation of optically active P-Cell according to example embodiments will be described below with reference to Figures 6 to 9.

[0051] Communication of Optical Signals according to an example embodiment:

[0052] Implementation of optical transmission from one emitter to a detector according to an example embodiment can include: 1. Encoding of optical data to electrical signals, 2. Modification of electrical signals based on optical attenuation / radiometric spreading, and 3. Decoding of electrical signals into optical data.

[0053] Encoding: To facilitate one photo-emitter having the capability to communicate with many photo-detectors ("one-to-many”) the electrical signal at the optical port of the photo-emitter according to an example embodiment emits a signal encoded as a voltage. This is to preferably ensure that adding additional detector devices does not dilute the optical signal that each of these devices can receive. If current were used, the signal would be split depending upon the number of parallel branches it was attached to causing the photo-emitter to appear weaker in the presence of additional photo-detectors. This is not the intended mode of operation; therefore, voltage is preferable. In one example embodiment, this can be done through a unit transformation from Watts (optical power) to Volts (electrical power). This voltage is then written to the output optical port of the photo-emitter optically active P-Cell. Other encoding schemes are also possible in different example embodiments so long as the photon flux is preferably encoded as a voltage.

[0054] Transmission: The transmission of optical signal from a photo-emitter to a photo-detector is facilitated in an example embodiment by a custom ray path P-Cell. It is the role of the ray path P-Cell to account for the physical path of the optical signal before reaching the detector. This preferably includes radiometric spreading (i.e., solid angle / light spreading) and attenuation by absorption and / or reflection or scattering before the photons arrive at the detector in an example embodiment. The summation of all these radiometric effects can be lumped together into an optical coupling coefficient denoted as: a. This a coefficient, with decimal values between 0 and 1 in an example embodiment, can be determined empirically (backed by sufficient amounts of experimental data to be considered reliable) or through non sequential ray tracing analysis or finite difference time domain (FDTD) modeling in a preferred embodiment, as will be described in detail below. Additionally, to facilitate one detector being able to accept optical data from multiple photo-emitters at the same time, the optical signal encoded as a voltage received from the photo-emitter optically active P-Cell is re-encoded as a current to allow one detector to receive inputs from many different photoemitters at the optical port (many-to-one). Current is used in the example embodiment, because voltages are not additive at a single circuit node meaning that multiple sources would be unable to provide information simultaneously to the same photo-detector. The current based encoding is done in the following way: lopt = Voptxa, according to an example embodiment. Decoding: Finally, at the input optical port of the optically active photodetector / receiver P- Cell the current value IOpt is detected and decoded into a density of electron-hole pairs. This quantity of electron-hole pairs is used as an input to the optically enabled model plug-in in addition to / of the existing compact model equations, which enables modifications to the device behavior as explained herein.

[0055] Extraction of optical coupling coefficients according to an example embodiment:

[0056] Similar to parasitic extraction of resistances and capacitances from the physical layouts in a traditional analog mixed signal design flow, the quantity of light that reaches a device adjacent to a photo-emitter should preferably be extracted from a physical layout to maintain high simulation accuracy and confident design verification. While for resistance and capacitance, this parasitic extraction can be done with simple area or length dependencies, optical interactions typically require ray tracing or solving wave equations with rigorously coupled wave analysis or finite-difference time domain modeling to determine the quantity of light which is incident on any device instance.

[0057] To do this, in an example embodiment the layout is converted into a 3-D model of a local region of the chip. This can be done e.g. by interpreting the GDSII file and defining 3D object files based on this 2D layout information as well as information about layer thicknesses and etch depths from a process description file. This 3D object file can then be used in any of the many commercial or open-source optical modeling software in order to simulate the quantity of light that is reaching a detector device (i.e. MOSFET, diode, BJT, etc.), according to an example embodiment. To first order, this is done by placing a software defined uniform emitter layer with a known power within the emissive region of the photoemitter and a software-defined detector placed at the locations of the various detector devices of interest. Then the ratio between emitted power and detected power (a) can be calculated for that particular device pair, according to an example embodiment.

[0058] Circuit Design according to an example embodiment:

[0059] For the purposes of an example embodiment, a designer is attempting to create 2 distinct photo-emitter photo-detector pairs denoted by LS / LD and RS / RD, see Figure 4a). LS and RS represent the optically active photo-emitter P-Cells, while LD and RD represent the optically active P-Cells for MOSFETs acting as photodetectors / receivers. LD is located at distances xi and X2 away from LS and RS, respectively, while RD is positioned distances xs and X4 away from LS and RS, respectively. In the schematic shown in Figure 4a), the transmission of the optical signal from LS at the optical port 400 to the optical port 402 of LD is facilitated by one ray path P-Cell denoted by RP1, and similarly, RP2 is used for the transmission of optical data from RS to RD. In the example embodiment, advantageously the impact of absorbed photons on the electrical behavior of LD and RD is considered, especially in view of the intended function of the circuit and the relatively short distance, xi between LS and LD, as well as X4 between RS and RD. In an example embodiment, the coupling coefficients am and am for RP1 and RP2 respectively can be adjusted similar to other design variables to preferably ensure that the circuit operates as intended across a realistic range of coupling coefficients. These values can also be empirically estimated by previous tapeout iterations based on distance xi and X4; noting that the precise values of a and a.RP2 are not available until the layout is performed, as will be appreciated by a person skilled in the art. It should also be noted that the schematic circuit in Figure 4a) does not account for the influence of absorbed photons on the photodetectors emitted by the respective other photo-emitter (i.e., the impact of light from LS on RD or the impact of light from RS on LD). The designer might initially intuit these other optical interactions to have a negligible effect on the electrical characteristics because of the more considerable distance, X2 and xs, when compared to xi and X4. However, these interactions can be similarly considered for more accurate circuit design according to an example embodiment, compare also Figure 4c) described below. Hereinafter, the impact from LS on LD and RS on RD is also referred to as “intentional coupling”, whereas the impact from LS on RD and RS on LD is also referred to as “unintentional coupling”.

[0060] In an example embodiment, as an initial step, the corresponding layout for Figure 4a) is generated and presented in Figure 4b). At this point, the physical dimensions of the circuit are known, and the physical structure can be created via 3D modelling using e.g. process information and the GDSII file as described above. Next, a commercial optical simulation engine such as Zemax, Lumerical or others can be used to calculate the optical coupling coefficients U.RP I and U.RP more accurately for the consideration of the impact of LS on LD and RS on RD. In addition, similar to post layout extraction of backend metallization parasitic resistance and capacitance, device interactions between RS and LD as well as LS and RD can advantageously also be evaluated for impact, using additional ray path P-Cells denoted RP3 and RP4. The associated additional coupling coefficients CIRP3 and appi can be extracted simultaneously to OIRPI and ap, 2 during ray tracing. At this point automated creation of a schematic which includes all of the possible ray paths is performed according to an example embodiment, as shown in Figure 4c).

[0061] Design validation can then be performed, for example on the schematic given in Figure 4c) according to the desired functionality and considering both intentional and unintentional coupling between relevant optical elements. It is noted that design validation may be performed directly based on the schematic circuit design in Figure 4a) according to another example embodiments, for example if unintentional coupling can be ignored for some reason, such as the distances and / or shielding between the relevant optical elements. It is further noted that in an example embodiment, a modified physical layout may be generated based on the modified schematic in Figure 4c). For example, the modified schematic could lead the designer to revise or edit the schematic and / or layout as a result of the data provided by the modified schematic.

[0062] In an example embodiment in which both the intentional and unintentional coupling have been considered, the validation data can be generated by simulation based on the extracted optical parameters, here the coupling coefficients, and are displayed in Figures 5a)-d). Figures 5a) and c) exhibit the intentional photo coupling between RS / RD and LS / LD. The solid lines show the changes due to accounting for the intentional photo coupling, advantageously resulting in an increase in the accuracy post layout extraction, according to an example embodiment. Figures 5b) and d) show the unintentional coupling between LS / RD and RS / LD respectively. For comparison, if initially the designer did not account for this coupling, leading to no perceived response (compare flat dotted lines); however, after the post layout extraction according to an example embodiment, the unintentional coupling effect is seen clearly (compare solid lines). On the other hand, as can be seen from Figures 5a) and c), even if unintentional coupling is not considered, the validation data differs between pre- and post-layout extraction, hence providing useful information for the actual circuit design fabrication, e.g. where certain limits are imposed on voltages an / or current on the chip. It would also be known by a person skilled in the art, that if, at the point of design validation, the circuit is not behaving as desired or meeting the necessary performance metrics, that alterations to the schematic and or physical layout could be performed.

[0063] Next, more detailed non-limiting example embodiments of the specific architecture of an optically active P-Cell both for the transmitter (i.e. photo-emitter) and receiver (i.e. photodetector) side, for a transceiver (i.e. photo-emitter with photo-absorption), and a ray path P-Cell will be described.

[0064] As is appreciated by a person skilled in the art, the implementation of an existing P-Cell comprises schematic symbols, layout generation scripts, and files related to modeling the electrical behavior of the device. In order to facilitate the addition of optical information into the simulation environment, both the schematic symbol and the files related to the electrical modeling of the device are adjusted, according to an example embodiment. The implementation details to the changes to the inner workings of the calculation of the electrical and optical behavior of the device according to example embodiments of the optically active P-Cell both for the transmitter and receiver side, and as a transceiver, will be described.

[0065] In an existing EDA P-Cell 600, the flow of information that determines electrical behavior of the cell can be described with reference to Figure 6, where there are, for example, three sets of parameters 601, 602, 603, one set of compact model equations 604, and a set of electrical ports 605. The first set of parameters 601 are the physical constants such as intrinsic carrier concentration, temperature, electron charge, etc. The second set of parameters 602 are calibrated model card parameters. These parameters 602 are the values that are used by the PDK developer to calibrate the electrical behavior of a given device. These parameters 602 are mainly fitting parameters and specific manufacturing process relevant information. The third set of parameters 603 are the user defined parameters. An example of these parameters 603 are the physical dimensions of the electrical device which will certainly impact the electrical behavior (e.g. gate length or gate width in a MOSFET).

[0066] The electrical behavior (currents and voltages at the electrical ports 605) is determined by the combination of the circuit schematic connections (not pictured) to the electrical ports 605 and the above-described parameters 601-603. These values are used in the compact model equations (e g. Berkeley Short-channel IGFET Model (BSIM), PSP) in an iterative method to satisfy convergence requirements of the simulation engine (e.g. SPICE). The electrical ports 605 serve as both inputs and outputs from the compact model equations 604 which mandates an iterative solution for solving the current and voltage values at the electrical ports, as is appreciated by a person skilled in the art.

[0067] In order to create a P-Cell with the added ability to understand the impact of absorbed light on the electrical behavior according to an example embodiment, certain additions and modifications are made to this existing P-Cell structure 600.

[0068] As shown in Figure 7, the addition of an input optical port 701 to the optically active P-Cell structure 700 according to an example embodiment for a receiver side provides the mechanism for receiving the optical power from other circuit elements as described above. Additional optical absorption compact model equations 702 and parameter sets 703, 704 which in turn modify additional inputs 705, 706 to the electrical compact model equations 604, thereby modifying the electrical outputs 707.

[0069] The optically enabled P-Cell 700 according to an example embodiment for a receiver side comprises the same parameter sets 601-603 and equations 604 as the existing P-Cell (compare Figure 7), as it preferably remains accurate in the absence of light. In addition, physical constants 703 relevant to optical absorption, optical model card parameters 704 for model calibration, and optical compact model equations 702 are added. The additional parameters 703, 704 are used as inputs 713, 714 to the physically relevant optical compact models equations 702 to capture the underlying physics and calibrate the optical effects.

[0070] The input optical port 701 (compare e.g. element 300 in Figure 3(a) described above) receives an electrical current that corresponds to the received optical power. This electrical current is decoded into an optical power 715 before being used in the optical absorption compact model equations 702, according to an example embodiment.

[0071] The optical compact model equations 702 are not only different mathematically to those of the electrical compact model equations 604 but also are different architecturally. While still receiving inputs from 3 parameter sets, i.e. 703, 704, 603), the optical absorption compact model 702 modifies a subset of the electrical calibrated model card parameters 705 and physical constants 706. This is in contrast to the existing P-Cell shown in Figure 6 where the electrical compact model equations 604 directly impact the electrical ports 605. Parameters from either, or both of, the physical constant parameters 601, and from the foundry calibrated model equations 602 can be modified by the optical absorption compact model equations, as indicated at 706 and 705, respectively. As an example, under high levels of optical injection into a receiver device, the mobile electron and hole concentration in a semiconductor material is increased. This change in a physical model parameter will manifest itself as a change in the electrical behavior of the device and therefore the adjusted value of carrier concentration is accounted for in an example embodiment when calculating the resultant electrical behavior of the device. It should also be noted that some parameters 716 from the calibrated model card parameters 702 and / or the physical constants 717 may remain unmodified by the optical absorption compact model 802. Additionally, in an example embodiment, the resultant outputs 707 of the electrical compact model equations 604 can also be used as inputs to the optical absorption compact model equations 702 to account for bias dependent optical absorption effects. This involves iterative solving of the model equations, which can be supported by existing EDA tools, as is understood by a person skilled in the art.

[0072] For the transmitter optically active P-CELL 800 according to an example embodiment shown in Figure 8, there are some differences when compared to the receiver P-CELL 700 (Figure 7) according to an example embodiment. The diagram detailing the architecture of the optically active transmitter side P-Cell 800 is shown in Figure 8.

[0073] Akin to the existing EDA P-Cell 600 (Figure 6), the optically active transmitter end P-Cell 800 comprises electrical ports 605 that serve as the input and output schematic ports and are controlled by the results of the electrical compact model equations 604 just as in the existing EDA P-Cell. Additionally, the electrical behavior is impacted by 3 parameter sets which serve as inputs to the electrical compact model: user defined parameters 603, electrical model equations 604, and electrical physical constants 601.

[0074] In addition to these electrical models and parameters, the optically active portion of the P- Cell 800 has an additional port, the output optical port 806, used to communicate the optical emission information out of the cell 800. This port 806 is fed information by the optical emission compact model equations 807 after encoding the result as a voltage 808. These optical emission compact model equations 807 are physically relevant equations that can predict the optical power produced given the amount current through and / or voltage across the optically emissive device. Thus, the outputs 809 of the electrical compact model equations 604 are also used as an input to the optical emission compact model equations 807. To calibrate these equations, there are 2 sets of additional parameters in an example embodiment: Optical emission physical constants 810 and optical emission model card parameters 811. It should be noted that the user defined parameters 603 such as length and width are also relevant parameters in the optical emission compact model equations 807 and are thus also used as inputs, in an example embodiment.

[0075] As is understood by a person skilled in the art, light-emitting diodes (LEDs) could act as both a receiver and transmitter of optical flux (duplex mode). A simplified version of a P-Cell 900 for duplex mode according to an example embodiment is shown in Figure 9. In such a case a combination, also referred to as a transceiver optical active P-Cell herein, of the above transmitter and receiver P-Cell architectures 700, 800 can be provided by combining the above architectures in Figures 7 and 8, where e g. 3 sets of model equations 901-903 and multiple sets e.g. 904-908 of parameters can be used to control an optical input port 909, an optical output port 910 and a set of electrical ports 911.

[0076] The receiver information path acts identically to the receiver only P-Cell 700 where optical data is recorded in the form of an electrical current at the input optical port 909 and is used in the absorption compact model equations 902 to modify input parameters to the electrical compact model equations 912, 913. The result of the electrical compact model equations 914, and the emission specific parameter sets 915 are fed into the emission compact model equations 903, the outputs of which are encoded as a voltage 916 before being written at the output optical port 910, thus enabling optical duplex operation (receiving and emission) according to an example embodiment.

[0077] A ray path P-Cell 1000 according to an example embodiment is shown in Figure 10. This architecture is relatively simple as its sole function, according to an example embodiment, is to attenuate the optical signal and to re-encode the data from a voltage to a current as described above. A voltage is received at the input optical port 1001, then the voltage is decoded into an optical power at 1002. Then, the optical power is attenuated by the coupling factor 1003, before being re-encoded to a current at 1004 at the optical output port 1005.

[0078] As described above, the methods and tools according to example embodiments can advantageously allow for simulation of the intentional and unintentional coupling effects with a high degree of accuracy due to the layout extraction of coupling coefficients for ray path P- Cells, and communication of optical information between calibrated optically active P-Cells at the schematic level. The validated design example exemplifies the benefit of this optically- enabled PDK approach using optically active P-Cells and ray path P-Cells according to an example embodiment, advantageously allowing for the design consideration of both intentional opto-coupling between devices as well as the unintentional effects of proximal optically active devices.

[0079] Figure 11 shows a flowchart 1100 illustrating a method for validating a physical layout of a circuit for electronic design automation, comprising:

[0080] At step 1102, providing a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P- Cells; at step 1104, using a processor to generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P-Cells; at step 1106, using the processor to process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; at step 1108, using the processor to extract one or more optical parameters from the physical layout of the circuit; and at step 1110 using the processor to generate validation data, as a third output via the graphical user interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; and wherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

[0081] The one or more optically active P-Cells may comprise a photo-emitter optically active P- Cell.

[0082] The one or more optically active P-Cells may comprise a photodetector optically active P- Cell.

[0083] The one or more optically active P-Cells comprise a transceiver optically active P-Cell.

[0084] The method may comprise using respective ray path P-Cells for interconnecting different pairs of optically active P-Cells.

[0085] The method may comprise considering intentional coupling between one or more pairs of optically active P-Cells and / or unintentional coupling between one or more pairs of optically active P-Cells.

[0086] The method may comprise using two or more ray path P-Cells for interconnecting one optically active P-Cell to two or more other optically active P-Cells.

[0087] The method may comprise using the processor to generate, via the graphical user interface, a modified schematic circuit design based on the generated physical layout and the extracted optical parameters and using the processor to generate the validation data based on the modified schematic circuit design and the one or more extracted optical parameters for validation of the physical layout.

[0088] The method may comprise empirically determining parameters for parametrization of the properties of the optical path between two optical elements for modeling the appropriate optical coupling between optically active P-Cells by the processor.

[0089] The method may comprise calculating parameters for parametrization of the properties of the optical path between two optical elements, wherein the calculating may comprise any modality of optical analysis, such as ray tracing analysis or solving wave equations with rigorously coupled wave analysis or finite-difference time domain modeling.

[0090] The method may comprise fabricating an integrated circuit based on the validated physical layout.

[0091] Figure 12 shows a schematic drawing illustrating a system 1200 for validating a physical layout of a circuit for electronic design automation, comprising: a database 1202 having stored therein a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P-Cells; a processor 1204 configured to: generate, as a first output via a graphical user interface 1206, a schematic circuit design comprising at least one of the optically active P-Cells; process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface 1206; extract one or more optical parameters from the physical layout; and generate validation data, as a third output via the graphical user interface 1208, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; and wherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

[0092] The one or more optically active P-Cells may comprise a photo-emitter optically active P- Cell. P-Cell

[0093] The one or more optically active P-Cells may comprise a photodetector optically active P- Cell.

[0094] The one or more optically active P-Cells may comprise a transceiver optically active P-Cell. P-Cell.

[0095] The processor 1204 may be configured to use respective ray path P-Cells for interconnecting different pairs of optically active P-Cells

[0096] The processor 1204 may be configured to consider intentional coupling between one or more pairs of optically active P-Cells and / or unintentional coupling between one or more pairs of optically active P-Cells.

[0097] The processor 1204 may be configured for use one ray path P-Cell for interconnecting one optically active P-Cell to two or more optically active P-Cells.

[0098] The processor 1204 may be configured to generate, via the graphical user interface 1206, a modified schematic circuit design based on the generated physical layout and the extracted optical parameters and to generate the validation data based on the modified schematic circuit design and the one or more extracted optical parameters for validation of the physical layout.

[0099] The processor 1204 may be configured to empirically determine parameters for parametrization of the properties of the optical path between two optical elements for modeling the appropriate optical coupling between optically active P-Cells. The processor 1204 may be configured to calculate parameters for parametrization of the properties of the optical path between two optical elements, wherein the calculating may comprise any modality of optical analysis, such as ray tracing analysis or solving wave equations with rigorously coupled wave analysis or finite-difference time domain modeling.

[0100] The system may comprise fabrication equipment 1208 for fabricating an integrated circuit based on the validated physical layout.

[0101] Figure 12 also shows a computer readable data storage medium 1210 having stored thereon instructions executable by the system 1200 for validating a physical layout of a circuit for electronic design automation by executing the method of embodiments of the present invention described herein.

[0102] Industrial applications of example embodiments include, but are not limited to:

[0103] - Design and fabrication of fully integrated micro displays where the CMOS and LED devices are tightly integrated together either on the same wafer or in the same package.

[0104] - Design and fabrication of optocoupler structures for noise isolation where the CMOS and LED devices are tightly integrated together either on the same wafer or in the same package.

[0105] It is noted that the challenge that the time for optical simulation will grow linearly with the number of emitters is expected to be readily addressable with optimizations to the optical simulation process such as the use of GPUs for acceleration.

[0106] Aspects of the systems and methods described herein may be implemented on computing device(s), including cloud-based computing device(s) and / or Intemet-of-Things computing device(s), for example as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs). Some other possibilities for implementing aspects of the system include: microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the system may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies like complementary metal- oxide semiconductor (CMOS), bipolar technologies like emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc. The various functions or processes disclosed herein may be described as data and / or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and / or other characteristics. Computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and / or instructions through wireless, optical, or wired signaling media or any combination thereof. When received into any of a variety of circuitry (e g. a computer), such data and / or instruction may be processed by a processing entity (e.g., one or more processors).

[0107] It will be appreciated by a person skilled in the art that numerous variations and / or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive. Also, the invention includes any combination of features described for different embodiments, including in the summary section, even if the feature or combination of features is not explicitly specified in the claims or the detailed description of the present embodiments.

[0108] In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

[0109] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "hereunder," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

[0110] References

[0111] [1] Hanxin Jia etal 2006 Semicond. Sd. Technol. 21 112 DOI 10.1088 / 0268-1242 / 21 / 2 / 002

[0112] [2] https: / / www.youtube.com / watch?v=jOgKCKqvgOA [3] htps: / / www.ansys.com / products / photonics

Claims

CLAIMS1. A method for validating a physical layout of a circuit for electronic design automation, comprising the steps of: providing a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P-Cells; using a processor to generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P-Cells; using the processor to process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; using the processor to extract one or more optical parameters from the physical layout of the circuit; and using the processor to generate validation data, as a third output via the graphical user interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; and wherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

2. The method of claim 1 , wherein the one or more optically active P-Cells comprise a photoemitter optically active P-Cell.

3. The method of claims 1 or 2, wherein the one or more optically active P-Cells comprise a photodetector optically active P-Cell.

4. The method of any one of the preceding claims, wherein the one or more optically active P-Cells comprise a transceiver optically active P-Cell.

5. The method of any one of the preceding claims, comprising using respective ray path P- Cells for interconnecting different pairs of optically active P-Cells.

6. The method of any one of the preceding claims, comprising considering intentional coupling between one or more pairs of optically active P-Cells and / or un-intentionally coupling between one or more pairs of optically active P-Cells.

7. The method of any one of the preceding claims, comprising using two or more ray path P- Cells for interconnecting one optically active P-Cell to two or more other optically active P- Cells8. The method of any one of the preceding claims, comprising using the processor to generate, via the graphical user interface, a modified schematic circuit design based on the generated physical layout and the extracted optical parameters and using the processor to generate the validation data based on the modified schematic circuit design and the one or more extracted optical parameters for validation of the physical layout.

9. The method of any one of the preceding claims, comprising empirically determining parameters for parametrization of the properties of the optical path between two optical elements for modeling the appropriate optical coupling between optically active P-Cells by the processor.

10. The method of any one of the preceding claims, comprising calculating parameters for parametrization of the properties of the optical path between two optical elements, wherein the calculating may comprise any modality of optical analysis, such as ray tracing analysis or solving wave equations with rigorously coupled wave analysis or finite-difference time domain modeling.

11. The method of any one of the preceding claims, comprising fabricating an integrated circuit based on the validated physical layout.

12. A system for validating a physical layout of a circuit for electronic design automation, comprising: a database having stored therein a design library of parameterized cells, P-Cells, in a database, wherein the P-Cells include one or more optically active P-Cells and one or more ray path P-Cells; a processor configured to: generate, as a first output via a graphical user interface, a schematic circuit design comprising at least one of the optically active P-Cells; process the schematic circuit design to generate the physical layout of the circuit as a second output via the graphical user interface; extract one or more optical parameter from the physical layout; and generate validation data, as a third output via the graphical user interface, based on the schematic circuit design and the one or more extracted optical parameters for validation of the physical layout; wherein each optically active P-Cell comprises two or more first ports for facilitating parametrization of the input / output of electrical signals of an optical circuit element and at least one second port for facilitating parametrization of the input and / or output of optical signals of the optical element; andwherein the ray path P-Cell comprises two third ports for facilitating parametrization of properties of an optical path between two optical elements.

13. The system of claim 12, wherein the one or more optically active P-Cells comprise a photo-emitter optically active P-Cell. P-Cell14. The system of claims 12 or 13, wherein the one or more optically active P-Cells comprise a photodetector optically active P-Cell.

15. The system of any one of claims 12-14, wherein the one or more optically active P-Cells comprise a transceiver optically active P-Cell. P-Cell.

16. The system of any one of claims 12 to 15, wherein the processor is configured to use respective ray path P-Cells for interconnecting different pairs of optically active P-Cells.

17. The system of any one of claims 12 to 16, wherein the processor is configured to consider intentional coupling between one or more pairs of optically active P-Cells and / or unintentionally coupling between one or more pairs of optically active P-Cells.

18. The system of any one of claims 12 to 17, wherein the processor is configured for use one ray path P-Cell for interconnecting one optically active P-Cell to two or more optically active P-Cells.

19. The system of any one of claims 12 to 18, wherein the processor is configured to generate, via the graphical user interface, a modified schematic circuit design based on the generated physical layout and the extracted optical parameters and to generate the validation data based on the modified schematic circuit design and the one or more extracted optical parameters for validation of the physical layout.

20. The system of any one of claims 12 to 19, wherein the processor is configured to empirically determine parameters for parametrization of the properties of the optical path between two optical elements for modeling the appropriate optical coupling between optically active P-Cells.

21. The system of any one of claims 12 to 20, wherein the processor is configured to calculate parameters for parametrization of the properties of the optical path between two optical elements, wherein the calculating may comprise any modality of optical analysis, such as ray tracing analysis or solving wave equations with rigorously coupled wave analysis or finite-difference time domain modeling22. The system of any one of claims 12 to 21, comprising fabrication equipment for fabricating an integrated circuit based on the validated physical layout.

23. A computer readable data storage medium having stored thereon instructions executable by a system for validating a physical layout of a circuit for electronic design automation by executing the method of any one of claims 1 to 11.

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