Power semiconductor module having trapezoidal substrate

Abstract

A semiconductor device package. The semiconductor device package may include a baseplate, the baseplate comprising at least one through hole, and a substrate assembly, comprising a plurality of ceramic plates that are affixed to the base plate, wherein at least one ceramic plate of the plurality of ceramic plates comprises a trapezoidal shape. As such, at least one ceramic plate of the plurality of ceramic plates has a trapezoidal shape as defined within a main plane of base plate.

Description

POWER SEMICONDUCTOR MODULE HAVING TRAPEZOIDAL SUBSTRATEBackgroundField

[0001] Embodiments relate to the field of semiconductor devices, and in particular, packages for powering semiconductor chips.Discussion of Related Art

[0002] Power semiconductor modules based upon an insulating substrate (e.g. direct bonded copper (DBC), directed bonded aluminum (DBA), AMB) are known. Such substrates may generally be formed as a sandwich structure with an inner insulating substrate such as alumina or aluminum nitride, and a layer of copper or aluminum on opposite main surfaces of the inner insulating substrate. These power semiconductor modules include a housing, attached to the substrate by glue or other material, while semiconductor chips are attached to the substrate, by soldering, sintering, or other method. These semiconductor chips may include Si, SiC, GaN or other semiconductor materials, and may be employed as diodes, thyristors, silicon controlled rectifier (SCR), insulated gate bipolar transistors (IGBT), or metal oxide semiconductor field effect transistors (MOSFETS), as an example.

[0003] In known power Semiconductor Modules the substrates used to support semiconductor die (chips) are formed of ceramic such as aluminum oxide (A12O3), silicon nitride (Si3N4), or aluminum nitride (AIN), for example. The substrates are cut into rectangular shapes, which may or may not be attached to a base plate. In some examples, the generally rectangular substrate shapes may have chamfered comers. Generally, a housing such as a molded frame is formed to encapsulate the substrate. Additionally, a heat sink may be provided to provide coolingto the power semiconductor module. In order to attach the power semiconductor module to a heat sink, through holes may be formed in the power semiconductor module, such as in regions of the heat sink adjacent to the periphery of the substrates. These through holes may accommodate fasteners that are used to fasten the power semiconductor module to heat sink. Due to the limited size or footprint constraints inside the power semiconductor module package, in combination with required terminal and screw positions - it may be useful to extend some substrate areas to specific locations, which extensions cannot be realized by the use ok known, rectangular shaped substrates.

[0004] In view of the above, the present embodiments are provided.Brief Description of the Drawings

[0005] FIG. 1 A depicts a top view of a semiconductor device package assembly according to some embodiments of the disclosure;

[0006] FIG. IB depicts a top view of a semiconductor device package assembly according to other embodiments of the disclosure;

[0007] FIG. 1C depicts a top view of a semiconductor device package assembly according to further embodiments of the disclosure;

[0008] FIG. ID depicts a top view of a semiconductor device package assembly according to additional embodiments of the disclosure;

[0009] FIG. IE depicts a top view of a semiconductor device package assembly according to some embodiments of the disclosure;

[0010] FIG. IF depicts a top view of a semiconductor device package assembly according to still further embodiments of the disclosure;

[0011] FIG. 1G presents a reference semiconductor device package assembly; and

[0012] FIG. 2 depicts a semiconductor package module, according to embodiments of the disclosure.Description of Embodiments

[0013] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. The embodiments are not to be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey their scope to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0014] In the following description and / or claims, the terms "on," "overlying," "disposed on" and "over" may be used in the following description and claims. "On," "overlying," "disposed on" and "over" may be used to indicate that two or more elements are in direct physical contact with one another. Also, the term "on,", "overlying," "disposed on," and "over", may mean that two or more elements are not in direct contact with one another. For example, "over" may mean that one element is above another element while not contacting one another and may have another element or elements in between the two elements. Furthermore, the term "and / or" may mean "and", it may mean "or", it may mean "exclusive-or", it may mean "one", it may mean "some, but not all", it may mean "neither", and / or it may mean "both", although the scope of claimed subject matter is not limited in this respect.

[0015] In various embodiments, a semiconductor device package having a novel arrangement of substrates is provided.

[0016] FIG. 1A-FIG. IF depict a top view of alternative respective designs for a semiconductor device package assembly according to various embodiments of the disclosure.Turning to FIG. 1A is particular, there is shown a semiconductor device package assembly 100, according to embodiments of the disclosure. The semiconductor device package assembly 100 may fomi part of a semiconductor device package module that includes a housing and suitable connector components for external connections, and heat sink (not shown), for example. The semiconductor device package assembly 100 may include a baseplate 102 that extends in an X-Y plane of the cartesian coordinate system shown. The baseplate 102 may include at least one hole, such as a through hole, which components are shown as holes 101. In the embodiment specifically depicted in FIG. 1A, the baseplate 102 includes two of the holes 101, which holes may act as screw holes to accommodate fasteners to affix the baseplate 102 to another component, such as a heatsink, a housing, and so forth. In the embodiment of FIG 1A, the holes 101 are disposed at two opposite sides of the baseplate 102, at positions similar to the arrangement of many known semiconductor device modules.

[0017] The semiconductor device package assembly 100 further may include a substrate assembly 104 that includes a plurality of ceramic plates. These ceramic plates are shown as substrate 104A and substrate 104B in this embodiment. The substrate assembly 104 is affixed to the base plate 102. According to various embodiments of the disclosure, the substrate 104A and substrate 104B may include, in addition to a ceramic plate body, metal layers that are attached on opposite main surfaces of the substrate 104A and substrate 104B. For example, the substrate 104A and substrate 104B may be so called direct copper bonded (DCB) substrates, as known in the art, where layers of copper are bonded to opposite main surfaces of a ceramic substrate such as AI2O3.Alternatively, the substrate 104A and substrate 104B may be direct aluminum bonded (DAB) substrates where aluminum sheets are bonded to opposite main surfaces of a ceramic substrate.

[0018] As illustrated in FIG. 1A the substrate assembly 104 includes ceramic plates that have a trapezoidal shape, within the main plane of the substrate 102, meaning, within the X-Y plane. In particular, the substrate 104 A and substrate 104B are arranged as two opposing trapezoidal shapes, having similar edges that are aligned adjacent to one another.

[0019] More generally, according to various embodiments of the disclosure, a substrate assembly may be arranged to contain a plurality of substrates where the substrates have a quadrilateral shape that may be described as a trapezoid. In particular, a first ceramic plate has a first edge having a first length, and a second edge, having a second length, different from the first length, where the first edge is disposed opposite the second edge. In some embodiments of an ideal trapezoid shape, the first edge may lie parallel to the second edge in a given ceramic substrate, while in other embodiments, the first edge and the second edge may be mutually disposed with respect to another up to several degrees from parallel, but may still be deemed to form a trapezoid. In various embodiments, the first edge of a first ceramic plate faces a first edge of a second ceramic plate. Said differently, in some substrate assemblies, a shorter edge of a trapezoidal given ceramic plate will face a shorter edge of a another trapezoidal ceramic plate, and / or a longer edge of a trapezoidal ceramic plate will face a longer edge of an additional trapezoidal ceramic plate. Advantages of these configurations are detailed with respect to the figures to follow.

[0020] In the embodiment of FIG. 1A, a first edge 104A-1 of substrate 104A is shorter than a second edge 104A-2. The arrangement of FIG. 1A places the substrate 104B such that a first edge 104B-1 of substrate 104B faces the first edge 104A-1 of substrate 104A. In this embodiment, a first angled edge 104A-3 of the first ceramic plate (meaning the substrate 104A) and a first angled edge 104B-3 of the second ceramic plate (meaning substrate 104B) define a first recess region 108A on the base plate 102. Likewise, a second angled edge 104-A4 of the substrate104A and a second angled edge 104B-4 of the substrate 104B define a second recess region 108B on the base plate 102. Additionally, the hole 101 A may be first through hole and is disposed at least partially in the first recess region 108 A, while the hole 10 IB may be a second through hole and is disposed at least partially in the second recess region 108B.

[0021] An advantage of the configuration of FIG. 1A, is that the ceramic plates that form the substrate 104A and the substrate 104 B may be extended sufficiently, for example along the second edge 104A-2 of the substrate 104A, and along the second edge 104B-2 of the substrate 104B, in a manner that may accommodate the terminals 106 as shown, without interfering with the holes 101, or increasing the size of the base plate 102. Said differently, a given semiconductor device package configuration may specify a given base plate size, hole positions and temiinal positions, depending upon the number of semiconductor die to be placed in the package. The architecture of the trapezoidal substrates of FIG. 1A can more readily accommodate all these requirements than, for example, a rectangular substrate, arranged according to the known art. To illustrate this point further, FIG. 1G presents a reference semiconductor device package assembly 180, having a rectangular substrate, shown as substrate 182. In this example, the baseplate 102 may be the same size as in FIG. 1 A, while the terminal positions are also the same for terminals 106. In addition, the hole positions for hole 101A and hole 101B may be the same as in FIG. 1A. Note that this architecture may place the edge 182A and edge 182B of the substrate 182 unduly close to the hole 101A and hole 101B, respectively, as compared to the configuration of FIG. 1A.

[0022] FIG. IB depicts a top view of a semiconductor device package assembly 110, according to other embodiments of the disclosure. In this embodiment, the substrates are arranged on the baseplate 102 into a substrate assembly 114 that is composed of a set of four ceramic plates, substrate 114A, substrate 114B, substrate 114C, and substrate 114D. Each ceramic plate of the setof four ceramic plates has a trapezoidal shape with a short edge and a long edge that are opposite one another and may lie parallel to one another or close to parallel to one another, as discussed above. In this arrangement, a short edge 114A-1 of substrate 114A faces a short edge 114C-1 of substrate 114C, and a short edge 114B-1 of substrate 114B faces a short edge 114D-1 of substrate 114D. In this embodiment, a hole 101, such as a through hole, is disposed adjacent to short edge 114A-1, short edge 114B-1, short edge 114C-1, and short edge 114D-1, in a central region of the base plate 102.

[0023] FIG. 1C depicts a top view of a semiconductor device package assembly 120, according to further embodiments of the disclosure. In this embodiment, the substrate assembly 124 is formed of a pair of ceramic plates, shown as substrate 124A and substrate 124B. In this example, each substrate has a trapezoidal shape where the first edge, edge 124A-1 of substrate 124A faces the first edge 14B-1 of substrate 124B, where the length of the first edge 124A-1 and length of the first edge 124B-1 are greater than the length of the second edge 124A-2 and second edge 124B-2, respectively. As shown, the base plate 102 has a rectangular shape. An advantage of this configuration, where the second edge (meaning edge 124B-2 and edge 124A-2) of respective substrates are disposed toward respective opposite edges of the base plate 102, is that the substrate 124A and the substrate 124B together define a set of four corner regions on the base plate 102. These four comer regions, designated as comer region 126A, region 126B, region 126C, and region 126D, provide sufficient room to accommodate holes 101, without placing the substrates 124A, 124B unduly close to the holes.

[0024] FIG. ID depicts a top view of a semiconductor device package assembly 130, according to additional embodiments of the disclosure. In this embodiment, the architecture of semiconductor device package assembly 130 is similar to the architecture of semiconductor devicepackage assembly 100, where like features are labeled the same. A difference is that in this embodiment, the baseplate 102A has a plurality of chamfered edges.

[0025] FIG. IE depicts a top view of a semiconductor device package assembly 140, according to some additional embodiments of the disclosure. In this embodiment, a substrate assembly 144 includes a middle substrate, substrate 144 A, having a rectangular shape, which substrate is bounded by a trapezoidal substrate on two opposing sides, where the longer edges of the respective trapezoidal substrates are disposed adjacent to the substrate 144A. More particularly, the edge 144B-1 of substrate 144B lies adjacent to the left side of substrate 144A, while the edge 144C-1 of substrate 144C lies adjacent to the right side of substrate 144A. This configuration defines a set of four comer regions, shown as corner region 148 A, corner region 148B, corner region 148C, and comer region 148D in baseplate 102, so that a set of four of the holes 101 may be accommodated therein.

[0026] FIG. IF depicts a top view of a semiconductor device package assembly 150, according to still further embodiments of the disclosure. In this embodiment, the substrates are arranged on the baseplate 102 into a substrate assembly 144 that is composed of a set of four ceramic plates, substrate 154A, substrate 154B, substrate 154C, and substrate 154D. Like the embodiment of FIG. IB, each ceramic plate of the set of four ceramic plates has a trapezoidal shape with a short edge and a long edge that are opposite one another and may lie parallel to one another or close to parallel to one another, as discussed above. Similarly to the embodiment of FIG. IB, in this arrangement, a short edge 154A-1 of substrate 154A faces a short edge 154C-1 of substrate 154C, and a short edge 1 4B-1 of substrate 154B faces a short edge 154D-1 of substrate 154D. Unlike the configuration of FIG. IB, in this embodiment, the substrate 154A and substrate 154C are substantially smaller than the substrate 154B and substrate 154D. This circumstanceleads to the situation where a first of the holes 101 may be placed in a first region 158A that is bounded by the short edge 154A1 of the substrate 154A, a first angled edge 154B-2 of the substrate 154B, and a first angled edge 154D-2 of the substrate 154D. Moreover, a second of the holes 101 may be placed in a second region 158B that is bounded by the short edge 154C-1 of the substrate 154C, a second angled edge 154B-3 of the substrate 154B, and a second angled edge 154D-3 of the substrate 154D.

[0027] FIG. 2 depicts a semiconductor package module 200, according to embodiments of the disclosure. In this example, the semiconductor package module 200 includes a baseplate 202 and housing 203, which housing may be formed of a known material, such as an insulator. Substrates such as trapezoidal ceramic plates may be provided on the baseplate 202 and are not visible in the view of FIG. 2. The same applies to semiconductor die that are disposed on the substrates and terminal connections to the semiconductor die.

[0028] In summary, the present embodiments, by incorporating novel arrangements of trapezoidal substrates on a baseplate, overcome limitations of existing power device modules, by extending the area of substrates to specific located that can’t be realized using rectangular substrates.

[0029] While the present embodiments have been disclosed with reference to certain embodiments, numerous modifications, alterations and changes to the described embodiments are possible while not departing from the sphere and scope of the present disclosure, as defined in the appended claims. Accordingly, the present embodiments are not to be limited to the described embodiments, and may have the full scope defined by the language of the following claims, and equivalents thereof.

Claims

What is claimed is:

1. A semiconductor device package, comprising: a baseplate, the baseplate comprising at least one through hole; and a substrate assembly, comprising a plurality of ceramic plates that are affixed to the base plate, wherein at least one ceramic plate of the plurality of ceramic plates comprises a trapezoidal shape, wherein at least one ceramic plate of the plurality of ceramic plates has a trapezoidal shape as defined within a main plane of base plate.

2. The semiconductor device package of claim 1, wherein the at least one ceramic plate comprises: a first edge having a first length; and a second edge, having a second length, different from the first length, the second edge extending parallel to the first edge, wherein the first edge of the given ceramic plate faces a first edge of a second ceramic plate of the plurality of ceramic plates.

3. The semiconductor device package of claim 2, wherein the substrate assembly comprises a pair of ceramic plates, wherein the first length is less than the second length, wherein the first edge of the given ceramic plate is disposed adjacent to the first edge of the second ceramic plate, wherein a first angled edge of the given ceramic plate and a first angled edge of the second ceramic plate define a first recess region on the base plate, wherein a second angled edge of the given ceramic plate and a second angled edge of the second ceramic plate define a second recess region on the base plate, wherein the base plate comprises a first through hole, disposed at least partially within the first recess region, and wherein the base plate comprises a second through hole, disposed at least partially within the second recess region.

4. The semiconductor device package of claim 2, wherein the base plate comprises a plurality of chamfered edges.

5. The semiconductor device package of claim 2, wherein the substrate assembly comprises a pair of ceramic plates, wherein the first length is greater than the second length, wherein the first edge of the given ceramic plate is disposed adjacent to the first edge of the second ceramic plate, wherein the base plate has a rectangular shape, wherein the given ceramic plate and the second ceramic plate define a set of corner regions on the base plate, and wherein the base plate comprises a set of through holes that are disposed in the set of corner regions, respectively.

6. The semiconductor device package of claim 1, wherein the substrate assembly comprises a set of four ceramic plates, wherein each ceramic plate of the set of four ceramic plates has a short edge and a long edge that are parallel to one another, wherein a first short edge of a first ceramic plate faces a second short edge of a second ceramic plate, and wherein a third short edge of a third ceramic plate faces a fourth short edge of a fourth ceramic plate.

7. The semiconductor device package of claim 6, wherein the base plate comprises a through hole that is disposed adjacent to the first short edge, the second short edge, the third short edge, and the fourth short edge.

8. The semiconductor device package of claim 6, wherein the first ceramic plate and the second ceramic plate have a first size, andwherein the third ceramic plate and the fourth ceramic plate have a second size, greater than the first size.

9. The semiconductor device package of claim 8, wherein the base plate comprises: a first through hole, disposed in a first region that is bounded by the first short edge of the first substrate, a first angled edge of the third substrate, and a first angled edge of the fourth substrate; and a second through hole, disposed in a second region that is bounded by the second short edge of the second substrate, a second angled edge of the third substrate, and a second angled edge of the fourth substrate.

10. The semiconductor device package of claim 1, wherein the substrate assembly comprises: a rectangular substrate; a first trapezoidal substrate, having a first long edge facing a first edge of the rectangular substrate; and a second trapezoidal substrate, having a second long edge facing a second edge of the rectangular substrate, opposite the first edge.

11. The semiconductor device package of claim 10, wherein the first trapezoidal substrate and the second trapezoidal substrate define a set of corner regions on the base plate, and wherein the base plate comprises a set of through holes that are disposed in the set of corner regions, respectively.

12. A semiconductor device module, comprising: a heat sink; a baseplate, the baseplate comprising at least one through hole for affixing to the heat sink; anda substrate assembly, comprising a plurality of ceramic plates that are affixed to the base plate wherein at least one ceramic plate of the plurality of ceramic plates comprises a trapezoidal shape, wherein at least one ceramic plate of the plurality of ceramic plates has a trapezoidal shape as defined within a main plane of base plate.

13. The semiconductor device module of claim 12, wherein the at least one ceramic plate comprises: a first edge having a first length; and a second edge, having a second length, different from the first length, the second edge extending parallel to the first edge, wherein the first edge of the given ceramic plate faces a first edge of a second ceramic plate of the plurality of ceramic plates.

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