Chip package structure, electronic device, and manufacturing method for chip package structure

Abstract

The present application provides a chip package structure, an electronic device, and a manufacturing method for the chip package structure. The chip package structure comprises: a first carrier plate, a first chip, a second carrier plate, and a second chip which are successively stacked, wherein the first chip is electrically connected to the first carrier plate, and the second chip is electrically connected to the first carrier plate by means of the second carrier plate. The chip package structure also comprises a first heat conductor, wherein the first heat conductor is interposed between the first chip and the second chip, and a gap is present between the first heat conductor and the second chip. The chip package structure further comprises an adhesive layer, wherein the adhesive layer is located on the side of the second chip facing the second carrier plate, and the adhesive layer is partially located in the gap. The present application can improve the heat dissipation effect of the chip package structure, so as to reduce the thermal resistance, thereby avoiding overheating-induced thermal throttling of the second chip.

Description

Chip packaging structure, electronic device, and manufacturing method of chip packaging structure Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure, an electronic device, and a method for manufacturing the chip packaging structure. Background Art

[0002] Electronic devices like mobile phones and watches typically include a system-on-chip (SOC) and double data rate (DDR) synchronous dynamic random access memory (SDRAM). These SOC and DDR SDRAM need to be packaged together, for example using a fan-out package on package (FOPoP). Consequently, the SOC and DDR SDRAM are stacked.

[0003] In related technologies, a film layer and a glue layer are provided between the SOC and the DDR SDRAM. The thermal conductivity of the film layer and the glue layer is poor, which makes it difficult for the DDR SDRAM to dissipate heat, thereby causing the DDR SDRAM to overheat and reduce its frequency.

[0004] Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a chip packaging structure, an electronic device and a method for manufacturing a chip packaging structure, which can improve the heat dissipation effect of the chip packaging structure, thereby reducing thermal resistance and avoiding over-temperature and frequency reduction of the second chip.

[0006] In a first aspect of the present application, a chip packaging structure is provided, comprising: a first carrier, a first chip, a second carrier, and a second chip stacked in sequence, wherein the first chip is electrically connected to the first carrier. The second chip is electrically connected to the first carrier via the second carrier. Exemplarily, the chip packaging structure further comprises a conductor connected between the second carrier and the first carrier. The chip packaging structure further comprises a first heat conductor and an adhesive layer. The first heat conductor is stacked between the first chip and the second chip, and has a gap between the first heat conductor and the second chip. The adhesive layer is located on the side of the second chip facing the second carrier, and a portion of the adhesive layer is located in the gap between the second chip and the first heat conductor.

[0007] During use of the chip packaging structure, the second chip generates heat. Since the adhesive layer is located on the side of the second chip facing the second carrier, the second chip conducts the generated heat to the adhesive layer. Because the first heat conductor is located between the first and second chips, and part of the adhesive layer is located within the gap between the second chip and the first heat conductor, the adhesive layer conducts the heat from the second chip to the first heat conductor, where it is dissipated. Furthermore, heat is dissipated along the length and width of the first heat conductor, thereby improving the heat dissipation efficiency of the chip packaging structure, reducing thermal resistance, and preventing overheating and frequency throttling of the second chip.

[0008] In some embodiments, the chip packaging structure further includes a second heat conductor, which contacts the surface of the first chip facing the second carrier. During use, the first chip generates heat, and since the second heat conductor is in contact with the first chip, the first chip can conduct the generated heat to the second heat conductor, which then dissipates the heat along its length and width. This further improves the heat dissipation of the chip packaging structure, thereby reducing thermal resistance and preventing overheating and frequency throttling of the first chip.

[0009] Furthermore, the second carrier includes a dielectric structure and a first conductive portion. At least a portion of the first conductive portion is disposed within the dielectric structure, and the first and second heat conductors are respectively connected to the first conductive portion. The first conductive portion is typically made of metal, which has excellent thermal conductivity. Thus, the second heat conductor can transfer heat to the first heat conductor via the first conductive portion, thereby dissipating heat collectively through the first heat conductor, the first conductive portion, and the second heat conductor, thereby further improving heat dissipation.

[0010] Furthermore, the thickness of the first heat conductor is greater than that of the second heat conductor. Thus, when the first chip conducts heat to the first heat conductor through the second heat conductor and the first conductive portion, the heat can be dissipated by the first heat conductor. Because the first heat conductor is thicker than the second heat conductor, the first heat conductor can dissipate heat along its height, further improving the heat dissipation effect.

[0011] Based on this, the second carrier also includes a second conductive portion, at least a portion of which is disposed within the dielectric structure, and a surface facing the second conductive portion is exposed from the dielectric structure and connected to the second conductive portion, and the second conductive portion is electrically isolated from the first conductive portion. The first carrier may also include a dielectric structure and a first conductive portion and a second conductive portion disposed on the dielectric structure, wherein the first conductive portion of the first carrier is connected to the first chip. The second conductive portion of the second carrier is connected to the second conductive portion of the first carrier via a conductor. Thus, the second carrier can both facilitate heat conduction between the first heat conductor and the second heat conductor and enable connection between the second chip and the first carrier.

[0012] Regarding the structure of the first conductive part, in one possible embodiment, the first conductive part includes a metal block, and the thickness of the metal block is the same as the thickness of the second carrier. That is to say, the surface of the first conductive part facing the first chip and the surface of the first conductive part facing the second chip can be the same size as the surface of the second chip facing the first conductive part. Since the first conductive part can have a heat-conducting effect, adopting this structure can increase the heat-conducting area of ​​the first conductive part, thereby improving the heat-conducting effect of the first conductive part. In addition, the contact area between the first conductive part and the second heat conductor is larger, and the contact area between the first conductive part and the first heat conductor is larger. Therefore, the first conductive part can also quickly conduct the heat conducted by the second heat conductor to the first heat conductor, thereby facilitating rapid heat dissipation.

[0013] In another possible embodiment, the first conductive portion includes a metal layer and a connecting portion. The thickness of the metal layer is less than that of the second carrier plate, and the metal layer is connected to the second heat conductor and the first heat conductor respectively via the connecting portion. For example, the metal layer is located in the middle of the second carrier plate in the thickness direction. There may be multiple connecting portions, with some of the multiple connecting portions located between the metal layer and the first heat conductor, and others located between the metal layer and the second heat conductor. Thus, heat conduction between the first heat conductor and the second heat conductor is achieved.

[0014] In some embodiments, the chip packaging structure further includes a third heat conductor, the third heat conductor being located on a side of the second carrier facing away from the first carrier, and the third heat conductor being thermally connected to the first conductive portion. The thermal connection may refer to a direct connection or a connection via a heat conductor. Thus, after the first heat conductor and the second heat conductor transfer heat to the first conductive portion, the first conductive portion can transfer the heat to the third heat conductor, and the heat is dissipated through the third heat conductor. In other words, heat can be dissipated collectively by the first heat conductor, the first conductive portion, the second heat conductor, and the third heat conductor, thereby further improving the heat dissipation effect.

[0015] Based on this, the chip packaging structure also includes a third carrier stacked between the second carrier and the second heat conductor, and the third heat conductor is located on the side of the third carrier facing away from the second carrier. The third carrier includes a dielectric structure and a conductive structure, at least a portion of the conductive structure is located within the dielectric structure, and the conductive structure is connected to the second heat conductor, the third heat conductor, and the first conductive portion, respectively. The second heat conductor can conduct heat to the third heat conductor through the first conductive portion of the second carrier and the conductive structure of the third carrier in sequence, and the first heat conductor can conduct heat to the third heat conductor through the conductive structure of the third carrier, thereby dissipating heat through the second heat conductor, the first conductive portion of the second carrier, the conductive structure of the third carrier, the first heat conductor, and the third heat conductor, thereby further improving the heat dissipation effect.

[0016] Furthermore, the conductive structure includes a first conductive portion and a second conductive portion arranged along a first direction, and a connecting portion connecting the first conductive portion and the second conductive portion. The first conductive portion of the conductive structure corresponds to and is connected to the first conductive portion of the second carrier. The third heat conductor is disposed on the second conductive portion, and the first direction forms an angle with the thickness direction of the chip package structure. Thus, the second heat conductor can sequentially conduct heat to the first heat conductor through the first conductive portion of the second carrier and the first conductive portion of the third carrier. The second heat conductor can also sequentially conduct heat to the third heat conductor through the first conductive portion of the second carrier, the first conductive portion of the third carrier, the connecting portion, and the second conductive portion of the third carrier.

[0017] Regarding the structure of the first conductive portion of the conductive structure, in one possible embodiment, the first conductive portion of the conductive structure comprises a metal block, and the thickness of the metal block of the conductive structure is the same as the thickness of the third carrier. The surface of the first conductive portion facing the second chip is a complete surface, and the surface of the first conductive portion facing the second carrier is also a complete surface. Because the first conductive portion can serve as a heat conductor, adopting this structure can increase the heat conduction area of ​​the first conductive portion, thereby improving the heat conduction effect of the first conductive portion. In addition, the contact area between the first conductive portion and the first heat conductor is larger, which also achieves better heat conduction effect.

[0018] In another possible embodiment, the first conductive portion of the conductive structure includes a metal layer and a connecting portion. The thickness of the metal layer of the conductive structure is less than the thickness of the third carrier plate, and the metal layer is connected to the first heat conductor and the first conductive portion of the second carrier plate via the connecting portion. For example, the metal layer is located in the middle of the second carrier plate in the thickness direction. There may be multiple connecting portions, with some of the multiple connecting portions located between the metal layer and the second carrier plate, and others located between the metal layer and the first heat conductor. Thus, heat conducted from the second heat conductor via the second carrier plate can be conducted to the first heat conductor via the metal layer.

[0019] In some embodiments, the chip packaging structure further includes a second heat conductor, wherein the first heat conductor and the second heat conductor are stacked between the first chip and the second chip, and the thickness of the first heat conductor is greater than the thickness of the second heat conductor. In this way, the first chip can conduct the generated heat to the second heat conductor, and then the heat is conducted from the second heat conductor to the first heat conductor. As a result, the first heat conductor and the second heat conductor can jointly dissipate heat from the chip packaging structure. Since the second heat conductor is located above the first chip and the thickness of the first chip is greater than that of the second chip, the second heat conductor can assist the first chip in dissipating heat in the height direction, thereby further improving the heat dissipation effect.

[0020] Based on this, the chip packaging structure further includes a connecting layer stacked between the first heat conductor and the second heat conductor. In this way, when manufacturing the chip packaging structure, the first heat conductor can be fixed to the second heat conductor via the connecting layer, thereby facilitating the fixing of the first heat conductor to the second heat conductor.

[0021] Furthermore, the connecting layer is a silver paste layer or a solder layer. Since the material of the silver paste is silver, it is a metal. The material of the solder layer is usually tin, which is also a metal. Metal has good thermal conductivity. Therefore, after the first chip transfers heat to the second heat conductor, the second heat conductor can better transfer heat to the first heat conductor through the connecting layer, thereby dissipating heat through the first heat conductor, the connecting layer and the second heat conductor. Therefore, when the connecting layer is a silver paste layer or a solder layer, it can better transfer heat between the second heat conductor and the first heat conductor, thereby further improving the heat dissipation effect of the chip packaging structure.

[0022] Furthermore, the second carrier is provided with a through hole, and a portion of the first heat conductor is located in the through hole. In this way, the through hole provided on the second carrier can provide a space for the first heat conductor to avoid, thereby facilitating the arrangement of the first heat conductor between the first chip and the second chip.

[0023] Furthermore, the top surface of the first heat conductor is higher than the top surface of the second carrier. That is, the surface of the first heat conductor facing away from the first carrier is higher than the surface of the second carrier facing away from the first carrier. Furthermore, the surface of the first heat conductor facing the first carrier is lower than, or even with, the surface of the second carrier facing the first carrier. In other words, the thickness of the first heat conductor is greater than that of the second carrier. The thicker the first heat conductor, the greater its heat dissipation area, thereby enhancing the heat dissipation efficiency of the first heat conductor.

[0024] In some embodiments, the first heat conductor comprises a metal or silicon. Exemplarily, the first heat conductor comprises a metal, such as copper or aluminum. Because metals have good thermal conductivity, when the first heat conductor comprises a metal, heat conduction and heat dissipation are better achieved, thereby further enhancing the heat dissipation effect of the chip package structure. The second heat conductor may also comprise a metal or silicon.

[0025] Moreover, the material of the third heat conductor includes metal or silicon. Similarly, when the material of the third heat conductor includes metal, heat conduction and heat dissipation can be better achieved, thereby further improving the heat dissipation effect of the chip packaging structure.

[0026] In a second aspect of the present application, an electronic device is provided, comprising a circuit board and a chip packaging structure according to any one of the above embodiments, wherein the chip packaging structure is electrically connected to the circuit board. The electronic device can achieve all the effects of the chip packaging structure.

[0027] A third aspect of the present application provides a method for manufacturing a chip packaging structure. The method comprises: manufacturing a first carrier on a substrate; securing a first chip on the first carrier; manufacturing a second carrier on the first carrier; manufacturing a first heat conductor; securing a second chip on the second carrier, with the first heat conductor positioned between the first and second chips, and with a gap between the first heat conductor and the second chip; manufacturing an adhesive layer on a side of the second chip facing the second carrier, with a portion of the adhesive layer positioned between the second chip and the first heat conductor; and removing the substrate.

[0028] During use of the chip packaging structure, the second chip generates heat. Since the adhesive layer is located on the side of the second chip facing the second carrier, the second chip conducts the generated heat to the adhesive layer. Because the first heat conductor is located between the first and second chips, and part of the adhesive layer is located within the gap between the second chip and the first heat conductor, the adhesive layer conducts the heat from the second chip to the first heat conductor, where it is dissipated. Furthermore, heat is dissipated along the length and width of the first heat conductor, thereby improving the heat dissipation efficiency of the chip packaging structure, reducing thermal resistance, and preventing overheating and frequency throttling of the second chip.

[0029] In some embodiments, after securing the first chip to the first carrier, the manufacturing method further includes forming a second heat conductor on the first chip, the second heat conductor being positioned between the first heat conductor and the first chip, the thickness of the second heat conductor being less than that of the first heat conductor. During use of the chip packaging structure, the first chip also generates heat, and since the second heat conductor is in contact with the first chip, the first chip can conduct the generated heat to the second heat conductor, where it is dissipated. This further improves the heat dissipation of the chip packaging structure, thereby reducing thermal resistance and preventing overheating and frequency throttling of the first chip.

[0030] Furthermore, the second carrier includes a dielectric structure and a first conductive portion, at least a portion of the first conductive portion is disposed within the dielectric structure, and the first conductive portion is connected to the second heat conductor. The step of fabricating the first heat conductor includes fabricating the first heat conductor on the dielectric structure and the first conductive portion. This allows the first heat conductor and the second heat conductor to be connected via the first conductive portion. The first conductive portion is typically made of metal, which has excellent thermal conductivity. Thus, the second heat conductor can transfer heat to the first heat conductor via the first conductive portion, thereby dissipating heat collectively through the first heat conductor, the first conductive portion, and the second heat conductor, further enhancing heat dissipation.

[0031] Based on this, after the step of manufacturing the second carrier on the first carrier, the manufacturing method further includes: manufacturing a third carrier on the second carrier, the third carrier including a dielectric structure and a conductive structure, at least a portion of the conductive structure being disposed within the dielectric structure, and the conductive structure being connected to the first conductive portion; manufacturing a third heat conductor on the third carrier, the conductive structure being connected to the third heat conductor; and the step of manufacturing the first heat conductor includes: manufacturing a first heat conductor on the third carrier, the first heat conductor being connected to the conductive structure. In this way, after the second heat conductor and the first heat conductor transfer heat to the first conductive portion, the first conductive portion can transfer heat to the third heat conductor, and the heat is dissipated through the third heat conductor. In other words, the heat can be dissipated collectively by the first heat conductor, the first conductive portion, the second heat conductor, and the third heat conductor, thereby further improving the heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] FIG1 is a schematic structural diagram of a chip packaging structure according to a first embodiment of the present application;

[0034] FIG2 is a schematic structural diagram of a chip packaging structure in a second embodiment of the present application;

[0035] FIG3 is a cross-sectional view taken along line AA in FIG1 ;

[0036] FIG4 is a schematic structural diagram of a chip packaging structure in a third embodiment of the present application;

[0037] FIG5 is a schematic structural diagram of a chip packaging structure in a fourth embodiment of the present application;

[0038] FIG6 is a cross-sectional view taken along line BB in FIG5 ;

[0039] FIG7 is a cross-sectional view taken along line CC in FIG5 ;

[0040] FIG8 is another cross-sectional view taken along CC in FIG5 ;

[0041] FIG9 is a schematic structural diagram of a chip packaging structure in a fifth embodiment of the present application;

[0042] FIG10 is a schematic flow chart of a method for manufacturing the chip packaging structure shown in FIG1 ;

[0043] FIG11 is a schematic diagram of the manufacturing process of the first part of the steps in the manufacturing method shown in FIG10;

[0044] FIG12 is a schematic diagram of the manufacturing process of the second part of the steps in the manufacturing method shown in FIG10;

[0045] FIG13 is a schematic diagram of the manufacturing process of the third step in the manufacturing method shown in FIG10;

[0046] FIG14 is a schematic flow chart of a method for manufacturing the chip packaging structure of FIG2 ;

[0047] FIG15 is a schematic diagram of the manufacturing process of the first part of the steps in the manufacturing method shown in FIG14;

[0048] FIG16 is a schematic diagram of the manufacturing process of the second part of the steps in the manufacturing method shown in FIG14;

[0049] FIG17 is a schematic diagram of a manufacturing process of some steps in another manufacturing method of the chip packaging structure shown in FIG2 ;

[0050] FIG18 is a schematic diagram of the manufacturing process of the third step in the manufacturing method shown in FIG14;

[0051] FIG19 is a schematic flow chart of a method for manufacturing the chip packaging structure shown in FIG5 ;

[0052] FIG20 is a schematic diagram of the manufacturing process of some steps in the manufacturing method shown in FIG19 .

[0053] Icons: 1-chip packaging structure; 10-first carrier; 11-dielectric structure; 12-first conductive portion; 13-second conductive portion; 20-first chip; 31-first dielectric layer; 311-conductor; 312-groove; 32-third dielectric layer; 34-fourth dielectric layer; 35-adhesive layer; 40-second carrier; 41-dielectric structure; 42-first conductive portion; 421-metal layer; 422-connecting portion; 43-through hole; 44-second conductive portion; 51-second thermal conductor; 511 -first sub-heat conductor; 512-second sub-heat conductor; 52-connecting layer; 53-first heat conductor; 60-second chip; 61-substrate; 62-wafer; 63-second solder ball; 64-second dielectric layer; 71-capacitor; 72-first solder ball; 73-substrate; 80-third carrier; 81-dielectric structure; 82-conductive structure; 821-first conductive part; 8211-metal layer; 8212-connecting part; 822-second conductive part; 823-connecting part; 90-third heat conductor. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0056] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0057] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0058] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0060] Electronic devices such as mobile phones, watches, and tablets usually include a circuit board and a chip packaging structure, and the chip packaging structure is electrically connected to the circuit board. The chip packaging structure includes at least two chips. Here, the chip packaging structure includes two chips as an example for explanation. The two chips can be SOC and DDR SDRAM, respectively. When making the chip packaging structure, the SOC and DDR SDRAM can be packaged in a FOPoP manner. Therefore, the SOC and DDR SDRAM are stacked. A film layer and an adhesive layer are provided between the SOC and the DDR SDRAM. The thermal conductivity of the film layer and the adhesive layer is poor, which makes it difficult for the DDR SDRAM to dissipate heat, which in turn causes the DDR SDRAM to overheat and reduce its frequency.

[0061] Based on this, as shown in Figure 1, an embodiment of the present application provides a chip packaging structure 1, including: a first carrier 10, a first chip 20, a first dielectric layer 31, a second chip 60, a first heat conductor 53, a second heat conductor 51, a connecting layer 52, a second carrier 40 and a third dielectric layer 32.

[0062] The first carrier 10 may be a metal redistribution layer (RDL). As shown in FIG1 , the first carrier 10 is located near the bottom of the chip package structure 1 and includes a dielectric structure 11, a first conductive portion 12, and a second conductive portion 13. A portion of the first conductive portion 12 is located within the dielectric structure 11, while the remaining portion extends beyond the bottom of the dielectric structure 11 and is connected to a capacitor 71 located at the bottom of the first carrier 10. The top surface of the first conductive portion 12 is flush with the top surface of the dielectric structure 11, that is, the top surface of the first conductive portion 12 is exposed from the dielectric structure 11.

[0063] It is understood that in the embodiment of the present application, both the "top surface" and the "bottom surface" are defined with reference to the first solder ball 72 as the bottom of the chip package structure 1. For any component, the surface facing the first solder ball 72 is the bottom surface, and the surface facing away from the first solder ball 72 is the top surface.

[0064] As shown in Figure 1 , a portion of the second conductive portion 13 is located within the dielectric structure 11, while the remaining portion extends from the bottom surface of the first carrier 10 and is connected to a first solder ball 72 disposed on the bottom surface of the first carrier 10. The top surface of the second conductive portion 13 is flush with the top surface of the dielectric structure 11, that is, the top surface of the second conductive portion 13 is exposed from the dielectric structure 11.

[0065] As shown in FIG1 , the two first conductive parts 12 are located between the two second conductive parts 13 . The two first conductive parts 12 are electrically isolated from each other, the two second conductive parts 13 are electrically isolated from each other, and the first conductive part 12 and the second conductive part 13 are also electrically isolated from each other.

[0066] As shown in Figure 1, the first chip 20 is provided on the first carrier 10. The first chip 20 can be an unpackaged chip, that is, a bare chip. Exemplarily, in this embodiment, the first chip 20 can be a SOC. The SOC can be an integrated circuit with a dedicated purpose, which contains a complete structure for implementing one or more functions and is embedded with software. In other embodiments, the first chip 20 can also be a packaged chip. The first chip 20 can be soldered to the first carrier 10 using a chip flip-chip process. The pads on the first chip 20 can be connected to the pads on the first conductive portion 12 of the first carrier 10 via solder balls, thereby achieving electrical connection between the first chip 20 and the first carrier 10.

[0067] After soldering the first chip 20 to the first carrier 10, the first chip 20 can be plastic-encapsulated to obtain the first dielectric layer 31 as shown in Figure 1. The bottom surface of the first chip 20 is higher than the bottom surface of the first dielectric layer 31, and the top surface of the first chip 20 is lower than the top surface of the first dielectric layer 31.

[0068] As shown in FIG1 , the chip package structure 1 further includes a conductor 311 disposed in the same layer as the first dielectric layer 31. The conductor 311 may be a through interposer via (TIV). The thickness of the conductor 311 may be the same as that of the first dielectric layer 31. That is, the bottom surface of the conductor 311 is flush with the bottom surface of the first dielectric layer 31, and the top surface of the conductor 311 is flush with the top surface of the first dielectric layer 31. The bottom surface of the conductor 311 is connected to the second conductive portion 13 of the first carrier 10. The material of the conductor 311 may include copper, nickel, silver, or tin.

[0069] As shown in Figure 1, the second carrier 40 is disposed on the side of the first dielectric layer 31 facing away from the first carrier 10. In other words, the first dielectric layer 31 is stacked between the first carrier 10 and the second carrier 40. The second carrier 40 includes a dielectric structure 41 and a first conductive portion 42. A portion of the first conductive portion 42 is located within the dielectric structure 41, while the remainder of the first conductive portion 42 extends above the top surface of the dielectric structure 41. The bottom surface of the first conductive portion 42 is flush with the bottom surface of the dielectric structure 41 and is connected to the conductor 311. Thus, the first conductive portion 42 can be electrically connected to the second conductive portion 13 of the first carrier 10 and the first solder ball 72 via the conductor 311.

[0070] In this embodiment, the second chip 60 can be a packaged chip, such as a DRR SDRAM. The second chip 60 can be located on the side of the second carrier 40 facing away from the first carrier 10. The second chip 60 includes a substrate 61, a chip 62, second solder balls 63, and a second dielectric layer 64. The substrate 61 is soldered to the first conductive portion 42 of the second carrier 40 via the second solder balls 63. Thus, the second chip 60 can be connected to the second conductive portion 13 of the first carrier 10 via the second solder balls 63, the first conductive portion 42 of the second carrier 40, and the conductor 311. The chip 62 is fixed to the top surface of the substrate 61, and the top surface of the chip 62 is also electrically connected to the top surface of the substrate 61. The bottom surface of the substrate 61 is flush with the bottom surface of the second dielectric layer 64, while the top surface of the second dielectric layer 64 is higher than the top surface of the chip 62.

[0071] As shown in FIG1 , the second heat conductor 51 covers the surface of the first chip 20 facing the second chip 60, that is, the second heat conductor 51 covers the top surface of the first chip 20. Exemplarily, the second heat conductor 51 is in contact with the top surface of the first chip 20. During the application of the chip packaging structure 1, the first chip 20 generates heat. When the second heat conductor 51 covers the top surface of the first chip 20, the first chip 20 can conduct the generated heat to the second heat conductor 51, and dissipate the heat in the X and Y directions (not shown in FIG1 ) through the second heat conductor 51, thereby improving the heat dissipation effect of the chip packaging structure 1, thereby reducing thermal resistance, and further avoiding over-temperature and frequency reduction of the first chip 20. Among them, the Y direction is a direction perpendicular to both the X and Z directions shown in FIG1 .

[0072] As shown in Figure 1, the second heat conductor 51 can be located below the second carrier 40. That is, the top surface of the second heat conductor 51 can be lower than the bottom surface of the second carrier 40. To reserve space for the second heat conductor 51, a through hole 43 is provided in the middle of the second carrier 40. The size of the through hole 43 along the X direction can be smaller than the size of the first chip 20 along the X direction. To increase the heat dissipation area of ​​the second heat conductor 51 and improve the heat dissipation effect, the size of the second heat conductor 51 along the X direction can be the same as the size of the first chip 20 along the X direction. That is, the size of the second heat conductor 51 along the X direction is larger than the size of the through hole 43 along the X direction.

[0073] In this embodiment, the material of the second heat conductor 51 may include metal or silicon. When the material of the second heat conductor 51 includes metal, the material of the second heat conductor 51 may specifically include copper or aluminum. Metal has good thermal conductivity. Therefore, when the material of the second heat conductor 51 includes metal, the second heat conductor 51 can better dissipate heat.

[0074] As shown in FIG1 , the connecting layer 52 covers the second heat conductor 51. The dimension of the connecting layer 52 along the X-direction can be the same as the dimension of the first heat conductor 53 along the X-direction. The bottom surface of the connecting layer 52 is lower than the bottom surface of the second carrier 40, and the top surface of the connecting layer 52 can be flush with the bottom surface of the second carrier 40 or higher than the top surface of the second carrier 40.

[0075] In this embodiment, the connection layer 52 is a silver paste layer or a solder layer. Since the silver paste is made of silver, it is a metal. The solder layer is typically made of tin, also a metal, which has good thermal conductivity. In other embodiments, the connection layer 52 may also be a connecting adhesive layer, exemplarily a die attach film (DAF).

[0076] The second heat conductor 51 is typically thin. To improve heat dissipation, a first heat conductor 53 can be disposed between the connection layer 52 and the second chip 60. The thickness of the first heat conductor 53 is greater than that of the second heat conductor 51. This allows the first chip 20 to transfer heat to the second heat conductor 51. The second heat conductor 51 can then transfer the heat to the first heat conductor 53 through the connection layer 52, further dissipating heat through the second heat conductor 51, the connection layer 52, and the first heat conductor 53. Because the first heat conductor 53 is located above the first chip 20, it can assist in dissipating heat from the first chip 20 along the Z-direction, further improving heat dissipation.

[0077] It can be understood that, in the embodiment of the present application, “above” and “below” are both directions determined with reference to the first solder ball 72 as the bottom of the chip packaging structure 1 .

[0078] In addition, when the connection layer 52 between the second heat conductor 51 and the first heat conductor 53 is a silver paste layer or a solder layer, heat can be better conducted between the second heat conductor 51 and the first heat conductor 53 , thereby further improving the heat dissipation effect of the chip packaging structure 1 .

[0079] Furthermore, the surface of the first heat conductor 53 facing the first carrier 10 is lower than the surface of the second carrier 40 facing the first carrier 10, and the surface of the first heat conductor 53 facing away from the first carrier 10 is higher than the surface of the second carrier 40 facing away from the first carrier 10. In other words, the bottom surface of the first heat conductor 53 is lower than the bottom surface of the second carrier 40, and the top surface of the first heat conductor 53 is higher than the top surface of the second carrier 40. In other words, the thickness of the first heat conductor 53 is greater than the thickness of the second carrier 40. The thicker the first heat conductor 53, the larger the heat dissipation area of ​​the first heat conductor 53, thereby improving the heat dissipation effect of the first heat conductor 53. Furthermore, the top surface of the first heat conductor 53 is lower than the bottom surface of the substrate 61 of the second chip 60. This prevents the second solder balls 63 of the second chip 60 from being unable to contact and connect with the first conductive portion 42 of the second carrier 40 due to the top surface of the first heat conductor 53 being too high.

[0080] There is a gap between the two sides of the first heat conductor 53 and the sidewalls of the through hole 43. In this way, the through hole 43 provided on the second carrier 40 can provide a space for the first heat conductor 53 to avoid, thereby facilitating the installation of the first heat conductor 53 between the first chip 20 and the second chip 60.

[0081] The first heat conductor 53 is made of metal or silicon. Specifically, the first heat conductor 53 may be copper or aluminum. Since metals have good thermal conductivity, metals can better conduct and dissipate heat, thereby further improving the heat dissipation of the chip package structure 1.

[0082] To enhance the connection strength between the first chip 20, the second carrier 40, the second heat conductor 51, the connecting layer 52, the first heat conductor 53, and the first chip 20, in this embodiment, as shown in FIG1 , the chip package structure 1 further includes an adhesive layer 35. A portion of the adhesive layer 35 is located between the second chip 60 and the second carrier 40, a portion of the adhesive layer 35 is located within the gap between the first heat conductor 53 and the second carrier 40, and a portion of the adhesive layer 35 is also located within the gap between the second chip 60 and the first heat conductor 53. When the chip package structure 1 is in use, the second chip 60 generates heat. Since the adhesive layer 35 is located on the side of the second chip 60 facing the second carrier 40, the second chip 60 transfers the generated heat to the adhesive layer 35. Because the first heat conductor 53 is located between the first chip 20 and the second chip 60, and part of the adhesive layer 35 is located within the gap between the second chip 60 and the first heat conductor 53, the adhesive layer 35 can transfer heat conducted by the second chip 60 to the first heat conductor 53, where it is dissipated by the first heat conductor 53. Therefore, the heat generated by the second chip 60 can be transferred to the first heat conductor 53 through the adhesive layer 35, and dissipated along the X and Y directions of the first heat conductor 53 (not shown in FIG. 1 ). This improves the heat dissipation effect of the chip package structure 1, thereby reducing thermal resistance and preventing overheating and frequency throttling of the second chip 60.

[0083] After the first chip 20 is fixed to the second carrier 40 , the first chip 20 may be plastic-encapsulated to form the third dielectric layer 32 . In other words, the third dielectric layer 32 may be disposed on the top surface of the second carrier 40 and wrap the first chip 20 and the adhesive layer 35 .

[0084] Other embodiments of the present application differ from the embodiment shown in FIG1 in the structure of the second carrier 40 and the fact that the connection layer 52 is removed from the embodiment shown in FIG1 . For example, in this embodiment, as shown in FIG2 , the second carrier 40 includes a dielectric structure 41, a first conductive portion 42, and a second conductive portion 44. The second heat conductor 51 and the first heat conductor 53 are connected via the first conductive portion 42.

[0085] Specifically, as shown in Figure 3, the second carrier 40 includes two second conductive portions 44 disposed opposite each other and spaced apart from each other, with the two second conductive portions 44 being electrically isolated from each other. As shown in Figure 2, a portion of the second conductive portion 44 is disposed within the dielectric structure 41, while the remainder extends above the top surface of the dielectric structure 41 and connects to the second solder balls 63 of the second chip 60. The bottom surface of the second conductive portion 44 is flush with the bottom surface of the dielectric structure 41, that is, the bottom surface of the second conductive portion 44 is exposed above the bottom surface of the dielectric structure 41 and is connected to the conductor 311. Thus, the second chip 60 can be electrically connected to the second conductive portion 13 of the first carrier 10 via the second conductive portion 44 and the conductor 311.

[0086] As shown in FIG2 , the first conductive portion 42 is located between the two second conductive portions 44 and is electrically isolated from the second conductive portions 44. The top surface of the first conductive portion 42 is flush with the top surface of the dielectric structure 41 and is connected to the bottom surface of the first thermal conductor 53. The bottom surface of the first conductive portion 42 is also flush with the bottom surface of the dielectric structure 41 and is connected to the top surface of the second thermal conductor 51. In other words, the first conductive portion 42 is connected between the second thermal conductor 51 and the first thermal conductor 53. Because the first conductive portion 42 can be made of metal, which has high thermal conductivity, after the first chip 20 transfers the generated heat to the second thermal conductor 51, the second thermal conductor 51 can transfer the heat to the first thermal conductor 53 through the first conductive portion 42. Heat is thus dissipated through the second thermal conductor 51, the first conductive portion 42, and the first thermal conductor 53, thereby further improving the heat dissipation effect. Therefore, the second carrier 40 can not only realize the connection between the second chip 60 and the first carrier 10 , but also realize the heat conduction between the second heat conductor 51 and the first heat conductor 53 .

[0087] 2 , to achieve electrical isolation between the first conductive portion 42 and the second conductive portion 44, the first conductive portion 42 has a smaller dimension along the X direction than the second heat conductor 51. The first heat conductor 53 may have the same dimension along the X direction as the first conductive portion 42.

[0088] Regarding the structure of the first conductive portion 42, in one possible embodiment, as shown in FIG2 , the first conductive portion 42 includes a metal layer 421 and a connecting portion 422. The thickness of the metal layer 421 is less than that of the second carrier 40, and the metal layer 421 is connected to the first heat conductor 53 and the second heat conductor 51, respectively, via the connecting portion 422. Exemplarily, the metal layer 421 is located in the middle portion of the second carrier 40 in the Z direction. There may be multiple connecting portions 422, with some of the multiple connecting portions 422 located between the metal layer 421 and the second heat conductor 51, and some of the multiple connecting portions 422 located between the metal layer 421 and the first heat conductor 53. Thus, heat conduction between the second heat conductor 51 and the first heat conductor 53 can be achieved.

[0089] In another possible embodiment, as shown in Figure 4, the first conductive part 42 includes a metal block, and the thickness of the metal block is the same as the thickness of the second carrier 40. Exemplarily, the structure of the metal block can be a cubic structure. The surface size of the metal block facing the second heat conductor 51 and the surface size of the metal block facing the first heat conductor 53 are both the same as the surface size of the first heat conductor 53 facing the second carrier 40, that is, the bottom surface size of the metal block and the top surface size of the metal block are both the same as the bottom surface size of the first heat conductor 53. That is, the bottom surface size of the first conductive part 42 and the top surface size of the first conductive part 42 are both the same as the bottom surface size of the first conductive part 42. Since the first conductive part 42 can play a heat-conducting effect, adopting this structure can increase the heat-conducting area of ​​the first conductive part 42, thereby increasing the heat-conducting effect of the first conductive part 42. In addition, the contact area between the first conductive part 42 and the first heat conductor 53 is larger, and the contact area between the first conductive part 42 and the second heat conductor 51 is larger. Therefore, the first conductive part 42 can also quickly conduct the heat conducted by the second heat conductor 51 to the first heat conductor 53, thereby facilitating rapid heat dissipation.

[0090] In other embodiments of the present application, as shown in FIG5 , the difference from the embodiment shown in FIG2 is that the second heat conductor 51 and the chip packaging structure 1 further include a third heat conductor 90 and a third carrier 80 based on the embodiment shown in FIG2 .

[0091] As shown in Figure 5 , the second heat conductor 51 includes a first sub-heat conductor 511 and a second sub-heat conductor 512. The first sub-heat conductor 511 is connected to the first chip 20, and the second sub-heat conductor 512 is connected between the first sub-heat conductor 511 and the first conductive portion 42. The top surface of the second sub-heat conductor 512 is higher than the bottom surface of the dielectric structure 41 of the second carrier 40.

[0092] As shown in FIG5 , the third carrier 80 may be an RDL. The third carrier 80 is stacked between the second carrier 40 and the first heat conductor 53. The third carrier 80 includes a dielectric structure 81 and a conductive structure 82. As shown in FIG6 , the conductive structure 82 includes a first conductive portion 821, a plurality of second conductive portions 822, and a connecting portion 823. The number of first conductive portions 821 may be one or more. For example, in FIG6 , the number of first conductive portions 821 is two, and the two first conductive portions 821 are arranged along the X direction and have a spacing therebetween. As shown in FIG5 , in this embodiment, the two first conductive portions 821 correspond to and are connected to the two first conductive portions 42 of the second carrier 40, respectively, and the top surfaces of the two first conductive portions 821 are also connected to the first heat conductor 53. In other words, the two first conductive portions 821 are connected between the first conductive portion 42 of the second carrier 40 and the first heat conductor 53.

[0093] As shown in FIG6 , a plurality of second conductive portions 822 are arranged along the X direction and have a spacing therebetween. For example, in this embodiment, the number of second conductive portions 822 is two, and the two second conductive portions 822 are arranged along the X direction and have a spacing therebetween. The first conductive portion 821 is located between the two second conductive portions 822, and each second conductive portion 822 is connected to the first conductive portion 821 via a connecting portion 823. It is understood that in the third carrier 80, the first conductive portion 821, the second conductive portion 822, and the connecting portion 823 are manufactured using the same process, and therefore, the materials of the three can be the same, for example, all metal. Moreover, as shown in FIG5 , the first conductive portion 821 includes a metal layer 8211 and a connecting portion 8212. The thickness of the metal layer 8211 is less than the thickness of the third carrier 80, and the metal layer 8211 is connected to the first heat conductor 53 and the first conductive portion 42 of the second carrier 40 via the connecting portion 8212. Exemplarily, the metal layer 8211 is located in the middle of the third carrier 80 in the Z direction, the number of the connecting parts 8212 can be multiple, and a part of the multiple connecting parts 8212 are located between the metal layer 8211 and the second carrier 40, and another part of the multiple connecting parts 8212 are located between the metal layer 8211 and the first heat conductor 53. Thus, the heat conducted by the second heat conductor 51 through the second carrier 40 can be conducted to the first heat conductor 53 through the metal layer 8211.

[0094] In other embodiments, the number of first conductive portions 821 can be one. For example, as shown in FIG9 , the first conductive portion 821 comprises a metal block, and the thickness of the metal block of the conductive structure 82 is the same as the thickness of the third carrier plate 80. Because the first conductive portion 821 can conduct heat, adopting this structure can increase the heat conduction area of ​​the first conductive portion 821, thereby increasing the heat conduction effect of the first conductive portion 821. Furthermore, the contact area between the first conductive portion 821 and the first heat conductor 53 is larger, which also increases the heat conduction effect of the first conductive portion 821.

[0095] It will be appreciated that, in the embodiments shown in Figures 5 and 9 , the first conductive portion 42 of the second carrier plate 40 and the first conductive portion 821 of the third carrier plate 80 have the same structure. In other embodiments, the first conductive portion 42 of the second carrier plate 40 and the first conductive portion 821 of the third carrier plate 80 may have different structures. For example, the first conductive portion 42 of the second carrier plate 40 may have the structure shown in Figure 5 , and the first conductive portion 821 of the third carrier plate 80 may have the structure shown in Figure 9 . Alternatively, the first conductive portion 42 of the second carrier plate 40 may have the structure shown in Figure 9 , and the first conductive portion 821 of the third carrier plate 80 may have the structure shown in Figure 5 .

[0096] As shown in FIG5 , the third heat conductor 90 is located on a side of the third carrier 80 facing away from the second carrier 40. Exemplarily, the third heat conductor 90 is disposed on the second conductive portion 822 of the third carrier 80. Specifically, the third heat conductor 90 contacts the second conductive portion 822 of the third carrier 80. Furthermore, the top surface of the third heat conductor 90 can be flush with or slightly lower than the top surface of the third dielectric layer 32. In this manner, the first chip 20 can sequentially conduct heat generated therefrom to the first heat conductor 53 through the second heat conductor 51, the first conductive portion 42 of the second carrier 40, and the first conductive portion 821 of the third carrier 80. On the other hand, the first chip 20 can also conduct the generated heat to the third heat conductor 90 in sequence through the second heat conductor 51, the first conductive portion 42 of the second carrier 40, the first conductive portion 821 of the third carrier 80, the connecting portion 823 shown in Figure 6, and the second conductive portion 822 of the third carrier 80, so that the heat is jointly dissipated by the second heat conductor 51, the first conductive portion 42 of the second carrier 40, the conductive structure 82 of the third carrier 80, the first heat conductor 53 and the third heat conductor 90, thereby further improving the heat dissipation effect.

[0097] In one exemplary embodiment, as shown in FIG7 , the number of the third heat conductors 90 may be two, and the two third heat conductors 90 are respectively located on both sides of the second chip 60. In another example, as shown in FIG8 , the number of the third heat conductors 90 may be four, six, or more, with some of the third heat conductors 90 located on one side of the second chip 60 and others located on the other side of the second chip 60.

[0098] The third heat conductor 90 is made of metal or silicon. Exemplarily, the third heat conductor 90 is made of metal, such as copper or aluminum. Since metal has good thermal conductivity, when the third heat conductor 90 is made of metal, it can better conduct heat and dissipate heat, thereby further improving the heat dissipation effect of the chip package structure 1.

[0099] The present application also provides a method for manufacturing a chip packaging structure 1, which can be applied to the chip packaging structure 1 shown in Figure 1. As shown in Figure 10, the manufacturing method includes:

[0100] S101, manufacturing a first carrier plate on a substrate.

[0101] As shown in Figure 11(a), the top surface of the substrate 73 is covered with a fourth dielectric layer 34. A first carrier 10 can be fabricated on the fourth dielectric layer 34. The first carrier 10 includes a dielectric structure 11, a first conductive portion 12, and a second conductive portion 13. Next, a conductor 311 is fabricated on the second conductive portion 13 of the first carrier 10. The conductor 311 can be a TIV.

[0102] S102 , manufacturing a second heat conductor on the first chip, and fixing the first chip on a first carrier.

[0103] In this embodiment, the second heat conductor 51 can be fabricated on the first chip 20 first. Then, as shown in FIG11(b), the first chip 20 with the second heat conductor 51 affixed thereto can be affixed to the first carrier 10. Specifically, a flip chip (FC) method can be used to affix the first chip 20 with the second heat conductor 51 affixed thereto to the first conductive portion 12 of the first carrier 10. In other embodiments, the first chip 20 can also be affixed to the first carrier 10 first, followed by fabricating the second heat conductor 51 on the first chip 20.

[0104] S103, plastic-sealing the first chip and grinding it.

[0105] As shown in FIG11( c ), during the molding (MD) process of the first chip 20, a first dielectric layer 31 may be formed. The first dielectric layer 31 may encapsulate the first chip 20, the second thermal conductor 51, and the electrical conductor 311. The top surface of the first dielectric layer 31 is higher than the top surface of the electrical conductor 311, and the top surface of the first dielectric layer 31 is also higher than the top surface of the second thermal conductor 51.

[0106] As shown in FIG. 11 ( d ), after the molding process, the top surface of the first dielectric layer 31 may be subjected to backside grinding (BG) to thin the first dielectric layer 31 and expose the conductor 311 .

[0107] S104, making a second carrier board.

[0108] As shown in FIG12(a), a second carrier 40 can be fabricated on the first dielectric layer 31. A through hole 43 is provided on the second carrier 40. The second carrier 40 includes a dielectric structure 41 and a first conductive portion 42. The first conductive portion 42 is connected to the conductor 311. The second carrier 40 can also be an RDL.

[0109] As shown in FIG. 12( b ), a laser cavity drill process may be used to form a groove 312 on the first dielectric layer 31 , thereby exposing a portion of the top surface of the second heat conductor 51 .

[0110] S105 , forming a connection layer on the second heat conductor.

[0111] As shown in FIG. 12( c ), a connection layer 52 may be formed on the exposed top surface of the second heat conductor 51 .

[0112] S106, manufacturing a first heat conductor on the connection layer.

[0113] As shown in FIG. 13( a ), the first heat conductor 53 may be attached to the connection layer 52 .

[0114] S107, fixing the second chip on the second carrier board.

[0115] As shown in FIG13( b ), the second chip 60 can be soldered to the first conductive portion 42 of the second carrier 40 using a surface mount technology (SMT) process, and an adhesive layer 35 can be formed between the second chip 60 and the second carrier 40 using an underfill (UF) method. A portion of the adhesive layer 35 is located between the substrate 61 of the second chip 60 and the second carrier 40. Another portion of the adhesive layer 35 is located within the through-hole 43 of the second carrier 40, between the connecting layer 52 and the second carrier 40, and within the gap between the first heat conductor 53 and the second carrier 40.

[0116] As shown in FIG13( b ), the second chip 60 is plastic-encapsulated to form a third dielectric layer 32 . The third dielectric layer 32 can wrap the second chip 60 and the adhesive layer 35 , and the top surface of the third dielectric layer 32 is higher than the top surface of the second chip 60 .

[0117] S108, removing the substrate.

[0118] The substrate 73 and fourth dielectric layer 34 can be removed from the chip package structure 1 by debonding (DB). Next, the capacitor 71 is soldered to the bottom surface of the first conductive portion 12 of the first carrier 10, and the first solder ball 72 is soldered to the bottom surface of the second conductive portion 13 of the first carrier 10. The top surface of the third dielectric layer 32 is ground and thinned to form the chip package structure 1 shown in FIG1 .

[0119] In other embodiments of the present application, a method for manufacturing a chip packaging structure 1 is also provided, and the method is applied to the chip packaging structure 1 shown in FIG2 . As shown in FIG14 , the method includes:

[0120] S111, as shown in FIG15(a), a first carrier is manufactured on the substrate.

[0121] Refer to step S101 shown in FIG. 10 .

[0122] S112, fixing the first chip on the first carrier board.

[0123] As shown in FIG. 15( b ), the first chip 20 may be fixed on the first conductive portion 12 of the first carrier 10 by using a FC method.

[0124] S113, plastic-encapsulating the first chip and grinding it.

[0125] As shown in FIG15( c ), during the process of plastic encapsulating the first chip 20, a first dielectric layer 31 may be formed. The first dielectric layer 31 may enclose the first chip 20 and the conductor 311. The top surface of the first dielectric layer 31 is higher than the top surface of the conductor 311 and the top surface of the first dielectric layer 31 is also higher than the top surface of the first chip 20.

[0126] As shown in FIG16( a ), after the plastic packaging, the top surface of the first dielectric layer 31 may be ground to thin the first dielectric layer 31 and expose the conductors 311 . The top surface of the first chip 20 is lower than the top surface of the first dielectric layer 31 .

[0127] S114 , manufacturing a second heat conductor and a second carrier board on the first chip.

[0128] As shown in Figure 16(b), a groove 312 can be first formed in the first dielectric layer 31 to expose a portion of the top surface of the first chip 20. Next, as shown in Figure 16(c), a second thermal conductor 51 is formed within the groove 312 and on the first chip 20. The top surface of the second thermal conductor 51 is flush with the top surface of the first dielectric layer 31.

[0129] It is understood that in this embodiment, the first chip 20 is first fixed to the first carrier 10, and then the second heat conductor 51 is fabricated on the first chip 20. In other embodiments, the second heat conductor 51 can be first fabricated on the first chip 20, and then the first chip 20 with the second heat conductor 51 fixed thereto is fixed to the first carrier 10. For example, as shown in FIG17(a), the first carrier 10 and the conductor 311 are fabricated on the substrate 73. As shown in FIG17(b), the second heat conductor 51 is fabricated on the first chip 20, and then the first chip 20 with the second heat conductor 51 fixed thereto is soldered to the first carrier 10. As shown in FIG17(c), the first chip 20 is plastic-encapsulated to form a first dielectric layer 31, which wraps the first chip 20 and the conductor 311. The top surface of the first dielectric layer 31 can be flush with the top surface of the conductor 311 and higher than the top surface of the second heat conductor 51. As shown in FIG. 17( d ), the first dielectric layer 31 is polished to expose the top surface of the second heat conductor 51 .

[0130] As shown in FIG18( a ), a second carrier 40 is fabricated on the first dielectric layer 31 and the second heat conductor 51 . The first conductive portion 42 of the second carrier 40 is connected to the second heat conductor 51 , and the second conductive portion 44 is connected to the conductor 311 .

[0131] S115 , manufacturing a first heat conductor on the second carrier board.

[0132] As shown in FIG. 18( b ), a first heat conductor 53 is manufactured on the second carrier board 40 , and the first heat conductor 53 is connected to the first conductive portion 42 .

[0133] S116, fixing the second chip on the second carrier board.

[0134] As shown in FIG. 18( c ), the second chip 60 may be soldered to the first conductive portion 42 of the second carrier 40 by SMT technology, and an adhesive layer 35 may be formed between the second chip 60 and the second carrier 40 by dispensing glue.

[0135] As shown in FIG18( c ), the second chip 60 is plastic-encapsulated to form a third dielectric layer 32 . The third dielectric layer 32 can wrap the second chip 60 and the adhesive layer 35 , and the top surface of the third dielectric layer 32 is higher than the top surface of the second chip 60 .

[0136] S117, removing the substrate.

[0137] The substrate 73 and fourth dielectric layer 34 can be removed from the chip package structure 1 by debonding. Next, the capacitor 71 is soldered to the bottom surface of the first conductive portion 12 of the first carrier 10, and the first solder ball 72 is soldered to the bottom surface of the second conductive portion 13 of the first carrier 10. The top surface of the third dielectric layer 32 is ground and thinned to form the chip package structure 1 shown in FIG. 2 .

[0138] In other embodiments of the present application, a method for manufacturing a chip packaging structure 1 is also provided, and the method is applied to the chip packaging structure 1 shown in FIG5 . As shown in FIG19 , the method includes:

[0139] S121, as shown in FIG11(a), a first carrier is manufactured on the substrate.

[0140] Refer to step S101 shown in FIG. 10 .

[0141] S122 , manufacturing a first sub-heat conductor on the first chip, and fixing the first chip on a first carrier.

[0142] Refer to step S102 shown in FIG. 10 .

[0143] In other embodiments, the first chip 20 may be fixed on the first carrier 10 first, and then the first sub-heat conductor 511 may be manufactured on the first chip 20 .

[0144] S123, plastic-encapsulating the first chip and grinding it.

[0145] Refer to step S103 shown in FIG. 10 .

[0146] S124, forming grooves on the first dielectric layer.

[0147] As shown in FIG20( a ), a laser grooving process can be used to form a groove 312 in the first dielectric layer 31, thereby exposing a portion of the top surface of the first sub-heat conductor 511. In this embodiment, the dimension of the groove 312 along the X-direction can be smaller than the dimension of the first sub-heat conductor 511 along the X-direction. In other embodiments, the dimension of the groove 312 along the X-direction can also be the same as the dimension of the first sub-heat conductor 511 along the X-direction.

[0148] S125 , manufacturing a second sub-heat conductor and a second carrier board.

[0149] As shown in FIG20( b ), before fabricating the second carrier 40, the second sub-heat conductor 512 can be fabricated. A portion of the second sub-heat conductor 512 is located within the slot and connected to the first sub-heat conductor 511 to form the second heat conductor 51. The remaining portion extends beyond the slot 312. That is, the top surface of the second sub-heat conductor 512 is higher than the top surface of the first dielectric layer 31. Next, the second carrier 40 is fabricated on the second heat conductor 51 and the first dielectric layer 31. The second carrier 40 includes a dielectric structure 41, a first conductive portion 42, and a second conductive portion 44. The first conductive portion 42 is connected to the second heat conductor 51, and the second conductive portion 44 is connected to the conductor 311.

[0150] S126, manufacturing a third carrier board on the second carrier board.

[0151] As shown in FIG20( b ), a third carrier 80 is fabricated on the second carrier 40. The third carrier 80 includes a dielectric structure 81 and a conductive structure 82. The conductive structure 82 includes a first conductive portion 821, a connecting portion (not shown in FIG20( b )), and a second conductive portion 822. The first conductive portion 821 is connected to the first conductive portion 42 of the second carrier 40.

[0152] S127, manufacturing a first heat conductor on the third carrier board.

[0153] As shown in FIG. 20( b ), the first heat conductor 53 may be attached to the third carrier 80 , and the first heat conductor 53 is connected to the first conductive portion 821 of the third carrier 80 .

[0154] S128, manufacturing a third heat conductor on the third carrier board.

[0155] As shown in FIG. 20( c ), the third heat conductor 90 may be attached to the third carrier 80 , and the third heat conductor 90 is connected to the second conductive portion 822 of the third carrier 80 .

[0156] S129, fixing the second chip on the third carrier board.

[0157] As shown in FIG. 20( c ), the second chip 60 can be soldered to the second conductive portion 44 of the second carrier 40 by surface mounting technology, and an adhesive layer 35 can be made between the second chip 60 and the third carrier 80 by dispensing glue.

[0158] As shown in FIG20( c ), the second chip 60 is plastic-encapsulated to form a third dielectric layer 32 . The third dielectric layer 32 can wrap the second chip 60 and the adhesive layer 35 , and the top surface of the third dielectric layer 32 is higher than the top surface of the second chip 60 .

[0159] S1210, remove the substrate.

[0160] The substrate 73 and fourth dielectric layer 34 can be removed from the chip package structure 1 by debonding (DB). Next, the capacitor 71 is soldered to the bottom surface of the first conductive portion 12 of the first carrier 10, and the first solder ball 72 is soldered to the bottom surface of the second conductive portion 13 of the first carrier 10. The top surface of the third dielectric layer 32 is ground and thinned to form the chip package structure 1 shown in FIG1 .

[0161] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip packaging structure, characterized in that, include: A first carrier, a first chip, a second carrier, and a second chip are stacked in sequence, the first chip is electrically connected to the first carrier, and the second chip is electrically connected to the first carrier through the second carrier; The chip packaging structure further includes a first heat conductor, which is stacked between the first chip and the second chip, and there is a gap between the first heat conductor and the second chip; The chip packaging structure further includes an adhesive layer, wherein the adhesive layer is located on a side of the second chip facing the second carrier board, and a portion of the adhesive layer is located in the gap.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a second heat conductor, wherein the second heat conductor is in contact with a surface of the first chip facing the second carrier.

3. The chip packaging structure according to claim 2, wherein, The second heat conductor is located between the second carrier and the second chip; The second carrier includes a dielectric structure and a first conductive portion, at least a portion of the first conductive portion is disposed in the dielectric structure, and the first heat conductor and the second heat conductor are respectively connected to the first conductive portion.

4. The chip packaging structure according to claim 2 or 3, characterized in that The thickness of the first heat conductor is greater than the thickness of the second heat conductor.

5. The chip packaging structure according to claim 3, wherein The second carrier also includes a second conductive portion, at least a portion of which is disposed in the dielectric structure, and a surface facing the second conductive portion is exposed from the dielectric structure and connected to the second conductive portion, and the second conductive portion is electrically isolated from the first conductive portion.

6. The chip packaging structure according to claim 5, wherein The first conductive portion includes a metal block, and the thickness of the metal block is the same as the thickness of the second carrier board.

7. The chip packaging structure according to claim 5, wherein The first conductive part includes a metal layer and a connecting part. The thickness of the metal layer is smaller than the thickness of the second carrier board, and the metal layer is respectively connected to the second heat conductor and the first heat conductor through the connecting part.

8. The chip packaging structure according to any one of claims 3-7, characterized in that, The material of the first heat conductor includes metal or silicon.

9. The chip packaging structure according to any one of claims 3-8, characterized in that, The chip packaging structure further includes a third heat conductor, which is located on a side of the second carrier away from the first carrier, and is thermally connected to the first conductive portion.

10. The chip package structure according to claim 9, wherein The chip packaging structure further includes a third carrier plate stacked between the second carrier plate and the second heat conductor, wherein the third heat conductor is located on a side of the third carrier plate away from the second carrier plate; The third carrier includes a dielectric structure and a conductive structure. At least a portion of the conductive structure is disposed in the dielectric structure. The conductive structure is connected to the second heat conductor, the third heat conductor and the first conductive part, respectively.

11. The chip packaging structure according to claim 10, wherein, The conductive structure includes a first conductive portion, a second conductive portion, and a connecting portion connected between the first conductive portion and the second conductive portion, the first conductive portion of the conductive structure corresponds to and is connected to the first conductive portion of the second carrier, the third heat conductor is arranged on the second conductive portion, and the first direction and the thickness direction of the chip packaging structure have an angle.

12. The chip packaging structure according to claim 11, wherein The first conductive portion of the conductive structure includes a metal block, and the thickness of the metal block of the conductive structure is the same as the thickness of the third carrier.

13. The chip packaging structure according to claim 11, wherein, The first conductive portion of the conductive structure includes a metal layer and a connecting portion. The thickness of the metal layer of the conductive structure is less than the thickness of the third carrier board, and is connected to the first conductive portion of the second heat-conducting body and the second carrier board through the connecting portion.

14. The chip packaging structure according to claim 1, wherein The chip packaging structure further includes a second heat-conducting body. The first heat-conducting body and the second heat-conducting body are stacked between the first chip and the second chip. The thickness of the first heat-conducting body is greater than the thickness of the second heat-conducting body.

15. The chip packaging structure according to claim 14, wherein The chip packaging structure further includes a connecting layer located between the first heat-conducting body and the second heat-conducting body.

16. The chip package structure according to claim 15, wherein, The connecting layer is a silver paste layer or a solder layer.

17. The chip packaging structure according to any one of claims 14-16, characterized in that, Through holes are provided on the second carrier board. A part of the first heat-conducting body is located in the through holes, and the top surface of the first heat-conducting body is higher than the top surface of the second carrier board.

18. The chip packaging structure according to any one of claims 9-13, characterized in that, The material of the third heat-conducting body includes metal or silicon.

19. An electronic device, characterized in that, Including a circuit board and the chip packaging structure according to any one of claims 1-18, and the chip packaging structure is electrically connected to the circuit board.

20. A manufacturing method of a chip packaging structure, characterized in that, The manufacturing method includes: Manufacturing a first carrier board on a substrate; Fixing a first chip on the first carrier board; Manufacturing a second carrier board on the first carrier board; Manufacturing a first heat-conducting body; Fixing a second chip on the second carrier board. The first heat-conducting body is located between the first chip and the second chip and has a gap therebetween; Manufacturing an adhesive layer on the side of the second chip facing the second carrier board, and a part of the adhesive layer is located between the second chip and the first heat-conducting body; Removing the substrate.

21. The manufacturing method according to claim 20, characterized in that, After the step of fixing the first chip on the first carrier board, the manufacturing method further includes: Manufacturing a second heat-conducting body on the first chip. The second heat-conducting body is located between the first heat-conducting body and the first chip, and the thickness of the second heat-conducting body is less than the thickness of the first heat-conducting body.

22. The manufacturing method according to claim 21, characterized in that, The second carrier board includes a dielectric structure and a first conductive portion. At least part of the first conductive portion is disposed in the dielectric structure, and the first conductive portion is connected to the second heat-conducting body; The step of manufacturing the first heat-conducting body includes: Manufacturing the first heat-conducting body on the dielectric structure and the first conductive portion.

23. The manufacturing method according to claim 22, wherein After the step of manufacturing the second carrier board on the first carrier board, the manufacturing method further includes: Manufacturing a third carrier board on the second carrier board. The third carrier board includes a dielectric structure and a conductive structure, and at least part of the conductive structure is disposed in the dielectric structure, and the conductive structure is connected to the first conductive portion; Manufacturing a third heat-conducting body on the third carrier board, and the conductive structure is connected to the third heat-conducting body; The step of manufacturing the first heat-conducting body includes: Manufacturing the first heat-conducting body on the third carrier board, and the first heat-conducting body is connected to the conductive structure.

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